A data processing method, apparatus and device

Abstract

This application provides a data processing method, apparatus, and device. The apparatus includes an instruction fetch unit, a decode-and-issue unit, a write-back unit, and multiple execution units, each corresponding to a specific subtask. The instruction fetch unit reads instructions from tightly coupled memory and sends the instructions to the decode-and-issue unit. The decode-and-issue unit decodes data to be processed from the instructions and, if the data satisfies parallel processing conditions, sends the data to be processed to the multiple execution units. The multiple execution units execute the subtasks corresponding to them based on the data to be processed, obtain task processing results, and send the task processing results to the write-back unit. The write-back unit writes the task processing results to the tightly coupled memory. This technical solution converts idle time into effective computing time, maximizing hardware resource utilization.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and device. Background Technology

[0002] PON (Passive Optical Network) is a point-to-multipoint fiber optic access technology. In the optical distribution network from the central office to the user, there are no active electronic devices (such as switches or routers); it consists of passive components such as optical fibers and splitters. PON is composed of the following parts, with a tree or star topology: OLT (Optical Line Terminal): Located in the operator's central office, it is the core equipment of PON, responsible for network management and data scheduling. ODN (Optical Distribution Network): Composed of passive optical splitters and optical fibers. The splitter can divide a single optical signal into multiple paths, allowing one optical fiber to serve multiple users. ONU (Optical Network Unit): Installed on the user side, it is responsible for terminating the optical fiber signal and providing users with interfaces for data, voice, and video. An ONU can also be an ONT (Optical Network Terminal).

[0003] GPON (Gigabit Passive Optical Network) is an optical access network composed of an OLT, ODN, and ONUs. An OLT connects to multiple ONUs via the ODN, and each ONU connects to multiple TCONTs (Transmission Containers, also known as service containers). The TCONT is the smallest unit of DBA (Dynamic Bandwidth Assignment). Based on the dynamic bandwidth allocation result, uplink data (from ONU to OLT) is transmitted using time-division multiplexing. That is, each ONU sends uplink data in its own time slot according to the dynamic bandwidth allocation result, occupying uplink bandwidth.

[0004] Dynamic bandwidth allocation improves the effectiveness of PON uplink bandwidth by dynamically adjusting bandwidth among multiple ONUs based on bursty traffic needs of the ONUs. Because more efficient bandwidth is available, network administrators can add more users to the PON, allowing users to enjoy better service.

[0005] However, there is no effective way to achieve dynamic bandwidth allocation in related technologies. Summary of the Invention

[0006] This application provides a data processing apparatus, which includes an instruction fetching unit, a decoding and transmitting unit, a write-back unit, and multiple execution units, wherein the multiple execution units correspond one-to-one with multiple subtasks; The instruction fetch unit is used to read instructions from tightly coupled memory and send the instructions to the decoding and transmitting unit; A decoding and transmitting unit is configured to decode data to be processed from the instructions, and send the data to be processed to the plurality of execution units when the data to be processed meets the conditions for parallel processing; wherein, during the process of the decoding and transmitting unit decoding the data to be processed from the instructions, the instruction fetching unit has already read the next instruction from the tightly coupled memory; The plurality of execution units are configured to execute the plurality of sub-tasks corresponding to the plurality of execution units based on the data to be processed, obtain task processing results, and send the task processing results to the write-back unit; wherein, during the process of the plurality of execution units executing the plurality of sub-tasks based on the data to be processed, the decoding and transmitting unit has already decoded the data to be processed from the next instruction; The write-back unit is used to write the task processing results to the tightly coupled memory.

[0007] This application provides a data processing method, the method comprising: Read instructions from tightly coupled memory, and decode the data to be processed from the instructions; If the data to be processed meets the conditions for parallel processing, multiple sub-tasks corresponding to multiple execution units are executed based on the data to be processed to obtain the task processing result; wherein, the multiple execution units correspond one-to-one with the multiple sub-tasks; The task processing result is written to the tightly coupled memory.

[0008] This application provides an electronic device, which includes a processor and tightly coupled memory; The processor includes an instruction fetch unit, a decode-and-transmit unit, a write-back unit, and multiple execution units, each of which corresponds to a subtask. The instruction fetch unit is used to read instructions from tightly coupled memory and send the instructions to the decoding and transmitting unit; A decoding and transmitting unit is configured to decode data to be processed from the instructions, and send the data to be processed to the plurality of execution units when the data to be processed meets the conditions for parallel processing; wherein, during the process of the decoding and transmitting unit decoding the data to be processed from the instructions, the instruction fetching unit has already read the next instruction from the tightly coupled memory; The plurality of execution units are configured to execute the plurality of sub-tasks corresponding to the plurality of execution units based on the data to be processed, obtain task processing results, and send the task processing results to the write-back unit; wherein, during the process of the plurality of execution units executing the plurality of sub-tasks based on the data to be processed, the decoding and transmitting unit has already decoded the data to be processed from the next instruction; The write-back unit is used to write the task processing results to the tightly coupled memory.

[0009] As can be seen from the above technical solutions, in this embodiment, by deploying an instruction fetch unit, a decode-issue unit, a write-back unit, and multiple execution units, the instruction fetch unit reads instructions from tightly coupled memory, the decode-issue unit decodes the data to be processed from the instructions, and when the data to be processed meets the conditions for parallel processing, sends the data to be processed to multiple execution units. The multiple execution units execute multiple sub-tasks based on the data to be processed to obtain the task processing results, and the write-back unit writes the task processing results back to the tightly coupled memory. In a dynamic bandwidth allocation scenario, the data to be processed is DBA report information, and the task processing results are a bandwidth allocation mapping table, thus achieving dynamic bandwidth allocation through the instruction fetch unit, decode-issue unit, write-back unit, and multiple execution units. During task processing, multiple tasks can be processed concurrently without increasing hardware costs or power consumption by utilizing the processor's idle hardware resources (such as multiple execution units), thereby accelerating task computation and reducing the total task time. Idle time wasted on memory access waiting and pipeline pauses can be converted into effective computation time, maximizing hardware resource utilization. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of a data processing device according to one embodiment of this application; Figure 2 This is a schematic diagram of the structure of PON or GPON in one embodiment of this application; Figure 3A This is a schematic diagram of the processor structure in one embodiment of this application; Figure 3B This is a schematic diagram of the connection between the processor and tightly coupled memory in one embodiment of this application; Figure 3C This is a schematic diagram showing the connection between a programmable logic unit and a processor in one embodiment of this application; Figure 3D This is a schematic diagram of the structure of a data processing device according to one embodiment of this application; Figure 4 This is a schematic diagram of the serial bandwidth allocation process in one embodiment of this application; Figure 5AThis is a schematic diagram of the memory data layout in one embodiment of this application; Figure 5B This is a schematic diagram of a hierarchical storage architecture in one embodiment of this application; Figure 5C This is a spatiotemporal schematic diagram of an instruction pipeline in one embodiment of this application; Figure 5D This is a schematic diagram of the spatiotemporal distribution of the serial execution pipeline in one embodiment of this application; Figure 6 This is a flowchart illustrating a data processing method in one embodiment of this application. Detailed Implementation

[0011] This application provides a data processing apparatus that can be deployed on a processor, such as a processor in an electronic device. See also Figure 1 The diagram shows the structure of a data processing device. The data processing device may include an instruction fetching unit 11, a decoding and transmitting unit 12, a write-back unit 13, and multiple execution units 14, with each execution unit 14 corresponding to a multiple subtask.

[0012] Instruction fetch unit 11 is used to read instructions from tightly coupled memory and send instructions to decoding and transmitting unit 12; The decoding and sending unit 12 is used to decode the data to be processed from the instruction and send the data to be processed to multiple execution units 14 when the data to be processed meets the conditions for parallel processing. During the process of decoding the data to be processed from the instruction by the decoding and sending unit 12, the instruction fetch unit 11 has already read the next instruction from the tightly coupled memory. That is, the instruction fetch unit 11 and the decoding and sending unit 12 can process the instruction in parallel.

[0013] Multiple execution units 14 are used to execute multiple sub-tasks corresponding to the multiple execution units 14 based on the data to be processed, obtain the task processing results, and send the task processing results to the write-back unit 13; while the multiple execution units 14 are executing multiple sub-tasks based on the data to be processed, the decoding and transmitting unit 12 has already decoded the data to be processed from the next instruction, that is, the decoding and transmitting unit 12 and the multiple execution units 14 can process instructions in parallel.

[0014] Write-back unit 13 is used to write the task processing results to tightly coupled memory.

[0015] In one example, the data to be processed may include DBA report information, and the task processing result may include a bandwidth allocation mapping table. Multiple execution units 14 may include a first execution unit and a second execution unit. The first execution unit corresponds to the memory access subtask, and the second execution unit corresponds to the arithmetic operation subtask. The first execution unit is used to obtain the ONU's desired requested bandwidth and bandwidth allocation type from the DBA report information, and send the requested bandwidth and bandwidth allocation type to the second execution unit. The second execution unit is used to determine the allocated bandwidth for the ONU based on the bandwidth allocation type and the requested bandwidth, and to determine the bandwidth allocation mapping table based on the allocated bandwidth.

[0016] In one example, when the second execution unit determines the allocated bandwidth of the ONU based on the bandwidth allocation type and the requested bandwidth, it is specifically used as follows: If the bandwidth allocation type is a fixed bandwidth type or a guaranteed bandwidth type, the minimum value between the pre-calculated maximum bandwidth and the requested bandwidth is determined as the allocated bandwidth; wherein, the maximum bandwidth is determined based on the configured bandwidth limit parameter value and the configured bandwidth allocation period of the ONU; if the bandwidth allocation type is a non-guaranteed bandwidth type, a best-effort bandwidth type, or a mixed bandwidth type, the maximum bandwidth is determined based on the remaining bandwidth, the current weight of the ONU, and the total weight, and the minimum value between the maximum bandwidth and the requested bandwidth is determined as the allocated bandwidth; wherein, the remaining bandwidth is the remaining bandwidth in the total bandwidth excluding the allocated bandwidth of the fixed bandwidth type ONU and the allocated bandwidth of the guaranteed bandwidth type ONU; wherein, the current weight represents the configured bandwidth limit parameter value of the ONU, and the total weight represents the sum of the weights of all ONUs competing for the remaining bandwidth.

[0017] In one example, the data processing device may further include a first register and a second register; the first register includes a first base address pointer and a second base address pointer corresponding to tightly coupled memory, the first base address pointer indicating the starting address of the instruction, and the second base address pointer indicating the starting address of the task processing result; the second register may include a reciprocal lookup table for storing a pre-calculated reciprocal value, which is determined based on the total weight. For example, when the second execution unit determines the maximum bandwidth based on the remaining bandwidth, the current weight of the ONU, and the total weight, it specifically does so by: obtaining the reciprocal value from the reciprocal lookup table in the second register, and determining the maximum bandwidth based on the remaining bandwidth, the current weight, and the reciprocal value; wherein, the second execution unit may use the following formula to determine the maximum bandwidth; ;in, Indicates the maximum bandwidth. Indicates the remaining bandwidth. This indicates the current weight of the ONU. Represents the reciprocal value; where, yes , This represents the total weight.

[0018] In one example, the process of the first execution unit processing the first DBA report information and the process of the second execution unit processing the second DBA report information are executed synchronously. The first DBA report information is the subsequent DBA report information, and the first and second DBA report information are independent of each other. The data processing device further includes a third register, a fourth register, a fifth register, and a sixth register. The third register is used to pre-store the second DBA report information, and during processing, the second DBA report information is moved from the third register to the fourth register. The fifth register is used to pre-store the first DBA report information, and during processing, the first DBA report information is moved from the fifth register to the sixth register.

[0019] In one example, second and first DBA report information are read from tightly coupled memory. The second DBA report information is pre-stored in a third register, and the first DBA report information is pre-stored in a fifth register. The data structures for the second and first DBA report information are symmetrically distributed in the tightly coupled memory, aligned to 8-byte intervals. The last M bytes of the tightly coupled memory are allocated to the data structure for the second DBA report information, and the first M bytes are allocated to the data structure for the first DBA report information, where M is a positive multiple of 8. The data structure for the second DBA report information includes the second DBA report information and its corresponding configuration information, while the data structure for the first DBA report information includes the first DBA report information and its corresponding configuration information.

[0020] In one example, write-back unit 13 is used to classify multiple bandwidth allocation mapping tables corresponding to ONUs based on ONU identifiers and write the multiple bandwidth allocation mapping tables into tightly coupled memory.

[0021] As can be seen from the above technical solutions, in this embodiment, by deploying an instruction fetch unit, a decode-issue unit, a write-back unit, and multiple execution units, the instruction fetch unit reads instructions from tightly coupled memory, the decode-issue unit decodes the data to be processed from the instructions, and when the data to be processed meets the conditions for parallel processing, sends the data to be processed to multiple execution units. The multiple execution units execute multiple sub-tasks based on the data to be processed to obtain the task processing results, and the write-back unit writes the task processing results back to the tightly coupled memory. In a dynamic bandwidth allocation scenario, the data to be processed is DBA report information, and the task processing results are a bandwidth allocation mapping table, thus achieving dynamic bandwidth allocation through the instruction fetch unit, decode-issue unit, write-back unit, and multiple execution units. During task processing, multiple tasks can be processed concurrently without increasing hardware costs or power consumption by utilizing the processor's idle hardware resources (such as multiple execution units), thereby accelerating task computation and reducing the total task time. Idle time wasted on memory access waiting and pipeline pauses can be converted into effective computation time, maximizing hardware resource utilization.

[0022] This application proposes an electronic device, which includes a processor and tightly coupled memory; wherein the processor includes an instruction fetch unit, a decode-transmit unit, a write-back unit and multiple execution units, and the multiple execution units correspond one-to-one with multiple subtasks, that is, the above-mentioned data processing device is deployed on the processor.

[0023] The instruction fetch unit is used to read instructions from tightly coupled memory and send them to the decode-issue unit. The decode-issue unit is used to decode the data to be processed from the instructions and, if the data to be processed meets the conditions for parallel processing, send the data to be processed to multiple execution units. During the process of the decode-issue unit decoding the data to be processed from the instructions, the instruction fetch unit has already read the next instruction from the tightly coupled memory. Multiple execution units are used to execute multiple subtasks corresponding to multiple execution units based on the data to be processed, obtain the task processing results, and send the task processing results to the write-back unit. During the process of each execution unit executing multiple subtasks based on the data to be processed, the decode-issue unit has already decoded the data to be processed from the next instruction. The write-back unit is used to write the task processing results to the tightly coupled memory.

[0024] In one example, the processor may also include a first register, which may include a first base address pointer and a second base address pointer corresponding to tightly coupled memory; wherein the first base address pointer is used to indicate the starting address of the instruction, and the second base address pointer is used to indicate the starting address of the task processing result.

[0025] The electronic device may also include a programmable logic unit that accesses tightly coupled memory through the processor's AXI interface; the programmable logic unit is used to write instructions to the tightly coupled memory based on a first base address pointer after fetching instructions from the ONU, so that the instruction fetch unit can read instructions from the tightly coupled memory; The programmable logic unit is used to read the task processing result from the tightly coupled memory based on the second base address pointer and send the task processing result to the ONU.

[0026] For the processing procedure of the processor (data processing device), please refer to the above embodiments.

[0027] The technical solutions described above in the embodiments of this application will be explained below in conjunction with specific application scenarios.

[0028] PON is a point-to-multipoint fiber optic access technology, while GPON is an optical access network. PON or GPON consists of an OLT, ODN, and ONUs. One OLT connects to multiple ONUs (or ONTs) through the ODN, and each ONU connects to multiple TCONTs. The OLT, located in the operator's central equipment room, is the core equipment of PON, responsible for network management and data scheduling. The ODN consists of passive optical splitters and optical fibers. The splitter divides a single optical signal into multiple paths, allowing one fiber to serve multiple users. The ONU is installed on the user side, responsible for terminating the fiber optic signal and providing users with interfaces for data, voice, and video.

[0029] See Figure 2 The diagram shown is a schematic of a PON or GPON network. Figure 2 Taking one OLT and one ONU as an example, in real-world scenarios, one OLT can connect to multiple ONUs via ODN. For instance, an ONU may include an ONU scheduler, which corresponds to multiple TCONTs, and a TCONT is the smallest unit of a DBA. An OLT may include a DBA module and a PON MAC (Passive Optical Network Medium Access Control), which is the MAC layer of PON.

[0030] Dynamic bandwidth allocation (DBA) is a method to improve the effectiveness of PON uplink bandwidth by dynamically adjusting bandwidth among multiple ONUs based on their burst traffic needs. For example, the ONU scheduler can send DBA report information to the DBA module, which continuously collects DBA report information from each ONU.

[0031] DBA report information is used to report ONU queue status and bandwidth requirements. For example, DBA report information is encapsulated in the uplink frame as a DBRu (Dynamic Bandwidth Report upstream) field. DBA report information may include queue status, status flags, timestamps / request IDs, etc. Queue status informs the ONU of the amount of data (usually in bytes) backlogged in each priority queue, allowing the OLT to know how much data the ONU urgently needs to send. Status flags indicate whether the buffer is about to overflow (congestion) or is idle. Timestamps / request IDs assist the OLT in accurate ranging and synchronization to ensure scheduling accuracy.

[0032] Based on the DBA report information from each ONU, the OLT (DBA module) can perform relevant calculations and distribute the results to each ONU in the form of a bandwidth allocation map (BW Map). For example, the OLT obtains the bandwidth allocation map based on the DBA report information of each ONU and sends the bandwidth allocation map to each ONU (such as the ONU scheduler). For example, the BW Map (Bandwidth Map) informs each ONU at which future time point, within what duration window, and for which T-CONT data to send. For example, the BW Map is an array of multiple allocation structures, each corresponding to a specific T-CONT.

[0033] The BW Map can contain the following key instructions: Alloc-ID (Allocation Identifier), indicating which T-CONT this bandwidth is allocated to; Flags, used to indicate specific attributes of the time slot, such as whether it is a "composite" time slot; Start Time (Sstart), in bytes, indicating the moment when the T-CONT can begin sending uplink data (relative to the start of a superframe); Stop Time (Sstop), in bytes, indicating the moment when the T-CONT stops sending uplink data. Using SStart and SStop, the OLT precisely calculates and allocates the time slot (time window) for each T-CONT to send data, the length of which is determined by (SStop - SStart).

[0034] Uplink data (ONU to OLT) is transmitted in a time-division multiplexing manner, that is, each ONU sends uplink burst data in its own time slot based on the bandwidth allocation mapping table (BWMap), occupying uplink bandwidth.

[0035] Dynamic bandwidth allocation improves the effectiveness of PON uplink bandwidth by dynamically adjusting bandwidth among multiple ONUs based on bursty traffic needs of ONUs. Because more efficient bandwidth is available, network administrators can add more users to the PON, allowing them to enjoy better service. For example, dynamic bandwidth allocation can be implemented using either SR (status report) or NSR (non-status report). In SR, bandwidth is allocated based on the remaining buffer reports submitted by ONUs in real time; in NSR, DBA (Data Access Optimization) is achieved using idle cell adjustment methods.

[0036] In one example, the GPON DBA function needs to be implemented in each TCONT connection. One TCONT connection can correspond to one type of service flow, which has its own QoS (Quality of Service) characteristics. The QoS characteristics are mainly reflected in the bandwidth guarantee, which can be divided into five types: fixed bandwidth type 1, guaranteed bandwidth type 2, non-guaranteed bandwidth type 3, best-effort bandwidth type 4, and mixed bandwidth type 5.

[0037] Fixed bandwidth is the highest priority bandwidth type. It involves periodically allocating fully reserved bandwidth, meaning that bandwidth requests from the TCONT are not considered, and a fixed amount of authorization is allocated each allocation period. Using fixed bandwidth can achieve low cell transmission latency. If the TCONT reserves fixed bandwidth but has no cells to send, the OLT will still send authorization for using fixed bandwidth to the TCONT, and the ONU will send idle cells to the OLT.

[0038] Regarding guaranteed bandwidth, it is the bandwidth that the ONU can always use when the TCONT needs to send cells. If the TCONT has no cells to send, this guaranteed bandwidth can be used by other TCONTs. Obviously, the guaranteed bandwidth can participate in dynamic allocation, that is, it ensures that the bandwidth can participate in dynamic allocation.

[0039] For non-guaranteed bandwidth, which is the additional bandwidth allocated to TCONTs that have guaranteed bandwidth, it has a higher priority among the additional bandwidths and can participate in dynamic bandwidth allocation.

[0040] Regarding best-effort bandwidth, when no high-priority services are using best-effort bandwidth, TCONT can use best-effort bandwidth, but the bandwidth used cannot be guaranteed, and it can only participate in dynamic bandwidth allocation.

[0041] Hybrid bandwidth is a combination of fixed bandwidth, guaranteed bandwidth, non-guaranteed bandwidth, and best-effort bandwidth.

[0042] Regarding the dynamic bandwidth allocation process, there is currently no effective implementation method in related technologies. For example, DBA calculations require extremely high real-time performance (such as a 125µs frame period). As the PON density increases, the single-core CPU frequency may not be able to support it, or extremely high processing latency may occur, resulting in high latency and low bandwidth utilization of the dynamic bandwidth allocation algorithm.

[0043] To address the aforementioned findings, this application proposes a DBA scheduling method based on spatial parallelism and temporal interleaving of instruction pipelines. Without increasing hardware costs or power consumption, it utilizes idle processor resources (such as multiple execution units and non-blocking memory access channels) and employs register grouping and pipelined processing to achieve concurrent processing of multiple tasks (e.g., pseudo-concurrency of two OLTs). This achieves instruction-level parallelism optimization, accelerates task computation, and reduces total task execution time (e.g., ensuring total execution time ≤ 125µs). Although a single-core processor cannot execute two instructions simultaneously, it can convert idle time wasted on memory access waiting and pipeline pauses into effective computation time, maximizing hardware resource utilization.

[0044] This application proposes a data processing device that can adopt a PS-PL interactive architecture, where PS refers to a processor (CPU) and PL refers to a programmable logic unit (PL). The PPL can include an FPGA (Field-Programmable Gate Array). The data processing device is deployed on the processor, while the PPL is a component outside the data processing device. See also Figure 3A The diagram shows the structure of a processor, which can be an embedded real-time processor (such as a 32-bit embedded real-time processor) with an FPU (Floating Point Unit).

[0045] The processor may include a TCM (Tightly Coupled Memory) interface, through which the processor connects to the TCM. For example, see... Figure 3B The diagram illustrates the connection between the processor and tightly coupled memory, which may include 128KB of ATCM and 128KB of BTCM. In DBA applications, ATCM stores the real-time instruction stream, while BTCM stores the AllocID status table and DBRu report information. TCM features zero wait state and constant latency. Figure 3BIn this configuration, the 128KB ATCM is divided into two TCM-A modules, each corresponding to 64KB. The 128KB BTCM can include a 64KB B0TCM and a 64KB B1TCM. The 64KB B0TCM is divided into two TCM-B0 modules, each corresponding to 32KB, and the 64KB B1TCM is divided into two TCM-B1 modules, each corresponding to 32KB.

[0046] See Figure 3A and Figure 3B As shown, the processor's TCM interface can be connected to the ATCM, the processor's TCM interface can be connected to the BOTCM, and the processor's TCM interface can be connected to the BOTCM.

[0047] The processor may include an AXI interface (such as an AXI slave interface), such as an L2 interface AXI slave interface. Programmable logic units (FPGAs) access tightly coupled memory through the processor's AXI slave interface; that is, programmable logic units are connected to the processor's AXI slave interface. See [link to relevant documentation]. Figure 3C The diagram shows the connection between the programmable logic unit (PLU) and the processor. Since the PLU can directly access tightly coupled memory (such as ATCM and BTCM) through the AXI slave interface, this "direct memory access" mode avoids the significant latency caused by DDR (Double Data Rate).

[0048] The processor may include an AXI master interface, such as an L2 interface AXI master interface, which communicates with external devices via the AXI master bus. The processor may include a P interface, which communicates with external devices via AXI or AHB. The processor may include an ETM interface, which communicates with external devices. The processor may include a debug interface, which communicates with external devices.

[0049] A processor may include a prefetch unit, a data processing unit (DPU), a floating-point unit (FPU), a load-store unit (LSU, a core execution unit within the processor responsible for performing all memory access operations, i.e., reading data from memory into processor registers (Load) or writing data from registers back to memory (Store)), a memory protection unit (MPU), L1 data cache control, L1 data cache RAM, L1 instruction cache control, and L1 instruction cache RAM. Of course, the above is merely an example of a processor architecture and does not limit the overall processor design.

[0050] Based on the aforementioned processor, this application proposes a data processing apparatus. The data processing apparatus may include an instruction fetch unit, a decode-and-issue unit, a write-back unit, and multiple execution units. These units can be deployed on the processor. For example, the processor may include a DBA module, which may include the instruction fetch unit, decode-and-issue unit, write-back unit, and multiple execution units. The DBA module operates in a highly collaborative heterogeneous environment.

[0051] See Figure 3D The diagram shows the structure of a data processing device. The instruction fetch unit is used to read instructions from tightly coupled memory and send those instructions to the decode-transmit unit. For example, the prefetch unit in the processor can be used as the instruction fetch unit, which is connected to the tightly coupled memory via the TCM interface. After the programmable logic unit (PLU) obtains instructions from the ONU, it can write instructions to the tightly coupled memory via the AXI slave interface, thus allowing the instruction fetch unit to read instructions from the tightly coupled memory.

[0052] After receiving an instruction, the decode-issue unit decodes the data to be processed (i.e., the data in the instruction) from the instruction. If the data to be processed meets the conditions for parallel processing, it sends the data to be processed to multiple execution units. For example, the data processing unit in the processor can be used as the decode-issue unit, and the data processing unit can be connected to the instruction fetch unit, which can send instructions to the decode-issue unit.

[0053] Multiple execution units are used to execute multiple subtasks corresponding to the data to be processed (each execution unit corresponds one-to-one with a subtask), obtain the task processing results, and send the task processing results to the write-back unit. For example, the multiple execution units may include a first execution unit and a second execution unit, where the first execution unit corresponds to the memory access subtask and the second execution unit corresponds to the arithmetic operation subtask.

[0054] For example, the floating-point processing unit (FPU) in a processor is used to perform arithmetic operations. It can be used as a second execution unit to perform arithmetic subtasks. Similarly, the load-memory unit (LSU) in a processor is used to perform all memory access operations. It can be used as a first execution unit to perform memory access subtasks.

[0055] The write-back unit is used to write the results of task processing to tightly coupled memory. For example, the floating-point processing unit (FPU) of the processor can be used as the write-back unit, or any other unit within the processor; there are no restrictions. The write-back unit can be connected to the tightly coupled memory via the TCM interface, thus enabling it to write the results of task processing to the tightly coupled memory.

[0056] In one example, the data processing device described above can be applied to a DBA computing scenario. The data to be processed may include DBA report information, and the task processing results may include a bandwidth allocation mapping table (BW Map). The data processing device described above can also be applied to other computing scenarios, as long as data processing is achieved through the data processing device described above. The following example will be the application of the data processing device to a DBA computing scenario.

[0057] In one example, the data processing unit may include an instruction fetch unit, a decode-and-transmit unit, a write-back unit, and multiple execution units. A programmable logic unit (FPGA) is a component located outside the data processing unit. The FPGA accesses tightly coupled memory through the processor's AXI interface (AXI slave interface), meaning the programmable logic unit accesses tightly coupled memory through the data processing unit. For instance, after fetching instructions from the ONU, the FPGA can write instructions to the tightly coupled memory through the processor's AXI interface.

[0058] For example, the data processing device may include a first register, which may be deployed on the processor, and the first register may include a first base address pointer and a second base address pointer corresponding to tightly coupled memory.

[0059] The first base address pointer is used to indicate the starting address of the instruction; that is, the instruction is stored starting from the first base address pointer of the tightly coupled memory. When the programmable logic unit (PLC) writes an instruction to the tightly coupled memory for the first time, it starts writing the instruction from the address corresponding to the first base address pointer. Assuming the instruction length is 1, when the PLC writes an instruction to the tightly coupled memory for the second time, it starts writing the instruction from the address corresponding to the first base address pointer, but at an offset of length 1. Assuming the instruction length is 2, when the PLC writes an instruction to the tightly coupled memory for the third time, it starts writing the instruction from the address corresponding to the first base address pointer, but at an offset of length 1 + length 2, and so on.

[0060] The prefetch unit in the processor can be used as the instruction fetch unit, which is connected to tightly coupled memory via the TCM interface. A single interrupt can trigger the instruction fetch unit to read data from the tightly coupled memory. After receiving an interrupt, the instruction fetch unit can read instructions from the tightly coupled memory and send them to the decode-issue unit. Alternatively, the data processing unit in the processor can be used as the decode-issue unit. After receiving instructions, the decode-issue unit decodes DBA report information from the instructions and, if the DBA report information meets the conditions for parallel processing, sends the DBA report information to multiple execution units.

[0061] The floating-point processing unit (FPU) in the processor is used as the second execution unit, and the load-memory unit (LSU) in the processor is used as the first execution unit. The first execution unit performs memory access subtasks, and the second execution unit performs arithmetic operation subtasks. Based on the DBA report information, the first and second execution units obtain a bandwidth allocation map (BW Map) and send the bandwidth allocation map (BW Map) to the write-back unit.

[0062] For example, the decoding and transmitting unit sends DBA report information to the first execution unit. The first execution unit obtains the ONU's desired requested bandwidth and bandwidth allocation type from the DBA report information, and then sends the requested bandwidth and bandwidth allocation type to the second execution unit. The second execution unit determines the allocated bandwidth for the ONU based on the bandwidth allocation type and the requested bandwidth, and determines the bandwidth allocation mapping table based on the allocated bandwidth.

[0063] The floating-point processing unit (FPU) in the processor can be used as a write-back unit. This write-back unit can connect to tightly coupled memory via the TCM interface, allowing it to write the bandwidth allocation map (BW Map) to the tightly coupled memory. For example, the first register may include a second base address pointer corresponding to the tightly coupled memory. This second base address pointer indicates the starting address of the task processing result; that is, the bandwidth allocation map is stored starting from the second base address pointer in the tightly coupled memory. When the write-back unit first writes the bandwidth allocation map to the tightly coupled memory, it starts writing from the address corresponding to the second base address pointer. Assuming the length of the bandwidth allocation map is length 'a', the second time it writes, it starts writing from the address corresponding to the second base address pointer, but at an offset of length 'a'. Assuming the length of this bandwidth allocation map is length 'b', the third time it writes, it starts writing from the address corresponding to the second base address pointer, but at an offset of length 'a' + length 'b', and so on.

[0064] The programmable logic unit (PLU) reads the bandwidth allocation map from tightly coupled memory based on the second base address pointer. After reading the bandwidth allocation map from tightly coupled memory based on the second base address pointer, it can send the bandwidth allocation map to the ONU. When the PLU reads the bandwidth allocation map from tightly coupled memory for the first time, it starts reading from the address corresponding to the second base address pointer. When the PLU reads the bandwidth allocation map from tightly coupled memory for the second time, it starts reading from the address corresponding to the second base address pointer, but at an address after the offset length 'a', and so on.

[0065] In summary, for the input stream, the programmable logic unit (FPGA) parses the PON uplink frame in real time to obtain the instruction for the DBA report information (DBRu report), and writes the instruction to the tightly coupled memory through the processor's AXI interface, that is, writes the DBA report information to the tightly coupled memory (such as BTCM).

[0066] For the processing flow, a single interrupt triggers the instruction fetch unit to read instructions from tightly coupled memory. The decode-issue unit decodes DBA report information from the instructions. If the DBA report information meets the conditions for parallel processing, it sends the DBA report information to the first execution unit. The first execution unit obtains the ONU's desired requested bandwidth and bandwidth allocation type from the DBA report information and sends the requested bandwidth and bandwidth allocation type to the second execution unit. The second execution unit determines the allocated bandwidth for the ONU based on the bandwidth allocation type and the requested bandwidth, determines the bandwidth allocation mapping table based on the allocated bandwidth, and sends the bandwidth allocation mapping table to the write-back unit.

[0067] For the output stream, the write-back unit can connect to the tightly coupled memory via the TCM interface. The write-back unit can write the bandwidth allocation map (BW Map) to the tightly coupled memory, that is, classify and write back the authorization results to the BTCM result area. The programmable logic unit (FPGA) is triggered by the AXI write signal, and the FPGA actively reads the bandwidth allocation map (BW Map) from the tightly coupled memory.

[0068] By deploying an instruction fetch unit, a decode-issue unit, a write-back unit, and multiple execution units, a DBA scheduling method based on spatial parallelism and temporal interleaving is implemented, thereby surpassing the performance of serial execution. Spatial parallelism means that the first execution unit and the second execution unit can process DBA report information in parallel. The process of the first execution unit processing the first DBA report information and the process of the second execution unit processing the second DBA report information are executed synchronously. The first DBA report information is the following DBA report information, and there is no dependency between the first and second DBA report information. Temporal interleaving means that during the process of the instruction fetch unit reading instructions from tightly coupled memory (such as the instruction corresponding to the first DBA report information), the decode-issue unit decodes the DBA report information (such as the second DBA report information) from the instructions, that is, the two can be executed synchronously. During the process of the decode-issue unit decoding the DBA report information (such as the instruction corresponding to the first DBA report information) from the instructions, the first execution unit and the second execution unit can process the DBA report information (such as the second DBA report information). In summary, while the first and second execution units are processing the previous DBA report information, the decoding and transmitting unit is processing the next DBA report information; while the decoding and transmitting unit is processing the previous DBA report information, the instruction fetching unit is processing the next DBA report information.

[0069] The DBA scheduling method, based on spatial parallelism and time interleaving of the instruction pipeline, can surpass the performance of serial execution because the processor has a dual-issue superscalar pipeline. For example, the processor has an eight-stage pipeline (this application uses a four-stage pipeline, namely, an instruction fetch unit, a decode-issue unit, a write-back unit, and multiple execution units), supporting dual-instruction issuance (i.e., processing tasks simultaneously through a first execution unit and a second execution unit). Dual-instruction issuance means that two instructions can be sent to different execution units simultaneously (e.g., an integer arithmetic instruction and a load / store instruction), with the load / store instruction sent to the first execution unit and the integer arithmetic instruction sent to the second execution unit.

[0070] Based on this, a maximum of two instructions can be issued per cycle. These two instructions belong to different execution units, such as the first execution unit (LSU) and the second execution unit (FPU or ALU), and there are no data hazards (i.e., the processing of one instruction does not depend on the processing of the other instruction). If both instructions require the second execution unit, only one instruction can be issued (the other instruction is deferred to the next cycle).

[0071] See Figure 3D As shown, the instruction fetch unit functions as follows: it fetches two instructions from the I-Cache / TCM (if aligned and without branches, it fetches 64 bits per cycle, meaning two instructions correspond to 64 bits). The decode-issue unit functions as follows: it checks for resource conflicts, register read / write dependencies, and whether the double-issue condition is met (the two instructions belong to different execution units and have no data hazards; if met, they can be issued in the same cycle). The second execution unit (FPU) SLOT0 functions as follows: arithmetic, logic, shift, comparison, etc. The first execution unit (LSU) SLOT1 functions as follows: loading, storing, address generation, and interaction with the D-Cache / TCM. The write-back unit (WB) functions as follows: updating registers (bandwidth allocation mapping table), branch parsing, pipeline flushing, and interaction with memory. The non-blocking load / store unit (Non-blocking LSU) allows subsequent instructions that do not depend on data to be issued before the previous load instruction has returned data from memory.

[0072] For example, the instruction fetch unit reads the first instruction from tightly coupled memory and sends it to the decode-issue unit. The decode-issue unit then decodes the DBA report information from the first instruction. While the decode-issue unit is decoding the DBA report information from the first instruction, the instruction fetch unit reads the second instruction from tightly coupled memory. If the first DBA report information meets the conditions for parallel processing, the decode-issue unit sends the first DBA report information to the first execution unit. While the first and second execution units are processing based on the first DBA report information, the decode-issue unit decodes the DBA report information from the second instruction. This process can be described as a time-interleaved instruction pipeline process.

[0073] For example, the first execution unit obtains the ONU's desired bandwidth request and bandwidth allocation type from the first DBA report and sends the requested bandwidth and bandwidth allocation type to the second execution unit. The second execution unit determines the bandwidth allocation mapping table corresponding to the first DBA report based on the bandwidth allocation type and the requested bandwidth. While the second execution unit is determining the bandwidth allocation mapping table corresponding to the first DBA report, the first execution unit obtains the ONU's desired bandwidth request and bandwidth allocation type from the second DBA report. This process can be described as a spatially parallel instruction pipeline process.

[0074] After decoding the DBA report information from the instruction, the decoding and transmitting unit determines whether the DBA report information meets the conditions for parallel processing. If so, it sends the DBA report information to the first execution unit without waiting for the processing result of the previous DBA report information. If not, it pauses the transmission of the DBA report information and waits for the processing result of the previous DBA report information. That is, it only sends the DBA report information to the first execution unit after obtaining the processing result of the previous DBA report information (i.e., the processing of the previous DBA report information is completed).

[0075] For example, the decoding and transmitting unit checks for resource conflicts. If the current DBA report depends on the processing result of the previous DBA report (i.e., the current DBA report needs to be processed based on the processing result of the previous DBA report), then there is a resource conflict, and the DBA report does not meet the conditions for parallel processing. If the current DBA report does not depend on the processing result of the previous DBA report, meaning the current DBA report and the previous DBA report can be executed in parallel, then there is no resource conflict.

[0076] If there are no resource conflicts, the decoding and transmitting unit checks whether there are read / write dependencies in the registers. If a read / write dependency exists, meaning the register read / write operation of the current DBA report depends on the register read / write operation of the previous DBA report, then the dual-issue condition is not met, a data hazard exists, and the DBA report does not meet the parallel processing condition. If no read / write dependency exists, meaning the register read / write operation of the current DBA report does not depend on the register read / write operation of the previous DBA report, then the dual-issue condition is met, no data hazard exists, and the DBA report meets the parallel processing condition.

[0077] The pipeline in this embodiment refers to implementation on a processor with a dual-issue superscalar architecture and non-blocking memory access units. It utilizes microarchitectural slot filling to achieve a performance multiplication of multiple independent DBA tasks. For example, see Table 1 for an example of instruction pipeline DBA scheduling that combines spatial parallelism and temporal interleaving.

[0078] Table 1 In one example, for a single-core serial DBA implementation process, interrupts are used to periodically check whether the priority token bucket queue is updated, triggering polling of the priority token bucket queue and performing real-time bandwidth allocation.

[0079] For example, based on the five DBA configuration templates, four priority token bucket queues can be generated, from high priority to low priority: fixed bandwidth token bucket queue (T1), guaranteed bandwidth token bucket queue (T2), non-guaranteed bandwidth token bucket queue (T3), and best-effort token bucket queue (T4). The type 5 configuration template is a hybrid type and can be decomposed into the other four types, which will not be elaborated here.

[0080] For example, the number of tokens in each priority token bucket is calculated as follows. For the T1 token bucket, the number of tokens in each bucket is calculated based on the fixed bandwidth and allocation period, i.e.: TokensFix = R F ×Tsch. TokensFix can represent the number of tokens in the T1 token bucket, R F Tsch can represent a fixed bandwidth, and Tsch can represent the allocation period. For a T2 token bucket, the number of tokens in each bucket is calculated based on the guaranteed bandwidth and the allocation period, i.e.: TokensAss = R A ×Tsch. TokensAss can represent the number of tokens in the T2 token bucket, R A This can represent guaranteed bandwidth. For T3 token buckets, the number of tokens in each bucket is calculated based on the non-guaranteed bandwidth and the allocation period, i.e.: TokensNA = R NA ×Tsch. TokensNA can represent the number of tokens in the T3 token bucket, R NA This can represent non-guaranteed bandwidth. For T4 token buckets, the number of tokens in each bucket is calculated based on the best-effort bandwidth and the allocation period, i.e.: TokensBE = R BE ×Tsch. TokensBE can represent the number of tokens in the T4 token bucket, R NA It can represent bandwidth that is done to the best of one's ability.

[0081] All token buckets can be categorized by priority. When there is remaining bandwidth in the allocation period, each TCONT is polled in round-robin according to its priority, and the required bandwidth is calculated based on the corresponding algorithm. For example, when there is remaining bandwidth in the allocation period, token bucket T1 is polled first, and bandwidth is allocated to T1. After allocating T1 token bucket, when there is remaining bandwidth in the allocation period, token bucket T2 is polled, and bandwidth is allocated to T2. After allocating T2 token bucket, when there is remaining bandwidth in the allocation period, token bucket T3 is polled, and bandwidth is allocated to T3. After allocating T3 token bucket, when there is remaining bandwidth in the allocation period, token bucket T4 is polled, and bandwidth is allocated to T4.

[0082] For example, see Figure 4 The diagram shown illustrates the process of serial bandwidth allocation, which may include: Step 401: Determine if the OMCI (ONT Management and Control Interface) configuration has been updated. If yes, proceed to step 402; otherwise, proceed to step 403.

[0083] Step 402: Generate a priority token bucket queue.

[0084] For example, if the OMCI configuration is updated, it indicates a change in the bandwidth allocation type, requiring the priority token bucket queue to be regenerated. For instance, if the type changes from fixed bandwidth to guaranteed bandwidth, the priority token bucket queue for guaranteed bandwidth needs to be regenerated. If the OMCI configuration is not updated, it indicates the bandwidth allocation type has not changed, and the priority token bucket queue does not need to be regenerated.

[0085] Step 403: Determine if the queue is empty.

[0086] If not, proceed to step 404; if yes, proceed to step 407.

[0087] Step 404: Obtain the TCONT cache.

[0088] Step 405: Execute the bandwidth allocation algorithm.

[0089] Step 406: Determine if there is any remaining bandwidth.

[0090] If yes, proceed to step 403; otherwise, proceed to step 407.

[0091] Step 407: Generate a bandwidth authorization table, i.e., a bandwidth allocation mapping table (BW Map).

[0092] Step 408: Determine whether to set the timer interrupt flag.

[0093] If yes, proceed to step 409; otherwise, repeat step 408 after a certain interval.

[0094] Step 409: Issue the bandwidth allocation mapping table (BW Map).

[0095] Based on the above processing flow, the serial bandwidth allocation process involves the following three main stages: Stage I: Configuration pre-calculation and static authorization (I / O intensive), task: token bucket update, calculate maximum bandwidth, such as maximum bandwidth maxBand = (Config_kbps × 125us) / 8, where Config_kbps represents the configured bandwidth limit parameter value of the ONU (i.e., the pre-negotiated bandwidth limit parameter value, indicating that the user purchases the service with this bandwidth limit parameter value). Stage II: Dynamic bandwidth decision (computation intensive), task: read the requested bandwidth (ReqBand) from the DBA report information, indicating that the user currently expects to send data corresponding to this requested bandwidth, execute min(maxBand, ReqBand), and process the remaining bandwidth allocation. Stage III: Result aggregation and write-back (write-back intensive), task: classify AllocID by ONU_ID (i.e., classify all bandwidth allocation mapping tables), and write the authorization value to the TCM storage area (tightly coupled memory).

[0096] For example, the performance bottlenecks of the aforementioned serial bandwidth allocation are: Memory Stall: Before each calculation of the min function, the ReqBand needs to be read from the TCM, leaving the CPU idle until the data is returned. Branch prediction overhead: Frequent if-else statements cause the pipeline to be frequently flushed, with each branch failure resulting in a loss of approximately 8 clock cycles. Context waste: After task A completes execution, all register states are discarded, and task B restarts its loop initialization, wasting a significant number of instruction cycles.

[0097] Furthermore, single-socket OLTs struggle to trigger dual-issue. In the standard code handling a single-socket OLT: LDR r1, [Req] (load request); CMP r1, r2 (compare request and token) – blocking occurs because instruction 2 depends on the result of instruction 1. Additionally, SUB r3, r2, r1 (subtraction) – blocking occurs because instruction 3 depends on the judgment of instruction 2 or the value of instruction 1. Under this logic, the CPU can only execute sequentially, wasting half of the dual-issue slots.

[0098] In light of the above findings, and considering that the serial bandwidth allocation process can involve three main stages—Stage I is configuration pre-computation and static granting, Stage II is dynamic bandwidth decision-making, and Stage III is result aggregation and write-back—this embodiment can divide the DBA calculation process into three logical stages and implement interleaved execution within a single interrupt service routine (ISR). These three logical stages can be parameter preloading, instruction-level interleaved calculation, ONU aggregation, and atomic write-back. The processing procedures for these three logical stages are described below.

[0099] First, regarding the parameter preloading process.

[0100] During parameter preloading, certain parameters can be calculated and stored in advance. In this way, during instruction-level interleaved computation, these parameters can be read directly without having to calculate them.

[0101] In one example, if the bandwidth allocation type corresponding to the ONU (TCONT) is either fixed bandwidth or guaranteed bandwidth, the maximum bandwidth corresponding to the ONU can be pre-calculated. For instance, fixed bandwidth (type 1) is the highest priority bandwidth type, which allocates fully reserved bandwidth periodically. This means that regardless of the TCONT's bandwidth request, a fixed amount of authorization is allocated each allocation period. Even if the TCONT does not send any cells, the OLT still sends an authorization to use the fixed bandwidth to the TCONT, and the ONU sends idle cells to the OLT. Furthermore, guaranteed bandwidth (type 2) indicates that the ONU always has access to the bandwidth when the TCONT needs to send cells. If the TCONT does not send any cells, this guaranteed bandwidth can be used by other TCONTs. Clearly, guaranteed bandwidth can participate in dynamic allocation, ensuring that the bandwidth can participate in dynamic allocation.

[0102] When pre-calculating the maximum bandwidth corresponding to the ONU, the maximum bandwidth is determined based on the ONU's configured bandwidth limit parameter value and the configured bandwidth allocation period. For example, the maximum bandwidth can be calculated using the following formula: maxBand = (Config_kbps × 125us) / 8. In the above formula, maxBand represents the maximum bandwidth, Config_kbps represents the configured bandwidth limit parameter value, that is, the pre-negotiated bandwidth limit parameter value, indicating that the user purchases the service with this bandwidth limit parameter value, such as 10M bandwidth service. 125us represents the configured bandwidth allocation period, which can be configured according to actual needs. "8" indicates converting bits to bytes. If it is necessary to convert bits to "single-precision floating-point numbers, corresponding to 4 bytes", then "8" in the formula should be replaced with 32.

[0103] For example, the maximum bandwidth can be calculated using the following formula: maxBand=(Config_kbps×125us) / 32, where maxBand can also be written as Grant and Config_kbps can also be written as nkbps.

[0104] After obtaining the maximum bandwidth corresponding to the ONU, this maximum bandwidth can be stored, such as in a register or in tightly coupled memory; there are no restrictions on this. During instruction-level interleaving computation, this maximum bandwidth is directly read. This method allows for pre-calculation and storage of the maximum bandwidth corresponding to the ONU, facilitating direct retrieval.

[0105] In one example, if the bandwidth allocation type corresponding to the ONU (TCONT) is non-guaranteed bandwidth, best-effort bandwidth, or a hybrid bandwidth type, the reciprocal of the total weight is pre-calculated. For instance, non-guaranteed bandwidth (type 3) represents the additional bandwidth allocated to a TCONT with guaranteed bandwidth, which has a higher priority among the additional bandwidths and can participate in dynamic bandwidth allocation. Best-effort bandwidth (type 4) means that when no high-priority service uses best-effort bandwidth, the TCONT uses best-effort bandwidth, which cannot be guaranteed and can only participate in dynamic bandwidth allocation. Hybrid bandwidth (type 5) represents a combination of fixed bandwidth, guaranteed bandwidth, non-guaranteed bandwidth, and best-effort bandwidth.

[0106] When pre-calculating the reciprocal of the total weight, this reciprocal is determined based on the total weight. For example, the reciprocal can be calculated using the following formula: = In the above formula, This represents the reciprocal of the total weight. This represents the total weight.

[0107] For example, in scheduling of non-guaranteed bandwidth types (type 3), best-effort bandwidth types (type 4), or mixed bandwidth types (type 5), weight-based allocation is the most computationally intensive part. It involves multiplying the remaining bandwidth by (current weight / total weight), and directly performing this division would require dozens of cycles, completely ruining the 125µs real-time performance. Therefore, regarding the formula for weight allocation... × The formula for weight allocation can be transformed into the following formula: × × This avoids division operations.

[0108] To complete the formula transformation for weight allocation, it can be pre-calculated. This is called the total weight. The corresponding reciprocal value, = .

[0109] After obtaining the reciprocal of the total weight, this reciprocal can be stored, such as in a register or in tightly coupled memory; there are no restrictions on this. During instruction-level interleaving computation, the reciprocal of the total weight is read directly. For example, the data processing device may include a second register, which can be deployed in the processor. This second register may include a reciprocal lookup table used to store the pre-calculated reciprocal. Thus, during instruction-level interleaving computation, the reciprocal is read from the reciprocal lookup table in the second register.

[0110] In summary, to improve system operating efficiency, parameter values ​​can be calculated and stored in advance, such as the maximum bandwidth corresponding to the ONU and the reciprocal value corresponding to the total weight, for easy retrieval later.

[0111] For example, the total weight represents the sum of the weights of all ONUs competing for the remaining bandwidth (i.e., the current weight of the ONU), while the current weight represents the configured bandwidth limit parameter value of the ONU, that is, the pre-negotiated bandwidth limit parameter value, which indicates that the user purchases the service with that bandwidth limit parameter value, such as 10M bandwidth service.

[0112] In GPON, uplink bandwidth is a shared medium. The OLT dynamically allocates uplink time slots to the T-CONTs of each ONU using the DBA algorithm. The DBA template defines the following key bandwidth parameters, which determine the "weight" or share of each T-CONT in the total bandwidth: Fix (Fixed Bandwidth): Highest priority, this bandwidth is reserved regardless of traffic. Similar to "exclusive weight". Assure (Guaranteed Bandwidth): The minimum guaranteed bandwidth. This bandwidth is guaranteed at least when the network is congested; it can be borrowed by other services when idle. Max (Maximum Bandwidth): The upper limit of allowed bandwidth. This value cannot be exceeded even when the network is idle. Best Effort (Best Effort Bandwidth): After satisfying all Fix and Assure requirements, the remaining bandwidth is allocated according to demand.

[0113] Bandwidth share based on DBA type: There are five types of DBA (Type 1-Type 5), each type can correspond to different bandwidth combinations, which actually defines the "weight level" of the T-CONT in the system: Type 1 corresponds to Fix bandwidth, with the highest weight, exclusive resource, not shared with others; Type 2 corresponds to Assure bandwidth, with high weight, guaranteeing the minimum share, and priority protection during congestion; Type 3 corresponds to Assure + Max bandwidth, with medium to high weight, guaranteeing the minimum, and can preempt remaining resources to the maximum value during bursts; Type 4 corresponds to Max bandwidth, with low weight, only limiting the upper limit, no guarantee, and competing for remaining bandwidth; Type 5 corresponds to Fix + Assure + Max bandwidth, with mixed weight, including exclusive, guaranteed, and bursty portions.

[0114] Dynamic weighting based on bandwidth utilization: In dynamic bandwidth allocation (SR-DBA, status reporting mode), the ONU reports its queue status (DBRu). The OLT calculates the bandwidth slots allocated to each ONU according to the following logic: Total available bandwidth = total uplink rate of PON port (e.g., 1.25 Gbps or 2.5 Gbps) - overhead (frame header, guard time, etc.). Total fixed bandwidth = sum of Fix parameters in all Type 1 / 5. Total guaranteed bandwidth = sum of Assure parameters in Type 2 / 3 / 5. Remaining bandwidth = total available bandwidth - total fixed bandwidth - actual guaranteed bandwidth used. Based on this, the current weight can be understood as the real-time bandwidth requirement or the configured guaranteed bandwidth ratio of a certain ONU. If the weighted fair queuing (WFQ) concept is used to handle best-effort traffic, then the current weight of the ONU is the maximum bandwidth configured for that ONU or its current queue length, and the total weight is the sum of the weights of all ONUs competing for the remaining bandwidth.

[0115] Of course, the above is just an example of the current weight. The current weight of the ONU can be configured according to actual needs. In this embodiment, the current weight represents the configured bandwidth limitation parameter value of the ONU. After knowing the current weight of each ONU, the total weight is the sum of the weights of all ONUs competing for the remaining bandwidth.

[0116] Second, regarding the instruction-level interleaved computing process.

[0117] During instruction-level interleaved computation, the first execution unit obtains the ONU's desired requested bandwidth and bandwidth allocation type from the DBA report information, and then sends the requested bandwidth and bandwidth allocation type to the second execution unit. The second execution unit determines the allocated bandwidth for the ONU based on the bandwidth allocation type and the requested bandwidth, and determines the bandwidth allocation mapping table based on the allocated bandwidth. Based on this, the first and second execution units can process data in parallel; for example, the first execution unit's processing of the first DBA report information and the second execution unit's processing of the second DBA report information are executed synchronously.

[0118] For example, the first DBA report is the DBA report that follows the second DBA report. The first DBA report and the second DBA report are not dependent on each other. In other words, the processing of the first DBA report does not depend on the processing result of the second DBA report.

[0119] For example, the first execution unit obtains the ONU's desired requested bandwidth and bandwidth allocation type from the second DBA report information, and sends the requested bandwidth and bandwidth allocation type to the second execution unit. The second execution unit then determines the allocated bandwidth for the ONU based on the bandwidth allocation type and the requested bandwidth, and determines the bandwidth allocation mapping table based on the allocated bandwidth. During the process of the second execution unit determining the bandwidth allocation mapping table corresponding to the second DBA report information, the first execution unit obtains the ONU's desired requested bandwidth and bandwidth allocation type from the first DBA report information. Thus, the process of the first execution unit processing the first DBA report information and the process of the second execution unit processing the second DBA report information are executed synchronously.

[0120] Based on the above processing, it is possible to simultaneously initiate the reading of configuration parameters (such as bandwidth configuration, weight, etc.) for two OLTs, utilizing the non-blocking characteristics of LSU (Load Memory Unit). When the CPU issues a read instruction for path A, it immediately issues a read instruction for path B without waiting for data to return. For example, after the first execution unit completes processing the second DBA report information, it does not receive the processing result of the second execution unit for the second DBA report information; the first execution unit continues to process the first DBA report information.

[0121] During instruction-level interleaved computation, the SR-DBA algorithm is executed, including token bucket deduction, bandwidth type (Type1, Type2, Type3, Type4, Type5) traversal, and decisions such as GrantSize=min(maxBand, ReqBand) and weight allocation. Through exclusive register partitioning, certain registers are forcibly designated as A-path contexts, and certain registers as B-path contexts. A-path corresponds to the first DBA report information, and B-path corresponds to the second DBA report information. The first DBA report information follows the second DBA report information.

[0122] During instruction-level interleaved computation, PUSH / POP instructions are not used throughout the process, eliminating memory stack overhead. Utilizing the processor's dual-issue superscalar architecture, logical comparison instructions (such as CMP) on path A and arithmetic operation instructions (such as ADD) on path B are scheduled in adjacent cycles. The pipeline bubbles of task A are filled with the effective instructions from task B, achieving microscopic "pseudo-parallelism."

[0123] In one example, to support instruction-level interleaved computation, the memory layout can be designed to place pre-computed values ​​and critical data (such as DBA report information) in tightly coupled memory (TCM). To ensure faster LSU operation in Slot 1, the data structures of the two OLTs (i.e., adjacent DBA report information) can be symmetrically distributed, fully utilizing the 64-bit AXI bus width, and arranged contiguously with 8-byte alignment. For instance, OLT-A (i.e., the first DBA report information corresponding to path A) and OLT-B (i.e., the first DBA report information corresponding to path B) can be stored in tightly coupled memory (TCM-B), with the first 32KB allocated to OLT-A and the last 32KB allocated to OLT-B.

[0124] For example, see Figure 5A The diagram shows a schematic of the memory data layout. The first 32KB (TCM-B0) of the tightly coupled memory is allocated to OLT-A to store the data structure for the first DBA report information. The data structure for the first DBA report information includes the first DBA report information (e.g., Req_A0) and the configuration information corresponding to the first DBA report information (e.g., Cfg_A0). The configuration information corresponding to the first DBA report information consists of parameters related to the first DBA report information, such as the pre-calculated maximum bandwidth mentioned above.

[0125] The last 32KB (TCM-B1) of the tightly coupled memory is allocated to OLT-B to store the data structure of the second DBA report information. The data structure of the second DBA report information includes the second DBA report information (such as Req_B0) and the configuration information corresponding to the second DBA report information. The configuration information corresponding to the second DBA report information consists of parameters related to the second DBA report information, such as the pre-calculated maximum bandwidth mentioned above.

[0126] In summary, the data structures for the second and first DBA report information are symmetrically distributed in tightly coupled memory, aligned to 8-byte intervals. The first M bytes of the tightly coupled memory are allocated to the data structure for the second DBA report information, and the last M bytes are allocated to the data structure for the first DBA report information. M can be a positive integer multiple of 8, such as 32KB, 64KB, etc.

[0127] See Figure 5A As shown, the structure is defined as 8-byte aligned (64-bit alignment). The processor's LDRD / STRD instructions are most efficient (1 cycle) when accessing 8-byte aligned addresses. If not aligned, it will be split into two 32-bit cycles, with each node being an integer multiple of 8 bytes, such as: Word 0 (32-bit): Request (real-time request updated by logic / hardware), Word 1 (32-bit): Config / Weight (static configuration or weight).

[0128] In one example, to support instruction-level interleaved computation, a register allocation strategy can be designed. To avoid register contention, the processor's 13 general-purpose registers can be strictly divided and physically isolated. The register layout is shown in Table 2.

[0129] Table 2 In the aforementioned registers, registers r0 and r1, designated as the sixth register, are used to store the current data of the OLT-A, i.e., the first DBA report information corresponding to path A. Registers r4 and r5, designated as the fifth register, are used to store the OLT-A prefetch buffer, i.e., the first DBA report information corresponding to path A. For example, during the first execution unit's processing of the second DBA report information, it can pre-read the first DBA report information from tightly coupled memory and pre-store it in the fifth register. The fifth register is used to pre-store the first DBA report information. Thus, after the processing of the second DBA report information is completed (i.e., when the first DBA report information needs to be processed), the first DBA report information can be moved from the fifth register to the sixth register, achieving rapid migration of the first DBA report information. After the first DBA report information is moved to the sixth register, the first execution unit can read the first DBA report information from the sixth register and process it. During the processing of the first DBA report information, the next DBA report information can be pre-stored in the fifth register, and so on, repeating the above process.

[0130] In the aforementioned registers, registers r2 and r3, designated as the fourth register, are used to store the current OLT-B data, i.e., the second DBA report information corresponding to the B path. Registers r6 and r7, designated as the third register, are used to store the OLT-B prefetch buffer, i.e., the first DBA report information corresponding to the B path. For example, during the second execution unit's processing of the previous DBA report information for the second DBA report information, it can pre-read the second DBA report information from tightly coupled memory and pre-store it in the third register. The third register is used to pre-store the second DBA report information. Thus, after the processing of the previous DBA report information is completed (i.e., when the second DBA report information needs processing), the second DBA report information can be moved from the third register to the fourth register, achieving rapid migration of the second DBA report information. After the second DBA report information is moved to the fourth register, the second execution unit can read the second DBA report information from the fourth register and process it. This process can be repeated in this manner.

[0131] In summary, the data processing device also includes a third register, a fourth register, a fifth register, and a sixth register, which can be deployed on the processor. The third register is used to pre-store second DBA report information; when processing the second DBA report information, it can be moved from the third register to the fourth register. The fifth register is used to pre-store first DBA report information; when processing the first DBA report information, it can be moved from the fifth register to the sixth register.

[0132] Registers r8 and r9 are used to store the TCM base address pointer. Registers r8 and r9 serve as the first registers and are used to store the first base address pointer and the second base address pointer corresponding to the tightly coupled memory.

[0133] Register r10 is used to store the remaining total bandwidth (remaining bandwidth). That is, after the remaining bandwidth is calculated, the remaining bandwidth is stored in register r10. The calculation process of the remaining bandwidth is described in subsequent embodiments.

[0134] Register r11 is used to store a reciprocal lookup table, which stores a pre-calculated reciprocal value, which can be 2^32 / TotalWeight, for deterministic normalization. That is, register r11 can be used as a second register, which can be deployed on the processor and can include a reciprocal lookup table.

[0135] Register r12 can be used as a calculation temporary register for UMULL high-order output or Type extraction. That is, after the first execution unit obtains the bandwidth allocation type, it stores the bandwidth allocation type in register r12, and the second execution unit reads the bandwidth allocation type from register r12 when it obtains the bandwidth allocation type.

[0136] Register lr (r14) can be used as a loop counter. It is a dedicated counter that ensures loop safety.

[0137] See Figure 5BThe diagram illustrates a hierarchical memory architecture. Utilizing the processor's 64-bit TCM bus, the OLT scheduling data (Request + Config) is loaded into the register set in one go via the LDRD instruction. A dual-window register arrangement is employed, with the register set internally divided into a prefetch buffer window (r4-r7) and a current processing window (r0-r3). The prefetch buffer window stores the next set of data pre-fetched by Slot 1 (LSU) within the current cycle, thus eliminating the impact of physical memory access latency on the computation logic. Computation and memory access instructions overlap; Slot 0 focuses on high-precision multiplication (UMULL) and real-time deduction of remaining bandwidth (r10). While Slot 1 executes its computation tasks in Slot 0, it simultaneously performs the prefetching of the next set of data, achieving 100% duty cycle operation for both computation and memory access units. The state machine cascades and switches, and at the end of a single scheduling cycle, pushes the data of the prefetch buffer window to the processing window through MOV operations between registers (or pointer rotation), ensuring that the DBA scheduling logic has extremely high deterministic timing in the processing of 512 AllocIDs. This will be explained below.

[0138] See Figure 5B As shown, the general-purpose register set may include registers r0 and r1, registers r2 and r3, registers r4 and r5, registers r6 and r7, and registers r10 and r11. In the expected cache window, the first DBA report information corresponding to path A can be read from tightly coupled memory and stored in registers r4 and r5; similarly, the second DBA report information corresponding to path B can be read from tightly coupled memory and stored in registers r6 and r5. In the current processing window, the first DBA report information corresponding to path A is moved to registers r0 and r1 for storage, and the second DBA report information corresponding to path B is moved to registers r2 and r3 for storage. Furthermore, the remaining bandwidth can be stored in register r10, and the normalization parameter can be stored in register r11, i.e., the reciprocal value is stored using a reciprocal lookup table.

[0139] For the dual-issue execution engine (i.e., the first execution unit and the second execution unit), operations such as UMULL calculation, normalization calculation, and bandwidth reduction can be performed in instruction pipeline 0. Operations such as LDRD prefetch loading, SRD result storage, and address auto-increment update can be performed in instruction pipeline 1.

[0140] In one example, during instruction-level interleaved computation, the first execution unit obtains the ONU's desired requested bandwidth and bandwidth allocation type from the DBA report information and sends the requested bandwidth and bandwidth allocation type to the second execution unit. The second execution unit determines the allocated bandwidth for the ONU based on the bandwidth allocation type and the requested bandwidth, and determines the bandwidth allocation mapping table based on the allocated bandwidth. The processing procedure of the second execution unit is explained below.

[0141] For example, if the bandwidth allocation type is fixed bandwidth or guaranteed bandwidth, the second execution unit reads the pre-calculated maximum bandwidth `maxBand`. Since the maximum bandwidth `maxBand` has already been calculated and stored during the pre-calculation process, the second execution unit can directly read the maximum bandwidth `maxBand`. Then, the second execution unit can determine the minimum value between the maximum bandwidth and the requested bandwidth as the allocated bandwidth. For example, the second execution unit can perform the following operation: `GrantSize = min(maxBand, ReqBand)`, to obtain the allocated bandwidth `GrantSize`. Based on this, a bandwidth allocation map (BW Map) can be determined. This embodiment does not impose restrictions on how the bandwidth allocation map is determined.

[0142] For example, if the bandwidth allocation type is a non-guaranteed bandwidth type, a best-effort bandwidth type, or a mixed bandwidth type, the second execution unit determines the maximum bandwidth `maxBand` based on the remaining bandwidth, the current weight of the ONU, and the total weight, and determines the minimum value between the maximum bandwidth and the requested bandwidth as the allocated bandwidth. For example, the second execution unit can perform the following operation: `GrantSize = min(maxBand, ReqBand)` to obtain the allocated bandwidth `GrantSize`. Based on this, a bandwidth allocation map (BW Map) can be determined. This embodiment does not impose restrictions on how the bandwidth allocation map is determined.

[0143] When determining the maximum bandwidth `maxBand` based on the remaining bandwidth, the current weight of the ONU, and the total weight, the first execution unit can read the pre-calculated reciprocal value. Since the reciprocal value has already been calculated and stored during the pre-calculation process, the second execution unit can directly read the reciprocal value. For example, the first execution unit can obtain the reciprocal value from the reciprocal lookup table in the second register. Based on this, the maximum bandwidth can be determined based on the remaining bandwidth, the current weight, and the reciprocal value. For example, the second execution unit can use the following formula to determine the maximum bandwidth; .

[0144] In the above formula, It can represent the maximum bandwidth, which can also be denoted as maxBand. This represents the remaining bandwidth, which is the bandwidth remaining in the total bandwidth after deducting the allocated bandwidth of ONUs with fixed bandwidth and the allocated bandwidth of ONUs with guaranteed bandwidth. This can represent the current weight of the ONU. It can represent the reciprocal of the total weight.

[0145] To address the problems inherent in serial implementations, this embodiment, based on the aforementioned instruction-level interleaving computation process, fully leverages CPU performance and employs an instruction-interleaving software pipeline to achieve the following functions: Spatial parallelism utilizes multiple independent execution units (such as the first and second execution units) within a superscalar processor to simultaneously drive different types of hardware resources within the same instruction issue cycle through microarchitecture-level instruction pairing. By explicitly pairing the arithmetic logic instructions of the OLT-A path (processed by the ALU) with the memory access instructions of the OLT-B path (processed by the LSU), two independent DBA tasks achieve physical execution overlap under the same clock pulse, thereby multiplying the instruction throughput (IPC) of a single-core processor. For example, spatial parallelism means that the process of the first execution unit processing the first DBA report information and the process of the second execution unit processing the second DBA report information are executed synchronously; the first DBA report information is the following DBA report information, and there is no dependency between the first and second DBA report information.

[0146] Latency Hiding: Leveraging non-blocking memory access, during the standby window between the memory access instruction and the data return to the register, computational tasks independent of the accessed data are scheduled for execution, thus eliminating memory access latency in the pipeline. This is achieved by utilizing the processor's non-blocking LSU feature to target the first... i+1 The data load instruction (LDRD) for the Alloc-ID is placed in the first... iThe Alloc-ID calculation logic begins at the specified location; utilizing a memory access latency window of 8-12 instruction cycles at a 600MHz clock frequency, the current node performs a 64-bit long multiplication and type determination, ensuring that the computation unit switches to the next node precisely when the data arrives, achieving zero-stop continuous scheduling. For example, latency masking refers to the process where, after the first execution unit completes the processing of the second DBA report, it processes the first DBA report directly without waiting for the second execution unit's processing result, thus eliminating memory access latency in the pipeline, i.e., eliminating waiting time.

[0147] Temporal interleaving (Software Pipelining) functionality: This feature simulates the stages of a hardware pipeline using software, breaking down tasks that were originally executed serially into sub-stages such as fetch, compute, and write-back. Tasks belonging to different time steps are interleaved within a single loop iteration, constructing a three-level software pipeline architecture. In a single DBA loop, the processor synchronously executes: the bandwidth result write-back of node [i-1], the composite bandwidth allocation calculation of node [i], and the prefetch of the original request of node [i+1]. This logical interleaving in the time dimension eliminates the serial waiting overhead between tasks in serial scheduling. For example, temporal interleaving means that the instruction fetch unit reads instruction 1 from tightly coupled memory and sends instruction 1 to the decode-issue unit. The decode-issue unit decodes DBA report information 1 from instruction 1 and sends DBA report information 1 to multiple execution units. Multiple execution units obtain bandwidth allocation mapping table 1 based on DBA report information 1 and send bandwidth allocation mapping table 1 to the write-back unit. The write-back unit writes the bandwidth allocation mapping table 1 into tightly coupled memory.

[0148] During the decoding and issuing unit's decoding of DBA report information 1 from instruction 1, the instruction fetch unit reads instruction 2 from tightly coupled memory and sends instruction 2 to the decoding and issuing unit. During the process of multiple execution units obtaining bandwidth allocation mapping table 1 based on DBA report information 1, the decoding and issuing unit decodes DBA report information 2 from instruction 2 and sends DBA report information 2 to multiple execution units. During the process of the write-back unit writing bandwidth allocation mapping table 1 into tightly coupled memory, multiple execution units obtain bandwidth allocation mapping table 2 based on DBA report information 2. Clearly, based on the above processing, the processing of each unit is interleaved in time.

[0149] Deterministic Computation: By eliminating conditional branching and variable-cycle instructions (such as hardware division) in the algorithm implementation, it ensures that the execution path length and the number of clock cycles consumed remain constant when processing any combination of input data. It replaces indeterminate-cycle division operations with a "reverse lookup table method" combined with "unsigned long multiplication (UMULL)," and utilizes ARM instruction set conditional execution suffixes to replace if-else jumps. This ensures that the processing time of 1024 Alloc-IDs is unaffected by the service traffic model, achieving nanosecond-level jitter control and meeting the hard real-time clock requirements of the XGSPON system. Deterministic computation refers to determining the maximum bandwidth by querying a reciprocal lookup table to obtain the reciprocal value, and then determining the maximum bandwidth based on this reciprocal value, thus eliminating division operations and using multiplication operations. The process of determining the maximum bandwidth can be seen in the formula above.

[0150] Third, regarding the ONU polymerization and atom write-back process.

[0151] The write-back unit can categorize multiple bandwidth allocation maps corresponding to an ONU based on the ONU's identifier and write these multiple bandwidth allocation maps into tightly coupled memory (TCM). For example, the calculated bandwidth allocation maps (AllocID grant values) can be physically categorized according to the identifier of the ONU (i.e., ONU_ID), thus categorizing multiple bandwidth allocation maps corresponding to the same ONU. Then, multiple bandwidth allocation maps (multiple grant results) for the same ONU are written into TCM at once. For example, an STM (Store Multiple) burst write instruction can be used to write multiple bandwidth allocation maps for the same ONU into TCM at once and trigger a single AXI register write operation to notify the FPGA to read the bandwidth allocation maps.

[0152] In one example, the pseudocode for DBA scheduling implementation, taking the scheduling of two OLTs with 1024 allocids per path as an example, can be shown as follows: #define DBA_ULTRA_ISO_MACRO \ / * --- 1. [A-path logic] Extract A-path Weight + store B-path [i-1] result--- * / \ "LSR r12, r1, #16 \n\t" / * [Slot 0] Extract path A[i]Weight * / \ "STRD r2, r3, [r9, #-16] \n\t" / * [Slot 1] Stores B-path [i-1] Final Grant+Config (r2 / r3 are stored from the previous round) * / \ / * --- 2. [A-way precision calculation] 64-bit long multiplication + B-way [i+1] prefetch (delay masking begins) ---* / \ "UMULL r12, r1, r12, r10 \n\t" / * [Slot 0] r1:r12 = Weight_A * RemBW(high bits of r1) * / \ "LDRD r6, r7, [r9], #8 \n\t" / * [Slot 1] [Non-blocking] Prefetch B-path [i+1] to r6 / r7 (memory access isolation) * / \ / * --- 3. [A-way normalization] 64-bit precision compensation + A-way [i+1] prefetch --- * / \ "UMULL r12, r1, r1, r11 \n\t" / * [Slot 0] Normalization: r1 = (Prod_High × Reciprocal) * / \ "LDRD r4, r5, [r8], #8 \n\t" / * [Slot 1] [Non-blocking] Prefetch A-path [i+1] to r4 / r5 (memory access isolation) * / \ / * --- 4. [Type A Branch] Type 1-5 Deterministic Decisions --- * / \ "TST r1, #0x01 \n\t" / * Check if it is Type 1 * / \ "MOVNE r1, r1, LSR #16 \n\t" / * [Correction] Type 1: Grant = Fixed bandwidth (overlaying dynamically calculated result r1) * / \ "CMP r1, r0 \n\t" / * [Deterministic] Compare Grant(r1) with the original Request(r0) * / \ "MOVHI r1, r0 \n\t" / * [Deterministic] Rate capping, r0 is not overwritten, logically sound * / "SUBr10, r10, r1 \n\t" / * Update global remaining bandwidth * / \ / * --- 5. [B-path logic] Extract B-path Weight + Store A-path[i] result--- * / \ "LSR r12, r3, #16 \n\t" / * [Slot 0] Extract B path[i]Weight * / \ "STRD r1, r1, [r8, #-16] \n\t" / * [Slot 1] Stores the result of path A[i] (Grant is stored in r1, Config is stored back) * / \ / * --- 6. [B-path precision calculation] Logic is the same as A-path --- * / \ "UMULL r12, r3, r12, r10 \n\t" / * B-way multiplication, the highest digit of the result is in r3 * / \ "UMULL r12, r3, r3, r11 \n\t" / * B-path normalization, final Grant at r3 * / \ "TST r3, #0x01\n\t" \ "MOVNE r3, r3, LSR #16 \n\t" \ "CMP r3, r2 \n\t" / * Compare B-path Grant(r3) with the original Request(r2) * / \ "MOVHI r3, r2\n\t" \ "SUB r10, r10, r3 \n\t" \ / * --- 7. [Pipeline Cascade Switching] Prepare for the next cycle--- * / \ "MOV r0, r4 \n\t" / * A[i+1] Req ->r0 (Computational update) * / \ "MOV r1, r5 \n\t" / * A[i+1] Cfg ->r1 (Computational update) * / \ "MOV r2, r6 \n\t" / * B[i+1] Req ->r2 (Computational update) * / \ "MOV r3, r7 \n\t" / * B[i+1] Cfg ->r3 (Computational update) * / Based on the example of the DBA scheduling pseudocode above, for spatial parallelism, through the physical isolation of r0-r3 (computation) and r4-r7 (memory access), the LSU execution unit and the ALU execution unit have no read-after-write (RAW) conflicts at the register level, satisfying the dual-issue execution condition. For example: Line 1 (ALU): Using a barrel shifter, the high 16 bits of the weight are extracted from the A-way configuration word r1 to r12 without adding extra cycles. Line 2 (LSU): The B-way result calculated in the previous loop is written back. Since r9 was incremented by 8 at the end of the previous round, -16 here accurately locates the B-way result slot. Slot 0 parses data, and Slot 1 moves data. The two OLTs achieve "one fast and one slow" alignment at the instruction issue level.

[0153] To address time interleaving, a single macro execution includes writing back the result of i-1, calculating the bandwidth of i, and prefetching the request for i+1. Initialization ensures that r0-r3 are filled at the start of the loop, while the MOV at the end of the loop ensures continuous iteration of the data stream. For delay masking, line 3 (ALU): performs a 32x32 unsigned multiplication. r1 obtains the high 32 bits of the product, at which point r1's original Config is overwritten, freeing up space to store intermediate values. Line 4 (LSU): Delay masking is initiated, prematurely starting the data read from the next node in the B-path. Data is loaded into registers r6 / r7, 15 instructions before it is used in the next round; this deep masking completely eliminates any pauses in TCM access. For deterministic computation, register locking is used: all computation parameters (RemBW, Reciprocal) are in registers, eliminating memory access jitter. By using jump-free logic: replacing if / else jumps with TST / MOVNE / MOVHI ensures constant instruction execution time regardless of the combination of business types, preventing pipeline flushing, and also taking advantage of the fact that r0 has not yet been overwritten. By using a lookup table: using r11 (the reciprocal) for the multiplication in line 5 avoids the uncertain time consumption of hardware division.

[0154] See Figure 5C The diagram shows the spatiotemporal schematic of the instruction pipeline. In Slot 0, the ALU execution unit performs the following operations: in cycle 1, extracts the A-path weight (LSR); in cycle 2, performs A-path multiplication 1 (UMULL); in cycle 3, performs A-path multiplication 1 (UMULL); in cycle 4, performs A-path type determination (TST); in cycle 5, performs A-path bandwidth allocation (CMP); in cycle 6, extracts the B-path weight (LSR); in cycle 7, performs B-path multiplication 1 (UMULL); and in cycle 8, performs data cascading switching (MOV).

[0155] In Slot 1, the LSU execution unit performs the following operations: in cycle 1, B-way results (STRD) are stored; in cycle 2, B-way requests (LDRD) are prefetched; in cycle 3, A-way requests (LDRD) are prefetched; in cycle 4, the LSU is busy; in cycle 5, A-way results (STRD) are stored; in cycle 6, the LSU is idle; in cycle 7, B-way prefetched data arrives; and in cycle 8, the LSU prepares for the next round.

[0156] from Figure 5C The following technical points can be derived, as shown in Table 3: Table 3 Phase interleaving technology is used to reassemble the computation instructions of the OLT-A path with the memory access instructions of the OLT-B path. During the waiting gaps for data reading from the OLT-B path, the weighted multiplication and type determination logic of the OLT-A path is filled, eliminating pipeline bubbles and enabling the processor to achieve minimal pauses within a 125µs scheduling window.

[0157] In one example, regarding the serial implementation analysis process, due to the strict data dependencies between instructions, the processor cannot initiate dual-issue and needs to pause (stand) during memory access to wait for data to return. This is illustrated using the process of handling an allocid bandwidth allocation (data fetch - weight calculation - bandwidth allocation - data storage) as an example. See [link to relevant documentation]. Figure 5D The diagram shown illustrates the spatiotemporal distribution of a serial execution pipeline. Figure 5D It can be seen that in the serial technique, there is a significant load-use penalty cycle between the instruction (LDRD) and the subsequent arithmetic instruction. Due to data dependency, the processor execution unit generates a Stall (pause bubble) in cycles 2 and 3, resulting in low utilization of dual-issue resources.

[0158] The following is a comparison and explanation of IPC (Instructions Per Cycle).

[0159] For the theoretical model of IPC implemented serially, the instruction stream exhibits severe data dependency, leading to frequent pipeline stalls. Based on this, IPC can be calculated using the following formula: . This indicates the number of instructions that complete a single Allocid-ID scheduling. This represents the ideal cycle time required for logical computation. This indicates the waiting period (typically 3-5 cycles) between the Load Directive (LDR) and the Use Directive (MUL). This indicates the clearing cycle (approximately 8 cycles each time) caused by branch prediction failure due to if-else type judgment.

[0160] Assumption =12, =8, =3, =3, then =0.8, which means that even with dual-transmit hardware, the actual efficiency of IPC is lower than that of single-transmit (<1.0).

[0161] The parallel interleaving IPC theoretical model of this invention fills the emitter slots through spatial parallelism, eliminates pause periods through temporal interleaving, and eliminates branch penalties through deterministic computation. Based on this, IPC can be calculated using the following formula: In the above formula, This indicates the number of instructions that complete a single Allocid-ID scheduling. This indicates the emitter slot fill rate (approximately 0.7, paired via ALU / LSU commands). This indicates the pause period (approximately 2 due to the prefetch full masking delay).

[0162] Assumption =12, =8, =2, then = 1.68, which means that the actual efficiency of IPC is greater than 1, and the actual efficiency of IPC is twice that of serial implementation.

[0163] In summary, for a serial implementation, the theoretical peak IPC is 0.8, the pipeline utilization is less than 40%, and the critical path latency is... High determinism (affected by branch prediction). For the parallel interleaving implementation, the theoretical peak IPC is greater than 1.6, overcoming the instruction dependency bottleneck; pipeline utilization is greater than 70%, maximizing hardware energy efficiency; critical path latency is... Other delays are masked, achieving zero-pause memory access; low determinism (fixed instruction flow) improves scheduling accuracy. The scheduling method in this embodiment increases the processor's instructions per cycle (IPC) from 0.6 in serial mode to 1.6 in parallel interleaved mode. By eliminating the load-use penalty between instructions, the total scheduling cycle of 1024 Alloc-IDs is compressed to within a 125us time window, thereby achieving zero-pause memory access.

[0164] As seen from the above technical solutions, for time interleaving, phase difference rearrangement of heterogeneous tasks creates an execution phase difference between the two OLT tasks, breaking the linear logic of a single task and transforming serial tasks into pipelined tasks, thus improving system throughput. For latency masking, physical isolation and prefetching techniques are used to divide the processor's general-purpose registers into computation operations (r0-r3) and memory access front-ends (r4-r7). Non-blocking LSUs (non-blocking memory access units) are used to mask the access latency of the TCM bus and AXI interconnect matrix, allowing the CPU to execute at full capacity even while waiting for data returns, eliminating pipeline bubbles. For spatial parallelism, dual-issue instruction gap filling technology achieves maximum filling of instruction issue slots, improving IPC (instructions per cycle) and achieving performance close to that of hardware accelerators without increasing the processor's clock speed. For cross-instance instruction pipeline filling, a code arrangement method is declared to insert computation instructions from instance A into memory access or jump delay slots in instance B, eliminating single-core pipeline stalls. For register-level zero-overhead context switching, a mechanism is declared to enable logical switching of multiple tasks without pushing / popping from the stack by defining the scope of the processor's general-purpose registers. For deterministic computation, a "pre-computed inverse lookup table + 64-bit unsigned long multiplication (UMULL)" method is used to replace hardware division. The conditional execution suffixes (MOVNE, MOVHI, ADDNE) and barrel shifters (LSR) of the ARM instruction set are used to extract configuration parameters (such as PreGrantSize) in real time, eliminating all conditional jump instructions. This ensures that no matter how complex the service combination of 1024 nodes is, the time error for processing each frame is less than one clock cycle, meeting the hard real-time cycle requirements of GPON / XGSPON.

[0165] By semantically partitioning registers (computation window and prefetch window), the composite data (request and configuration) obtained from a single 64-bit aligned memory access is cascaded and buffered at the physical register level. Leveraging the heterogeneous parallelism of the multiplication execution engine and the Load / Store unit, timing interleaving and compression of multi-tasks (A / B paths) are achieved at the macro instruction level, ultimately improving single-core throughput at a deterministic clock frequency with near-zero jitter. Based on a register prefetch architecture, a method for concurrent data scheduling on the processor is implemented by setting at least two independent physical register groups, defined as a computation group and a buffer group. Both the computation group and the buffer group use even-numbered register pairs (e.g., r0-r1, r4-r5) to match the processor's single-cycle 64-bit (double-word) memory access bandwidth. While the computation group executes the calculation of the current data frame, the memory access unit asynchronously loads the next frame of data into the buffer group. The staggered sequence of computation and memory access tasks is achieved through instruction orchestration. Within one instruction cycle, arithmetic and logic instructions from the first task are paired with store / load instructions from the second task through a dual-issue pairing. During the execution stage of the first task, which executes multi-cycle long instructions (such as UMULL), the instruction sequence orchestrates unrelated memory access instructions (such as LDRD) from the second task into the issue slots, utilizing the pipeline gaps occupied by the long instructions to complete the backfilling of memory access data.

[0166] The latency masking mechanism employs a dual-path (A-path and B-path) scheduling logic with cross-arrangement. The remaining bandwidth calculation for path A and the weight extraction for path B are initiated within the same clock cycle. Spatial register redundancy eliminates temporal load-use data dependency latency, improving single-core execution efficiency without increasing the clock frequency. Deterministic latency guarantee is achieved by replacing conditional branch logic with full-path conditional execution instructions (such as MOVNE / MOVHI) and deterministic computation, ensuring a constant number of machine cycles for the algorithm under all service loads (regardless of whether the rate limit is reached), thus meeting the nanosecond-level deterministic requirements of GPON systems for DBA scheduling cycles. Hardware and software co-optimization, combined with the low-latency TCM characteristics of the Zynq architecture, achieves high-concurrency DBA scheduling through fine-grained assembly-level orchestration, reducing system power consumption and cost.

[0167] As can be seen from the above technical solutions, this embodiment satisfies the stringent 125µs real-time scheduling cycle of the XGSPON system on a low-cost, single-core processor, while simultaneously handling 2048 scheduling nodes across two OLTs. By deeply exploring and utilizing the inherent microarchitectural characteristics of the processor (dual-issue, non-blocking memory access), performance is doubled through sophisticated software orchestration. It enables spatial parallelism: pairing computation instructions from one OLT with memory access instructions from another OLT to fill the processor's dual-issue slots. It enables temporal interleaving (software pipeline): breaking down tasks into stages and interleaving different stages of different tasks within a loop to form a pipeline. It enables latency masking: utilizing non-blocking memory access, data is pre-loaded, and other computations are inserted during waiting periods to "mask" memory access latency. It enables deterministic computation: using lookup tables instead of division and conditional execution instructions instead of branch jumps ensures constant execution time.

[0168] The above functions are achieved through specific register allocation strategies (such as registers r0-r3 as computation windows and registers r4-r7 as prefetch windows) and special memory layouts (8-byte alignment, dual-path symmetry).

[0169] For example, independent register sets can be allocated to the first OLT task and the second OLT task, respectively, as computation registers and prefetch registers. Within the same processor cycle, a first type of instruction belonging to the first OLT task is issued to the first execution unit, and simultaneously, a second type of instruction belonging to the second OLT task is issued to the second execution unit. The first type of instruction and the second type of instruction are of different types. While performing bandwidth calculation for the scheduling node at the current index i, a non-blocking load operation on the data of the scheduling node at index i+1 is initiated and loaded into the prefetch register. For example, allocating independent register sets to the first OLT task and the second OLT task includes: allocating registers r0 and r1 to the first OLT task as computation registers, allocating registers r2 and r3 to the second OLT task as computation registers; allocating registers r4 and r5 to the first OLT task as prefetch registers, and allocating registers r6 and r7 to the second OLT task as prefetch registers.

[0170] For example, the scheduling node data structures of the first and second OLT tasks are distributed symmetrically in tightly coupled memory, and each data structure is stored in 8-byte alignment. In the step of determining the allocated bandwidth based on the bandwidth allocation type and requested bandwidth, a pre-stored inverse lookup table is used for multiplication operations instead of division operations, and conditional execution instructions are used instead of branch jump instructions.

[0171] Based on the same application concept as the above method, this application proposes a data processing method, see [link to relevant documentation]. Figure 6 The diagram shown is a flowchart of a data processing method, which may include: Step 601: Read instructions from tightly coupled memory and decode the data to be processed from the instructions.

[0172] Step 602: If the data to be processed meets the conditions for parallel processing, execute multiple sub-tasks corresponding to multiple execution units based on the data to be processed to obtain the task processing result; wherein, the multiple execution units correspond one-to-one with the multiple sub-tasks; the multiple execution units are deployed on the processor.

[0173] Step 603: Write the task processing result into the tightly coupled memory.

[0174] In one example, the data to be processed includes DBA report information, and the task processing result includes a bandwidth allocation mapping table; the multiple execution units include a first execution unit and a second execution unit, the first execution unit corresponding to a memory access subtask, and the second execution unit corresponding to an arithmetic operation subtask.

[0175] In one example, multiple subtasks corresponding to multiple execution units are executed based on the data to be processed to obtain the task processing result, which may include, but is not limited to: obtaining the ONU's expected request bandwidth and bandwidth allocation type from the DBA report information through the first execution unit; The second execution unit determines the allocated bandwidth of the ONU based on the bandwidth allocation type and the requested bandwidth, and determines the bandwidth allocation mapping table based on the allocated bandwidth.

[0176] In one example, the second execution unit determines the allocated bandwidth of the ONU based on the bandwidth allocation type and the requested bandwidth, which may include, but is not limited to: If the bandwidth allocation type is a fixed bandwidth type or a guaranteed bandwidth type, then the minimum value between the pre-calculated maximum bandwidth and the requested bandwidth is determined as the allocated bandwidth; wherein, the maximum bandwidth is determined based on the configured bandwidth limit parameter value of the ONU and the configured bandwidth allocation period; If the bandwidth allocation type is a non-guaranteed bandwidth type, a best-effort bandwidth type, or a hybrid bandwidth type, then the maximum bandwidth is determined based on the remaining bandwidth, the current weight of the ONU, and the total weight, and the minimum value between the maximum bandwidth and the requested bandwidth is determined as the allocated bandwidth; wherein, the remaining bandwidth is the remaining bandwidth in the total bandwidth excluding the allocated bandwidth of ONUs with fixed bandwidth type and the allocated bandwidth of ONUs with guaranteed bandwidth type; wherein, the current weight represents the configured bandwidth limit parameter value of the ONU, and the total weight represents the sum of the weights of all ONUs competing for the remaining bandwidth.

[0177] In one example, the second register includes a reciprocal lookup table for storing pre-calculated reciprocal values, which are determined based on the total weight. The process of determining the maximum bandwidth based on the remaining bandwidth, the current weight of the ONU, and the total weight may include, but is not limited to: obtaining the reciprocal value from the reciprocal lookup table in the second register, and determining the maximum bandwidth based on the remaining bandwidth, the current weight, and the reciprocal value; wherein, the maximum bandwidth may be determined using the following formula. ; Indicates the maximum bandwidth. Indicates the remaining bandwidth. This indicates the current weight of the ONU. This represents the reciprocal value; yes , This represents the total weight.

[0178] In one example, the process of the first execution unit processing the first DBA report information and the process of the second execution unit processing the second DBA report information are executed synchronously; wherein, the first DBA report information is the DBA report information following the second DBA report information, and the first DBA report information and the second DBA report information have no dependency relationship.

[0179] In one example, a second DBA report and a first DBA report can be read from the tightly coupled memory. The data structures of the second and first DBA report are symmetrically distributed in the tightly coupled memory and aligned to 8 bytes. The last M bytes of the tightly coupled memory are allocated to the data structure of the second DBA report information, and the first M bytes are allocated to the data structure of the first DBA report information, where M is a positive integer multiple of 8; the data structure of the second DBA report information includes the second DBA report information and the configuration information corresponding to the second DBA report information, and the data structure of the first DBA report information includes the first DBA report information and the configuration information corresponding to the first DBA report information.

[0180] In one example, writing the task processing result to the tightly coupled memory may include, but is not limited to: classifying multiple bandwidth allocation mapping tables corresponding to the ONU based on the ONU's identifier, and writing the multiple bandwidth allocation mapping tables to the tightly coupled memory.

[0181] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.

Claims

1. A data processing apparatus, characterized in that, The device includes an instruction fetching unit, a decoding and transmitting unit, a write-back unit, and multiple execution units, each of which corresponds to a subtask. The instruction fetch unit is used to read instructions from tightly coupled memory and send the instructions to the decoding and transmitting unit; A decoding and transmitting unit is configured to decode data to be processed from the instructions, and send the data to be processed to the plurality of execution units when the data to be processed meets the conditions for parallel processing; wherein, during the process of the decoding and transmitting unit decoding the data to be processed from the instructions, the instruction fetching unit has already read the next instruction from the tightly coupled memory; The plurality of execution units are configured to execute the plurality of sub-tasks corresponding to the plurality of execution units based on the data to be processed, obtain task processing results, and send the task processing results to the write-back unit; wherein, during the process of the plurality of execution units executing the plurality of sub-tasks based on the data to be processed, the decoding and transmitting unit has already decoded the data to be processed from the next instruction; The write-back unit is used to write the task processing results to the tightly coupled memory.

2. The apparatus according to claim 1, characterized in that, The data to be processed includes DBA report information, and the task processing result includes a bandwidth allocation mapping table; the multiple execution units include a first execution unit and a second execution unit, the first execution unit corresponds to the memory access subtask, and the second execution unit corresponds to the arithmetic operation subtask; The first execution unit is configured to obtain the ONU's desired request bandwidth and bandwidth allocation type from the DBA report information, and send the request bandwidth and bandwidth allocation type to the second execution unit; The second execution unit is used to determine the allocated bandwidth of the ONU based on the bandwidth allocation type and the requested bandwidth, and to determine the bandwidth allocation mapping table based on the allocated bandwidth.

3. The apparatus according to claim 2, characterized in that, When the second execution unit determines the allocated bandwidth for the ONU based on the bandwidth allocation type and the requested bandwidth, it is specifically used for: If the bandwidth allocation type is a fixed bandwidth type or a guaranteed bandwidth type, then the minimum value between the pre-calculated maximum bandwidth and the requested bandwidth is determined as the allocated bandwidth; wherein, the maximum bandwidth is determined based on the configured bandwidth limit parameter value of the ONU and the configured bandwidth allocation period; If the bandwidth allocation type is a non-guaranteed bandwidth type, a best-effort bandwidth type, or a hybrid bandwidth type, then the maximum bandwidth is determined based on the remaining bandwidth, the current weight of the ONU, and the total weight, and the minimum value between the maximum bandwidth and the requested bandwidth is determined as the allocated bandwidth; wherein, the remaining bandwidth is the remaining bandwidth in the total bandwidth excluding the allocated bandwidth of ONUs with fixed bandwidth type and the allocated bandwidth of ONUs with guaranteed bandwidth type; wherein, the current weight represents the configured bandwidth limit parameter value of the ONU, and the total weight represents the sum of the weights of all ONUs competing for the remaining bandwidth.

4. The apparatus according to claim 3, characterized in that, The device further includes a first register and a second register; the first register includes a first base address pointer and a second base address pointer corresponding to the tightly coupled memory, the first base address pointer being used to indicate the starting address of the instruction, and the second base address pointer being used to indicate the starting address of the task processing result; the second register includes a reciprocal lookup table, the reciprocal lookup table being used to store a pre-calculated reciprocal value, and the reciprocal value being determined based on the total weight; When the second execution unit determines the maximum bandwidth based on the remaining bandwidth, the current weight of the ONU, and the total weight, it is specifically used to: obtain the reciprocal value from the reciprocal lookup table of the second register, and determine the maximum bandwidth based on the remaining bandwidth, the current weight, and the reciprocal value; The second execution unit determines the maximum bandwidth using the following formula; ； in, This indicates the maximum bandwidth. This indicates the remaining bandwidth. This indicates the current weight of the ONU. This represents the reciprocal value; yes , This represents the total weight.

5. The apparatus according to claim 2, characterized in that, The process by which the first execution unit processes the first DBA report information and the process by which the second execution unit processes the second DBA report information are executed synchronously. Wherein, the first DBA report information is the DBA report information following the second DBA report information, and the first DBA report information and the second DBA report information have no dependency relationship; The device further includes a third register, a fourth register, a fifth register, and a sixth register; the third register is used to pre-store second DBA report information, and when processing the second DBA report information, the second DBA report information is moved from the third register to the fourth register; the fifth register is used to pre-store first DBA report information, and when processing the first DBA report information, the first DBA report information is moved from the fifth register to the sixth register.

6. The apparatus according to claim 5, characterized in that, Read the second DBA report information and the first DBA report information from the tightly coupled memory, pre-store the second DBA report information in the third register, and pre-store the first DBA report information in the fifth register; The data structures of the second DBA report information and the first DBA report information are symmetrically distributed in the tightly coupled memory and aligned according to 8 bytes. The last M bytes of the tightly coupled memory are allocated to the data structure of the second DBA report information, and the first M bytes are allocated to the data structure of the first DBA report information, where M is a positive integer multiple of 8; the data structure of the second DBA report information includes the second DBA report information and the configuration information corresponding to the second DBA report information, and the data structure of the first DBA report information includes the first DBA report information and the configuration information corresponding to the first DBA report information.

7. The apparatus according to claim 2, characterized in that, The write-back unit is used to classify multiple bandwidth allocation mapping tables corresponding to the ONU based on the ONU's identifier, and write the multiple bandwidth allocation mapping tables into the tightly coupled memory.

8. A data processing method, characterized in that, The method includes: Read instructions from tightly coupled memory, and decode the data to be processed from the instructions; If the data to be processed meets the conditions for parallel processing, multiple sub-tasks corresponding to multiple execution units are executed based on the data to be processed to obtain the task processing result; wherein, the multiple execution units correspond one-to-one with the multiple sub-tasks; The task processing result is written to the tightly coupled memory.

9. The method according to claim 8, characterized in that, The data to be processed includes DBA report information, and the task processing result includes a bandwidth allocation mapping table; the multiple execution units include a first execution unit and a second execution unit, the first execution unit corresponds to the memory access subtask, and the second execution unit corresponds to the arithmetic operation subtask; Based on the data to be processed, execute multiple sub-tasks corresponding to multiple execution units to obtain task processing results, including: obtaining the ONU's expected request bandwidth and bandwidth allocation type from the DBA report information through the first execution unit; The second execution unit determines the allocated bandwidth of the ONU based on the bandwidth allocation type and the requested bandwidth, and determines the bandwidth allocation mapping table based on the allocated bandwidth.

10. The method according to claim 9, characterized in that, The step of determining the allocated bandwidth of the ONU by the second execution unit based on the bandwidth allocation type and the requested bandwidth includes: If the bandwidth allocation type is a fixed bandwidth type or a guaranteed bandwidth type, then the minimum value between the pre-calculated maximum bandwidth and the requested bandwidth is determined as the allocated bandwidth; wherein, the maximum bandwidth is determined based on the configured bandwidth limit parameter value of the ONU and the configured bandwidth allocation period; If the bandwidth allocation type is a non-guaranteed bandwidth type, a best-effort bandwidth type, or a hybrid bandwidth type, then the maximum bandwidth is determined based on the remaining bandwidth, the current weight of the ONU, and the total weight, and the minimum value between the maximum bandwidth and the requested bandwidth is determined as the allocated bandwidth; wherein, the remaining bandwidth is the remaining bandwidth in the total bandwidth excluding the allocated bandwidth of ONUs with fixed bandwidth type and the allocated bandwidth of ONUs with guaranteed bandwidth type; wherein, the current weight represents the configured bandwidth limit parameter value of the ONU, and the total weight represents the sum of the weights of all ONUs competing for the remaining bandwidth.

11. The method according to claim 10, characterized in that, The determination of the maximum bandwidth based on the remaining bandwidth, the current weight of the ONU, and the total weight includes: The reciprocal value is obtained from the acquired reciprocal lookup table, and the maximum bandwidth is determined based on the remaining bandwidth, the current weight, and the reciprocal value; wherein, the reciprocal lookup table is used to store pre-calculated reciprocal values, and the reciprocal value is determined based on the total weight; The maximum bandwidth is determined using the following formula; ； in, This indicates the maximum bandwidth. This indicates the remaining bandwidth. This indicates the current weight of the ONU. This represents the reciprocal value; yes , This represents the total weight.

12. An electronic device, characterized in that, The electronic device includes a processor and tightly coupled memory; The processor includes an instruction fetch unit, a decode-and-transmit unit, a write-back unit, and multiple execution units, each of which corresponds to a subtask. The instruction fetch unit is used to read instructions from tightly coupled memory and send the instructions to the decoding and transmitting unit; A decoding and transmitting unit is configured to decode data to be processed from the instructions, and send the data to be processed to the plurality of execution units when the data to be processed meets the conditions for parallel processing; wherein, during the process of the decoding and transmitting unit decoding the data to be processed from the instructions, the instruction fetching unit has already read the next instruction from the tightly coupled memory; The plurality of execution units are configured to execute the plurality of sub-tasks corresponding to the plurality of execution units based on the data to be processed, obtain task processing results, and send the task processing results to the write-back unit; wherein, during the process of the plurality of execution units executing the plurality of sub-tasks based on the data to be processed, the decoding and transmitting unit has already decoded the data to be processed from the next instruction; The write-back unit is used to write the task processing results to the tightly coupled memory.

13. The device according to claim 12, characterized in that, The processor further includes a first register, which includes a first base address pointer and a second base address pointer corresponding to the tightly coupled memory; wherein the first base address pointer is used to indicate the starting address of the instruction, and the second base address pointer is used to indicate the starting address of the task processing result; The electronic device further includes a programmable logic unit that accesses the tightly coupled memory through the processor's AXI interface; The programmable logic unit is configured to write instructions to the tightly coupled memory based on the first base address pointer after obtaining instructions from the ONU, so that the instruction fetch unit can read instructions from the tightly coupled memory; The programmable logic unit is used to read the task processing result from the tightly coupled memory based on the second base address pointer, and send the task processing result to the ONU.

Images