Audio data backoff circuit and system on chip
Patent Information
- Application Number
- CN202510328649.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2026-09-22
AI Technical Summary
[0002]在采用蓝牙设备(例如耳机、音响等)进行通话的场景下，例如用户用手机的扬声器播放来电语音，那么该下行音频信号经过周围环境(例如墙壁、家具、家电等)反射后，重新被该用户的手机的麦克风采集到，形成该下行音频信号的回声，并经上行通路输出给对端用户，从而导致输出的上行音频信号中不仅包括本端用户的语音，还包括上述对端用户的下行音频信号的回声，这严重影响了用户的通话体验
[0010]可见，通过本申请实施例提供的所述音频数据回采电路中，所述下行信号输出模块，对经过所述下行处理器解码后的下行音频数据进行数模转换处理后，对外输出音频模拟信号；所述上行信号提取模块，将输入的音频模拟信号进行模数转换后，输出上行音频数字信号给所述上行处理器，从而实现了下行通路的音频数据无损送回上行通路，进而在此情况下，进一步所述下行信号输出模块，输出音频数字信号给所述参考信号提取模块，从而使得参考信号提取模块，将所述音频数字信号转换为参考信号，并输出给所述上行处理器，用于所述上行处理器对上行音频信号消除回声，因此本申请可以在较低成本和功耗的情况下，提取到用于消除音频信号中的回声的参考信号，从而实现较低成本和功耗的回声消除。
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Figure CN122802840A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of audio technology, and in particular to an audio data acquisition circuit and system-on-a-chip. Background Technology
[0002] In scenarios where Bluetooth devices (such as headsets, speakers, etc.) are used for calls, for example, when a user plays the incoming call voice through their phone's speakerphone, the downlink audio signal is reflected by the surrounding environment (such as walls, furniture, appliances, etc.) and then re-collected by the user's phone microphone, forming an echo of the downlink audio signal. This echo is then output to the other user via the uplink path. As a result, the output uplink audio signal includes not only the user's voice but also the echo of the other user's downlink audio signal, which seriously affects the user's call experience. Summary of the Invention
[0003] This application provides an audio data back-sampling circuit and a system-on-a-chip (SoC) for extracting a reference signal for eliminating echoes in audio signals at a lower cost and power consumption, thereby achieving echo cancellation at a lower cost and power consumption.
[0004] This application provides an audio data acquisition circuit, comprising: a downlink processor, a downlink signal output module, a reference signal extraction module, an uplink signal extraction module, and an uplink processor; wherein,
[0005] The downlink processor is used to decode the input downlink audio data and output it to the downlink signal output module.
[0006] The downlink signal output module is used to perform digital-to-analog conversion processing on the downlink audio data decoded by the downlink processor and output an analog audio signal; and to output an analog audio signal to the reference signal extraction module.
[0007] The reference signal extraction module is used to convert the audio digital signal into a reference signal and output it to the uplink processor; wherein, the reference signal is used by the uplink processor to eliminate echo in the uplink audio signal;
[0008] The uplink signal extraction module is used to convert the input analog audio signal into digital signal and output the uplink digital audio signal to the uplink processor.
[0009] The uplink processor is configured to perform echo cancellation on the uplink digital audio signal based on the reference signal, and then encode and output the echo-cancelled uplink audio signal.
[0010] As can be seen, in the audio data back-sampling circuit provided in this application embodiment, the downlink signal output module performs digital-to-analog conversion on the downlink audio data decoded by the downlink processor and outputs an analog audio signal; the uplink signal extraction module performs analog-to-digital conversion on the input analog audio signal and outputs an uplink digital audio signal to the uplink processor, thereby realizing lossless transmission of audio data from the downlink path back to the uplink path. Furthermore, in this case, the downlink signal output module outputs an audio digital signal to the reference signal extraction module, so that the reference signal extraction module converts the audio digital signal into a reference signal and outputs it to the uplink processor for the uplink processor to eliminate echo in the uplink audio signal. Therefore, this application can extract a reference signal for eliminating echo in the audio signal with low cost and power consumption, thereby achieving echo cancellation with low cost and power consumption.
[0011] In some embodiments, the reference signal extraction module includes:
[0012] The delay processing module is used to perform delay processing on the input audio digital signal.
[0013] In some embodiments, the reference signal extraction module further includes:
[0014] A decimation filter is used to downsample the input digital audio signal.
[0015] In some embodiments, the decimation filter includes a series of multi-stage decimation filters, wherein different stages of the decimation filters employ preset different downsampling factors to downsample the input audio digital signal.
[0016] In some embodiments, the delay processing module includes a series of multi-stage delay processing modules, wherein different stages of the delay processing modules are connected in series between different stages of the decimation filter.
[0017] As can be seen, the embodiments of this application further reduce the number of delay units required by using a multi-stage decimation filter and a multi-stage delay processing module connected in series, thereby saving chip area.
[0018] In some embodiments, the circuit further includes:
[0019] The delay parameter calculation module is used to determine the range of values for the delay parameters of each stage of the delay processing module based on the delay resolution of the multi-stage delay processing module and the delay value that needs to be compensated for for the echo.
[0020] As can be seen, the present application embodiment can automatically obtain the specific configuration values of the delay parameters (e.g., the number of delay units) required by each delay processing module through the delay parameter calculation module, without the need for manual calculation, thus improving the efficiency of circuit configuration.
[0021] In some embodiments, the multi-stage decimation filter includes: a first-stage decimation filter, a second-stage decimation filter, and a third-stage decimation filter;
[0022] The multi-level delay processing module includes: a first-level delay processing module, a second-level delay processing module, a third-level delay processing module, and a fourth-level delay processing module;
[0023] The input terminal of the first-stage delay processing module is connected to the downlink signal output module, and the output terminal is connected to the input terminal of the first-stage decimation filter; the output terminal of the first-stage decimation filter is connected to the input terminal of the second-stage delay processing module; the output terminal of the second-stage delay processing module is connected to the input terminal of the second-stage decimation filter; the output terminal of the second-stage decimation filter is connected to the input terminal of the third-stage delay processing module; the output terminal of the third-stage delay processing module is connected to the input terminal of the third-stage decimation filter; and the output terminal of the third-stage decimation filter is connected to the input terminal of the fourth-stage delay processing module.
[0024] In some embodiments, the delay parameter calculation module includes: a first calculation unit, a second calculation unit, and a third calculation unit connected in series; wherein,
[0025] The first calculation unit is used to divide the delay value input from the first input terminal for the echo compensation by the delay resolution of the fourth-level delay processing module input from the second input terminal, take the integer part of the quotient as the maximum value of the delay parameter of the fourth-level delay processing module, and output it through the first output terminal; and output the remainder to the first input terminal of the second calculation unit through the second output terminal.
[0026] The second calculation unit is used to divide the number input at the first input terminal by the delay resolution of the third-level delay processing module input at the second input terminal, take the integer part of the quotient as the maximum value of the delay parameter of the third-level delay processing module, and output it through the first output terminal; and output the remainder through the second output terminal to the first input terminal of the third calculation unit.
[0027] The third calculation unit is used to divide the number input at the first input terminal by the delay resolution of the second-level delay processing module input at the second input terminal, and take the integer part of the quotient as the maximum value of the delay parameter of the second-level delay processing module and output it through the first output terminal; and take the remainder as the maximum value of the delay parameter of the first-level delay processing module and output it through the second output terminal.
[0028] In some embodiments, the reference signal extraction module further includes:
[0029] The volume adjustment module has its input terminal connected to the output terminal of the fourth-level delay processing module. The volume adjustment module is used to adjust the volume of the input audio digital signal.
[0030] This application provides a system-on-a-chip that includes any of the circuits described above. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 A schematic diagram of an audio data acquisition circuit provided in an embodiment of this application;
[0033] Figure 2 A schematic diagram of another audio data acquisition circuit provided in this application embodiment;
[0034] Figure 3 A schematic diagram of the structure of the third audio data acquisition circuit provided in the embodiments of this application;
[0035] Figure 4 This is a schematic diagram of the structure of a delay parameter calculation module provided in an embodiment of this application;
[0036] Figure 5 A schematic diagram of the delay resolution of each stage of the delay processing module in the third type of audio data retrieval circuit provided in the embodiments of this application;
[0037] Figure 6 A schematic diagram of another delay parameter calculation module provided in an embodiment of this application. Detailed Implementation
[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0039] This application provides an audio data back-sampling circuit and a system-on-a-chip (SoC) for extracting a reference signal for eliminating echoes in audio signals at a lower cost and power consumption, thereby achieving echo cancellation at a lower cost and power consumption.
[0040] The audio data acquisition circuit and the system-on-a-chip are based on the same application concept. Since the principles of solving the problem are similar, the implementation of the audio data acquisition circuit and the system-on-a-chip can refer to each other, and the repeated parts will not be described again.
[0041] The terms "first," "second," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0042] The following examples and embodiments are to be understood as illustrative only. While this specification may refer to "a," "an," or "some" examples or embodiments in several places, this does not mean that every such reference relates to the same example or embodiment, nor does it mean that the feature applies only to a single example or embodiment. Individual features of different embodiments may also be combined to provide other embodiments. Furthermore, terms such as "comprising" and "including" should be understood not to limit the described embodiments to consisting only of those features mentioned; such examples and embodiments may also include features, structures, units, modules, etc., not specifically mentioned.
[0043] The various embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be noted that the order in which the embodiments are presented in this application represents only a chronological order and does not represent the superiority or inferiority of the technical solutions provided by the embodiments.
[0044] See Figure 1This application provides an audio data acquisition circuit, comprising: a downlink processor 01, a downlink signal output module 02, a reference signal extraction module 03, an uplink signal extraction module 04, and an uplink processor 05; wherein,
[0045] The downlink processor 01 is used to decode the input downlink audio data and output it to the downlink signal output module 02.
[0046] The downlink signal output module 02 is used to perform digital-to-analog conversion processing on the downlink audio data decoded by the downlink processor 01 and output an analog audio signal to the outside; and to output an analog audio signal to the reference signal extraction module 03.
[0047] The reference signal extraction module 03 is used to convert the audio digital signal into a reference signal and output it to the uplink processor 05; wherein, the reference signal is used by the uplink processor 05 to eliminate echo in the uplink audio signal;
[0048] The uplink signal extraction module 04 is used to convert the input analog audio signal into digital signal and output the uplink digital audio signal to the uplink processor 05.
[0049] The uplink processor 05 is used to perform echo cancellation on the uplink audio digital signal based on the reference signal, and to encode and output the echo-cancelled uplink audio signal.
[0050] In some embodiments, the downlink processor 01 and the uplink processor 05 can both be processors such as CPUs and DSPs.
[0051] It should be noted that the downlink processor 01 and the uplink processor 05 can be the same CPU or DSP, or they can be different CPUs or DSPs. If the downlink processor 01 and the uplink processor 05 are the same CPU or DSP, then the downlink processor 01 and the uplink processor 05 can be different algorithm modules running on the same CPU / DSP, that is, different functional modules (or they can be independent processors).
[0052] In some embodiments, the downlink signal output module 02 and the uplink signal extraction module 04 each include a first-in-first-out (FIFO) unit, a digital unit, and an analog unit, respectively, see, for example, [link to relevant documentation]. Figure 2The downlink signal output module 02 includes a DAC FIFO unit 11, a DAC Digital unit 12, and a DAC Analog unit 13; the uplink signal extraction module 04 includes an ADC Analog unit 21, an ADC Digital unit 22, and an ADC FIFO unit 23.
[0053] Among them, DAC FIFO unit 11 and ADC FIFO unit 23 are both used to buffer data;
[0054] The DAC Digital unit 12 is used to process the digital part of the digital to analog converter (DAC). For example, it interpolates the DAC digital part to 128 times and filters it to obtain data at an oversampling rate. Then, it performs sigma-delta modulation and finally transforms the low-frequency, 24-bit high-bit PCM data fs into high-sampling-rate, low-bit data, so that the DAC Analog unit 13 can easily convert it into an analog signal.
[0055] The DAC Analog unit 13 is the analog section of the DAC, used to convert the digital signal output by the DAC Analog unit 13 into an analog signal;
[0056] The ADC Analog unit 21 is the analog part of the Analog to Digital Converter (ADC). The ADC Analog unit 21 operates at an oversampling rate, such as 256 fs (12.288 MHz). After the analog signal passes through the ADC Analog unit 21, it obtains a small number of bits of data (1 bit in extreme cases). Then, it is processed by the digital part of the ADC Digital unit 22, which is a decimation filter. For example, it downsamples the 12.288 MHz sampling rate data by 256 times to 48k, and expands the small number of bits to multiple bits, such as 24 / 32 bits.
[0057] Where fs represents the sampling rate, for example, it can be 44.1k / 48k. 1 / fs means the delay of one sampling point. For example, the delay of one sampling point at a sampling rate of 48k is (1 / 48k) seconds, which is 20.833us. Therefore, n*1 / fs represents the delay of n integer sampling points.
[0058] Similarly, 256fs in 1 / 256fs refers to 256 times the sampling rate. If fs is 48kHz, then 256fs is 12.288MHz. For example, the audio ADC-DAC architecture uses a sigma-delta architecture, and the circuit needs to operate at an oversampling rate. Therefore, the delay of one sampling point in this part of the circuit is 1 / 256fs.
[0059] When an electrical signal is converted into an audio signal by a DAC and a speaker, and then the audio signal is picked up by a microphone (MIC) and an ADC after propagating through the air, the delay over this distance also needs to be compensated. Since the speed of sound in air is 340 m / s, assuming a reflection propagation path of 1 m, the delay is 29411 μs. The delay of one sampling point, i.e., 1 / fs, is 20.833 μs. Compensating for 1411 points (i.e., 29411 divided by 20.833 and rounded down), the delay becomes 20.833 * 1411 = 29395.3 μs, which is 15 μs different from the actual delay of 29411 μs. This 15 μs difference requires 1 / 256 fs of sampling points to compensate for, thus meeting the signal delay accuracy.
[0060] In some embodiments, see Figure 2 The reference signal extraction module 03 includes:
[0061] The delay processing module 31 is used to perform delay processing on the input audio digital signal.
[0062] In some embodiments, see Figure 2 The reference signal extraction module 03 further includes:
[0063] Decimation filter 32 is used to downsample the input audio digital signal.
[0064] In some embodiments, see Figure 2 The reference signal extraction module 03 further includes:
[0065] The volume adjustment module 33 is used to adjust the volume of the input audio digital signal.
[0066] It should be noted that the volume adjustment module 33 is not a necessary module, and its function can also be implemented by the DSP or CPU.
[0067] Among them, the delay processing module 31 is a simple register-based module with delay function;
[0068] Decimation filter 32 may include a series of decimation filters to reduce the sampling rate. This is because a higher sampling rate results in a larger amount of data, requiring more resources to run, thus necessitating downsampling.
[0069] The signal output by the volume adjustment module 33 is the extracted reference signal; this reference signal is input to the uplink processor 05 for echo cancellation.
[0070] In some embodiments, the decimation filter includes a series of multi-stage decimation filters, wherein different stages of the decimation filters employ preset different downsampling factors to downsample the input audio digital signal.
[0071] In some embodiments, the delay processing module includes a series of multi-stage delay processing modules, wherein different stages of the delay processing modules are connected in series between different stages of the decimation filter.
[0072] The signal output by the DAC Digital Unit 12 is a digital signal at an oversampling rate (e.g., 1.536M, 3.072M, 6.144M, 12.288M, etc.). After delaying this signal, it is sent to the decimation filter for downsampling to the normal sampling rate fs (e.g., 8k, 12k, 24k, 32k, 48k, 44.1k, 96k, 88.2k). Finally, the volume is adjusted to obtain the required reference signal.
[0073] However, since the signal output by the DAC Digital Unit 12 is at an oversampling rate (taking 256 fs as an example), if the delay processing is performed directly at this sampling rate, it will result in too many delay units required. Specifically, at a 256x oversampling rate, a delay of 1 fs sampling point requires 256 delay units, a delay of 1.5 fs sampling points requires 384 delay units, and so on. Therefore, in order to save chip area, a structure of multi-stage decimation filters and multi-stage delay processing modules (each stage of delay processing module can be configured with multiple delay units as needed) can be adopted in series.
[0074] For example, see Figure 3 In some embodiments, the multi-stage decimation filter includes: a first-stage decimation filter 42, a second-stage decimation filter 44, and a third-stage decimation filter 46; wherein, for example, the first-stage decimation filter 42 may be a CIC (Cascaded Integrator-Comb); the second-stage decimation filter 44 and the third-stage decimation filter 46 may both be FIR (Finite Impulse Response, also known as a non-recursive filter).
[0075] The multi-level delay processing module includes: a first-level delay processing module 41, a second-level delay processing module 43, a third-level delay processing module 45, and a fourth-level delay processing module 47.
[0076] Specifically, the input terminal of the first-stage delay processing module 41 is connected to the downlink signal output module 02, and the output terminal is connected to the input terminal of the first-stage decimation filter 42; the output terminal of the first-stage decimation filter 42 is connected to the input terminal of the second-stage delay processing module 43; the output terminal of the second-stage delay processing module 43 is connected to the input terminal of the second-stage decimation filter 44; the output terminal of the second-stage decimation filter 44 is connected to the input terminal of the third-stage delay processing module 45; the output terminal of the third-stage delay processing module 45 is connected to the input terminal of the third-stage decimation filter 46; and the output terminal of the third-stage decimation filter 46 is connected to the input terminal of the fourth-stage delay processing module 47.
[0077] In some embodiments, the output of the fourth-level delay processing module 47 is connected to the input of the volume adjustment module 33. That is, when the volume adjustment module 33 is provided, the output of the fourth-level delay processing module 47 is connected to the input of the volume adjustment module 33, and the volume is adjusted through the volume adjustment module 33. If the volume adjustment module 33 is not provided, the volume can also be adjusted directly through the uplink processor 05.
[0078] The number of stages in the delay processing module (each stage can include multiple delay units) can be configured according to actual needs. The number of delay units included in each stage of the delay processing module can also be selected between 0 and (N-1) based on actual needs, where N is the decimation factor (i.e., the factor by which the sampling rate is reduced) of the decimation filter connected to the output of that stage of the delay processing module. The final stage of the delay processing module (e.g., Figure 3 The fourth-stage delay processing module 47 shown is a delay processing module under the normal sampling rate fs. The output of the last-stage delay processing module is no longer connected to the decimation filter and can be designed as needed. For example, in actual scenarios, the maximum compensation for the echo signal is 5 fs sampling points, so the delay unit in the last-stage delay processing module can be set to 5 (one delay unit is needed to compensate for 1 fs sampling point). Further examples are given below.
[0079] Taking a sampling rate of fs = 48kHz as an example, the DAC oversampling rate is 256fs (12.288MHz). If all delay units are located at 12.288MHz, then 256 delay units are needed to represent the delay of one fs sampling point. To downsample the DAC's 256fs oversampling rate audio data to a usable normal sampling rate of fs, a decimation filter (or simply filter) is required. Considering cost and performance, a multi-stage cascaded decimation filter can be used. For example, to reduce the audio signal sampling rate by 256 times, see [link to relevant documentation]. Figure 3 Therefore, the sampling rate can be reduced by a factor of 32 (from 256fs to 8fs) using a first-stage decimation filter 42, then reduced by a factor of 4 (from 8fs to 2fs) using a second-stage decimation filter 44, and finally reduced by a factor of 2 (from 2fs to fs) using a third-stage decimation filter 46. It is evident that the data sampling rate is different for each stage of the decimation filter. See [link to relevant documentation] Figure 3 The first-stage delay processing module 41 has a delay precision of 1 / 256 fs. After being decimated by the first-stage decimation filter 42, the sampling rate becomes 8 fs, and the precision becomes 1 / 8 fs. This means that every 32 delay values accumulated by the delay unit of the first-stage delay processing module 41 are carried over to become a delay value of the second-stage delay processing module 43. Therefore, the first-stage delay processing module 41 can be set with a maximum of 31 delay units (i.e., 32-1=31, where 32 is the value of N mentioned above). The same applies to all other delay processing modules except the last stage (i.e., the fourth-stage delay processing module 47). The maximum number of delay units set is equal to the decimation factor N of the decimation filter connected to its output terminal minus 1.
[0080] If downsampling is accomplished directly with a single-stage decimation filter, then 256-1=255 delay units need to be designed.
[0081] For example, if the echo algorithm requires a current frequency (fs) of 8kHz, then reducing the frequency from 12.288MHz to 8kHz is a factor of 1536 (i.e., 1536 = 32 * 8 * 3 * 2). Therefore, 1536 - 1 = 1535 delay units need to be designed. Each delay unit is a register, so it's clear that this requires a large chip area, leading to higher costs.
[0082] The embodiments of this application utilize Figure 3 The structure shown, which consists of a multi-stage decimation filter and a multi-stage delay processing module (each stage of the delay processing module can be configured with multiple delay units as needed), only requires 31 + 3 + 1 = 35 delay units (a significant reduction from the 255 delay units mentioned above).
[0083] Similarly, for 8kHz, this embodiment can set a four-stage decimation filter with the following decimation factors: 32x → 8x → 3x → 2x, which requires only 31 + 7 + 2 + 1 = 41 delay units (which is a significant reduction compared to the 1535 delay units mentioned above).
[0084] Therefore, it can be seen that the embodiments of this application utilize a structure of multi-stage decimation filters and multi-stage delay processing modules connected in series, which can greatly reduce the chip area occupied, thereby saving a lot of costs.
[0085] To facilitate the configuration of the delay parameters of the delay processing modules at each level (for example, specifically the number of delay units set in each delay processing module), a total delay value (i.e., the delay value that needs to be compensated for for echo) is input, and the required number of delay units for each delay processing module at each level can be automatically obtained. In some embodiments, the circuit further includes:
[0086] The delay parameter calculation module is used to determine the range of values for the delay parameters of each stage of the delay processing module based on the delay resolution of the multi-stage delay processing module and the delay value that needs to be compensated for for the echo.
[0087] For example, see Figure 4 Assuming that the delay parameter calculation module includes four calculation units for the above four-level delay processing module, namely the first calculation unit, the second calculation unit, the third calculation unit, and the fourth calculation unit.
[0088] Each computing unit includes:
[0089] Two input terminals, namely the first input terminal IN1 and the second input terminal IN2;
[0090] There are two output terminals, namely the first output terminal OUT1 and the second output terminal OUT2.
[0091] Let A represent the total delay value; let A1, A2, A3, and A4 represent the maximum values of the delay parameters of the first-level delay processing module 41, the second-level delay processing module 43, the third-level delay processing module 45, and the fourth-level delay processing module 47, respectively; and let D1, D2, D3, and D4 represent the delay resolutions of the first-level delay processing module 41, the second-level delay processing module 43, the third-level delay processing module 45, and the fourth-level delay processing module 47, respectively.
[0092] The delay resolution of each delay processing module, i.e., the sampling rate of the audio digital signal output by the downlink signal output module (e.g., an oversampling rate of 256 fs), is divided by the sampling rate of the audio signal output by that delay processing module. For example... Figure 5As shown, the delay resolutions of the first-level delay processing module 41 are D1 = 256fs / 256fs = 1, the second-level delay processing module 43 is D2 = 256fs / 8fs = 32, the third-level delay processing module 45 is D3 = 256fs / 2fs = 128, and the fourth-level delay processing module 47 is D4 = 256fs / fs = 256. That is, the delay resolutions of the delay processing modules are: D1 = 1, D2 = 2, D3 = 128, D4 = 256. It should be noted that the larger the delay resolution value, the larger the time granularity, indicating worse delay accuracy.
[0093] The above Figure 4 The operation of each calculation unit, such as division, involves dividing the value input to IN1 by the value input to IN2. The integer part of the quotient is output as the value of OUT1, and the remainder is output as the value of OUT2. In actual circuit design, the divisor can be continuously subtracted from the dividend until the dividend is less than the divisor; the remaining dividend is then the remainder. The specific setting can be adjusted according to actual needs.
[0094] It can be seen that, after Figure 4 After processing by each calculation unit, the maximum value of the delay parameter (i.e., the number of delay units) for each delay processing module can be obtained. Since the dividend of the last calculation unit (i.e., the fourth calculation unit), D1, is 1, this calculation unit can be omitted, and the value output by OUT2 of the third calculation unit can be directly used as the value of A1, i.e., the number of delay units in the first delay processing unit 41. Therefore, Figure 4 It can be simplified to Figure 6 The structure shown.
[0095] Therefore, see Figure 6 As shown, in some embodiments, the delay parameter calculation module includes: a first calculation unit 61, a second calculation unit 62, and a third calculation unit 63 connected in series; wherein,
[0096] The first calculation unit 61 is used to divide the delay value (e.g., A = 36139) input at the first input terminal IN1 for the echo compensation by the delay resolution (e.g., D4 = 256) of the fourth-level delay processing module 47 input at the second input terminal IN2, and take the integer part of the quotient as the maximum value of the delay parameter of the fourth-level delay processing module 47 (e.g., A4 = 141), and output it through the first output terminal OUT1; and output the remainder (e.g., 43) through the second output terminal OUT2 to the first input terminal IN1 of the second calculation unit.
[0097] The second calculation unit 62 is used to divide the number input at the first input terminal IN1 (e.g., 43) by the delay resolution of the third-level delay processing module 45 input at the second input terminal IN2 (e.g., D3 = 128), and take the integer part of the quotient as the maximum value of the delay parameter of the third-level delay processing module 45 (e.g., A3 = 0), and output it through the first output terminal OUT1; and output the remainder (e.g., 43) through the second output terminal OUT2 to the first input terminal IN1 of the third calculation unit.
[0098] The third calculation unit 63 is used to divide the number input at the first input terminal IN1 (e.g., 43) by the delay resolution of the second-level delay processing module 43 input at the second input terminal IN2 (e.g., D2 = 32), and take the integer part of the quotient as the maximum value of the delay parameter of the second-level delay processing module 43 (e.g., A2 = 1), and output it through the first output terminal OUT1; and take the remainder (e.g., 11) as the maximum value of the delay parameter of the first-level delay processing module 41 (e.g., A1 = 11), and output it through the second output terminal OUT2.
[0099] Specifically:
[0100] Given a sound speed of 340 m / s and assuming an echo distance of 1 m, after the user terminal's microphone picks up the downlink audio data played from the user terminal's speaker, the reflected echo needs 2.941 ms to reach the user terminal's microphone and be picked up as the input analog signal. In this case, the reference signal needs to compensate for a delay of 2.941 ms. Since the compensation process is performed at 256 fs (fs = 48 kHz), the minimum compensation unit, i.e., one delay unit, has a resolution of 1 / 256 fs. Therefore, equating 2.941 ms to an oversampling rate of 256 fs, we can obtain the compensation required:
[0101] 2.941ms / (1 / 256fs)=2.941ms / (1 / (256*48)ms)=36139 points@256fs sampling rate.
[0102] In other words, the delay value that the echo needs to compensate for at this time is A = 36139;
[0103] Input the delay value A = 36139. Figure 6The first input terminal IN1 of the first calculation unit 61 shows that the maximum number of delay units that need to be set in the fourth-level delay processing module 47 is 141 (i.e., the quotient of 36139 divided by 256 and rounded down). Since one delay point @48kfs in the fourth-level delay processing module 47 represents 256 12.288M fs, 141 @48kfs represent 36096 points @256fs sampling rate. The remaining 43 points @256fs sampling rate (i.e., 36139-36096=43) are then input into the first input terminal IN1 of the second calculation unit 62, and the maximum number of delay units that need to be set in the third-level delay processing module 45 is 0 (i.e., the quotient of 43 divided by 128 and rounded down, which is 0). Among them, @48kfs (frequency @sample(sampling frequency) indicates a sampling rate of 48kHz; @256fs indicates an oversampling rate of 256 times; @12.288M indicates a sampling rate of 12.288MHz.
[0104] Similarly, after calculation by the third calculation unit 63, the maximum number of delay units that need to be set in the second-level delay processing module 43 can be output as 1 (i.e., the quotient of 43 divided by 32 is rounded down to 1), and the maximum number of delay units that need to be set in the first-level delay processing module 41 is 11 (i.e., 43-32=11).
[0105] Therefore, the delay value A = 36139, and the number of delay units that need to be configured in each delay processing module is as follows:
[0106] The first-level delay processing module needs to be configured with 11 delay units;
[0107] The second-level delay processing module requires one delay unit to be configured;
[0108] The third-level delay processing module requires 0 delay units to be configured;
[0109] The fourth-level delay processing module requires 141 delay units.
[0110] For example, if the actual compensation delay value A is configured as 2.34375 fs sampling points (resolution is 0.00390625 fs, i.e. 1 / 256 fs), the equivalent configuration value under the oversampling rate is 2.34375 * 256 = 600, which means that 600 delay units need to be configured.
[0111] If the circuit structure provided in the embodiment of this application is adopted, the value of A and D4 = 256 are respectively input... Figure 6The first input terminal IN1 and the second input terminal IN2 of the first calculation unit 61 are calculated by the first calculation unit 61, and the value output by the first output terminal OUT1 is 2, and the value output by the second output terminal OUT2 is 88.
[0112] Then, the output values OUT2 = 88 and D3 = 128 of the first calculation unit 61 are respectively input into... Figure 6 The first input terminal IN1 and the second input terminal IN2 of the second calculation unit 62 are calculated by the second calculation unit 62, and the value output by the first output terminal OUT1 is 0, and the value output by the second output terminal OUT2 is 88.
[0113] Similarly, the output values OUT2 = 88 and D2 = 32 of the second calculation unit 62 are respectively input into... Figure 6 The first input terminal IN1 and the second input terminal IN2 of the third calculation unit 63 are processed by the third calculation unit 63 to obtain the value of the first output terminal OUT1 as 2 and the value of the second output terminal OUT2 as 24.
[0114] Finally, the number of delay units that need to be configured in each level of delay processing module is as follows:
[0115] The first-level delay processing module needs to be configured with 24 delay units;
[0116] The second-level delay processing module requires two delay units to be configured;
[0117] The third-level delay processing module requires 0 delay units to be configured;
[0118] The fourth-level delay processing module requires two delay units to be configured.
[0119] Therefore, it can be seen that the embodiments of this application are adopted. Figure 3 The cascaded structure of the multi-stage decimation filter and multi-stage delay processing module shown requires only 28 delay units to achieve the equivalent... Figure 2 The structure shown requires 600 delay units, which greatly saves chip area and reduces costs significantly.
[0120] This application provides a system-on-chip (SOC) including any of the audio data acquisition circuits provided in the above-described embodiments.
[0121] The electronic device provided in this application embodiment can be any type of user terminal device, such as a mobile phone, computer, smart TV, etc., and may include the system-on-a-chip provided in this application embodiment.
[0122] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. An audio data acquisition circuit, characterized in that, The circuit includes: a downlink processor, a downlink signal output module, a reference signal extraction module, an uplink signal extraction module, and an uplink processor; wherein, The downlink processor is used to decode the input downlink audio data and output it to the downlink signal output module. The downlink signal output module is used to perform digital-to-analog conversion processing on the downlink audio data decoded by the downlink processor and output an analog audio signal; and to output an analog audio signal to the reference signal extraction module. The reference signal extraction module is used to convert the audio digital signal into a reference signal and output it to the uplink processor; wherein, the reference signal is used by the uplink processor to eliminate echo in the uplink audio signal; The uplink signal extraction module is used to convert the input analog audio signal into digital signal and output the uplink digital audio signal to the uplink processor. The uplink processor is configured to perform echo cancellation on the uplink digital audio signal based on the reference signal, and then encode and output the echo-cancelled uplink audio signal.
2. The circuit according to claim 1, characterized in that, The reference signal extraction module includes: The delay processing module is used to perform delay processing on the input audio digital signal.
3. The circuit according to claim 2, characterized in that, The reference signal extraction module further includes: A decimation filter is used to downsample the input digital audio signal.
4. The circuit according to claim 3, characterized in that, The decimation filter includes a series of multi-stage decimation filters, wherein different stages of the decimation filters use different preset downsampling factors to downsample the input audio digital signal.
5. The circuit according to claim 4, characterized in that, The delay processing module includes a series of multi-stage delay processing modules, wherein different stages of the delay processing modules are connected in series between different stages of the decimation filter.
6. The circuit according to claim 5, characterized in that, The circuit also includes: The delay parameter calculation module is used to determine the range of values for the delay parameters of each stage of the delay processing module based on the delay resolution of the multi-stage delay processing module and the delay value that needs to be compensated for for the echo.
7. The circuit according to claim 6, characterized in that, The multi-stage decimation filter includes: a first-stage decimation filter, a second-stage decimation filter, and a third-stage decimation filter; The multi-level delay processing module includes: a first-level delay processing module, a second-level delay processing module, a third-level delay processing module, and a fourth-level delay processing module; The input terminal of the first-stage delay processing module is connected to the downlink signal output module, and the output terminal is connected to the input terminal of the first-stage decimation filter; the output terminal of the first-stage decimation filter is connected to the input terminal of the second-stage delay processing module; the output terminal of the second-stage delay processing module is connected to the input terminal of the second-stage decimation filter; the output terminal of the second-stage decimation filter is connected to the input terminal of the third-stage delay processing module; the output terminal of the third-stage delay processing module is connected to the input terminal of the third-stage decimation filter; and the output terminal of the third-stage decimation filter is connected to the input terminal of the fourth-stage delay processing module.
8. The circuit according to claim 7, characterized in that, The delay parameter calculation module includes: a first calculation unit, a second calculation unit, and a third calculation unit connected in series; wherein, The first calculation unit is used to divide the delay value input from the first input terminal for the echo compensation by the delay resolution of the fourth-level delay processing module input from the second input terminal, take the integer part of the quotient as the maximum value of the delay parameter of the fourth-level delay processing module, and output it through the first output terminal; and output the remainder to the first input terminal of the second calculation unit through the second output terminal. The second calculation unit is used to divide the number input at the first input terminal by the delay resolution of the third-level delay processing module input at the second input terminal, take the integer part of the quotient as the maximum value of the delay parameter of the third-level delay processing module, and output it through the first output terminal; and output the remainder through the second output terminal to the first input terminal of the third calculation unit. The third calculation unit is used to divide the number input at the first input terminal by the delay resolution of the second-level delay processing module input at the second input terminal, and take the integer part of the quotient as the maximum value of the delay parameter of the second-level delay processing module and output it through the first output terminal; and take the remainder as the maximum value of the delay parameter of the first-level delay processing module and output it through the second output terminal.
9. The circuit according to claim 7, characterized in that, The reference signal extraction module further includes: The volume adjustment module has its input terminal connected to the output terminal of the fourth-level delay processing module. The volume adjustment module is used to adjust the volume of the input audio digital signal.
10. A system-on-a-chip, characterized in that, The chip includes the circuit described in any one of claims 1 to 9.