Printed circuit board

Abstract

A printed circuit board can include an insulating layer, a wiring layer embedded in the insulating layer, a solder resist layer on the insulating layer, a cavity penetrating a portion of the insulating layer and the solder resist layer, and a barrier pattern on the insulating layer, around an edge of the cavity, and covered by the solder resist layer.

Description

Technical Field

[0001] This disclosure relates to a printed circuit board. Background Technology

[0002] A printed circuit board is a board in which circuit patterns are formed on an insulating material using a conductive material such as copper. As electronic devices in the information technology (IT) field (such as mobile phones) become smaller, methods have been proposed to form cavities in printed circuit boards and to mount electronic components such as integrated circuits (ICs), active components, or passive components inside the cavities.

[0003] When forming cavities in a printed circuit board, undercuts or protrusions can be formed on the lower sidewalls of the cavity. Furthermore, when forming a solder resist layer on the surface of a printed circuit board with cavities, the material used to form the solder resist may migrate into the cavity, resulting in solder resist forming in unwanted areas, or the solder resist layer at the edges of the cavity may be thinner. Summary of the Invention

[0004] An embodiment provides a printed circuit board having a solder mask layer surrounding a cavity to prevent material from the solder mask layer from moving into the cavity.

[0005] However, the problems that the embodiments attempt to solve are not limited to those described above, and can be extended in various ways within the scope of the technical ideas contained in the embodiments.

[0006] A printed circuit board according to an embodiment may include: an insulating layer; a wiring layer embedded in the insulating layer; a solder mask layer located on the insulating layer; a cavity penetrating a portion of the insulating layer and the solder mask layer; and a blocking pattern located on the insulating layer, surrounding the edge of the cavity, and covered by the solder mask layer.

[0007] The printed circuit board may also include a pad layer located on an insulating layer. The solder mask layer may have openings that expose the pad layer. The thickness of the solder mask pattern may be different from the thickness of the pad layer.

[0008] The blocking pattern and the pad layer may be located on the same layer and comprise the same material.

[0009] The thickness of the blocking pattern can be greater than the thickness of the pad layer.

[0010] The thickness of the blocking pattern can be substantially the same as the thickness of the pad layer.

[0011] The insulating layer may include a first insulating layer and a second insulating layer located on the first insulating layer, the wiring layer may include a first wiring layer embedded in the first insulating layer and a second wiring layer embedded in the second insulating layer, and the cavity may penetrate the second insulating layer and expose the first insulating layer.

[0012] The printed circuit board may also include a dummy pattern located on the first insulating layer and surrounding the bottom surface of the cavity along the sidewalls of the cavity.

[0013] The first part of the dummy pattern may be located below the side wall of the cavity.

[0014] The second part of the dummy pattern can be exposed by the cavity.

[0015] The printed circuit board may further include a connector located within the cavity and on the first insulating layer. The dummy pattern and the connector may be located on the same layer and may include the same material as each other.

[0016] The thickness of the dummy pattern can be basically the same as the thickness of the connecting part.

[0017] The second insulating layer may include a photosensitive insulating layer.

[0018] According to an embodiment, a printed circuit board may be provided having a dummy pattern along the sidewalls of a cavity and around the bottom surface of the cavity to prevent undercuts or protrusions on the lower sidewalls of the cavity.

[0019] However, it is readily understood that the effects of this disclosure are not limited to those described above, and various extensions can be made without departing from the concept and scope of this disclosure. Attached Figure Description

[0020] Figure 1 This is a plan view of a printed circuit board according to an embodiment.

[0021] Figure 2 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0022] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 This is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to various embodiments.

[0023] Figure 10 This is a plan view of a printed circuit board according to another embodiment.

[0024] Figure 11 It is along Figure 10 The cross-sectional view taken from line I-I'.

[0025] Figure 12 This is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to another embodiment.

[0026] Figure 13 This is a cross-sectional view of a printed circuit board according to another embodiment.

[0027] Figure 14 This is a cross-sectional view of a printed circuit board according to another embodiment. Detailed Implementation

[0028] Various embodiments of this disclosure will be described in detail below to enable those skilled in the art to readily implement it with reference to the accompanying drawings. This disclosure may be implemented in a variety of different forms and is not limited to the embodiments described herein.

[0029] For clarity of description, parts not related to the description have been omitted in the drawings, and the same reference numerals are designated for the same or similar elements throughout the specification.

[0030] The accompanying drawings are provided only to facilitate understanding of the embodiments disclosed in this specification and should not be construed as limiting the technical concepts disclosed in this specification. It should be understood that this disclosure includes all variations, equivalents and alternatives without departing from the scope and concept of this disclosure.

[0031] Furthermore, for ease of illustration, the dimensions (e.g., thickness) of each element shown are arbitrarily illustrated in the accompanying drawings, therefore this disclosure is not limited to the drawings. In the drawings, thicknesses are enlarged to clearly show layers and regions. Additionally, in the drawings, the thicknesses of some layers and regions are exaggerated for ease of illustration.

[0032] Furthermore, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be other elements in between. In contrast, when an element is referred to as being "directly" on another element, there are no intermediate elements. Additionally, in the specification, "on" the target portion or "above" the target portion means located on or below the target portion, and does not necessarily mean located on the upper side of the target portion based on a direction opposite to the direction of gravity.

[0033] Furthermore, throughout the specification, unless explicitly stated otherwise, “comprising” and variations such as “including” or “containing” will be understood to imply the inclusion of other elements but not exclude any other elements.

[0034] Throughout the instruction manual, the term "in plan view" refers to the target portion viewed from above, while the term "in section view" refers to the target portion viewed from the side after a vertical section has been drawn.

[0035] Furthermore, throughout the specification, "connection" can refer not only to the direct connection of two or more elements, but also to the indirect connection, physical connection, and electrical connection of two or more elements through other elements, or to the fact that although two or more elements are referred to by different names according to their location or function, they are actually one entity.

[0036] In the following text, various embodiments and variations will be described in detail with reference to the accompanying drawings.

[0037] Reference Figure 1 and Figure 2 This describes a printed circuit board according to an embodiment. Figure 1 This is a plan view of a printed circuit board according to an embodiment. Figure 2 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0038] Reference Figure 1 The printed circuit board 100 according to the embodiment may include a plurality of cavities 101, 102, 103, 104 and 105.

[0039] Electronic components or semiconductor elements may be installed in multiple cavities 101, 102, 103, 104 and 105.

[0040] The printed circuit board 100 may include blocking patterns 11, 12, 13, 14 and 15 surrounding the edges of a plurality of cavities 101, 102, 103, 104 and 105.

[0041] The blocking patterns 11, 12, 13, 14, and 15 may be covered (e.g., completely covered) by the solder resist layer as described later, and the embodiments are not limited thereto. However, as an example, in a plan view, the solder resist layer may not be disposed inside the blocking patterns 11, 12, 13, 14, and 15. As an example, the solder resist layer may be disposed outside and above the blocking patterns 11, 12, 13, 14, and 15.

[0042] Reference Figure 2 and Figure 1 The printed circuit board 100 according to this embodiment may include: a plurality of insulating layers 21, 22, 23; a plurality of wiring layers 31, 32, 33, 34, 35 embedded in the plurality of insulating layers 21, 22, 23; a plurality of vias 41, 42, 43 connecting some of the wiring layers 31, 32, 33, 34, 35 to each other; a plurality of pad layers 51, 52; solder mask layers 61, 62; a cavity 101; and a blocking pattern 11 located above the plurality of insulating layers 21, 22, 23 and surrounding the edge of the cavity 101. Figure 2 Only shown Figure 1One of the multiple cavities 101, 102, 103, 104 and 105 is cavity 101, but many features of cavity 101 apply to all the other cavities 102, 103, 104 and 105.

[0043] The plurality of insulating layers 21, 22, and 23 may include a first insulating layer 21, a second insulating layer 22 located on the first insulating layer 21 along the height direction, and a third insulating layer 23 located below the first insulating layer 21 along the height direction. At least one of the first insulating layer 21, the second insulating layer 22, and the third insulating layer 23 may be an insulating layer in which a plurality of insulating layers are stacked.

[0044] The first insulating layer 21 may comprise a resin, and may comprise a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide (PI). The first insulating layer 21 may comprise a prepreg (PPG) sheet or a stacked film, but the embodiments are not limited thereto.

[0045] The second insulating layer 22 may include a photosensitive material, and the second insulating layer 22 may include a photosensitive dielectric (PID).

[0046] The third insulating layer 23 may include a photosensitive material, and the third insulating layer 23 may include a PID.

[0047] The plurality of wiring layers 31, 32, 33 may include a plurality of first wiring layers 31 embedded in the first insulating layer 21, a plurality of second wiring layers 32 embedded in the second insulating layer 22, and a plurality of third wiring layers 33 embedded in the third insulating layer 23.

[0048] The plurality of vias 41, 42, and 43 may include a plurality of first vias 41 located in the first insulating layer 21, a plurality of second vias 42 located in the second insulating layer 22, and a plurality of third vias 43 located in the third insulating layer 23.

[0049] At least some of the plurality of first wiring layers 31 can be connected to each other through a plurality of first vias 41, at least some of the plurality of second wiring layers 32 can be connected to each other through a plurality of second vias 42, and at least some of the plurality of third wiring layers 33 can be connected to each other through a plurality of third vias 43.

[0050] Multiple first pad layers 51 and multiple fourth wiring layers 34 may be located on the second insulating layer 22 and may be connected to the multiple second wiring layers 32 through some of the multiple second vias 42.

[0051] Multiple second pad layers 52 and multiple fifth wiring layers 35 may be located below the third insulating layer 23 and may be connected to the multiple third wiring layers 33 via some of the multiple third vias 43.

[0052] Multiple wiring layers 31, 32, 33, 34, 35, multiple vias 41, 42, 43, and pad layers 51, 52 may include copper (Cu). The multiple wiring layers 31, 32, 33, 34, 35, multiple vias 41, 42, 43, and pad layers 51, 52 may contain conductive materials such as gold (Au), silver (Ag), tungsten (W), aluminum (Al), nickel (Ni), or palladium (Pd). However, embodiments are not limited thereto, and the conductive materials may be varied.

[0053] The solder mask layers 61 and 62 may include a first solder mask layer 61 located on a plurality of first pad layers 51 and a plurality of fourth wiring layers 34, and a second solder mask layer 62 located below a plurality of second pad layers 52 and a plurality of fifth wiring layers 35.

[0054] The first solder mask layer 61 may have a first opening 601 that exposes a plurality of first pad layers 51, and the second solder mask layer 62 may have a second opening 602 that exposes a plurality of second pad layers 52.

[0055] Cavity 101 may be formed to penetrate the second insulating layer 22 and the first solder resist layer 61.

[0056] Multiple connectors 71 may be located within the cavity 101, and electronic components or semiconductor elements installed within the cavity 101 may be electrically connected to the printed circuit board 100 via the multiple connectors 71.

[0057] Multiple connection portions 71 may be located on the first insulating layer 21 and may be formed of the same layer as the lowest layer of the multiple second wiring layers 32 embedded in the second insulating layer 22, and may be formed of the same material as the multiple second wiring layers 32, but the embodiments are not limited thereto.

[0058] The connector 71 may include copper (Cu). The connector 71 may also include a conductive material such as gold (Au), silver (Ag), tungsten (W), aluminum (Al), nickel (Ni), or palladium (Pd). However, the embodiments are not limited thereto, and the conductive material may be changed.

[0059] The barrier pattern 11 may be located on the second insulating layer 22. The barrier pattern 11 may be covered by the first solder resist layer 61.

[0060] The blocking pattern 11 may have a planar shape surrounding the cavity 101. For example, in a planar view, the blocking pattern 11 may have a shape corresponding to the shape of the cavity 101. For example, the blocking pattern 11 may have a rectangular shape. As an example, the blocking pattern 11 may be a dummy pattern not used for electrical connection. The blocking pattern 11 prevents material used to form the first solder resist 61 from moving into the cavity 101 when the first solder resist 61 is formed.

[0061] The blocking pattern 11 is located on the same layer as the plurality of first pad layers 51 and the plurality of fourth wiring layers 34, and may include the same material as the plurality of first pad layers 51 and the plurality of fourth wiring layers 34. In this disclosure, multiple layers being located on the same layer means that the upper or lower surfaces of the multiple layers are coplanar.

[0062] When forming the solder resist layer, the material used to form the solder resist layer, including epoxy resin and a hardener, can be laminated onto the second insulating layer 22 and then hardened by heat treatment or the like to form the solder resist layer. At this time, the material layer used to form the solder resist layer laminated around the cavity may move into the cavity due to the cavity's height difference. As a result, the solder resist layer may not form around the cavity or may form with a thinner thickness than other parts. In this case, the area surrounding the cavity may not be protected by the solder resist, and corrosion or the like may occur around the cavity.

[0063] According to an embodiment, the printed circuit board 100 may include a barrier pattern 11 located on the second insulating layer 22 and having a planar shape surrounding the cavity 101. When the solder resist layer is formed, the material layer used to form the solder resist layer can be prevented from moving into the cavity, thereby allowing the solder resist layer to be formed with a uniform thickness even around the cavity. Therefore, corrosion and the like can be prevented around the cavity.

[0064] Reference Figure 2 The first thickness D1 of the blocking pattern 11 may be greater than the second thickness D2 of the plurality of first pad layers 51 and the plurality of fourth wiring layers 34.

[0065] When the first thickness D1 of the blocking pattern 11 is greater than the second thickness D2 of the plurality of first pad layers 51 and the plurality of fourth wiring layers 34, the material layer used to form the solder resist layer can be more effectively prevented from moving into the cavity when the solder resist layer is formed.

[0066] Reference Figures 3 to 9 as well as Figure 2 This section briefly describes a method for manufacturing a printed circuit board according to an embodiment. Figures 3 to 9 This is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to an embodiment.

[0067] Reference Figure 3 It can form a first insulating layer 21, a plurality of first wiring layers 31 embedded in the first insulating layer 21, a plurality of first vias 41 located in the first insulating layer 21 and connecting some of the plurality of first wiring layers 31, a plurality of second wiring layers 32 and a plurality of connecting portions 71 located above the first insulating layer 21, and a plurality of third wiring layers 33 located below the first insulating layer 21.

[0068] Reference Figure 4A first sub-insulating layer 221 covering multiple second wiring layers 32 can be laminated on the first insulating layer 21, and a second sub-insulating layer 231 covering multiple third wiring layers 33 can be laminated below the first insulating layer 21.

[0069] Reference Figure 5 A plurality of first holes 201 that expose at least a portion of a plurality of second wiring layers 32 and a plurality of auxiliary cavities 1011 that expose a plurality of connection portions 71 may be formed in the first sub-insulating layer 221, and a plurality of second holes 301 that expose at least a portion of a plurality of third wiring layers 33 may be formed in the second sub-insulating layer 231. The auxiliary cavities 1011 may be part of the cavities 101.

[0070] Reference Figure 6 and Figure 7 Multiple second vias 42 can be formed in multiple first holes 201 of the first sub-insulating layer 221, multiple second wiring layers 32 can be formed on the first sub-insulating layer 221, multiple third vias 43 can be formed in multiple second holes 301 of the second sub-insulating layer 231, and multiple third wiring layers 33 can be formed below the second sub-insulating layer 231.

[0071] By repeatedly stacking the first sub-insulating layer 221 and the second sub-insulating layer 231, and forming a plurality of second vias 42, a plurality of second wiring layers 32, a plurality of third vias 43 and a plurality of third wiring layers 33, as shown... Figure 7 As shown, a second insulating layer 22, a cavity 101 formed in the second insulating layer 22 and exposing a plurality of connection portions 71, a plurality of second wiring layers 32 embedded in the second insulating layer 22, a plurality of second vias 42 located in the second insulating layer 22 and connecting some of the plurality of second wiring layers 32, a plurality of fourth wiring layers 34 located on the second insulating layer 22, a preliminary blocking pattern 111, a plurality of first pad layers 51, a third insulating layer 23, a plurality of third wiring layers 33 embedded in the third insulating layer 23, a plurality of third vias 43 located within the insulating layer 23 and connecting some of the plurality of third wiring layers 33, a plurality of fifth wiring layers 35 located below the third insulating layer 23, and a plurality of second pad layers 52 may be formed.

[0072] Multiple fourth wiring layers 34, preliminary barrier pattern 111 and multiple first pad layers 51 may be formed together and located on the second insulating layer 22, and may include the same material.

[0073] The thickness of the initial blocking pattern 111 can be substantially equal to the thickness of the plurality of fourth wiring layers 34 and the plurality of first pad layers 51.

[0074] Reference Figure 8The barrier pattern 11 can be formed by forming an additional conductive layer on the initial barrier pattern 111 using methods such as plating. Thus, a barrier pattern 11 with a first thickness D1 that is larger than the second thickness D2 of the plurality of first pad layers 51 and the plurality of fourth wiring layers 34 can be formed.

[0075] Reference Figure 9 A solder resist layer SRM can be coated on the second insulating layer 22 in which the cavity 101 is formed. Figure 9 In the illustration, the solder resist layer SRM is shown to be coated onto the second insulating layer 22 using a scraper SQ, but the embodiment is not limited to this, and the solder resist layer SRM can be coated by spin coating or inkjet coating processes, etc.

[0076] When the solder resist layer SRM is applied to the second insulating layer 22, the barrier pattern 11 having a planar shape surrounding the cavity 101 can act like a dam, thereby preventing the solder resist layer SRM applied around the cavity 101 from moving into the cavity 101.

[0077] As described above, the first thickness D1 of the blocking pattern 11 can be greater than the second thickness D2 of the plurality of first pad layers 51 and the plurality of fourth wiring layers 34, and in this case, the solder resist layer SRM can be more effectively prevented from moving into the cavity 101.

[0078] Furthermore, since at least a portion of the barrier pattern 11 can be formed together with the plurality of first pad layers 51 and the plurality of fourth wiring layers 34 and formed through an additional plating process, the manufacturing process can be prevented from becoming complicated when forming the barrier pattern 11.

[0079] Reference Figure 10 and Figure 11 The following describes a printed circuit board 200 according to another embodiment. Figure 10 This is a plan view of a printed circuit board according to another embodiment. Figure 11 It is along Figure 10 The cross-sectional view taken from line I-I'.

[0080] Reference Figure 10 and Figure 11 The printed circuit board 200 according to this embodiment is similar to the printed circuit board 100 according to the previously described embodiment. Detailed descriptions of the same components are omitted.

[0081] Reference Figure 10 as well as Figure 1 The printed circuit board 200 according to this embodiment may include a plurality of cavities 101, 102, 103, 104 and 105 and blocking patterns 11, 12, 13, 14 and 15 surrounding the edges of the plurality of cavities 101, 102, 103, 104 and 105.

[0082] and Figure 1 and Figure 2 Unlike the printed circuit board 100 shown in the embodiment, the printed circuit board 200 according to this embodiment may also include dummy patterns 81, 82, 83, 84 and 85 disposed along the edges of a plurality of cavities 101, 102, 103, 104 and 105.

[0083] Reference Figure 10 and Figure 11 as well as Figure 1 and Figure 2 The printed circuit board 200 may include: a plurality of insulating layers 21, 22, 23; a plurality of wiring layers 31, 32, 33, 34, 35 embedded in the plurality of insulating layers 21, 22, 23; a plurality of vias 41, 42, 43 connecting some of the plurality of wiring layers 31, 32, 33, 34, 35 to each other; a plurality of pad layers 51, 52; solder mask layers 61, 62; a cavity 101; a blocking pattern 11 located above the plurality of insulating layers 21, 22, 23 and surrounding the edge of the cavity 101; and a dummy pattern 81 located between the first insulating layer 21 and the second insulating layer 22.

[0084] Figure 11 Only shown Figure 10 One of the multiple cavities 101, 102, 103, 104 and 105 is cavity 101, but many features of cavity 101 apply to all the other cavities 102, 103, 104 and 105.

[0085] Along the height direction DRH, the dummy pattern 81 may be located on the first insulating layer 21. A portion of the dummy pattern 81 may be covered by the second insulating layer 22, and the remainder of the dummy pattern 81 may be exposed through the cavity 101.

[0086] The dummy pattern 81 can be arranged along the side wall of cavity 101 around the bottom surface of cavity 101.

[0087] The dummy pattern 81 may be located on the same layer as the plurality of connecting parts 71 located in the cavity 101, and may contain the same material as the plurality of connecting parts 71.

[0088] The third thickness D3 of the dummy pattern 81 can be substantially equal to the fourth thickness D4 of the connecting portion 71 located within the cavity 101. However, the embodiments are not limited to this.

[0089] The dummy pattern 81 is used to define the area formed by the sidewall of cavity 101 when cavity 101 is formed, thereby preventing the second insulating layer 22 from being over-etched or having unetched and residual portions in the lower region of the sidewall of cavity 101 while cavity 101 is being formed.

[0090] like Figure 12As shown, when cavity 101 is formed by exposing the second insulating layer 22, if insufficient light reaches the edge of cavity 101 or if an unnecessarily strong amount of light reaches the edge of cavity 101, a protrusion or undercut may appear on the lower part of the sidewall of cavity 101.

[0091] According to this embodiment, the printed circuit board 200 may include a virtual pattern 81 located on the lower part of the sidewall of the cavity 101 to surround the bottom surface of the cavity 101 along the sidewall of the cavity 101, so that the lower region of the cavity 101 may be defined by the virtual pattern 81 before the cavity 101 is formed.

[0092] According to an embodiment, the printed circuit board 200 may include a dummy pattern 81 that can be exposed to the edge of the cavity 101 with sufficient light to prevent the insulating layer 22 from being left unremoved and partially retained inside the cavity 101. Even if unnecessary light reaches the edge of the cavity 101, unnecessary light can be applied to the dummy pattern 81 to prevent the insulating layer 22 from being over-etched.

[0093] Additionally, according to an embodiment, the printed circuit board 200 includes a barrier pattern 11 located on the second insulating layer 22 and having a planar shape surrounding the cavity 101. This prevents the material layer used to form the solder resist from moving into the cavity when the solder resist layer is formed, thereby allowing the solder resist layer to be formed with a uniform thickness even around the cavity. Therefore, corrosion and the like can be prevented from occurring around the cavity.

[0094] The first thickness D1 of the blocking pattern 11 may be greater than the second thickness D2 of the plurality of first pad layers 51 and the plurality of fourth wiring layers 34.

[0095] The first thickness D1 of the blocking pattern 11 is greater than the second thickness D2 of the plurality of first pad layers 51 and the plurality of fourth wiring layers 34, so that when the solder mask is formed, the material layer used to form the solder mask can be more effectively prevented from moving into the cavity.

[0096] Furthermore, since at least a portion of the barrier pattern 11 can be formed simultaneously with a plurality of first pad layers 51 and a plurality of fourth wiring layers 34, and is formed by an additional plating process, the manufacturing process can be prevented from becoming complicated when forming the barrier pattern 11.

[0097] Many features of the printed circuit board 100 according to the above embodiments are applicable to the printed circuit board 200 according to this embodiment.

[0098] Reference Figure 13 The following describes a printed circuit board 300 according to another embodiment. Figure 13 This is a cross-sectional view of a printed circuit board according to another embodiment.

[0099] Reference Figure 13The printed circuit board 300 according to this embodiment is similar to the printed circuit board 100 according to the above embodiment. Detailed descriptions of the same components are omitted.

[0100] Reference Figure 13 The printed circuit board 300 according to this embodiment may include: a plurality of insulating layers 21, 22, 23; a plurality of wiring layers 31, 32, 33, 34, 35 embedded in the plurality of insulating layers 21, 22, 23; a plurality of vias 41, 42, 43 connecting some of the plurality of wiring layers 31, 32, 33, 34, 35 to each other; a plurality of pad layers 51, 52; solder mask layers 61, 62; a cavity 101; and a blocking pattern 11 located above the plurality of insulating layers 21, 22, 23 and surrounding the edge of the cavity 101.

[0101] The blocking pattern 11 may be located on the second insulating layer 22 in which the cavity 101 is formed, and the blocking pattern 11 may be covered by the first solder resist layer 61.

[0102] The barrier pattern 11 may have a planar shape surrounding the cavity 101. When the first solder mask 61 is formed, the barrier pattern 11 can prevent the material used to form the first solder mask 61 from moving into the cavity 101.

[0103] Multiple first pad layers 51 and multiple fourth wiring layers 34 and the blocking pattern 11 may be located on the same layer and may include the same material.

[0104] Unlike the printed circuit board 100 according to the previously described embodiment, in this embodiment, the first thickness D1 of the blocking pattern 11 may be substantially equal to the second thickness D2 of the plurality of first pad layers 51 and the plurality of fourth wiring layers 34, but the embodiment is not limited thereto.

[0105] Since the barrier pattern 11 can be formed simultaneously with multiple first pad layers 51 and multiple fourth wiring layers 34, it is possible to prevent the manufacturing process from becoming complicated, the manufacturing time from increasing and / or the manufacturing cost from increasing when forming the barrier pattern 11.

[0106] Many features of the printed circuit boards 100 and 200 according to the above embodiments are applicable to the printed circuit board 300 according to this embodiment.

[0107] Reference Figure 14 This describes a printed circuit board 400 according to another embodiment. Figure 14 This is a cross-sectional view of a printed circuit board according to another embodiment.

[0108] Reference Figure 14 The printed circuit board 400 according to this embodiment is similar to the printed circuit board 200 according to the previously described embodiment. Detailed descriptions of the same components are omitted.

[0109] Reference Figure 14 The printed circuit board 400 may include: a plurality of insulating layers 21, 22, 23; a plurality of wiring layers 31, 32, 33, 34, 35 embedded in the plurality of insulating layers 21, 22, 23; a plurality of vias 41, 42, 43 connecting some of the plurality of wiring layers 31, 32, 33, 34, 35 to each other; a plurality of pad layers 51, 52; solder mask layers 61, 62; a cavity 101; a blocking pattern 11 located above the plurality of insulating layers 21, 22, 23 and surrounding the edge of the cavity 101; and a dummy pattern 81 located above the first insulating layer 21 and below the sidewall of the cavity 101.

[0110] The blocking pattern 11 may be located on the second insulating layer 22 in which the cavity 101 is formed, and the blocking pattern 11 may be covered by the first solder resist layer 61.

[0111] The barrier pattern 11 may have a planar shape surrounding the cavity 101. When the first solder mask 61 is formed, the barrier pattern 11 can prevent the material used to form the first solder mask 61 from moving into the cavity 101.

[0112] Multiple first pad layers 51 and multiple fourth wiring layers 34, as well as a barrier pattern 11, may be located on the same layer, and the barrier pattern 11 may comprise the same material as the multiple first pad layers 51 and multiple fourth wiring layers 34. The first thickness D1 of the barrier pattern 11 may be substantially equal to the second thickness D2 of the multiple first pad layers 51 and multiple fourth wiring layers 34, but the embodiments are not limited thereto.

[0113] Since the blocking pattern 11 can be formed simultaneously with multiple first pad layers 51 and multiple fourth wiring layers 34, it can prevent the manufacturing process from becoming complicated, the manufacturing time from increasing and / or the manufacturing cost from increasing.

[0114] Along the height direction DRH, the dummy pattern 81 may be located on the first insulating layer 21. A portion of the dummy pattern 81 may be covered by the second insulating layer 22, and the remainder of the dummy pattern 81 may be exposed through the cavity 101. That is, a portion of the dummy pattern 81 may be covered by the sidewall of the cavity 101.

[0115] The dummy pattern 81 may be located on the same layer as the plurality of connecting portions 71 located within the cavity 101, and the dummy pattern 81 may include the same material as the plurality of connecting portions 71.

[0116] The third thickness D3 of the dummy pattern 81 can be substantially equal to the fourth thickness D4 of the connecting portion 71 located within the cavity 101. However, the embodiments are not limited to this.

[0117] The dummy pattern 81 is used to define the area formed by the sidewall of cavity 101 when forming cavity 101, thereby preventing the second insulating layer 22 from being over-etched or having unetched portions remaining in the lower region of the sidewall of cavity 101.

[0118] Many features of the printed circuit boards 100, 200, and 300 according to the above embodiments are applicable to the printed circuit board 400 according to this embodiment.

[0119] Although preferred embodiments have been described above, the inventive concept is not limited thereto, and various modifications can be made within the scope of the claims, detailed description and drawings, which also fall within the scope of this disclosure.

Claims

1. A printed circuit board, comprising: Insulating layer; A wiring layer, embedded in the insulating layer; A solder resist layer is located on the insulating layer; The cavity penetrates a portion of the insulating layer and the solder resist layer; as well as A blocking pattern is located on the insulating layer, around the edge of the cavity, and is covered by the solder resist layer.

2. The printed circuit board according to claim 1, further comprising: The pad layer is located on the insulating layer. The solder mask layer has openings that expose the solder pad layer, and The thickness of the blocking pattern is different from the thickness of the pad layer.

3. The printed circuit board according to claim 2, in, The blocking pattern and the pad layer are located on the same layer and comprise the same material.

4. The printed circuit board according to claim 3, in, The thickness of the blocking pattern is greater than the thickness of the pad layer.

5. The printed circuit board according to claim 2, in, The insulating layer includes a first insulating layer and a second insulating layer located on the first insulating layer. The wiring layer includes a first wiring layer embedded in the first insulating layer and a second wiring layer embedded in the second insulating layer. The cavity penetrates the second insulating layer and exposes a portion of the first insulating layer.

6. The printed circuit board according to claim 5, further comprising: A dummy pattern is located on the first insulating layer and surrounds the bottom surface of the cavity along the sidewalls of the cavity.

7. The printed circuit board according to claim 6, in, The first part of the dummy pattern is located below the side wall of the cavity.

8. The printed circuit board according to claim 7, in, The second part of the dummy pattern is exposed through the cavity.

9. The printed circuit board according to claim 8, further comprising: The connecting portion is located within the cavity and on the first insulating layer. The dummy pattern and the connecting part are located on the same layer and contain the same material.

10. The printed circuit board according to claim 9, in, The thickness of the dummy pattern is the same as the thickness of the connecting part.

11. The printed circuit board according to claim 5, in, The second insulating layer includes a photosensitive insulating layer.

12. The printed circuit board according to claim 1, further comprising: The pad layer is located on the insulating layer. The solder mask layer has a first opening that exposes the solder pad layer, and The thickness of the blocking pattern is the same as the thickness of the pad layer.

13. The printed circuit board according to claim 12, in, The blocking pattern and the pad layer are located on the same layer and comprise the same material.

14. The printed circuit board according to claim 12, in, The insulating layer includes a first insulating layer and a second insulating layer located on the first insulating layer. The wiring layer includes a first wiring layer embedded in the first insulating layer and a second wiring layer embedded in the second insulating layer. The cavity penetrates the second insulating layer and exposes a portion of the first insulating layer.

15. The printed circuit board of claim 14, further comprising: A dummy pattern is located between the first insulating layer and the second insulating layer and surrounds the bottom surface of the cavity along the sidewall of the cavity.

16. The printed circuit board according to claim 15, in, The first part of the dummy pattern is located below the side wall of the cavity.

17. The printed circuit board according to claim 16, in, The second part of the dummy pattern is exposed through the cavity.

18. The printed circuit board of claim 17, further comprising: The connecting portion is located in the cavity and on the first insulating layer, and The dummy pattern and the connecting part are located on the same layer and are made of the same material.

19. The printed circuit board according to claim 18, in, The thickness of the dummy pattern is the same as the thickness of the connecting part.

20. The printed circuit board according to claim 14, in, The second insulating layer includes a photosensitive insulating layer.

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