Circuit board

Abstract

A circuit board according to an aspect of the present invention includes an insulating layer, a pad portion disposed on the insulating layer, and a bonding portion disposed on the pad portion, wherein a concave portion having a concave shape is disposed on an upper surface of the bonding portion, and the concave portion is disposed eccentrically with respect to a center of the bonding portion.

Description

Technical Field

[0001] The teachings of the present invention, in their exemplary and non-limiting embodiments, generally relate to a circuit board. Background Technology

[0002] Electronic devices containing electronic components include a variety of active and passive circuit elements that can be integrated onto semiconductor chips or dies. Furthermore, semiconductor chips or dies can be supplied in the form of electronic packages, which are mounted onto a substrate including circuit wiring, such as a printed circuit board (PCB).

[0003] Meanwhile, flip-chip interconnects, utilizing connection structures, are widely used in electronic packaging when mounting semiconductor chips onto printed circuit boards and electrically connecting them. For example, flip-chip interconnects using bumps facilitate the implementation of various forms of semiconductor chip stacking structures. Furthermore, flip-chip interconnects allow for the use of multiple interconnect structures to secure a large number of input / output (I / O) terminals.

[0004] One method for forming this type of connection structure is the solder on pad (SOP) method. The SOP method manufactures the connection structure by printing metal paste onto or mounting spherical solder onto connection pads exposed by a solder mask pattern on the surface of a printed circuit board, and then using the surface tension effect to form spherical solder joints through reflow soldering.

[0005] Consistent with the recent trend towards higher integration in semiconductor packaging, the number of terminals on semiconductor chips is also increasing, leading to more complex wiring. Therefore, achieving fine pitch of the bonding pads that connect to the semiconductor chips arranged on the circuit board is a key factor affecting circuit board quality.

[0006] To achieve fine pitch, one approach is to reduce the horizontal width of each bonding region. However, in this case, as the horizontal width of the bonding regions decreases, they become more susceptible to shear stress, leading to a compromise in the durability of the bonding regions themselves. Summary of the Invention

[0007] [Technical Issues]

[0008] The present invention aims to provide a circuit board that facilitates fine pitch by reducing the horizontal width of the bonding portion, while enhancing the durability of the bonding portion itself.

[0009] [Technical Solution]

[0010] A circuit board according to one embodiment may include: an insulating layer; pads disposed on the insulating layer; a protective layer disposed on the pads; and a bonding portion disposed on the pads, wherein the protective layer includes a through hole in a vertical direction, and wherein the bonding portion includes a through portion and a protrusion, the through portion being disposed in the through hole, the protrusion being disposed on the through portion and having a width greater than the width of the through portion, and the width of the through portion being in the range of more than 50% and less than 90% of the width of the protrusion.

[0011] A circuit board according to another embodiment may include: a multilayer insulating portion comprising a plurality of insulating layers stacked vertically; a pad portion disposed on the multilayer insulating portion; a protective layer disposed on the pad portion; a bonding portion disposed on the protective layer and connected to the pad portion through the protective layer; and a plurality of via electrodes disposed below the pad portion and through at least a portion of the multilayer insulating portion, wherein the bonding portion includes a through portion overlapping the protective layer in a horizontal direction and a protrusion disposed on the protective layer, wherein the horizontal width of the through portion is at least 50% to at most 90% of the horizontal width of the protrusion, and at least some of the plurality of via electrodes vertically overlap the pad portion, the protective layer and the protrusion.

[0012] [Beneficial Effects]

[0013] According to this embodiment, the surface treatment of the protective layer enables an increase in the bonding strength with the bonding portion. Therefore, compared with conventional methods, the horizontal width of the bonding portion can be reduced, thereby providing the advantage of facilitating the achievement of fine pitch.

[0014] Furthermore, by penetrating the insulating layer and vertically overlapping the bonding portion via the via, the shear strength of the bonding portion can be enhanced, thus presenting another advantage. Attached Figure Description

[0015] Figure 1 This is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0016] Figure 2 This is an enlarged view showing the arrangement structure of the bonding portions on the insulating layer according to an embodiment of the present invention.

[0017] Figure 3 and Figure 4 This is a photograph of the bonding interface of the protective layer of the bonding portion according to an embodiment of the present invention.

[0018] Figure 5 This is a diagram illustrating the bonding strength of the bonding portion on a circuit board according to an embodiment of the present invention.

[0019] Figure 6 It is an image of the bonding interface between the bonding portion and the protective layer in the comparative example.

[0020] Figure 7 This is a diagram used to illustrate the bonding strength of the bonding portion on the circuit board according to the comparative example.

[0021] Figure 8 This is a table showing the shapes of the bonding portions of various widths of the through portion according to embodiments of the present invention.

[0022] Figure 9 It is based on comparison Figure 8 A graph showing the shear stress at the bonded joint.

[0023] Figure 10 It is a table comparing the shear stress of the bonding portion based on the presence or absence of the protective layer, the horizontal width of the protrusion, the horizontal width of the through portion, the horizontal width of the second region, and the horizontal width of the pad portion.

[0024] Figure 11 yes Figure 10 Photographs showing the fracture test results of the bonded sections D and E.

[0025] Figure 12 This is a diagram illustrating the arrangement of the bonding portion and protrusions according to an embodiment of the present invention.

[0026] Figures 13 to 17 The diagram illustrates various variations of the arrangement of the bonding portion and protrusions according to embodiments of the present invention.

[0027] Figure 18 This is a diagram showing the fracture surface of the bonded portion based on the number of protrusions that overlap perpendicularly with the through portion.

[0028] Figure 19 This is a diagram illustrating the shear strength of the bonding portion achieved by protrusions according to an embodiment of the present invention.

[0029] Figure 20 It is a graph showing the shear stress based on the number of protrusions that overlap perpendicularly with the through section.

[0030] Figure 21 This is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. Detailed Implementation

[0031] In the following explanation, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0032] However, the technical concept of the present invention is not limited to the described embodiments, but can be implemented in various different forms, and one or more components between embodiments can be selectively combined or replaced within the scope of the technical concept of the present invention.

[0033] Furthermore, unless explicitly defined and described and generally understood by those skilled in the art, the terms (including technical and scientific terms) used in the embodiments of this invention may be interpreted as having the meaning that would be understood by those skilled in the art. Commonly used terms (e.g., terms defined in dictionaries) may be interpreted in the context of the relevant art.

[0034] Furthermore, the terminology used in the embodiments of the present invention is intended to explain the embodiments and is not intended to limit the invention. In this specification, unless otherwise stated in the text, the singular form may include the plural form, and when described as “A and (and / or) B, C; at least one (or more than one) of A, B, and C”, it may include one or more of all combinations of A, B, and C.

[0035] Furthermore, terms such as 1, 2, A, B, (a), and (b) may be used to describe components of embodiments of the present invention. Such terms are intended only to distinguish components from other components and are not limited by the nature, order, or sequence of the components.

[0036] Furthermore, if any component is described as “connected,” “joined,” or “attached” to another component, then that component may be directly connected, joined, or attached to that other component, as well as “connected,” “joined,” or “attached” to another component located between that component and that other component.

[0037] Furthermore, when stating that each component is formed or arranged "above or below," "above or below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or arranged between these two components. Additionally, when expressed as "above" or "below," it can include both the downward and upward directions based on a component.

[0038] Furthermore, the statement "structure A is arranged between structure B and structure C" must also be understood to include the meaning that structure A is arranged such that at least a portion of it overlaps with structure B and structure C in the horizontal and / or vertical directions.

[0039] The description of directions includes both horizontal and vertical directions, with the horizontal direction comprising a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. This corresponds to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis) in a Cartesian coordinate system. Overlapping along horizontal directions must also include overlap along the first horizontal direction and / or overlap along the second horizontal direction.

[0040] Furthermore, the meaning of "construction A is exposed from construction B" should be understood as follows: it is exposed from construction B, not from the product that construction A claims to protect. In other words, when it is stated that construction A is exposed from construction B, it should be understood that construction A is not exposed from the product that construction C claims to protect, other than construction B.

[0041] Furthermore, when stating that “structure A “contacts” structure B, this can encompass not only direct “contact” between these structures themselves, but also “contact” via another structure located between them. Therefore, if the intention is to understand structure A only as being in “direct contact” with structure B, it should be stated as “direct contact”.

[0042] Furthermore, when stating that "construction A is 'covered' by construction B," this should be understood to mean that construction A is covered by construction B such that, taking into account the function and purpose being addressed, at least some parts of construction A are covered by construction B. Unless otherwise specifically stated, it should not be understood that the entire construction A is covered by construction B.

[0043] Figure 1 This is a cross-sectional view of a circuit board according to an embodiment of the present invention. Figure 2 This is an enlarged view showing the arrangement structure of the bonding portions on the insulating layer according to an embodiment of the present invention. Figure 3 and Figure 4 This is a photograph of the bonding interface of the protective layer of the bonding portion according to an embodiment of the present invention. Figure 5 This is a diagram illustrating the bonding strength of the bonding portion on a circuit board according to an embodiment of the present invention. Figure 6 It is an image of the bonding interface between the bonding portion and the protective layer of the comparative example, and Figure 7 This is a diagram used to explain the bonding strength of the bonding portion on the circuit board according to the comparative example.

[0044] refer to Figures 1 to 7 According to an embodiment of the present invention, the circuit board (10) may include a multilayer structure (100) and a protective layer (190).

[0045] The multilayer structure (100) may include multilayer insulation, multiple wiring portions (120), multiple via portions (130), and bonding portions (150).

[0046] The multilayer structure (100) may include a multilayer insulating portion. This multilayer insulating portion may include a plurality of insulating layers (110) stacked in a vertical direction. The plurality of insulating layers (110) may be stacked in a vertical direction. For example, the plurality of insulating layers may include a third insulating layer (113), a second insulating layer (112) disposed on the third insulating layer (113), and a first insulating layer (111) disposed on the second insulating layer (112). The number of insulating layers constituting the multilayer structure (100) is exemplary; the circuit board (10) may have a greater number of vertically stacked insulating layers.

[0047] The first to third insulating layers (111, 112, 113) can each be any insulating material, such as photocurable and / or thermosetting materials. Thermosetting insulating materials may include insulating materials in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto laminated film) manufactured by Ajinomoto Corporation, and prepregs (PPG) containing glass fibers within the resin. Furthermore, the aforementioned resins may, exemplarily, be epoxy resins, bismaleimide triazine resins (BT resins), phenolic resins, etc., and the inorganic and / or organic fillers may be provided by materials such as silica, plastics, etc. When the insulating resin is used as the core layer, it may include reinforcing materials provided by glass fibers or aramid fibers, etc. In cases where at least some of the insulating layers constituting the first to third insulating layers (111, 112, 113) are photocurable insulators, at least some of the insulating layers constituting the first to third insulating layers (111, 112, 113) may each be a PID (photographic imaging dielectric).

[0048] The circuit board (10) may include a protective layer (190). The protective layer (190) may include a first protective layer disposed on the surface of a first insulating layer (111) and a second protective layer disposed on the surface of a third insulating layer (113). When semiconductor devices are disposed on the surface of the circuit board (10) using a material such as solder, the protective layer (190) is able to prevent short circuits between solders due to the low wettability of the protective layer (190) with the solder. It also prevents external contaminants from penetrating the multilayer structure and reducing reliability. The protective layer (190) may utilize a photocurable insulating material. Therefore, the protective layer (190) is provided as a solder resist, rather than the aforementioned ABF, PPG, BT resin, or PID. However, this is not limited to this, and as mentioned above, it may be provided with various materials capable of preventing short circuits between solders due to its low wettability with the solder.

[0049] The first protective layer may include a hole (192) to expose wiring portions (121) arranged vertically on the first insulating layer (111). The second protective layer may include a hole to expose wiring portions (124) arranged vertically on the surface of the third insulating layer (113) of the circuit board (10).

[0050] The circuit board (10) may include a multilayer wiring structure for transmitting electrical signals and / or power to electronic devices such as semiconductor chips. The multilayer wiring structure may include a plurality of wiring portions (120), a plurality of via portions (130), and bonding portions (150).

[0051] The plurality of wiring portions (120) may each be arranged on the surface of a plurality of insulating layers (110). Here, "arranged on the surface" may also mean that at least a portion of the plurality of wiring portions (120) is embedded within each of the plurality of insulating layers (110) or protective layers (190) and exposed to the outside from the surface. Furthermore, the surface of the plurality of insulating layers (110) includes a surface, another surface, and a side surface located between the one surface and the other surface. Here, one surface of the insulating layer (110) may be understood as the upper surface, and the other surface of the insulating layer (110) may be understood as the lower surface. The meaning of wiring portions (120) being arranged on the surface is that they are arranged on at least one of the one surface, the other surface, or the side surface of the plurality of insulating layers (110). The structure may also include wiring portions (120) arranged on both the one surface and the other surface of some of the plurality of insulating layers (110), while on other portions of the plurality of insulating layers (110), wiring portions (120) are arranged only on the one surface or the other surface.

[0052] The plurality of wiring portions (120) may include a first wiring portion (121) disposed on a first insulating layer (111), a second wiring portion (122) disposed on a second insulating layer (112), a third wiring portion (123) disposed on a third insulating layer (113), and a fourth wiring portion (124) disposed on the lower surface of the third insulating layer (113). Among the plurality of wiring portions (120), the second wiring portion (122) and the third wiring portion (123) may, for example, have an ETS (Embedded Trace Substrate) structure to achieve fine patterning. Specifically, the second wiring portion (122) and the third wiring portion (123) may be embedded within the second insulating layer (112) and the third insulating layer (113). Here, "embedded" means that at least a portion of the side surface of the wiring portion having the ETS structure is covered by the insulating layer (110). Concave portions (concave portions) with concave shapes for placing the second wiring portion (122) and the third wiring portion (123) can be respectively provided on the upper surface of the second insulating layer (112) and the upper surface of the third insulating layer (113).

[0053] Meanwhile, the first wiring portion (121) and the fourth wiring portion (124) arranged on the surfaces of the plurality of insulating layers (110) may also be referred to as the first pad portion and the second pad portion, respectively. In the following text, for the purpose of explanation, the first wiring portion (121) arranged on the insulating layer (110) shall be referred to as the pad portion (121).

[0054] The plurality of vias (130) may be metal material disposed within a via formed in each of the plurality of insulating layers (110) to connect a plurality of wiring portions (120) facing each other in the vertical direction. Here, the via vertically penetrates at least a portion of each of the plurality of insulating layers (110), and the via (130) may be disposed within the via.

[0055] The plurality of vias (130) may include a first via (131) penetrating at least a portion of a first insulating layer (111), a second via (132) penetrating at least a portion of a second insulating layer (112), and a third via (133) penetrating at least a portion of a third insulating layer (113). The first via (131) can electrically connect a first wiring portion (121) and a second wiring portion (122). The second via (132) can electrically connect the second wiring portion (122) and the third wiring portion (123). The third via (133) can electrically connect the third wiring portion (123) and the fourth wiring portion (124).

[0056] The first to third via portions (131, 132, 133) may each have a shape in which the horizontal width gradually increases in the direction from the first insulating layer (111) toward the third insulating layer (113). The vertical length of at least some of the plurality of via portions (130) may be different from the vertical length of the other via portions. For example, the vertical length of the first via portion (131) may be longer than the vertical length of the second via portion (132) or the third via portion (133).

[0057] The circuit board (10) may include a bonding portion (150). The bonding portion (150) may be disposed on top of the plurality of insulating layers (110). The bonding portion (150) may have a shape that protrudes above the circuit board (10), with at least a portion therethrough through the protective layer (190). The bonding portion (150) may be connected to a pad portion (121).

[0058] The bonding portion (150) may include a through portion (152) penetrating the protective layer (190) and a protrusion (156) protruding from the through portion (152) and disposed on the protective layer (190).

[0059] A through portion (152) may be arranged on the pad portion (121). The through portion (152) may be arranged to pass through a hole (192) in the protective layer (190). The through portion (152) may be arranged to overlap with the protective layer (190) in the horizontal direction. The horizontal width (D2) of the through portion (152) may be less than the horizontal width of the pad portion (121) or the horizontal width (D1) of the protrusion (156). The horizontal width (D2) of the through portion (152) may be equal to the horizontal width of the hole (192). The vertical length of the through portion (152) may be shorter than the vertical length of the protrusion (156).

[0060] A protrusion (156) may be disposed on the through portion (152). The upper surface of the protrusion (156) may be bonded to a semiconductor chip. The horizontal width (D1) of the protrusion (156) may be greater than the horizontal width (D2) of the through portion (152). The horizontal width (D1) of the protrusion (156) may be less than the horizontal width of the pad portion (121). The vertical length of the protrusion (156) may be longer than the vertical length of the through portion (152).

[0061] The protrusion (156) may include a first region (157) that vertically overlaps with the hole (192) and the through portion (152) of the protective layer (190), and a second region (158) that is offset so as not to vertically overlap with the hole (192) and the through portion (152). The second region (158) may be arranged on the outer side of the first region (157) in the horizontal direction.

[0062] The circuit board (10) may include a seed layer (160) for forming bonding portions (150). The bonding portions (150) may be formed via the seed layer (160) by a plating method. The size of the grains constituting the seed layer (160) may be larger than the size of the grains constituting the bonding portions (150).

[0063] The seed layer (160) may include a first portion (162) disposed on the pad portion (121), a second portion (164) disposed on the inner wall of the hole (192) of the protective layer (190), and a third portion (166) disposed on the protective layer (190). The first portion (162) may be arranged to overlap perpendicularly with the first region (157) of the through portion (152) and the protrusion (156). The third portion (166) may be arranged to overlap perpendicularly with the second region (158) of the protrusion (156). Therefore, by means of the electroplating method performed by the first to third portions (162, 164, 166), the bonding portion (150) can be realized on the pad portion (121).

[0064] like Figure 3 and Figure 4 As shown, the surface of the protective layer (190) that forms a bonding interface with the bonding portion (150) can be surface-treated. For example, the surface of the protective layer (190) to be bonded to the bonding portion (150) can be plasma-treated. Therefore, as Figure 4 As shown, a concave portion (193) with a concave shape is formed on the surface of the protective layer (190) to be bonded to the bonding portion (150), and a protrusion (159) for bonding with the concave portion (193) can be arranged on the surface of the bonding portion (150). Therefore, during the process of forming the bonding portion (150) on the surface of the protective layer (190), a bonding structure is formed via the concave portion (193) and the protrusion (159), thereby enabling robust bonding of the bonding portion (150) to the surface of the protective layer (190).

[0065] The concave portion (193) and the protrusion (159) are each provided as multiple, such as Figure 3 and Figure 4 As shown, and arranged along the bonding interface between the protective layer (190) and the bonding portion (150). The shape of each of the plurality of concave portions (193) and the shape of each of the plurality of protrusions (159) may be different from each other. Here, the difference in shape may mean that the horizontal width and vertical length of each of the plurality of concave portions (193) and / or each of the plurality of protrusions (159) are different.

[0066] Figure 5A fracture test of the bond portion (150) bonded to the surface of the plasma-treated protective layer (190) is shown. When a bond is firmly established between the protective layer (190) and the bond portion (150), if an external force is applied to separate the bond portion (150) from the circuit board (10), it can be observed that a portion of the protective layer (190) and / or a portion of the insulating layer (110) separates from the bond portion (150). In this case, as Figure 5 As shown on the left, the upper surface of the insulating layer (110) is exposed upward through the fractured surface of the bonding portion (150) on the circuit board (10).

[0067] Figure 6 An enlarged view of the bonding interface between the untreated protective layer (300) and the bonding portion (150) is shown. The protective layer (300) comprises resin and filler disposed within the resin. During the plating process used to form the bonding portion (150), the filler (310) may become exposed from the surface of the protective layer (300). Therefore, the plating area may encapsulate the filler (310) exposed from the surface of the protective layer (300), thereby potentially reducing the bonding affinity between the protective layer (300) and the bonding portion (150). Furthermore, irregular surfaces of the protective layer (300) forming the bonding interface may lead to plating defects, such as voids forming within the bonding portion (150).

[0068] Figure 7 A fracture test of the bond portion (150) bonded to the surface of the untreated protective layer (300) is shown. Due to the reduced bond strength of the bond portion (150) caused by the filler (310) exposed from the surface of the protective layer (300), when an external force is applied to separate the bond portion (150) from the pad portion (120), only the bond portion (150) separates from the pad portion (120). That is, as Figure 7 As shown on the left, the upper surface of the pad portion (120) becomes exposed upward through the fractured surface of the bonding portion (150) on the circuit board (10).

[0069] Therefore, in this embodiment, by surface treatment of the protective layer (190) bonded to the bonding portion (150), the bonding strength between the bonding portion (150) and the protective layer (190) can be enhanced due to the structure in which the filler is not exposed from the surface of the resin in the protective layer (190).

[0070] Figure 8 This is a table showing the shapes of the bonding portions according to various widths of the through portion, based on embodiments of the present invention. Figure 9 It is based on comparison Figure 8 A graph showing the shear stress at the bonded joint.

[0071] refer to Figure 8While fixing the horizontal width of the protrusion (156) at 230 μm, the bonding portions (150) with horizontal widths of the through portions (152) set to 120 μm, 150 μm, 180 μm and 210 μm are shown as 1, 2, 3 and 4 respectively.

[0072] refer to Figure 9 It can be observed that as the horizontal width of the through portion (152) increases, the shear stress in the bonding portion (150) increases. This is due to the increase in the bonding area with the protective layer (190) and the increase in the durability of the bonding portion (150) itself. However, if the horizontal width of the through portion (152) exceeds 90% of the horizontal width of the protrusion (156), the effect of the increased shear stress becomes negligible. Furthermore, increasing the width of the through portion (152) can lead to an increase in the width of the hole (192) within the protective layer (190), and can also increase the amount of plating required to form the bonding portion (150). In addition, achieving fine spacing between multiple bonding portions (150) on the circuit board (10) may prove difficult. Therefore, it is desirable that the horizontal width of the through portion (152) according to this embodiment is less than 90% of the horizontal width of the protrusion (157).

[0073] Furthermore, if the horizontal width of the through portion (152) is less than 50% of the horizontal width of the protrusion (156), it will have a shear stress of 300gf or less, which is the fracture strength of the bond portion (150). Therefore, according to this embodiment, it is desirable that the horizontal width of the through portion (152) is more than 50% and less than 90% of the horizontal width of the protrusion (156).

[0074] Figure 10 It is a table comparing the shear stress of the bonding portion based on the presence or absence of the protective layer, the horizontal width of the protrusion, the horizontal width of the through portion, the horizontal width of the second region, and the horizontal width of the pad portion. Figure 11 yes Figure 10 Photographs showing the fracture test results of the bonded sections D and E.

[0075] refer to Figure 10 It can be observed that, compared with bonding portions B, C, D, and E which have a protective layer (190), bonding portion A without a protective layer (190) exhibits lower shear stress. Specifically, when comparing bonding portions A and B with the same horizontal width of the protrusion (156), it can be confirmed that the shear stress of the bonding portion (150) is increased by more than 10% due to the presence of the protective layer (190). This effect stems from the enhanced bonding strength of the bonding portion (150) achieved on the circuit board (10) via the protective layer (190).

[0076] Furthermore, as mentioned earlier, when the horizontal width of the protrusion (156) is the same, the shear stress increases as the horizontal width of the through portion (152) increases. That is, as... Figure 11 As shown, for bond portions D and E, where the horizontal widths of the protrusions (156) are the same, fracture surfaces obtained from fracture tests show that, compared to bond portion D, bond portion E, with its relatively larger horizontal width of the through portion (152), exposes a relatively larger area of ​​the insulating layer (110) surface on the circuit board (10). Here, the fact that the insulating layer (110) has a larger exposed area indicates, as... Figure 5 The bonding strength between the bonding portion (150) and the protective layer (190) and between the bonding portion (150) and the pad portion (120) is relatively high.

[0077] Furthermore, when the horizontal width of the through portion (152) is the same, the larger the horizontal width of the protrusion (156), the greater the shear stress may become. For bond portions C and D with the same horizontal width of the through portion (152), such as Figure 10 As shown in the table, it can be confirmed that the bonding portion D, with its larger horizontal width, exhibits higher shear stress compared to the bonding portion C. However, when the horizontal width of the protrusion (156) is large, it is not conducive to achieving fine pitch between multiple bonding portions (150) on the circuit board (10). Therefore, it is desirable that the horizontal width of the protrusion (156) is less than or equal to the horizontal width of the pad portion (121).

[0078] Figure 12 This is a diagram illustrating the arrangement of the bonding portion and protrusions according to an embodiment of the present invention. Figures 13 to 17 These are diagrams illustrating various variations of the arrangement of the bonding portions and protrusions according to embodiments of the present invention. Figure 18 This is a diagram showing the fracture surface of the bonded portion according to the number of protrusions that vertically overlap with the through portion. Figure 19 This is a diagram illustrating the shear strength of the bonding portion achieved by protrusions according to an embodiment of the present invention, and Figure 20 It is a graph showing the shear stress based on the number of protrusions that vertically overlap with the through section.

[0079] refer to Figures 1 to 20 The circuit board (10) may include an insulating layer (110), pad portions (120) disposed on the insulating layer (110), a protective layer (190) disposed on the insulating layer (110), and bonding portions (150) disposed on the pad portions (120) and penetrating the protective layer (190). The pad portions (120) disposed on the insulating layer (110) may be electrically connected via wiring such as circuit lines to another pad portion disposed on the insulating layer (110) and horizontally spaced apart from the pad portions (120).

[0080] Furthermore, the pad portion (120) may include a protrusion (114) on its lower surface that vertically penetrates at least a portion of the multilayer insulating portion. The protrusion (114) may be electrically connected to the multilayer wiring portion embedded within the multilayer insulating portion, but it is not necessarily limited thereto; it may be provided without electrical connection to perform only an anchoring function to improve bond strength. In this case, the pad portion (120) may extend horizontally on the multilayer insulating portion and connect to the wiring portion disposed thereon.

[0081] like Figure 1 As shown, when the protrusion (114) is used as a via for electrical connection with the multilayer wiring portion, the protrusion (114) can electrically connect the pad portion (120) disposed on the second insulating layer (112) and the second wiring portion (122). Furthermore, the expansion direction of the protrusion (114) (where the horizontal width varies along the vertical direction) can be the same as the expansion direction of the plurality of via portions (130) disposed within the multilayer insulating portion. However, this is not limiting, and as... Figure 13 As shown, the expansion direction of the protrusion (114) may differ from the expansion direction of the plurality of via portions (130). For example, the first to third via portions (131, 132, 133) may have a shape in which the horizontal width gradually increases as it moves downward in the vertical direction. In this case, the protrusion (114) may have a shape in which the horizontal width gradually decreases as it extends downward in the vertical direction. This may mean that the hole forming process for producing the protrusion (114) is performed using a different process than the hole forming process used to produce the plurality of via portions (130). Therefore, the warpage characteristics of the circuit board (10) can be improved by the reverse diameter expansion structure between the protrusion (114) and the plurality of via portions (130).

[0082] The protrusions (114) are provided in multiple forms and can be arranged along the horizontal direction of the insulating layer (110). At least some of the multiple protrusions (114) can be arranged to overlap perpendicularly with the pad portion (120), the protective layer (190), the through portion (152), and the protrusion (156). At least one of the multiple protrusions (114) can be arranged to overlap perpendicularly with the pad portion (120), the protective layer (190), the through portion (152), and the protrusion (156). At least some of the multiple protrusions (114) can be arranged to overlap perpendicularly with the hole (192) in the protective layer (190). The protrusions (114) that overlap perpendicularly with the hole (192) can also be understood as being vertically offset (offset) relative to the protective layer (190).

[0083] like Figure 12As shown, when the plurality of protrusions (114) include a first protrusion (114a) and two (2) second protrusions (114b) horizontally spaced apart from the first protrusion (114a), the first protrusion (114a) can be arranged to overlap the through portion (152) vertically. The second protrusions (114b) can have a portion that overlaps vertically with the through portion (152) and a remaining portion that is vertically offset from the through portion (152). For example, the second protrusion (114b) can include a first region (114c) that overlaps vertically with the pad portion (120), the protective layer (190), and the protrusion (156), and a second region (114d) that overlaps vertically with the pad portion (120), the protrusion (156), and the through portion (152).

[0084] The horizontal width of each protrusion (114) can be smaller than the horizontal width of the through portion (152). Therefore, if the horizontal width of the protrusions (114) within the insulating layer (110) is greater than the horizontal width of the through portion (152), it becomes difficult to achieve a fine spacing between the multiple protrusions (114) within the insulating layer (110). Furthermore, as the horizontal width of the inner wall of the through hole (i.e., the area for placing the protrusions (114)) within the insulating layer (110) shortens, the inner wall of the through hole may collapse.

[0085] At the same time, such as Figure 12 As shown, the vertical thickness of the protrusion (114) can be the same as the vertical thickness of the insulating layer (110). However, this is not limiting; when the wiring portion is embedded in the lower surface of the insulating layer (110) in an ETS structure and the wiring portion and the pad portion (120) are vertically connected via the protrusion (114), the vertical thickness of the protrusion (114) can be less than the vertical thickness of the insulating layer (110).

[0086] In addition, such as Figures 14 to 17 As shown, the lower surface of the protrusion (114) can be spaced apart from the lower surface of the insulating layer (110) in the vertical direction. In this case, the vertical thickness (t1) of the insulating layer (110) can be greater than the vertical thickness (t2) of the protrusion (114). In this case, the pad portion (120) and the second wiring portion (122) are not electrically connected through the protrusion (114). For example, as Figure 16 As shown, the vertical thickness (t2) of the protrusion (114) can be at least half of the vertical thickness (t1) of the insulating layer (110). Therefore, the bonding strength between the bonding portion (150) and the insulating layer (110) and the protective layer (190) can be improved by the protrusion (114).

[0087] However, as Figure 17As shown, the vertical thickness (t2) of the protrusion (114) can be less than half the vertical thickness (t1) of the insulating layer (110). In this case, the amount of plating required to form the protrusion (114) is reduced, and the machining process of the protrusion (114) can be performed more easily.

[0088] Furthermore, since the vertical thickness (t2) of the protrusion (114) is formed to be shorter than the vertical thickness (t1) of the insulating layer (110), even in a structure where no electrical connection is established between the pad portion (120) and the second wiring portion (122) through the protrusion (114), the expansion direction (i.e., the shape in which the horizontal width of the protrusion (114) increases or decreases in the vertical direction) can be similar to that of the protrusion (114). Figure 14 The enlargement direction of the multiple vias (130) shown is the same, but it can also be similar to that shown in the example. Figure 15 The enlargement directions of the multiple vias (130) shown are opposite.

[0089] refer to Figure 19 When a protrusion (114) is present and the protrusion (114) vertically overlaps with the through portion (152), the vertical bonding structure between the through portion (152) and the pad portion (120) and between the pad portion (120) and the protrusion (114) increases the bonding strength of the bonding portion (150) on the circuit board (10), thereby potentially increasing the bonding strength of the bonding portion (150) on the circuit board (10). That is, compared with the insulating layer (110) made of insulating material, the bonding portion (150) forms a higher vertical bonding force with the pad portion (120) and the protrusion (114). Therefore, the horizontal shear strength of the bonding portion (150) on the circuit board (10) can be further improved. In summary, the shear strength of the bonding portion (150) itself can be increased by the protrusion (114) that vertically overlaps with the through portion (152).

[0090] Recently, with the trend towards higher performance and greater integration in semiconductor chips, the size of the bonding portion (150) connected to the semiconductor chip has also increased with the growth of chip size. Specifically, the vertical thickness of the bonding portion (150) tends to increase; according to an embodiment, the vertical thickness of the bonding portion (150) can be more than 120 μm and less than 200 μm. If the vertical thickness of the bonding portion (150) is less than 120 μm, it is insufficient to ensure the vertical distance between the semiconductor chip and the circuit board (10). This has disadvantages in terms of heat dissipation and the bonding process from the semiconductor chip to the bonding portion. If the vertical thickness of the bonding portion (150) exceeds 200 μm, it becomes susceptible to shear stress within the bonding portion (150) itself, thus posing a risk of breakage. In addition, the increased plating volume leads to higher manufacturing costs. Within the above range, advantages are achieved in ensuring sufficient distance from the semiconductor chip and enhancing the durability of the bonding portion (150) itself.

[0091] Furthermore, in this embodiment, the vertical thickness of the bonding portion (150) is formed to be greater than the vertical thickness of the insulating layer (110) in the placement area of ​​the protrusion (114). This facilitates the bonding process and heat dissipation of the semiconductor chip. However, the potential problem of reduced durability can be addressed by the aforementioned anchoring function of the protrusion (114).

[0092] refer to Figure 18 In the absence of protrusions (114) vertically overlapping the through portion (152), only the surface of the insulating layer (110) forms a fracture surface during the breakage test of the bonding portion (150). However, when protrusions (114) vertically overlapping the through portion (152) are present, it can be observed that holes corresponding to the number of protrusions (114) are formed on the upper surface of the insulating layer (110), i.e., the fracture surface of the bonding portion (150). This indicates that during the breakage process of the bonding portion (150), the protrusions (114) separate from the circuit board (10) together with the bonding portion (150).

[0093] In addition, refer to Figure 20 It can be observed that as the number of protrusions (114) that overlap vertically with the through portion (152) increases, the shear stress in the bonding portion (150) also increases. However, when the number of protrusions (114) that overlap vertically with the through portion (152) is four, it forms more than twice the shear strength compared to when there are no such protrusions. By arranging the multiple protrusions (114) connected to the single pad portion (120) to overlap vertically with the through portion (152), and considering the possibility of short circuits between the multiple protrusions (114) or collapse of the inner wall of the hole in the insulating layer (110) due to the reduction of the horizontal distance between the multiple protrusions (114), it is desirable that the number of protrusions (114) that overlap vertically with the through portion (152) is four or less.

[0094] According to the embodiment, the vertical support structure achieved via the protrusions (114) that overlap vertically with the through portion (152) enables the bonding portion (150) to be more securely bonded to the circuit board (10). Furthermore, as described above, it ensures shear stress to improve the reliability of the protrusions (156), and by including at least one of the aforementioned protrusions (114) (wherein the horizontal width of the through portion (152) is set to be more than 50% but not more than 90% of the horizontal width of the protrusion (156) to achieve fine pitch), the bonding portion and the multilayer insulation portion can be bonded more securely.

[0095] According to an embodiment, the protrusions (114) can be provided in multiple forms. When multiple protrusions are provided, at least one of the protrusions (114) may include a region that overlaps perpendicularly with the protrusion (156) and the protective layer (190). By positioning the protective layer (190) with a different coefficient of thermal expansion between the protrusion (156) and the protrusion (114), stress can be reduced and the bonding strength between the bonding portion (150) and the laminated insulation portion can be further enhanced.

[0096] Figure 21 This is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0097] refer to Figure 21 Multiple bonding regions (150) can be arranged on the surface of the circuit board (10). Multiple bonding sites (150) can accommodate semiconductor chips (1000, 2000). For example, a first semiconductor chip (1000) can be placed on some of the bonding sites (150), while a second semiconductor chip (2000) can be placed on the other bonding sites (150). The semiconductor chips (1000, 2000) have terminals, which can be electrically and physically bonded to the surface of the bonding regions (150) via connecting elements (180) such as solder balls or solder paste.

[0098] The foregoing description of the combination or combined operation of components constituting embodiments of the present invention does not imply that the invention must be limited to these embodiments. That is, within the scope of the purpose of the invention, all components may be optionally combined and operated in one or more ways. Furthermore, unless otherwise specifically stated, terms such as “comprising,” “including,” or “having” as described above imply that the component may be present and should therefore be interpreted as not excluding other components but potentially including additional components. Unless otherwise defined, all terms (including technical or scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Common terms (e.g., terms defined in dictionaries) should be interpreted according to their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0099] The above description is merely illustrative of the technical concept of the present invention. Those skilled in the art will understand that various modifications and variations can be made without departing from the essential features of the invention. Therefore, the embodiments disclosed herein are intended to illustrate the technical concept of the invention, not to limit it, and the scope of the technical concept of the invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the appended claims, and all technical concepts within the scope of these claims should be interpreted as falling within the scope of the present invention.

[0100] Furthermore, when a circuit board having the above-described features of the present invention is used in IT equipment or home appliances such as smartphones, server computers, or televisions, it can reliably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention performs semiconductor packaging functions, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, or electrical open circuits in terminals supplying power to the semiconductor chip. In addition, when responsible for signal transmission functions, it can solve noise problems. Therefore, a circuit board having the above-described features of the present invention enables IT equipment or home appliances to operate stably, thereby achieving functional integrity or technical interconnectivity between the entire product and the circuit board containing the present invention.

[0101] When a circuit board having the features of the above invention is used in transportation equipment such as vehicles, it can solve the problem of signal distortion transmitted to the transportation equipment, or safely protect the semiconductor chips controlling the transportation equipment from external sources. It can also solve problems such as leakage current, electrical short circuits between terminals, or electrical open circuits in terminals supplying power to the semiconductor chips, thereby further improving the stability of the transportation equipment. Therefore, the transportation equipment and the circuit board incorporating the present invention can achieve functional integration or technological synergy.

Claims

1. A circuit board, comprising: Insulating layer; A pad portion, wherein the pad portion is disposed on the insulating layer; A protective layer is disposed on the pad portion; as well as The bonding portion is disposed on the solder pad portion. The protective layer includes a hole extending vertically. The bonding portion includes a through portion and a protrusion. The through portion is disposed in the hole, and the protrusion is disposed on the through portion and has a width greater than the width of the through portion. The width of the through portion is in the range of more than 50% and less than 90% of the width of the protrusion.

2. The circuit board of claim 1, wherein, The surface of the protective layer is a region treated with plasma.

3. The circuit board according to claim 2, wherein, The protective layer includes a resin and a filler disposed within the resin, wherein the filler is not exposed on the surface of the resin.

4. The circuit board according to claim 1, wherein, A concave portion is arranged on the surface of the protective layer facing the bonding portion. Furthermore, a protrusion that engages with the concave portion is provided on the surface of the bonding portion facing the protective layer.

5. The circuit board according to claim 3, wherein, The concave portions and the protrusions are provided in a plurality of forms, and each of the plurality of concave portions and each of the plurality of protrusions has a different planar shape from the others.

6. The circuit board according to claim 1, wherein, The horizontal width of the protrusion is smaller than the horizontal width of the pad portion.

7. The circuit board according to claim 1, wherein, The pad portion includes a plurality of protrusions extending through at least a portion of the insulating layer from the lower surface of the pad portion, and at least one of the plurality of protrusions overlaps perpendicularly with the through portion.

8. The circuit board according to claim 7, wherein, The plurality of protrusions includes a first protrusion and a plurality of second protrusions horizontally spaced apart from the first protrusion. The first protrusion overlaps perpendicularly with the through portion, and the second protrusion overlaps at least partially perpendicularly with the through portion, while the remaining portion of the second protrusion is not perpendicularly aligned with the through portion.

9. The circuit board according to claim 7, wherein, The number of the plurality of protrusions that overlap vertically with the through portion is four or fewer.

10. The circuit board according to claim 8, wherein, The horizontal width of the first protrusion is smaller than the horizontal width of the through portion.

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