Substrate plate, circuit board and preparation method thereof, display module

Abstract

The present disclosure provides a substrate plate, a circuit board and a preparation method thereof, and a display module, and relates to the technical field of display. The substrate plate is used for a circuit board, and the substrate plate comprises a first conductive layer, a second conductive layer and an insulating substrate. The insulating substrate is stacked between the first conductive layer and the second conductive layer, and the thickness of the first conductive layer is greater than the thickness of the second conductive layer. This is conducive to the miniaturization of the circuit board.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a substrate, a circuit board, a method for preparing the same, and a display module. Background Technology

[0002] With the advent of the 5G and 6G era, consumer electronics circuit boards are rapidly developing towards high density, high transmission speed, flexibility, and miniaturization. As a result, flexible printed circuit boards (FPCs) have become the mainstream circuit boards for electronic products. With the increasing performance, thinness, miniaturization, folding, and rollability of electronic products, it is necessary to continuously reduce the area of ​​flexible printed circuit boards.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a circuit board and its manufacturing method, as well as a display module, which is beneficial for the miniaturization of the circuit board.

[0005] According to a first aspect of this disclosure, a substrate board is provided for a circuit board, the substrate board comprising a first conductive layer, a second conductive layer and an insulating substrate; The insulating substrate is stacked between the first conductive layer and the second conductive layer, and the thickness of the first conductive layer is greater than the thickness of the second conductive layer.

[0006] According to a second aspect of this disclosure, a circuit board is provided, comprising two first wiring boards stacked together and a first adhesive insulating layer located between the two first wiring boards; wherein the first wiring boards are made of the aforementioned substrate board.

[0007] In one embodiment of this disclosure, the first wiring board includes a first wiring layer, a second wiring layer, and an insulating substrate; The first wiring layer has a plurality of first wirings, the second wiring layer has a plurality of second wirings, the thickness of the first wiring layer is less than the thickness of the second wiring layer, and the insulating substrate is stacked between the first wiring layer and the second wiring layer. The first adhesive insulating layer is disposed between two adjacent first wiring layers.

[0008] In one embodiment of this disclosure, the first trace layer is formed by a masking etching process from the first conductive layer, and the second trace layer is formed by a modified semi-additive process from the second conductive layer.

[0009] In one embodiment of this disclosure, the second trace layer includes a second conductive layer and a first metal plating layer stacked on the insulating substrate on the side away from the first trace layer, wherein the thickness of the first trace layer is greater than the thickness of the second conductive layer; The second trace includes a plurality of first sub-traces located in the second conductive layer and a plurality of second sub-traces located in the first metal plating layer. The plurality of first sub-traces and the plurality of second sub-traces are arranged in a one-to-one correspondence. The orthographic projection of the first sub-traces on the first adhesive insulating layer and the orthographic projection of the corresponding second sub-traces on the first adhesive insulating layer at least partially overlap.

[0010] In one embodiment of this disclosure, the circuit board further includes at least one first stacking unit, the first stacking unit including a second adhesive insulating layer and a second wiring board stacked sequentially on the side of the first wiring board away from the first adhesive insulating layer; The structure of the second wiring board is the same as that of the first wiring board, and the second adhesive insulating layer is located between one of the first metal plating layers of the first wiring board and the first wiring layer of the second wiring board. Alternatively, the circuit board may further include at least one second stacking unit, the second stacking unit including a third adhesive insulating layer and a third wiring board stacked sequentially on the side of the first wiring board away from the first adhesive insulating layer; The third wiring board includes a third wiring layer and an insulating substrate. The third wiring layer includes a third conductive layer and a second metal plating layer stacked on the insulating substrate on the side away from the third adhesive insulating layer. The thickness of the first wiring layer is greater than the thickness of the third conductive layer. The third wiring layer is made from the third conductive layer by a modified semi-additive process.

[0011] According to a third aspect of this disclosure, a method for manufacturing a circuit board is provided, the method comprising: Two substrate boards are provided; each of the substrate boards includes a first conductive layer, a second conductive layer, and an insulating substrate; wherein the insulating substrate is stacked between the first conductive layer and the second conductive layer, and the thickness of the first conductive layer is greater than the thickness of the second conductive layer; A photoresist layer is disposed on the side of the second conductive layer away from the first conductive layer; A first wiring layer is formed on the first conductive layer by a masking etching process; Two substrate boards are laminated together by a first adhesive insulating layer; wherein the first adhesive insulating layer is located between the two first wiring layers; Remove the photoresist layer; A second trace layer is formed on the second conductive layer using a modified semi-additive process to form a first trace board; wherein the first trace board includes a first trace layer, a second trace layer, and an insulating substrate; the first trace layer has a plurality of first traces, the second trace layer has a plurality of second traces, and the thickness of the first trace layer is less than the thickness of the second trace layer.

[0012] In one embodiment of this disclosure, forming a second wiring layer on the second conductive layer using a modified semi-additive process includes: A first metal plating layer is formed on the side of the second conductive layer away from the first adhesive insulating layer using a modified semi-additive process; wherein, the second trace layer includes the second conductive layer and the first metal plating layer stacked on the side of the insulating substrate away from the first trace layer, the thickness of the first trace layer is greater than the thickness of the second conductive layer, and the first metal plating layer has a plurality of second sub-traces. Multiple first sub-traces are formed in the second conductive layer by an improved semi-additive process to form multiple second traces; wherein the second conductive layer has multiple first sub-traces, and the multiple first sub-traces and the multiple second sub-traces are arranged in a one-to-one correspondence, and the orthographic projection of the first sub-traces on the first adhesive insulating layer and the orthographic projection of the corresponding second sub-traces on the first adhesive insulating layer at least partially overlap.

[0013] In one embodiment of this disclosure, after forming the first wiring board, the fabrication method further includes: At least one first stacking unit is formed on the side of the first wiring board away from the first adhesive insulating layer; wherein, the first stacking unit includes a second adhesive insulating layer and a second wiring board stacked together; the structure of the second wiring board is the same as the structure of the first wiring board, and the second adhesive insulating layer is located between a first metal plating layer of the first wiring board and the first wiring layer of the second wiring board; Alternatively, at least one second stacking unit is formed on the side of the first wiring board away from the first adhesive insulating layer; wherein, the third wiring board includes a third wiring layer and an insulating substrate, the third wiring layer includes a third conductive layer and a second metal plating layer stacked on the insulating substrate on the side away from the third adhesive insulating layer, the thickness of the first wiring layer is greater than the thickness of the third conductive layer; the third wiring layer is made from the third conductive layer by a modified semi-additive process.

[0014] According to a fourth aspect of this disclosure, a display module is provided, including the circuit board described in any of the above embodiments.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] Figure 1 This is a schematic diagram of the film layer of a substrate in one embodiment of the present disclosure.

[0018] Figure 2 This is a schematic diagram of the film layers on a circuit board in one embodiment of this disclosure.

[0019] Figure 3 This is a schematic diagram of the film layers on a circuit board in one embodiment of this disclosure.

[0020] Figure 4 This is a schematic diagram of the film layers on a circuit board in one embodiment of this disclosure.

[0021] Figure 5 This is a schematic diagram of the film layers on a circuit board in one embodiment of this disclosure.

[0022] Figure 6 This is a schematic diagram of the film layers on a circuit board in one embodiment of this disclosure.

[0023] Figure 7 This is a schematic diagram of the film layers on a circuit board in one embodiment of this disclosure.

[0024] Figure 8 This is a schematic diagram of the film layers on a circuit board in one embodiment of this disclosure.

[0025] Figure 9 This is a schematic diagram of the fabrication of a circuit board in one embodiment of the present disclosure, intended to illustrate step S100.

[0026] Figure 10 This is a schematic diagram of the fabrication of a circuit board in one embodiment of the present disclosure, intended to illustrate steps S200 and S310.

[0027] Figure 11 This is a schematic diagram of the fabrication of a circuit board in one embodiment of the present disclosure, intended to illustrate step S400.

[0028] Figure 12 This is a schematic diagram of the fabrication of a circuit board in one embodiment of the present disclosure, intended to illustrate steps S500 and S611.

[0030] Figure 13 This is a schematic diagram of the fabrication of a circuit board in one embodiment of the present disclosure, intended to illustrate the final circuit board structure fabricated through step S600.

[0031] Figure 14 This is a schematic diagram of the fabrication of a circuit board in one embodiment of the present disclosure, intended to illustrate a masking etching process.

[0032] Figure 15 This is a schematic diagram of the fabrication of a circuit board in one embodiment of the present disclosure, intended to illustrate a modified semi-additive process. Detailed Implementation

[0033] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0034] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0035] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0036] In this paper, structural layer A is located on the side of structural layer B away from the substrate. This can be understood as structural layer A being formed on the side of structural layer B away from the substrate. When structural layer B is a patterned structure, some structures of structural layer A may also be located at the same physical height as structural layer B or below the physical height of structural layer B, wherein the substrate serves as the height reference.

[0037] In this article, the "thickness" of a film layer refers to its height in a direction perpendicular to the plane of the adhesive insulating layer. The "linewidth" of a trace refers to its width in a direction parallel to the plane of the adhesive insulating layer. The "line spacing" refers to the distance between two adjacent traces in the same film layer, which is parallel to the plane of the adhesive insulating layer.

[0038] This disclosure provides a substrate BML for use in circuit boards. See also Figure 1 The substrate BML includes a first conductive layer EC1, a second conductive layer EC2, and an insulating substrate SL. The insulating substrate SL is stacked between the first conductive layer EC1 and the second conductive layer EC2, and the thickness of the first conductive layer EC1 is greater than the thickness of the second conductive layer EC2.

[0039] Thus, the substrate BML provided in this embodiment of the present disclosure has an asymmetric structure because the thickness of the first conductive layer EC1 is greater than the thickness of the second conductive layer EC2. When it is used to manufacture a circuit board, a masking etching process (Tenting) can be used to form a first trace with a small thickness, line width, and line spacing in the first conductive layer EC1, or a modified semi-additive process (MSAP) can be used to form a second trace with a larger thickness, line width, and line spacing in the second conductive layer EC2, which is beneficial for the miniaturization of the circuit board.

[0040] It should be noted that existing masking etching processes are limited by copper thickness and etching capabilities, making it impossible to fabricate traces with ultra-fine linewidths and spacings (e.g., traces with a thickness ≥18μm and a linewidth and spacing of 35μm). Their yield is extremely low, with a CPK (Process Capability Index) <0.2, far below the requirement of a qualified product CPK >1.33. Existing improved semi-additive processes can fabricate traces with a thickness ≥18μm and a linewidth and spacing of 15μm~40μm, achieving a CPK >1.33. However, they are limited by ultra-thin flexible copper-clad laminates and equipment capabilities, leading to wrinkles in the inner layer boards. This makes them unsuitable for inner layer circuit fabrication, and their yield is extremely low. They are mainly used in rigid PCBs, and cannot be used in flexible circuit boards. However, in this disclosure, based on the asymmetric structure of the substrate BML, a masking etching process (Tenting) can be used to form a first trace with a small thickness, line width, and line spacing in the first conductive layer EC1, and a modified semi-additive process (MSAP) can be used to form a second trace with a larger thickness, line width, and line spacing in the second conductive layer EC2, so as to facilitate the fabrication of ultra-fine traces.

[0041] In one embodiment of this disclosure, the thickness of the first conductive layer EC1 is 9 μm to 18 μm, and the thickness of the second conductive layer EC2 is 2 μm to 5 μm. For example, the thickness of the first conductive layer EC1 can be 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, or 18 μm. The thickness of the second conductive layer EC2 can be 2 μm, 3 μm, 4 μm, or 5 μm. Thus, the thickness of the first conductive layer EC1 is suitable for masking etching processes, enabling precise machining of lines with small linewidths, improving wiring density and etching yield. The smaller thickness of the second conductive layer EC2 is suitable for modified semi-additive processes.

[0042] In one embodiment of this disclosure, the insulating substrate SL is either a flexible substrate or a rigid substrate. In one example, the insulating substrate SL can be a flexible substrate to facilitate the fabrication of flexible circuit boards and rigid-flex circuit boards; in another example, the insulating substrate SL can be entirely rigid substrates to facilitate the fabrication of printed circuit boards and rigid-flex circuit boards. The flexible substrate may include one or more flexible materials such as polyimide, polyester film, and polyethylene naphthalate; the rigid substrate may include one or more rigid materials such as fiberglass cloth, epoxy resin, aluminum, and ceramics. The thickness of the insulating substrate SL is 12.5 μm to 25 μm. For example, the thickness of the insulating substrate SL can be 12.5 μm, 13.5 μm, 14.5 μm, 15.5 μm, 16.5 μm, 17.5 μm, 18.5 μm, 19.5 μm, 20.5 μm, 21.5 μm, 22.5 μm, 23.5 μm, 24.5 μm, or 25 μm. In this way, any one of the following can be manufactured: flexible circuit board, printed circuit board, or rigid-flex circuit board.

[0043] In one embodiment of this disclosure, the materials of the first conductive layer EC1 and the second conductive layer EC2 can be conductive materials such as copper, aluminum, nickel, gold, and silver.

[0044] In one embodiment of this disclosure, the substrate BML can be an asymmetric flexible copper clad laminate (FCCL).

[0045] This disclosure also provides a circuit board. See also Figure 2The circuit board includes two stacked first trace boards CM1 and a first adhesive insulating layer IL1 located between the two first trace boards CM1. The first trace boards CM1 are fabricated using a substrate board BML as described in the above embodiment. Thus, when fabricating the circuit board using the first adhesive insulating layer IL1 and two asymmetrical substrate boards BML, a masking etching process (Tenting) can be used to form first traces with small thickness, line width, and line spacing in the first conductive layer EC1, or a modified semi-additive process (MSAP) can be used to form second traces with larger thickness, line width, and line spacing in the second conductive layer EC2, thereby forming a circuit board including the first adhesive insulating layer IL1 and the two first trace boards CM1, which is beneficial for circuit board miniaturization.

[0046] In one embodiment of this disclosure, see Figure 2 The first trace board CM1 includes a first trace layer RL1, a second trace layer RL2, and an insulating substrate SL. The first trace layer RL1 has multiple first traces, and the second trace layer RL2 has multiple second traces. The thickness of the first trace layer RL1 is less than the thickness of the second trace layer RL2. The insulating substrate SL is stacked between the first trace layer RL1 and the second trace layer RL2. The first adhesive insulating layer IL1 is disposed between two adjacent first trace layers RL1. That is, in the same first trace board CM1, the first trace layer RL1 is formed from the first conductive layer EC1 through a masking etching process, and the second trace layer RL2 is formed from the second conductive layer EC2 through a modified semi-additive process. The two first trace boards CM1 are stacked opposite each other and symmetrically arranged about the plane containing the first adhesive insulating layer IL1.

[0047] Thus, two first trace boards CM1 are symmetrically stacked, and the first adhesive insulating layer IL1 insulates and bonds the two first trace boards CM1. In each first trace board CM1, the thickness of the first trace layer RL1 is less than the thickness of the second trace layer RL2. A masking etching process (Tenting) can be used to form the first trace with a smaller thickness, line width, and line spacing in the first conductive layer EC1. Alternatively, a modified semi-additive process (MSAP) can be used to form the second trace with a larger thickness, line width, and line spacing in the second conductive layer EC2. Because the line width and line spacing of both the first and second traces are significantly reduced, the overall area of ​​the circuit board can be reduced (e.g., the overall area of ​​the circuit board is reduced by 25% to 55%), which is beneficial for circuit board miniaturization and facilitates circuit board layout in display devices. Simultaneously, the larger thickness of the second trace layer RL2 effectively improves the current carrying capacity, bending resistance, and structural strength of the lines. Furthermore, the first adhesive insulating layer IL1 is placed between the two first trace layers RL1, which can precisely isolate the two first trace layers, improving the bonding stability and insulation reliability of the circuit board.

[0048] In one embodiment of this disclosure, the first trace layer RL1 is formed from the first conductive layer EC1 using a masking etching process, and the second trace layer RL2 is formed from the second conductive layer EC2 using a modified semi-additive process. Thus, since the required thickness of the first trace is relatively small, it is advantageous to form a first trace with a small linewidth and line spacing using the masking etching process on the first conductive layer EC1; conversely, the required thickness of the second trace is relatively large, which is advantageous to form a second trace with a small linewidth and line spacing using the modified semi-additive process on the second conductive layer EC2. Therefore, a circuit board with a small linewidth and line spacing can be fabricated using the masking etching process and the modified semi-additive process, reducing the circuit board area and facilitating circuit board miniaturization.

[0049] In one embodiment of this disclosure, see Figure 2 The second trace layer RL2 includes a second conductive layer EC2 and a first metal plating layer ML1 stacked on the insulating substrate SL on the side away from the first trace layer RL1. The thickness of the first trace layer RL1 is greater than the thickness of the second conductive layer EC2. The second trace includes a plurality of first sub-traces located on the second conductive layer EC2 and a plurality of second sub-traces located on the first metal plating layer ML1. The plurality of first sub-traces and the plurality of second sub-traces are arranged in a one-to-one correspondence. The orthographic projection of the first sub-traces on the first adhesive insulating layer IL1 at least partially coincides with the orthographic projection of the corresponding second sub-traces on the first adhesive insulating layer IL1. In other words, the linewidth of the first sub-traces and the second sub-traces can be the same, and the second sub-traces are located directly above the corresponding first sub-traces. The first metal plating layer ML1 can be formed on the second conductive layer EC2 by an electroplating process. Thus, on the one hand, the adhesion and structural stability of the circuit on the insulating substrate SL are improved by relying on the second conductive layer EC2, and the thickness of the second trace is supplemented by electroplating the first metal plating layer ML1, which takes into account both process feasibility and circuit conductivity; on the other hand, the first sub-trace and the second sub-trace have overlapping parts, which is conducive to increasing the effective cross-sectional area of ​​the second trace, reducing resistance, and improving current carrying capacity.

[0050] Furthermore, the linewidths of the first trace and the second trace are 20μm to 50μm, respectively. For example, the linewidth of the first trace can be 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, or 50μm; the linewidth of the second trace can be 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, or 50μm.

[0051] The spacing between two adjacent first traces is 20μm to 50μm, and the spacing between two adjacent second traces is 20μm to 50μm. For example, the spacing between two adjacent first traces can be 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, or 50μm, and the spacing between two adjacent second traces can be 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, or 50μm. This allows for increased wiring density on the circuit board, reduces the overall area of ​​the circuit board, and enables miniaturization of the circuit board.

[0052] Furthermore, the thickness of the first routing layer RL1 is 5μm to 16μm, that is, the thickness of the first routing layer is 5μm to 16μm. For example, the thickness of the first routing layer RL1 can be 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, or 16μm.

[0053] The thickness of the second trace layer RL2 is greater than 18 μm, meaning the total thickness of the second conductive layer EC2 and the first metal plating layer ML1 is not less than 18 μm, and thus the thickness of the second trace is not less than 18 μm. Since the thickness of the second conductive layer EC2 is 2 μm to 5 μm, the thickness of the first metal plating layer ML1 is not less than 13 μm. For example, the thickness of the second trace layer RL2 can be 18 μm, 20 μm, 25 μm, 30 μm, 35 μm, or 40 μm, and the thickness of the first metal plating layer ML1 can be 13 μm, 18 μm, 23 μm, or 28 μm.

[0054] In one embodiment of this disclosure, see Figure 3 , Figure 4 , Figure 5 The circuit board further includes at least one first stacking unit Q1, which comprises a second adhesive insulating layer IL2 and a second wiring board CM2 stacked sequentially on the side of the first wiring board CM1 away from the first adhesive insulating layer IL1. The structure of the second wiring board CM2 is the same as that of the first wiring board CM1, that is, the second wiring board CM2 includes a first wiring layer RL1, a second wiring layer RL2, and an insulating substrate SL of the first wiring board CM1. The second adhesive insulating layer IL2 is located between a first metal plating layer ML1 of the first wiring board CM1 and the first wiring layer RL1 of the second wiring board CM2. This improves the applicability of the circuit board.

[0055] As an example, see Figure 3The number of first stacking units Q1 can be one. One first stacking unit Q1 is stacked on the side of a first trace board CM1 away from the first adhesive insulating layer IL1. Specifically, the second adhesive insulating layer IL2 of the first stacking unit Q1 is located between the first metal plating layer ML1 of the first trace board CM1 and the first trace layer RL1 of the second trace board CM2, so that the circuit board includes three stacked trace boards (first trace board CM1 and second trace board CM2).

[0056] As an example, see Figure 4 The number of first stacking units Q1 can be two. The first first stacking unit Q1 is stacked on the side of a first trace board CM1 away from the first adhesive insulating layer IL1, and the second first stacking unit Q1 is stacked on the side of the first first stacking unit Q1 away from the first adhesive insulating layer IL1. Specifically, the second adhesive insulating layer IL2 of the first first stacking unit Q1 is located between the first metal plating layer ML1 of the first trace board CM1 and the first trace layer RL1 of the second trace board CM2 of the first first stacking unit Q1, and the second adhesive insulating layer IL2 of the second first stacking unit Q1 is located between the first trace layer RL1 of the second trace board CM2 of the first first stacking unit Q1 and the first trace layer RL1 of the second trace board CM2 of the second first stacking unit Q1, so that the circuit board includes four stacked trace boards (first trace board CM1 and second trace board CM2).

[0057] As an example, see Figure 5 The number of first stacking units Q1 can be two. The first first stacking unit Q1 is stacked on the side of a first trace board CM1 away from the first adhesive insulating layer IL1, and the second first stacking unit Q1 is stacked on the side of another first trace board CM1 away from the first adhesive insulating layer IL1. Specifically, the second adhesive insulating layer IL2 of the first first stacking unit Q1 is located between the first metal plating layer ML1 of the first trace board CM1 and the first trace layer RL1 of the second trace board CM2 of the first first stacking unit Q1, and the second adhesive insulating layer IL2 of the second first stacking unit Q1 is located between the first metal plating layer ML1 of the other first trace board CM1 and the first trace layer RL1 of the second trace board CM2 of the second first stacking unit Q1, so that the circuit board includes four stacked trace boards (first trace board CM1 and second trace board CM2).

[0058] Of course, in addition to the above examples, the number of the first stacking units Q1 of the circuit board can be three, four, five, six, etc., and they can be stacked in a similar way to the above examples, which will not be elaborated here.

[0059] In one embodiment of this disclosure, see Figure 6, Figure 7 , Figure 8 The circuit board further includes at least one second stacking unit Q2, which includes a third adhesive insulating layer IL3 and a third wiring board CM3 stacked sequentially on the side of the first wiring board CM1 away from the first adhesive insulating layer IL1. The third wiring board CM3 includes a third wiring layer RL3 and an insulating substrate SC. The third wiring layer RL3 includes a third conductive layer EC3 and a second metal plating layer ML2 stacked on the side of the insulating substrate SC away from the third adhesive insulating layer IL3. The thickness of the first wiring layer RL1 is greater than the thickness of the third conductive layer EC3. The third wiring layer RL3 is fabricated from the third conductive layer EC3 using a modified semi-additive process.

[0060] The material and thickness of the third conductive layer EC3 can be the same as those of the second conductive layer EC2, and the material and thickness of the insulating substrate SC can be the same as those of the insulating base material SL. In other words, the third wiring board CM3 is a structure of the first wiring board CM1 excluding the first wiring layer RL1.

[0061] As an example, see Figure 6 The number of second stacking units Q2 can be one, and one second stacking unit Q2 is stacked on the side of a first trace board CM1 away from the first adhesive insulating layer IL1; specifically, the third adhesive insulating layer IL3 of the second stacking unit Q2 is located between the first metal plating layer ML1 of the first trace board CM1 and the third trace layer RL3 of the third trace board CM3, so that the circuit board includes three stacked trace boards (first trace board CM1 and third trace board CM3).

[0062] As an example, see Figure 7 The number of second stacking units Q2 can be two. The first second stacking unit Q2 is stacked on the side of a first wiring board CM1 away from the first adhesive insulating layer IL1, and the second second stacking unit Q2 is stacked on the side of the first second stacking unit Q2 away from the first adhesive insulating layer IL1. Specifically, the third adhesive insulating layer IL3 of the first second stacking unit Q2 is located between the first metal plating layer ML1 of the first wiring board CM1 and the third wiring layer RL3 of the third wiring board CM3 of the first second stacking unit Q2, and the third adhesive insulating layer IL3 of the second third wiring board CM3 is located between the third wiring layer RL3 of the third wiring board CM3 of the first second stacking unit Q2 and the third wiring layer RL3 of the third wiring board CM3 of the second second stacking unit Q2, so that the circuit board includes four stacked wiring boards (first wiring board CM1 and third wiring board CM3).

[0063] As an example, see Figure 8 The number of second stacking units Q2 can be two. The first second stacking unit Q2 is stacked on the side of a first trace board CM1 away from the first adhesive insulating layer IL1, and the second second stacking unit Q2 is stacked on the side of another first trace board CM1 away from the first adhesive insulating layer IL1. Specifically, the third adhesive insulating layer IL3 of the first second stacking unit Q2 is located between the first metal plating layer ML1 of the first trace board CM1 and the third wiring layer RL3 of the third trace board CM3 of the first second stacking unit Q2, and the third adhesive insulating layer IL3 of the second second stacking unit Q2 is located between the first metal plating layer ML1 of the other first trace board CM1 and the third wiring layer RL3 of the third trace board CM3 of the second second stacking unit Q2, so that the circuit board includes four stacked trace boards (first trace board CM1 and third trace board CM3).

[0064] Of course, in addition to the above examples, the number of second stacking units Q2 on the circuit board can be three, four, five, six, etc., and they can be stacked in a similar way to the above examples, which will not be elaborated here.

[0065] In one embodiment of this disclosure, the circuit board may simultaneously include a first wiring board CM1, a first stacking unit Q1, and a second stacking unit Q2 arranged in a stacked manner to form a circuit board with diverse structures.

[0066] In one embodiment of this disclosure, see Figure 2 When there are two first trace boards CM1, in the same substrate board BML, the first trace layer RL1 and the second trace layer RL2 are electrically connected through a first via Via1, which penetrates the second conductive layer EC2 and the insulating substrate SL. The two first trace layers RL1 and the two second trace layers RL2 are electrically connected through a second via Via2, which penetrates the first adhesive insulating layer IL1, the two second conductive layers EC2, the insulating substrate SL, and the first trace layer RL1. The first via Via1 and the second via Via2 are formed using a modified semi-additive process. A first metal plating layer ML1 fills the first via Via1 and the second via Via2 to facilitate the electrical connection of the first traces and the second traces through the first metal plating layer ML1, forming a complete circuit board circuit.

[0067] Furthermore, the first adhesive insulating layer IL1 can be made of PP glass fiber material, and the thickness of the first adhesive insulating layer IL1 can be set according to specific requirements in order to facilitate the lamination of the two substrate boards BML.

[0068] Further, see Figure 2The first wiring layer RL1 may have blind vias MK. When the two substrate boards BML are laminated, the blind vias MK can accommodate the portion of the first adhesive insulation layer IL1 that is melted, so as to improve the yield.

[0069] Optionally, see Figure 3 When a first stacking unit Q1 is disposed on the side of the first wiring board CM1 away from the first adhesive insulating layer IL1, the first stacking unit Q1 may be provided with a third via Via3, a fourth via Via4, and a fifth via Via5. The third via Via3 penetrates the first conductive layer EC1, the second conductive layer EC2, and the insulating substrate SL of the second wiring board CM2. The fourth via Via4 penetrates the second conductive layer EC2 and the insulating substrate SL of the second wiring board CM2. The fifth via Via5 penetrates the first conductive layer EC1 and the second adhesive insulating layer IL2 of the second wiring board CM2. The third via Via3 and the fourth via Via4 can be formed by a modified semi-additive process, and the fifth via Via5 can be formed by a masking etching process. The first metal plating layer ML1 of the second wiring board CM2 can fill the third via Via3, the fourth via Via4, and the fifth via Via5 to achieve electrical connection between the first wiring board CM1 and the second wiring board CM2. The material and dimensions of the second adhesive insulating layer IL2 can be the same as those of the first adhesive insulating layer IL1.

[0070] Optionally, see Figure 6 When a second stacking unit Q2 is disposed on the side of the first wiring board CM1 away from the first adhesive insulating layer IL1, the second stacking unit Q2 may have a sixth via Via6. The sixth via Via6 penetrates the third conductive layer EC3, the insulating substrate SC, and the third adhesive insulating layer IL3. The sixth via Via6 can be formed by a modified semi-additive process. The second metal plating layer ML2 can fill the sixth via Via6 to achieve electrical connection between the first wiring board CM1 and the third wiring board CM3. The material and dimensions of the third adhesive insulating layer IL3 can be the same as those of the first adhesive insulating layer IL1.

[0071] Of course, the vias on the circuit board are not limited to the forms described above.

[0072] This disclosure also provides a method for manufacturing a circuit board, used to manufacture the circuit board of the above embodiments. The manufacturing method includes the following steps: Step S100, see Figure 9 Two substrate boards BML are provided; wherein each substrate board BML includes a first conductive layer EC1, a second conductive layer EC2 and an insulating substrate SL; wherein the insulating substrate SL is stacked between the first conductive layer EC1 and the second conductive layer EC2, and the thickness of the first conductive layer EC1 is greater than the thickness of the second conductive layer EC2. Step S200, see Figure 10 A photoresist layer PR is disposed on the side of the second conductive layer EC2 away from the first conductive layer EC1; wherein, the photoresist layer PR is a wet film photoresist layer PR. Step S300, see Figure 14 The first wiring layer RL1 is formed in the first conductive layer EC1 by a masking etching process; Step S400, see Figure 11 Two substrate boards BML are pressed together by a first adhesive insulating layer IL1; wherein, the first adhesive insulating layer IL1 is located between two first wiring layers RL1; Step S500, see Figure 12 Remove the photoresist layer PR; Step S600, see Figure 13 , Figure 15 A second trace layer RL2 is formed in the second conductive layer EC2 using a modified semi-additive process to form a first trace board CM1. The first trace board CM1 includes a first trace layer RL1, a second trace layer RL2, and an insulating substrate SL. The first trace layer RL1 has multiple first traces, and the second trace layer RL2 has multiple second traces. The thickness of the first trace layer RL1 is less than the thickness of the second trace layer RL2.

[0073] Thus, two substrate boards BMLs are symmetrically stacked, with the first adhesive insulating layer IL1 insulatingly bonding the two substrate boards BMLs. In each substrate board BML, the thickness of the first conductive layer EC1 is greater than the thickness of the second conductive layer EC2. The insulating substrate SL achieves insulation isolation between the first trace layer RL1 and the second trace layer RL2, forming an asymmetrical structure of the substrate board BMLs. With this structure, a masking etching process can be used to form a first trace with a smaller thickness, line width, and line spacing in the first conductive layer EC1, and a modified semi-additive process can be used to form a second trace with a larger thickness, line width, and line spacing in the second conductive layer EC2. Since the line width and line spacing of both the first and second traces are reduced, the overall area of ​​the circuit board can be reduced (for example, the overall area of ​​the circuit board is reduced by 25% to 55%), which is beneficial for the miniaturization of the circuit board and facilitates the layout of the circuit board in the display device. At the same time, the larger thickness of the second trace layer RL2 effectively improves the current carrying capacity, bending resistance, and structural strength of the lines. In addition, the first adhesive insulating layer IL1 is disposed between the two first trace layers RL1, which can accurately isolate the two first trace layers and improve the bonding stability and insulation reliability of the circuit board.

[0074] In one embodiment of this disclosure, in step S300, a first trace layer RL1 is formed in the first conductive layer EC1 by a masking etching process, including: Step S310, see Figure 10 Drilling; wherein, a blind hole MK is drilled in the first conductive layer EC1; Step S320, see Figure 14 The first dry film GM1 is pressed together; wherein the first dry film GM1 is located on the side of the first conductive layer EC1 away from the insulating substrate SL; Step S330, see Figure 14 The first conductive layer EC1 is patterned; the patterning process includes exposure, development, and etching. Step S340, see Figure 14 Remove the first dry film GM1; Step S350, see Figure 14 This forms the first routing layer RL1, which includes multiple first routing layers.

[0075] Thus, by using a masking etching process, a first trace with a small thickness, line width, and line spacing can be formed in the first conductive layer EC1.

[0076] In one embodiment of this disclosure, in step S600, a second wiring layer RL2 is formed on the second conductive layer EC2 using a modified semi-additive process, including the following steps: Step S610, see Figure 15 A first metal plating layer ML1 is formed on the side of the second conductive layer EC2 away from the first adhesive insulating layer IL1 using a modified semi-additive process; wherein, the second wiring layer RL2 includes the second conductive layer EC2 and the first metal plating layer ML1 stacked on the side of the insulating substrate SL away from the first wiring layer RL1, the thickness of the first wiring layer RL1 is greater than the thickness of the second conductive layer EC2, and the first metal plating layer ML1 has a plurality of second sub-wirings; Step S620, see Figure 15 Multiple first sub-traces are formed in the second conductive layer EC2 by a modified semi-additive process to form multiple second traces; wherein, the second conductive layer EC2 has multiple first sub-traces, and the multiple first sub-traces are arranged in a one-to-one correspondence with the multiple second sub-traces, and the orthographic projection of the first sub-traces on the first adhesive insulating layer IL1 at least partially overlaps with the orthographic projection of the corresponding second sub-traces on the first adhesive insulating layer IL1.

[0077] Thus, by forming a first metal plating layer ML1 on the second conductive layer EC2, the first sub-trace and the second sub-trace together form the second trace, which helps to increase the thickness of the second trace and adapt it to the improved semi-additive process.

[0078] In one embodiment of this disclosure, step S610 includes the following steps: Step S611, see Figure 12Drilling; wherein, a first via Via1 is formed on the two second conductive layers EC2, the first via Via1 penetrates the second conductive layer EC2 and the insulating substrate SL, and a second via Via2 is formed, the second via Via2 penetrates the first adhesive insulating layer IL1, each of the second conductive layers EC2, the insulating substrate SL, and the first wiring layer RL1. Step S612, see Figure 15 A second dry film GM2 is laminated onto the second conductive layer EC2; wherein the second dry film GM2 is located on the side of the second conductive layer EC2 away from the first adhesive insulating layer IL1; Step S613, see Figure 15 The second dry film GM2 is exposed and developed to reveal the location of the first sub-trace. Step S614, see Figure 15 A first metal plating layer ML1 is formed on the second conductive layer EC2 by an electroplating process, see [link to documentation]. Figure 13 The first metal plating layer ML1 fills each of the first vias Via1 ( Figure 15 (not shown in the image) and second via Via2 ( Figure 15 (Not shown in the text)

[0079] In one embodiment of this disclosure, step S620 includes the following steps: Step S621, see Figure 15 Remove the second dry film GM2; Step S622, see Figure 15 A flash etching operation is performed on the second conductive layer EC2 to form the first sub-trace; wherein the flash etching does not etch the second sub-trace of the first metal plating layer ML1.

[0080] In one embodiment of this disclosure, after step S600, the preparation method further includes the following steps: In step S700, at least one first stacking unit Q1 is formed on the side of the first wiring board CM1 away from the first adhesive insulating layer IL1; wherein, the first stacking unit Q1 includes a second adhesive insulating layer IL2 and a second wiring board CM2 stacked together; the structure of the second wiring board CM2 is the same as the structure of the first wiring board CM1, and the second adhesive insulating layer IL2 is located between a first metal plating layer ML1 of the first wiring board CM1 and a first wiring layer RL1 of the second wiring board CM2.

[0081] In step S700, the first trace layer RL1 of the second trace board CM2 is formed by a masking etching process, and the second trace layer RL2 of the second trace board CM2 is formed by a modified semi-additive process.

[0082] In one embodiment of this disclosure, after step S600, the preparation method further includes the following steps: In step S800, at least one second stacking unit Q2 is formed on the side of the first wiring board CM1 away from the first adhesive insulating layer IL1; wherein, the third wiring board CM3 includes a third wiring layer RL3 and an insulating substrate SC, the third wiring layer RL3 includes a third conductive layer EC3 and a second metal plating layer ML2 stacked on the side of the insulating substrate SC away from the third adhesive insulating layer IL3, the thickness of the first wiring layer RL1 is greater than the thickness of the third conductive layer EC3; the third wiring layer RL3 is made by the third conductive layer EC3 through a modified semi-additive process.

[0083] This disclosure provides a display device. The display device can be an in-vehicle display (e.g., a ceiling-mounted screen, dashboard, center console, head-up display, etc.), a smartphone, tablet computer, laptop computer, wearable watch, VR device, AR device, television set, vehicle window glass, cabin glass, or other types of display devices.

[0084] The display device may include a display module, a driving module, and a housing. The display module and the driving module are located within a cavity in the housing for protection. The driving module is electrically connected to the display module to drive the display module to display an image. The driving module may include chips such as a timing control chip and a power management chip.

[0085] The display module may include a display panel, a driver chip, and the circuit board described in the above embodiments. The circuit board is electrically connected to the display panel, and the driver chip is electrically connected to the circuit board, so that the driver chip drives the display panel to display an image. In one example, the circuit board may be a flexible circuit board, with the display panel electrically connected to the flexible circuit board. The flexible circuit board is electrically connected to the driver chip via a chip-on-film (COF) film, and the flexible circuit board is bent to the back of the display panel via a bending area to reduce the bezel of the display panel. In another example, the circuit board is a printed circuit board, which is disposed on the back of the display panel via the flexible circuit board. The printed circuit board is electrically connected to the flexible circuit board via the COF film, and the flexible circuit board is electrically connected to the display panel. The driver chip is disposed on the COF film. In other examples, the circuit board may be a rigid-flex circuit board, having a rigid layer and a flexible layer. The flexible layer is located in the bending area of ​​the circuit board, so that the rigid-flex circuit board can be bent to the back of the display panel, and the rigid layer is used to bond the driver chip.

[0086] The display device has all the beneficial effects of the aforementioned circuit board, which will not be elaborated here.

[0087] It should be noted that although the various steps of the preparation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0088] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A substrate board for use in circuit boards, characterized in that, The substrate includes a first conductive layer, a second conductive layer, and an insulating substrate; The insulating substrate is stacked between the first conductive layer and the second conductive layer, and the thickness of the first conductive layer is greater than the thickness of the second conductive layer.

2. A circuit board, characterized in that, It includes two first wiring boards stacked together and a first adhesive insulation layer located between the two first wiring boards; The first wiring board is made of the substrate board described in claim 1.

3. The circuit board according to claim 2, characterized in that, The first wiring board includes a first wiring layer, a second wiring layer, and an insulating substrate; The first wiring layer has a plurality of first wirings, the second wiring layer has a plurality of second wirings, the thickness of the first wiring layer is less than the thickness of the second wiring layer, and the insulating substrate is stacked between the first wiring layer and the second wiring layer. The first adhesive insulating layer is disposed between two adjacent first wiring layers.

4. The circuit board according to claim 3, characterized in that, The first trace layer is formed by the first conductive layer through a masking etching process, and the second trace layer is formed by the second conductive layer through a modified semi-additive process.

5. The circuit board according to claim 4, characterized in that, The second trace layer includes a second conductive layer and a first metal plating layer stacked on the side of the insulating substrate away from the first trace layer, wherein the thickness of the first trace layer is greater than the thickness of the second conductive layer; The second trace includes a plurality of first sub-traces located in the second conductive layer and a plurality of second sub-traces located in the first metal plating layer. The plurality of first sub-traces and the plurality of second sub-traces are arranged in a one-to-one correspondence. The orthographic projection of the first sub-traces on the first adhesive insulating layer and the orthographic projection of the corresponding second sub-traces on the first adhesive insulating layer at least partially overlap.

6. The circuit board according to claim 5, characterized in that, The circuit board further includes at least one first stacking unit, the first stacking unit including a second adhesive insulating layer and a second wiring board stacked sequentially on the side of the first wiring board away from the first adhesive insulating layer; The structure of the second wiring board is the same as that of the first wiring board, and the second adhesive insulating layer is located between one of the first metal plating layers of the first wiring board and the first wiring layer of the second wiring board. Alternatively, the circuit board may further include at least one second stacking unit, the second stacking unit including a third adhesive insulating layer and a third wiring board stacked sequentially on the side of the first wiring board away from the first adhesive insulating layer; The third wiring board includes a third wiring layer and an insulating substrate. The third wiring layer includes a third conductive layer and a second metal plating layer stacked on the insulating substrate on the side away from the third adhesive insulating layer. The thickness of the first wiring layer is greater than the thickness of the third conductive layer. The third wiring layer is made from the third conductive layer by a modified semi-additive process.

7. A method for manufacturing a circuit board, characterized in that, The preparation method includes: Two substrate boards are provided; each of the substrate boards includes a first conductive layer, a second conductive layer, and an insulating substrate; wherein the insulating substrate is stacked between the first conductive layer and the second conductive layer, and the thickness of the first conductive layer is greater than the thickness of the second conductive layer; A photoresist layer is disposed on the side of the second conductive layer away from the first conductive layer; A first wiring layer is formed on the first conductive layer by a masking etching process; Two substrate boards are laminated together by a first adhesive insulating layer; wherein the first adhesive insulating layer is located between the two first wiring layers; Remove the photoresist layer; A second trace layer is formed on the second conductive layer using a modified semi-additive process to form a first trace board; wherein the first trace board includes a first trace layer, a second trace layer, and an insulating substrate; the first trace layer has a plurality of first traces, the second trace layer has a plurality of second traces, and the thickness of the first trace layer is less than the thickness of the second trace layer.

8. The method for manufacturing a circuit board according to claim 7, characterized in that, Forming a second wiring layer in the second conductive layer using a modified semi-additive process includes: A first metal plating layer is formed on the side of the second conductive layer away from the first adhesive insulating layer using a modified semi-additive process; wherein, the second trace layer includes a second conductive layer and a first metal plating layer stacked on the side of the insulating substrate away from the first trace layer, the thickness of the first trace layer is greater than the thickness of the second conductive layer, and the first metal plating layer has a plurality of second sub-traces. Multiple first sub-traces are formed in the second conductive layer by an improved semi-additive process to form multiple second traces; wherein the second conductive layer has multiple first sub-traces, and the multiple first sub-traces and the multiple second sub-traces are arranged in a one-to-one correspondence, and the orthographic projection of the first sub-traces on the first adhesive insulating layer and the orthographic projection of the corresponding second sub-traces on the first adhesive insulating layer at least partially overlap.

9. The method for manufacturing a circuit board according to claim 7, characterized in that, After forming the first wiring board, the fabrication method further includes: At least one first stacking unit is formed on the side of the first wiring board away from the first adhesive insulating layer; wherein, the first stacking unit includes a second adhesive insulating layer and a second wiring board stacked together; the structure of the second wiring board is the same as the structure of the first wiring board, and the second adhesive insulating layer is located between a first metal plating layer of the first wiring board and the first wiring layer of the second wiring board; Alternatively, at least one second stacking unit is formed on the side of the first wiring board away from the first adhesive insulating layer; wherein, the third wiring board includes a third wiring layer and an insulating substrate, the third wiring layer includes a third conductive layer and a second metal plating layer stacked on the side of the insulating substrate away from the third adhesive insulating layer, the thickness of the first wiring layer is greater than the thickness of the third conductive layer; the third wiring layer is made from the third conductive layer by a modified semi-additive process.

10. A display module, characterized in that, Includes the circuit board as described in any one of claims 2 to 6.

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