Printed circuit board

Abstract

The application provides a printed circuit board, which comprises a top layer, a plurality of inner layers and a bottom layer arranged from top to bottom; at least one blind hole is arranged between the top layer and an inner layer LP, the top layer and the inner layer LP are communicated through the blind hole, the inner layer LP-1 and the inner layer LP+1 located on both sides of the inner layer LP are both ground layers, and at least one inner layer exists between the top layer and the inner layer LP; at least one buried hole is arranged between the inner layer LP and an inner layer LQ, the inner layer LP and the inner layer LQ are communicated through the buried hole; the inner layer LQ-1 and the inner layer LQ+1 located on both sides of the inner layer LQ are both ground layers, and at least one inner layer exists between the inner layer LQ and the bottom layer; the bottom layer opening of the blind hole and the top layer opening of the buried hole are electrically connected at the inner layer LP. The application can significantly shorten the signal transmission path, reduce the parasitic inductance and capacitance, improve the impedance continuity, reduce the loop inductance and improve the wiring density.

Description

Technical Field

[0001] This application belongs to the field of printed circuit board design technology, and specifically relates to a printed circuit board. Background Technology

[0002] With the rapid development of high-speed domain control in vehicles, AI edge computing, and high-speed serial interface technologies, electronic systems are placing unprecedentedly stringent requirements on the signal integrity, power integrity, and electromagnetic compatibility of printed circuit boards (PCBs). In multi-layer, high-density interconnected PCB designs, the traditional through-hole structure has become a major bottleneck restricting high-speed signal transmission performance.

[0003] Traditional through-hole vias are prone to residual pile effects in high-speed scenarios, leading to high-frequency reflections, insertion loss, and impedance discontinuities. This results in increased eye diagram closure and bit error rate. Furthermore, traditional through-hole vias cause excessive parasitic inductance and capacitance, worsening the impedance of the power distribution network and increasing crosstalk and electromagnetic interference radiation. In addition, through-holes penetrate the plane, disrupting the return path and occupying significant space, making it difficult to meet the high-density wiring requirements of small packages. To alleviate these problems, the industry has adopted a hybrid blind / buried via solution. However, non-overlapping structures require horizontal signal transitions, introducing via impedance discontinuities, path lengthening, and parasitic parameter accumulation, resulting in limited performance improvements. While staggered vias reduce manufacturing difficulty, they result in low vertical interconnect density, longer signal paths, and greater parasitic effects, failing to meet the requirements of extremely high-speed scenarios. Therefore, providing a printed circuit board that can solve the performance defects of traditional through-holes and conventional blind / buried vias is a technical problem urgently needing to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a printed circuit board to solve the technical problem of performance defects of traditional through holes and conventional blind / buried vias.

[0005] The first aspect of this application provides a printed circuit board, the printed circuit board comprising a top layer, a plurality of inner layers and a bottom layer disposed from top to bottom;

[0006] At least one blind hole is provided between the top layer and the inner layer LP, and the top layer and the inner layer LP are connected through the blind hole. The inner layers LP-1 and LP+1 located on both sides of the inner layer LP are ground layers, and there is at least one inner layer between the top layer and the inner layer LP.

[0007] At least one buried via is provided between the inner layer LP and the inner layer LQ, and the inner layer LP and the inner layer LQ are connected through the buried via; the inner layers LQ-1 and LQ+1 located on both sides of the inner layer LQ are both ground layers, and there is at least one inner layer between the inner layer LQ and the bottom layer.

[0008] The bottom opening of the blind hole and the top opening of the buried hole are electrically connected at the inner layer LP.

[0009] In some implementations of the first aspect, the number of buried vias corresponds to the number of blind vias, and the blind vias overlap with the corresponding buried vias to form at least one signal via stack.

[0010] In some implementations of the first aspect, the top pad of the buried via and the bottom pad of the blind via have an overlapping area, and the area of ​​the overlapping area is not less than 50% of the area of ​​the top pad of the buried via and not less than 50% of the area of ​​the bottom pad of the blind via, and the offset between the central axis of the blind via and the central axis of the buried via is not greater than 0.02 mm.

[0011] In some implementations of the first aspect, a plurality of grounding vias are arranged around the signal vias, and the plurality of grounding vias are arranged in a surrounding manner and are respectively connected to each ground layer in the printed circuit board.

[0012] In some implementations of the first aspect, the number of inner layers sandwiched between the inner layer LP and the top layer is minimized.

[0013] In some implementations of the first aspect, the number of inner layers sandwiched between the inner layer LQ and the bottom layer is minimized.

[0014] In some implementations of the first aspect, the diameter of the blind hole is larger than that of the buried hole; or, the diameters of the blind hole and the buried hole are equal and the tapers of the blind hole and the buried hole are opposite.

[0015] In some implementations of the first aspect, two of the signal vias constitute a differential signal pair; or four of the signal vias constitute a four-channel array; a grounding via is provided between two adjacent differential signal pairs or between two adjacent four-channel arrays; wherein each of the signal vias or the grounding vias includes a blind via segment extending from the top layer to the inner layer LP, and a buried via segment extending from the inner layer LP to the inner layer LQ, the blind via segment and the buried via segment being electrically connected at the LP layer.

[0016] In some implementations of the first aspect, the LQ+1 layer is connected to the bottom layer via a via; or, the LQ+1 layer is connected to the bottom layer via a second blind via.

[0017] In some implementations of the first aspect, the printed circuit board further includes through-holes that extend from layer LQ+1 along the thickness direction to the bottom layer; the through-holes are back-drilled through-holes. As described above, in the printed circuit board of this application, blind vias only extend from the top layer to the inner layer LP, and buried vias only extend from the inner layer LP to the inner layer LQ. The interconnection path formed by the two on the critical signal network from the top layer to the inner layer LP, and the adjacent layers of the two inner layers are both ground layers; this has the following beneficial effects:

[0018] 1. Zero residual pile design: No suspended residual piles, completely eliminating the residual pile effect of traditional through holes;

[0019] 2. Under normal operating conditions, the adjacent layers of the two inner layers are grounded, which can achieve shielding and isolation of the signals of the two inner layers and improve the robustness of the signals; in addition, it can also reduce the signal return path on the two inner layers and improve the decoupling effect.

[0020] 3. This application arranges multiple grounding vias around the signal stack vias. Due to the addition of impedance matching design, the impedance matching of the interconnect path from the top layer to the inner LQ layer is ensured (50Ω for single-ended and 100Ω for differential), reducing signal reflection caused by impedance abrupt changes.

[0021] 4. Return path design: This application does not penetrate the LQ+1 layer below the inner LQ to the bottom layer, ensuring a continuous high-speed signal return path while reducing parasitic interference in the power network.

[0022] 5. Overlapping design of blind and buried vias: After signals enter the inner layer through blind vias from the surface layer, they directly connect with the buried vias below, and then propagate to deeper layers. This shortens the signal path and avoids the additional impedance and noise coupling caused by horizontal leads. It also reduces the amount of trace space occupied by different via areas, which is beneficial for multi-layer high-density interconnect board layouts. Furthermore, it reduces series inductance and improves decoupling performance. Attached Figure Description

[0023] Figure 1 A schematic diagram of the architecture of the printed circuit board described in an embodiment of this application is shown.

[0024] Figure 2 A schematic diagram of the architecture of an 8-layer printed circuit board according to an embodiment of this application is shown.

[0025] Figure 3 A schematic diagram of the architecture of an 8-layer printed circuit board according to yet another embodiment of this application is shown.

[0026] Figure 4 A schematic diagram of the grounding via and signal via described in an embodiment of this application is shown.

[0027] Figures 5a to 5dA schematic diagram comparing the S11 and S12 parameters of the printed circuit board structure described in the embodiments of this application and the conventional through-hole structure is shown.

[0028] Figure 6a and Figure 6b A schematic diagram showing a comparison of TDR simulation results between the printed circuit board structure described in the embodiments of this application and the traditional through-hole structure is presented.

[0029] Component designation explanation

[0030] 121034 67 Blind vias, buried vias, printed circuit board chips, signal stacking vias, grounding vias, annular slots Detailed Implementation

[0031] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0032] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of this application. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of this application. The following detailed description should not be considered limiting, and the scope of the embodiments of this application is defined only by the claims of the published patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. Spatial terms such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0033] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are to be interpreted inclusively, or mean any one or any combination thereof.

[0034] Figure 1 A schematic diagram of the printed circuit board architecture described in an embodiment of this application is shown. Figure 1As shown, the printed circuit board 10 provided in this application embodiment includes a top layer L1, several inner layers L2~LN-1 and a bottom layer LN disposed from top to bottom;

[0035] At least one blind hole 1 is provided between the top layer L1 and the inner layer LP. The top layer L1 and the inner layer LP are connected through the blind hole. The inner layers LP-1 and LP+1 located on both sides of the inner layer LP are ground layers. There is at least one inner layer between the top layer L1 and the inner layer LP.

[0036] At least one buried via is provided between the inner layer LP and the inner layer LQ, and the inner layer LP and the inner layer LQ are connected through the buried via; the inner layers LQ-1 and LQ+1 located on both sides of the inner layer LQ are both ground layers, and there is at least one inner layer between the inner layer LQ and the bottom layer LN;

[0037] The top opening of the blind via 1 is located on the top layer L1, and the bottom opening of the buried via 2 is located on the inner layer LQ. The bottom opening of the blind via 1 and the top opening of the buried via 2 are electrically connected at the inner layer LP. In some embodiments, the inner layer LP needs to meet the following two conditions: the distance between the LP layer and the L1 layer is as small as possible, that is, the number of inner layers sandwiched between the inner layer LP and the top layer is minimized; the upper LP-1 layer and the lower LP+1 layer of the inner layer LP are both ground layers. The ground layer is a conductive layer in the PCB stack-up structure specifically designed to provide a low-impedance, stable reference potential. It typically exists as a complete copper foil plane and is connected to the ground network in the circuit system vias or directly.

[0038] Furthermore, the distance between the LP layer and the L1 layer should be as small as possible. When the LP layer is arranged adjacent to the L1 layer, the L1 layer serves as the upper adjacent layer of the LP layer and is a ground layer. In some other embodiments, if the LP+1 layer above the LP layer is located between the top layer L1 and the inner layer LP, then the upper LP+1 layer serves as a ground layer and should have a clearance window or insulating isolation structure at the blind hole 1.

[0039] In some embodiments, the inner LQ layer must meet the following two conditions: the distance between the LQ layer and the bottom layer LN is as small as possible, that is, the number of inner layers sandwiched between the inner LQ layer and the bottom layer is minimized; the upper LQ-1 layer and the lower LQ+1 layer of the LQ layer are both ground layers.

[0040] Furthermore, the distance between the LQ layer and the bottom layer LN should be as small as possible. When the LQ layer is arranged adjacent to the LN layer, the LN layer serves as the LP+1 layer below the LP layer, which is a ground layer. In some other embodiments, if the LQ+1 layer below the LQ layer is located between the inner LQ layer and the bottom layer LN, then the LQ+1 layer serves as a ground layer and should have a clearance window or insulating isolation structure at the buried via 2.

[0041] Furthermore, at least one buried via 2 is provided between the inner layer LP and the inner layer LQ. In some embodiments, M buried vias are designed between the LP layer and the LQ layer. In this case, the buried vias do not penetrate the entire board thickness, but only connect several intermediate layers.

[0042] From the perspectives of manufacturability, reliability, and electrical performance, the number of buried vias 2 should follow the principle of "the fewer the better." That is, while meeting signal connectivity requirements, the number of buried vias 2 should be minimized. Preferably, one buried via 2 is provided between the inner layer LP and the inner layer LQ, meaning only one buried via is designed in the entire PCB stack-up structure. This minimizes process complexity (reducing multiple lamination and drilling operations), avoids mutual interference between buried vias, and improves yield and long-term reliability. Only when electrical performance or physical routing cannot meet the requirements should the number of buried vias be increased based on the actual situation.

[0043] Furthermore, the top opening of the blind via 1 is located on the top layer L1, and the bottom opening of the buried via 2 is located on the inner layer LQ. The bottom opening of the blind via 1 and the top opening of the buried via 2 are electrically connected at the inner layer LP. The bottom opening of the blind via 1 and the top opening of the buried via 2 are seamlessly electrically connected at the inner layer LP via copper foil with a thickness of not less than 1 oz. The connection area is free of oxidation and cold solder joints, ensuring continuous signal and power transmission.

[0044] Furthermore, it allows buried holes 2 and blind holes 1 to be set in an overlapping manner, or it allows them to be set independently without overlapping.

[0045] In some embodiments, the number of buried vias corresponds to the number of blind vias, and the blind vias are overlapped with the corresponding buried vias to form at least one signal via stack.

[0046] In some embodiments, the top pad of the buried via and the bottom pad of the blind via have an overlapping area, and the area of ​​the overlapping area is not less than 50% of the area of ​​the top pad of the buried via and not less than 50% of the area of ​​the bottom pad of the blind via, and the offset between the central axis of the blind via and the central axis of the buried via is not greater than 0.02 mm.

[0047] In some embodiments, blind via 1 and buried via 2 are vertically overlapped to form signal via stacking. That is, blind via 1 and buried via 2 are vertically aligned and overlapped, with blind via 1 directly above buried via 2, meaning their central axes are the same. By vertically overlapping blind via 1 and buried via 2, signals can firstly enter the inner layer from the surface layer via blind via 1 and then directly interface with the buried via 2 below to continue transmitting to deeper layers, eliminating the need for horizontal leads and effectively shortening the signal path, avoiding additional impedance and noise coupling. Secondly, since blind via 1 and buried via 2 overlap in their vertical projection, they share a common footprint, significantly reducing the encroachment on surface and inner layer routing channels and freeing up valuable space for high-density wiring. Simultaneously, for power or ground network via overlap, this vertical overlap reduces series inductance and improves the response efficiency of decoupling capacitors, thereby improving power integrity. Furthermore, when blind via 1 and buried via 2 are coaxially overlapped, two drilling and electroplating operations can be completed sequentially at the same drilling location. Compared to the staggered design, it is easier to control the alignment accuracy between layers and simplifies the process flow. Overall, this overlap rule brings positive benefits in terms of electrical performance, space utilization, and manufacturing yield.

[0048] In other embodiments, blind via 1 and buried via 2 can be staggered micro-overlay vias, that is, the offset between the central axis of blind via 1 and the central axis of buried via 2 is no more than 0.02mm. In this way, while maintaining a high wiring density, the extreme requirements for interlayer alignment accuracy are reduced, and the production yield is improved. This makes it suitable for factories with slightly weaker interlayer alignment capabilities or scenarios with slightly lower array density requirements.

[0049] Furthermore, the top pad of the buried via 2 and the bottom pad of the blind via 1 have an overlapping area, and the area of ​​the overlapping area is not less than 50% of the area of ​​the top pad of the buried via 2 and not less than 50% of the area of ​​the bottom pad of the blind via 1. In some embodiments, the blind via 1 and the buried via 2 are arranged in an overlapping alignment in the vertical direction. In this case, the annular pad at the top of the buried via 2 and the annular pad at the bottom of the blind via 1 must have a common intersection area that covers each other in the vertical projection direction. This area must not be less than 50% of the area of ​​the top pad of the buried via 2 and not less than 50% of the area of ​​the bottom pad of the blind via 1. That is, both of these benchmark thresholds must be met to ensure that the overlapping area is sufficient. This ensures that the two types of vias of different layers have a sufficiently large physical contact and electrical conduction cross section at the intersection, thereby effectively reducing contact resistance, enhancing the anti-peel strength of the pads, and preventing the risk of poor soldering, open circuits, or reliability degradation caused by misalignment (layer misalignment) during the manufacturing process. This is an important structural constraint to ensure the electrical performance and long-term stability of PCB boards with high-density interconnection.

[0050] Furthermore, the buried via 2 contains a partially filled first conductive filler, the top surface of which protrudes from the buried via and forms a pad; the blind via 1 contains a fully filled second conductive filler, the top surface of which protrudes from the blind via and forms a pad. In some embodiments, the top surface of the first conductive filler protrudes from the buried via 2 and forms the top pad of the buried via 2, and the top surface of the second conductive filler protrudes from the blind via 1 and forms the bottom pad of the blind via 1. The top pad of the buried via 2 and the bottom pad of the blind via 1 form the aforementioned overlapping area on the inner layer LP, allowing current and signals to be transmitted from one conductive filler to another from this overlapping area, thereby achieving vertical interconnection between vias in different layers.

[0051] For example, the buried via 2 is provided with a first conductive filler that is not completely filled, that is, the buried via is filled with micro-voids in a controllable manner, allowing for the existence of tiny shrinkage pores with a volume fraction of <3% in the center of the buried via, thus avoiding stress concentration at the inner LP interface. The blind via 1 is filled with void-free overfill to ensure a dense connection interface with the buried via 2.

[0052] Furthermore, such as Figure 4 As shown, an annular groove 7 is provided around the signal via formed by blind via 1 and buried via 2. The annular groove 7 is concentrically arranged with the pad. For example, an annular groove 7 with a width of 0.1 mm is etched 0.15 mm around the pad of the signal via in the inner layer LP. The groove is filled with flexible solder resist or left empty (without copper). This annular groove 7 severs the rigid connection between the large area of ​​copper on the inner layer LP and the pad, allowing the pad to have a small radial displacement during thermal expansion, thereby absorbing the shear stress caused by CTE mismatch.

[0053] In some embodiments, blind vias 1 and buried vias 2 can be filled with all copper to obtain excellent conductivity and heat dissipation performance; or filled with conductive silver paste to achieve lower cost and suitability for low-frequency applications; or filled with non-conductive epoxy resin and then cap plating can effectively avoid short circuit risks, especially suitable for vias under high-density BGA packages; or a hollow, unfilled via method can be used, with only the via walls metallized and a reinforcing ring added at the interface of the LP layer to enhance structural strength.

[0054] In some embodiments, the borehole 2 is covered with a conductive paste layer.

[0055] In some embodiments, a dielectric material is provided on the upper and / or lower surfaces of the inner LP layer; the dielectric material includes a ceramic film or aerogel. For example, an extremely thin high-k ceramic film or low-k aerogel layer is introduced as an interface modification layer on the upper and lower surfaces of the inner LP layer to change the dielectric constant distribution at the LP layer interface, actively adjust parasitic capacitance, and achieve more precise impedance matching without significantly altering the pad geometry.

[0056] Furthermore, in some embodiments, the diameter of the blind via 1 is larger than the diameter of the buried via 2. Or in yet other embodiments, the diameter of the blind via 1 is equal to the diameter of the buried via 2, but their taper directions are opposite (the blind via 1 has a positive taper and the buried via 2 has an inverted taper), which can accommodate special wiring requirements, such as fan-out scenarios where the L1 layer space is ample but the inner LQ layer space is extremely limited.

[0057] Furthermore, in some embodiments, the top layer L1 to the inner layer LP are located in the flexible region, while the LP layer to the LQ layer cross the rigid-flexible transition region into the rigid region. The flexible region uses a polyimide (PI) substrate, while the rigid region uses FR4 or a high-frequency board material. Furthermore, the signal via stack structure formed by blind vias 1 and buried vias 2 requires a specially designed stress-relief meniscus to accommodate the bending stress in the flexible region.

[0058] In some embodiments, a blind via 1 is provided between the top layer L1 and the inner layer LP, and a buried via 2 is provided between the inner layers LP and LQ. A single blind via 1 and a single buried via 2 form a single signal via stack, i.e., a single signal channel. In other embodiments, the original single signal channel blind-buried via vertical stack can be expanded into a differential signal pair or even a four-channel array layout, i.e., two of the signal via stacks form a differential signal pair; or four of the signal via stacks form a four-channel array. For example, in the same vertical region from L1 to LQ, at least two signal via stacks are provided to form a differential pair, or four via stacks form a four-channel array, with a ground via between two adjacent differential signal pairs or between two adjacent four-channel arrays. Each of these signal via stacks includes a blind via segment from L1 to LP and a buried via segment from LP to LQ, achieving vertical conductivity at the LP layer. Simultaneously, a shared grounding via wall is arranged between adjacent differential pairs or channels. The grounding vias within this wall also employ a blind-via-buried via stack, meaning they include blind via segments extending from the top layer to the inner LP layer, and buried via segments extending from the inner LP layer to the inner LQ layer. The blind via segments and buried via segments are electrically connected at the LP layer, meaning the grounding vias are respectively connected to L1, LP, LQ, and the intermediate reference ground layer, forming a low-impedance vertical shielding barrier. This design is specifically for high-speed differential signal transmission such as PCIe, USB4, and Ethernet. By sharing the grounding via wall, it effectively cuts off the electromagnetic coupling path between adjacent channels, suppressing even-mode noise and crosstalk to the greatest extent, ensuring signal integrity at high data rates.

[0059] In some other embodiments, multiple ground vias are arranged around the signal vias formed by blind via 1 and buried via 2. These ground vias are arranged in a surrounding pattern and are respectively connected to each ground layer in the printed circuit board. For example, as shown... Figure 4 As shown, eight ground vias 6 are arranged in a regular octagon around the signal vias, 0.4 mm from the center of the signal vias. These eight ground vias extend from the top L1 layer to the bottom LN layer (through-hole) and are tightly connected to the ground layers in the printed circuit board, thereby constructing a complete coaxial transmission line environment, reducing loop inductance by 50% and improving crosstalk rejection ratio by 15 dB.

[0060] Furthermore, the inner layer LQ+1 below the inner layer LQ is connected to the bottom layer LN via a through-hole. Alternatively, in some embodiments, the inner layer LQ+1 below the inner layer LQ is connected to the bottom layer LN via a second blind via. In the printed circuit board provided in this application, the connection between the inner layer LQ+1 below the inner layer LQ and the bottom layer LN can be flexibly selected according to design requirements; that is, it can be directly penetrated by a conventional through-hole, or a second blind via can be used to achieve partial interlayer conductivity. In certain non-critical signal networks, to balance manufacturing costs and electrical performance, vias running directly from the LQ+1 layer to the LN layer are allowed to be retained. Back-drilling is used to remove excess vias near the bottom layer (i.e., removing the invalid stub segment near the LN side between the LQ+1 and LN layers, i.e., removing the metallized via wall residue from the LQ+1 layer below the inner LQ layer to the bottom LN layer that does not participate in signal conduction and causes signal reflection and impedance discontinuity). Only short via segments required for effective transmission are retained. These, along with the aforementioned blind via 1 (L1-LP) and buried via 2 (LP-LQ), form a hybrid interlayer connection scheme of "overlapping vias + short back-drilled vias." For non-critical signals with less stringent rate requirements, using back-drilled vias instead of fully blind and buried overlapped vias can significantly reduce the difficulty of drilling and electroplating processes and material costs. Simultaneously, removing the stub avoids signal reflection caused by long vias, thus maintaining basic signal quality. For truly high-speed critical signals (such as PCIe and USB4), the complete fully blind buried via structure is retained to ensure optimal signal integrity. This differentiated design achieves an optimal trade-off between cost and performance in the overall PCB design, making it particularly suitable for scenarios requiring strict cost control in mass production.

[0061] Furthermore, when the inner layer LQ+1 below the inner layer LQ is connected to the bottom layer LN through a second blind via, the electrical connection between the second blind via and the buried via 2 is the same as the connection between the blind via 1 and the buried via 2.

[0062] Figures 2 to 3 A schematic diagram of an 8-layer PCB board architecture according to an embodiment of this application is shown. Please refer to [link / reference]. Figures 2 to 3 As shown in the embodiment of this application, in the 8-layer PCB board, blind vias are provided between layers L1 and L3, buried vias are provided between layers L3 and L6, and blind vias are provided between layers L6 and L8, forming a continuous interconnect path between layers L1 and L8. Specifically, the blind vias between layers L1 and L3 and the buried vias between layers L3 and L6 vertically overlap on layer L3, forming a continuous vertical interconnect path between layers L1 and L6.

[0063] In some embodiments, the architecture of the 8-layer PCB board provided in this application, from top to bottom, is as follows:

[0064] L1 Signal layer 0.5 1080 prepreg 60 L2 grounding layer 1.0 FR4 core board 100 L3 Inner signal layer 1.0 1067 prepreg 80 L4 grounding layer 1.0 FR4 core board 200 L5 grounding layer 1.0 1080 prepreg 90 L6 Power layer / signal layer 1.0 FR4 core board 150 L7 grounding layer 1.0 2116 Prepreg 120 L8 Signal layer 0.5 1080 prepreg 60

[0065] Furthermore, for the blind vias located from the top layer L1 to the inner layer L3, laser drilling is used to set the via diameter within the range of 0.1mm to 0.15mm, the copper thickness of the via wall to be 18μm to 35μm, and the via depth corresponding to the total thickness of the L1-L3 layers (approximately 0.2mm to 0.3mm). It is essential to ensure that the via walls are free of voids and cracks. In this embodiment, the vias are plugged with resin and then copper-plated to ensure the surface flatness of the L1 layer, which is beneficial for SMT mounting. Furthermore, the top opening of the blind via is located on the high-speed signal pads or traces of the L1 layer, while the bottom opening is located in the interconnect area of ​​the L3 layer. The opening diameter must be 0.05mm to 0.1mm larger than the via diameter to facilitate subsequent electroplating filling. In addition, blind vias can be evenly distributed on the high-speed paths of layers L1-L3 according to signal transmission requirements. The spacing between adjacent blind vias should not be less than 0.3mm to prevent crosstalk. At the same time, it is also necessary to ensure that the blind vias and the buried vias set in layers L3 to L6 are aligned in the vertical direction to achieve complete via interconnection.

[0066] Among them, L2 and L4 are grounding layers (ground signal layers).

[0067] Furthermore, for the buried vias located in the inner layers L3 to L6, mechanical drilling or laser drilling is used, with a hole diameter of 0.15mm~0.2mm, a copper wall thickness of 18μm~35μm, and a hole depth corresponding to the total thickness of layers L3-L6 (approximately 0.3mm~0.45mm). In this embodiment, electroplating is used to fill the holes to achieve a gapless connection. Furthermore, in terms of placement, the top pad of the buried via is located on layer L3, partially overlapping with the bottom pad of the aforementioned blind via on layer L3. The overlapping area is required to be no less than 50% of the area of ​​any pad, and the allowable offset between the centerlines of the buried via and the blind via is ≤0.02mm. In addition, the bottom opening of the buried via is located on the signal or power trace of layer L6, and its opening diameter is consistent with the bottom opening of the blind via, thereby ensuring a reliable connection between the buried via and the lower layer traces, and forming a complete vertical stacked via interconnect path with the upper layer blind via.

[0068] Among them, L5 and L7 are grounding layers (ground signal layers).

[0069] Furthermore, in the L3 layer, the bottom opening of the blind via and the top opening of the buried via are seamlessly electrically connected by copper foil with a thickness of not less than 1 oz. The connection area is free of oxidation and cold solder joints, ensuring continuous transmission of signals and power.

[0070] Furthermore, blind vias and buried vias are stacked vertically. The pads on the L3 layer are designed as fused pads with a diameter optimized to 0.32mm (slightly larger than the maximum of both) to cover alignment errors. And on the L2 and L4 layers, near the signal via stacks, the anti-pads are designed as elliptical shapes with their major axis along the signal path, and their size is 0.15mm larger than the pads to compensate for the additional parasitic capacitance caused by the via stacks.

[0071] Furthermore, the blind vias between layers L6 and L8, and their electrical connections with buried vias, are the same as those between layers L1 and L3, and will not be described again here.

[0072] like Figures 5a to 5d As shown (horizontal axis is frequency (GHz), vertical axis is S11 or S12 loss (dB)), according to HFSS simulation, in the range of 0-10GHz, taking 10GHz as an example, the S11 loss is -11.996dB, which is 9.5249dB lower than the traditional via; the S12 loss is 3.8377dB lower than the traditional via, with no obvious resonance valley.

[0073] In some other embodiments, this application performs in-depth impedance and loss optimization on the aforementioned 8-layer PCB board to obtain an ultra-high-speed, low-loss optimized structure. Specifically, the fusion pad on the L3 layer is designed as a three-layer stepped structure: the lower layer (contact via) has a diameter of 0.35mm, the middle layer 0.30mm, and the upper layer (contact blind via) 0.25mm. This gradient structure results in a more uniform electric field distribution and eliminates the capacitance abrupt change at the L3 interface. Furthermore, when L3 is used as a reference plane, its anti-pad size is increased to 0.50mm based on simulation results, and a teardrop transition is used to further reduce local capacitance.

[0074] In addition, eight grounding vias can be arranged in a regular octagon around the signal vias formed by blind and buried vias, 0.4 mm from the center of the signal vias. These eight grounding vias are drilled from L1 to L8 (through vias) and are tightly connected to the ground plane on all reference layers L2, L5, and L7.

[0075] In some embodiments, this application targets the automotive electronics or industrial control fields, focusing on solving the fracture problem caused by thermal stress to obtain a high-reliability automotive-grade structure based on the aforementioned 8-layer PCB board. Specifically, a 0.1mm wide annular groove is etched 0.15mm around the L3 layer via pads, filled with flexible solder resist or left empty (without copper). This annular groove severs the rigid connection between the large copper area of ​​the L3 layer and the pads, allowing for slight radial displacement of the pads during thermal expansion, thereby absorbing the shear stress caused by CTE mismatch. Furthermore, micro-void controllable filling is used for buried vias, allowing for micro-shrinkage holes with a volume fraction of <3% at the center of the via (between L4 and L5), avoiding stress concentration at the L3 interface. Blind vias (L1-L3 layers) are filled with void-free overfill to ensure a dense interface with the buried vias.

[0076] After 1000 thermal cycling tests (-55°C to +125°C), the resistance change rate of the above structure is <1%, and cross-sectional analysis shows that there are no cracks at the L3 interface.

[0077] Therefore, in terms of electrical performance, this application forms a continuous vertical channel from L1 to the inner layer LQ by directly connecting blind vias and buried vias at the inner layer LP, eliminating the need for horizontal interlayer traces required in traditional designs. This shortens the signal path length by 30%-50%. HFSS electromagnetic simulation verifies that at 10GHz, the stacked via structure reduces the equivalent series inductance by approximately 20%-35% compared to the traditional staggered via structure, significantly reducing energy loss and timing offset. Simultaneously, this signal stacked via structure merges multiple previously dispersed impedance abrupt changes into a continuous impedance region, making the impedance change during layer switching smoother. Figure 6a and Figure 6b As shown ( Figure 6a As shown in Figure b, the vertical axis represents instantaneous impedance (Ω), and the horizontal axis represents time (ns). TDR testing shows that the impedance fluctuation of the stacked via structure in this application is controlled within ±5Ω throughout the transmission path (compared to ±15-±20Ω for traditional through-hole structures), and the return loss (S11) is improved by 6-10dB, making it particularly suitable for high-speed interface standards such as PCIe 5.0 / 6.0 and SerDes. Furthermore, the vertical stacked vias, combined with the densely arranged grounding vias around them, provide a continuous, low-impedance axial return path for high-frequency signals, preventing the return current from being forced to detour between reference planes. The reduction in loop inductance effectively suppresses synchronous switching noise and electromagnetic radiation. Near-field scanning tests show that the near-field radiation intensity of the PCB board using this structure is reduced by 3-5dB compared to traditional designs.

[0078] In terms of spatial layout and wiring capabilities, this application saves valuable surface and inner layer wiring resources. Areas previously occupied by short lines can be used to arrange more signal lines or increase line width / spacing. Under the same board size, the wiring density of an 8-layer HDI board using the structure of this application can be increased by 15%-25%, or a larger safety distance can be reserved for critical high-speed signals to reduce crosstalk risk. At the same time, the space saved by the signal via stacking structure allows designers to arrange more grounding via arrays around critical signal vias, forming a shielding structure similar to a "Faraday cage". Three-dimensional full-wave electromagnetic field simulation shows that after setting 4-6 grounding vias around the via stacking, the crosstalk coupling coefficient between adjacent channels is reduced by 8-12dB, effectively ensuring the transmission purity of high-speed differential signals or sensitive clock signals.

[0079] Regarding process feasibility and reliability, this application overlaps blind vias and buried vias to form a signal stacked via structure, avoiding additional lamination steps. Compared to some complex second-order staggered via schemes, the stacked via design of this application can reduce one lamination cycle, shortening the production cycle by approximately 10%, while also reducing the cumulative alignment error between layers caused by multiple laminations, thus reducing the risk of process defects. In terms of structural reliability, this application achieves direct connection between the bottom layer of blind vias and the top layer of buried vias in the inner LP layer, avoiding the mechanical stress concentration problem of creating tiny pads and short lines on a thin dielectric layer in traditional designs. Thermal cycling test results show that the resistance change rate of the stacked via structure of this application is less than 5% during temperature cycling tests from -55℃ to +125℃, and its long-term reliability is superior to staggered via structures containing multiple micro-pads.

[0080] It should also be understood that the division of modules or units in the embodiments of this application is illustrative and only represents a logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0081] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0082] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A printed circuit board, characterized in that, The printed circuit board includes a top layer, several inner layers, and a bottom layer arranged from top to bottom; At least one blind hole is provided between the top layer and the inner layer LP, and the top layer and the inner layer LP are connected through the blind hole. The inner layers LP-1 and LP+1 located on both sides of the inner layer LP are ground layers, and there is at least one inner layer between the top layer and the inner layer LP. At least one buried via is provided between the inner layer LP and the inner layer LQ, and the inner layer LP and the inner layer LQ are connected through the buried via; the inner layers LQ-1 and LQ+1 located on both sides of the inner layer LQ are both ground layers, and there is at least one inner layer between the inner layer LQ and the bottom layer. The bottom opening of the blind hole and the top opening of the buried hole are electrically connected at the inner layer LP.

2. A printed circuit board according to claim 1, characterized in that, The number of buried vias corresponds to the number of blind vias, and the blind vias are overlapped with the corresponding buried vias to form at least one signal via stack.

3. A printed circuit board according to claim 2, characterized in that, The top pad of the buried via and the bottom pad of the blind via have an overlapping area, and the area of ​​the overlapping area is not less than 50% of the area of ​​the top pad of the buried via and not less than 50% of the area of ​​the bottom pad of the blind via, and the offset between the central axis of the blind via and the central axis of the buried via is not greater than 0.02mm.

4. A printed circuit board according to claim 2, characterized in that, Multiple grounding vias are arranged around the signal vias, and the multiple grounding vias are arranged in a surrounding manner and are respectively connected to each ground layer in the printed circuit board.

5. A printed circuit board according to claim 1, characterized in that, The minimum number of inner layers sandwiched between the inner layer LP and the top layer is selected.

6. A printed circuit board according to claim 1, characterized in that, The minimum number of inner layers sandwiched between the inner layer LQ and the bottom layer is selected.

7. A printed circuit board according to claim 1, characterized in that, The diameter of the blind hole is larger than that of the buried hole; or, the diameters of the blind hole and the buried hole are equal and the tapers of the blind hole and the buried hole are opposite.

8. A printed circuit board according to claim 2, characterized in that, Two of the signal vias form a differential signal pair; or four of the signal vias form a four-channel array; a grounding via is provided between two adjacent differential signal pairs or between two adjacent four-channel arrays; wherein each of the signal vias or the grounding vias includes a blind via segment extending from the top layer to the inner layer LP, and a buried via segment extending from the inner layer LP to the inner layer LQ, the blind via segment and the buried via segment being electrically connected at the LP layer.

9. A printed circuit board according to claim 1, characterized in that, The LQ+1 layer is connected to the bottom layer via a through-hole; or, the LQ+1 layer is connected to the bottom layer via a second blind via.

10. A printed circuit board according to claim 9, characterized in that, The through hole extends from layer LQ+1 along the thickness direction to the bottom layer; the through hole is a back-drilled through hole.

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