A high multi-layer server printed circuit board manufacturing process

Abstract

The present disclosure relates to the technical field of printed circuit board manufacturing, and provides a high multi-layer server printed circuit board manufacturing process, comprising: splitting a server printed circuit board to be manufactured into multiple pressing units; performing inner layer pattern manufacturing, first positioning hole and first slot hole processing on each pressing unit respectively, and performing first pin positioning lamination through the first slot hole to form a sub-board; manufacturing second positioning holes and second slot holes on the sub-board, and setting a prepreg with a predetermined dielectric constant and thickness as an impedance compensation layer between adjacent sub-boards; performing second pin positioning lamination through the second slot hole to form a mother board; and finally completing drilling, electroplating and outer layer circuit manufacturing to obtain a high multi-layer server printed circuit board. The present disclosure improves the interlayer alignment accuracy and impedance consistency of the high multi-layer PCB through two-stage pin positioning lamination combined with an impedance compensation layer design, and is suitable for the manufacturing of high multi-layer server printed circuit boards.

Description

Technical Field

[0001] This disclosure relates to the field of printed circuit board manufacturing technology, and more specifically, to a manufacturing process for a high-multilayer server printed circuit board. Background Technology

[0002] With the development of technologies such as cloud computing, big data and artificial intelligence, the requirements of server systems for data processing capabilities and high-speed signal transmission performance are constantly increasing. As a key basic component of server hardware, the number of layers and integration of high-multilayer printed circuit boards (PCBs) are continuously improving, and 16-layer and above structures are gradually becoming the mainstream development direction.

[0003] In existing technologies, high-multilayer server PCBs typically employ manufacturing processes such as multiple lamination stacking, precision drilling, and electroplating interconnects to achieve complex interlayer interconnect structures and meet high-speed signal transmission requirements through impedance control design. Currently, this type of product has relatively mature mass production capabilities for structures with 12 layers or less, and is gradually expanding to higher-layer products. However, in the manufacturing process of high-multilayer PCBs, the increased number of stacked layers and structural complexity lead to greater difficulty in controlling interlayer alignment accuracy and fluctuations in impedance consistency, thereby affecting the electrical performance and reliability of the product.

[0004] Therefore, improving interlayer alignment accuracy and stabilizing impedance consistency during the manufacturing process of high-multilayer server printed circuit boards is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The purpose of this disclosure is to provide a manufacturing process for high-multilayer server printed circuit boards, which solves the problems mentioned in the background art.

[0006] This disclosure provides a manufacturing process for a high-multilayer server printed circuit board, including: Step S100: The server printed circuit board to be manufactured is divided into multiple lamination units according to a preset number of layers. Each lamination unit includes at least one core board, and the stacking order of each lamination unit is determined. Step S200: Transfer the inner layer pattern of the core board in each of the pressing units, make the first positioning hole, make the first slot based on the first positioning hole, and perform the first pin positioning lamination on each of the core boards stacked in the stacking order through the first slot to form multiple sub-boards. Step S300: A second positioning hole is made on each of the sub-boards, and a second slot is made according to the second positioning hole. At the same time, a prepreg is provided between adjacent sub-boards as an impedance compensation layer. The prepreg has a predetermined dielectric constant and thickness and is used to compensate for the deviation of the overall impedance after lamination. Step S400: The sub-boards stacked in the stacking order are subjected to a second pin positioning lamination through the second slot to form a mother board; Step S500: Drilling, electroplating and outer layer circuitry are performed on the motherboard to obtain a high-multilayer server printed circuit board.

[0007] Optionally, step S300 includes: Step S310: Perform expansion and contraction measurements on each of the sub-boards, and determine the compensation amount for each of the sub-boards based on the expansion and contraction measurement results; Step S320: According to the compensation amount, a second positioning hole is made on each of the sub-boards using a punching machine or laser drilling method, and a second slot is made according to the second positioning hole. The second positioning hole is closer to the effective graphic area of ​​the sub-board than the first positioning hole. In step S330, before each of the sub-boards is stacked, a prepreg is provided between adjacent sub-boards as an impedance compensation layer.

[0008] Optionally, step S310 includes: Step S311: Use an X-ray inspection device or a CCD optical measurement device to measure the position offset of multiple targets on each of the sub-plates; Step S312: Based on the difference between the actual position and the theoretical position of each target, calculate the expansion and contraction rate of each sub-plate in the X-axis and Y-axis directions; Step S313: Determine the compensation amount of each sub-plate according to the expansion and contraction rate of each sub-plate, so that the second positioning holes of each sub-plate are aligned with each other when stacked.

[0009] Optionally, in step S300, the dielectric constant of the prepreg is selected based on the target impedance value of the circuit layer of the adjacent sub-board, the thickness of the prepreg is determined based on the target thickness of the dielectric layer after lamination, the resin content of the prepreg is 45%~65%, and the flowability of the prepreg is 15mm~30mm.

[0010] Optionally, the prepreg includes a first adhesive layer, a dielectric modulating core layer, and a second adhesive layer stacked sequentially. The resin content of the first adhesive layer and the second adhesive layer is 62%~68%, and the flowability is 25mm~32mm; the resin content of the dielectric control core layer is 42%~48%, and the flowability is 12mm~16mm. The dielectric control core layer contains a composite dielectric filler composed of barium titanate and molten silica in a mass ratio of 1:(2.5~4), and the composite dielectric filler accounts for 20%~35% of the total mass of the dielectric control core layer. The thickness of the dielectric control core layer accounts for 65% to 80% of the total thickness of the prepreg; the curing temperature of the first adhesive layer and the second adhesive layer is lower than the curing temperature of the dielectric control core layer.

[0011] Optionally, step S200 includes: Step S210: Perform a stacking and matching check on each core board layer in each pressing unit, and select a matching prepreg according to the expansion and contraction characteristics of each core board layer. Step S220: A first positioning hole is made in the process edge area of ​​each layer of the core board. The first positioning hole includes an inner ring positioning hole and an outer ring positioning hole. The inner ring positioning hole is set close to the effective graphic area of ​​the core board. Step S230: Using the inner ring positioning hole as a reference, a first slot is made by punching, and the positional deviation of the first slot in each core board is measured after the first slot is made; if the positional deviation of the first slot exceeds a preset threshold, the core board is scrapped or reworked. Step S240: After the core boards and the corresponding prepregs are stacked alternately, the first pin positioning lamination is performed under the conditions of a lamination temperature of 170℃~190℃ and a lamination pressure of 1.5MPa~2.5MPa for 60 minutes~90 minutes to form multiple sub-boards.

[0012] Optionally, in step S240, the heating rate during the lamination process is 1.5℃ / min to 2.5℃ / min, and the cooling rate is 1.0℃ / min to 2.0℃ / min.

[0013] Optionally, step S400 includes: Step S410: Divide the multiple sub-boards into several expansion and contraction level groups according to the compensation amount of each sub-board, pair the sub-boards belonging to the same expansion and contraction level group, and pre-stack them according to the stacking order determined in step S100, so that the second positioning holes of each sub-board are aligned with each other in the vertical direction. Step S420: A prepreg as an impedance compensation layer is placed between the adjacent sub-boards after pre-stacking, and a pre-compression pressure of 0.5MPa to 1.0MPa is applied to the pre-stacking stacked structure and maintained for 5 to 10 minutes to remove interlayer air bubbles and make the prepreg adhere tightly to the adjacent sub-boards. Step S430: Transfer the pre-compressed laminated structure to a laminator and perform a second pin-positioning lamination under the conditions of a pressing temperature of 180℃~200℃ and a pressing pressure of 2.0MPa~3.0MPa for 80 minutes~120 minutes to form a mother board; Step S440: After lamination is completed, the motherboard is cooled and the interlayer alignment and overall impedance of the motherboard are tested; if the test results do not meet the preset requirements, the process parameters are adjusted accordingly.

[0014] Optionally, in step S430, the heating rate during the lamination process is 1.0℃ / min to 2.0℃ / min, the cooling rate is 0.5℃ / min to 1.5℃ / min, and the vacuum degree of the laminator cavity during the lamination process is controlled below 10Pa.

[0015] Optionally, the number of the pressing units is 2 to 4, each pressing unit contains 2 to 6 core board layers, and the number of mother board layers is 16 or more.

[0016] As can be seen from the above technical solutions, the high-multilayer server printed circuit board manufacturing process in the exemplary embodiments of this disclosure has at least the following advantages and positive effects: This disclosure first divides the high-multilayer server printed circuit board into multiple lamination units, and performs a first-stage pin-positioning lamination to form a sub-board in each unit. Then, using second positioning holes and second slots, a second-stage pin-positioning lamination is performed to form a motherboard. This allows the positioning reference to be continuously updated during the manufacturing process, reducing the accumulation of core board expansion and contraction errors during multiple lamination processes and improving the interlayer alignment accuracy of each layer. Simultaneously, a prepreg with a predetermined dielectric constant and thickness is placed between adjacent sub-boards as an impedance compensation layer to compensate for impedance deviations caused by changes in dielectric layer thickness after lamination, resulting in more stable overall impedance. By combining two-stage pin-positioning lamination with impedance compensation, the interlayer positioning accuracy of the high-multilayer server printed circuit board is improved, while further enhancing the impedance consistency of high-speed signal transmission, reducing product manufacturing errors, and improving product yield, electrical performance, and long-term reliability.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings: Figure 1 A flowchart illustrating a high-multilayer server printed circuit board manufacturing process according to an embodiment of this disclosure is shown. Detailed Implementation

[0019] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0020] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0021] The manufacturing process of a high-multilayer server printed circuit board provided in this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only for explaining this disclosure and are not intended to limit the scope of protection of this disclosure.

[0022] It should be noted that, unless otherwise specified in this disclosure, high-multilayer server printed circuit boards refer to printed circuit boards with 16 or more layers, suitable for electronic products such as servers, high-performance computing devices, artificial intelligence servers, data center switching equipment, and high-speed network communication equipment. Because these types of printed circuit boards are characterized by a large number of layers, large board thickness, high interlayer interconnection density, and high requirements for high-speed signal integrity, they have high requirements for interlayer alignment accuracy and impedance consistency.

[0023] Furthermore, the terms "lamination unit," "sub-board," and "mother board" used in this disclosure are all names of process stages in the manufacturing process. Specifically, a lamination unit refers to a localized laminated structure pre-divided according to the overall laminated structure; a sub-board refers to an intermediate laminated structure formed after the first positioning lamination of multiple core boards; and a mother board refers to the overall laminated structure formed after the second positioning lamination of multiple sub-boards. These names are used only for the purpose of illustrating the technical solution of this disclosure and do not constitute a limitation on the scope of protection of this disclosure.

[0024] Please see Figure 1 This disclosure provides a manufacturing process for a high-multilayer server printed circuit board, including steps S100 to S500.

[0025] Step S100: The server printed circuit board to be manufactured is divided into multiple lamination units according to a preset number of layers. Each lamination unit includes at least one core board, and the stacking order of each lamination unit is determined.

[0026] It should be noted that as the number of layers in server PCBs continues to increase, if all core boards are laminated together in one go, the different degrees of thermal expansion, contraction, and stress release that occur during the heating, pressurization, and resin flow of each core board can easily cause cumulative misalignment of the circuit positions in each layer. This is especially true for high-multilayer PCBs with 16 or more layers, or even 20 or 24 or more layers, where the cumulative error is more pronounced. This can easily lead to a decrease in interlayer alignment accuracy, affecting the subsequent drilling quality and high-speed signal transmission performance.

[0027] Therefore, this disclosure first divides the entire high-multilayer server printed circuit board into multiple lamination units, so that multiple core boards first complete local lamination and then perform overall lamination, thereby reducing the number of core boards in a single lamination process, reducing the accumulation of thermal expansion error and resin flow error, and improving the interlayer positioning accuracy during subsequent overall lamination.

[0028] In this embodiment, the number of lamination units can be determined based on the total number of layers on the server printed circuit board. For example, when the server PCB has 16 layers, it can be divided into 2 to 4 lamination units; when the server PCB has 20 or 24 layers, it can be divided into 3 to 6 lamination units. Of course, the number of lamination units can also be adjusted according to the product thickness, circuit density, board material characteristics, and production equipment capabilities, and this disclosure does not limit this.

[0029] Preferably, each lamination unit includes 2 to 6 core layers, with corresponding prepregs placed between adjacent core layers. The core layers are preferably made of FR-4 copper-clad laminate, high-speed low-loss resin copper-clad laminate, BT resin copper-clad laminate, or other insulating substrates suitable for high-speed server PCB manufacturing. For high-speed server PCBs, high-speed materials with low dielectric constant and low dielectric loss factor can also be used to meet the requirements of high-speed signal transmission.

[0030] It should be noted that different core boards typically exhibit varying thermal expansion properties due to differences in glass fiber arrangement direction, resin content, copper foil thickness, and material batches. To further reduce expansion and contraction errors after the first lamination, this embodiment preferably groups core boards with similar thermal expansion properties into the same lamination unit, ensuring that each core board maintains a relatively consistent expansion and contraction trend during lamination, thereby reducing interlayer relative displacement.

[0031] In some embodiments, the division of lamination units is preferably determined by combining the number of product layers, board thickness, copper thickness distribution, high-speed signal layer location, and lamination equipment capabilities. For example, when the server printed circuit board has a 16-layer structure, it can be divided into two 8-layer lamination units or four 4-layer lamination units; when the server printed circuit board has a 20-layer structure, it can be divided into four 5-layer lamination units, or into two 6-layer lamination units and two 4-layer lamination units; for structures with 24 layers or more, 4 to 6 lamination units can be used for graded lamination.

[0032] Preferably, the high-speed signal layer, the reference ground layer, and the power layer are divided into the same lamination unit to reduce the relative displacement of the high-speed signal reference surface during lamination and improve impedance control stability.

[0033] In this embodiment, the stacking order is determined according to the final server PCB design file. It can be arranged in sequence according to the correspondence of the circuit layer, reference plane layer, power layer and signal layer, so that each lamination unit can finally form an overall stacking structure that meets the design requirements.

[0034] Preferably, the stacking sequence adopts a symmetrical arrangement about the center plane of the PCB, so that the upper and lower structures remain basically consistent, thereby reducing the overall warping caused by uneven heating during the lamination process and improving the dimensional stability of the final motherboard. For different server PCB products, asymmetrical stacking can also be adopted according to impedance design requirements, interlayer interconnection relationships, or high-speed signal routing requirements, and this disclosure does not impose any restrictions on this.

[0035] By setting up the above, the entire high-multilayer server printed circuit board is divided into multiple lamination units, and local lamination is completed separately. This not only reduces the cumulative positioning error caused by simultaneous lamination of multilayer core boards, but also creates conditions for re-establishing the positioning reference in the future. This improves the interlayer alignment accuracy in the entire high-multilayer server printed circuit board manufacturing process and provides a stable foundation for subsequent second positioning lamination and impedance control.

[0036] Step S200: Transfer the inner layer pattern of the core board in each of the pressing units, make the first positioning hole, make the first slot based on the first positioning hole, and perform the first pin positioning lamination on each of the core boards stacked in the stacking order through the first slot to form multiple sub-boards.

[0037] In some embodiments, step S200 further includes steps S210 to S240, each of which is as follows.

[0038] Preferably, the first slot adopts an elongated oval slot structure, with its major axis parallel to the PCB reference edge. The slot width is 0.01mm to 0.05mm larger than the pin diameter, and the slot length is 0.20mm to 0.50mm larger than the pin diameter, to balance positioning accuracy and thermal expansion release capability. The first pin is preferably made of cemented carbide or tool steel, and its cylindrical positioning section forms a micro-clearance fit with the first slot to ensure high repeatability during positioning while absorbing minor displacements caused by thermal expansion during lamination. The positional error of each first slot is controlled within ±20μm.

[0039] It should be noted that this step is the first positioning lamination stage in the entire high-multilayer server printed circuit board manufacturing process. Its main purpose is to establish a unified positioning benchmark within each lamination unit and to form a dimensionally stable sub-board through local lamination, thus establishing a reliable initial positioning foundation for subsequent overall lamination. Compared with the prior art, which directly performs overall positioning lamination on all core boards, this disclosure prioritizes local positioning and local lamination, which can effectively reduce the cumulative positioning error generated in the first lamination process of high-layer PCBs.

[0040] In this embodiment, the inner layer pattern transfer refers to transferring the inner layer circuit pattern to the copper foil surface of each core layer according to the circuit design file of the server printed circuit board. Preferably, the pattern transfer can be completed using a dry film exposure and development process or a laser direct imaging (LDI) process. For server PCBs with high requirements for line width and spacing, laser direct imaging is preferred to improve circuit fabrication accuracy and reduce pattern position errors. Of course, other mature processes capable of inner layer circuit fabrication can also be used, and this disclosure does not limit this approach.

[0041] After the inner layer circuitry is fabricated, each core board is etched to form the predetermined inner layer conductors, power layer, and ground layer patterns. The fabricated circuitry is then subjected to automated optical inspection (AOI) or manual inspection to confirm that there are no defects such as open circuits, short circuits, gaps, or residual copper.

[0042] It should be noted that since all subsequent positioning is based on the core board after the circuit is manufactured, it is preferable to process the positioning holes after the circuit is manufactured and tested, so as to avoid the impact of dimensional changes during the circuit manufacturing process on the positioning accuracy.

[0043] In some embodiments, a first positioning hole is formed in the process edge area of ​​each core board layer. The first positioning hole is used to establish a unified positioning reference during the first lamination. Preferably, the first positioning hole includes an outer ring positioning hole disposed around the process edge and an inner ring positioning hole disposed near the effective pattern area. The outer ring positioning hole is mainly used for core board handling, equipment clamping, and coarse positioning; the inner ring positioning hole is mainly used for the first pin positioning lamination.

[0044] Furthermore, the inner positioning holes are preferably located close to the effective circuit area. The thermal expansion and resin flow generated during the lamination process of the server PCB primarily affect the effective circuit area. If the positioning holes are too far from the circuit area, a large cumulative error can easily form between the positioning reference and the actual circuit area. Placing the inner positioning holes closer to the effective circuit area allows for a more accurate reflection of the true size changes of the circuit area, improving the alignment accuracy of the circuit after the first lamination. For server PCBs of different sizes and with different numbers of layers, the position, number, and arrangement of the first positioning holes can be adjusted according to product design requirements, and this disclosure does not impose any limitations on this.

[0045] After the first positioning hole is made, the first slot is made using the first positioning hole as the machining reference. It should be noted that the first slot in this disclosure is not a normal process hole, but a positioning slot for the first pin positioning.

[0046] Preferably, the first slot is formed by punching, but it can also be formed by CNC milling, laser processing, or other processing methods that can ensure processing accuracy. The first slot is preferably formed along the position of the first positioning hole, maintaining a fixed positional relationship between the first slot and the first positioning hole. Since the subsequent pin is directly inserted into the first slot for positioning, the positional accuracy of the first slot directly determines the interlayer alignment accuracy after the first lamination.

[0047] In this embodiment, the position of the first slot is preferably detected after the first slot is fabricated. Specifically, a CCD vision inspection device, an image measuring instrument, or a high-precision coordinate measuring device can be used to measure the positional deviation of the first slot relative to the first positioning hole and the circuit target. If the positional deviation of the first slot exceeds a preset allowable range, it is determined that the core board layer cannot meet the requirements for the first lamination.

[0048] In some embodiments, reprocessing or direct scrapping can be selected based on the degree of deviation. By completing the first slot inspection before the first lamination, core boards with large positioning errors can be prevented from entering subsequent lamination processes, thereby reducing the cumulative error after overall lamination and improving product manufacturing yield.

[0049] After the first slot processing and inspection are completed, the core boards belonging to the same pressing unit are stacked sequentially according to the stacking order determined in step S100. Prepreg sheets are placed between adjacent core boards, allowing them to alternate with the core boards to form a localized stacked structure. During subsequent heating and pressurization, the prepreg sheets undergo resin flow and curing, thereby achieving reliable bonding between the core boards.

[0050] It should be noted that, in order to ensure that the core layers can maintain an accurate positional relationship, this disclosure uses a pin positioning method for the first lamination.

[0051] Specifically, pins are passed through the first slots of each core board in sequence to keep each core board in a uniform position in the plane. Then, the stacked structure that has been positioned is sent into the laminating equipment for the first pin positioning lamination.

[0052] The first lamination temperature is controlled between 170℃ and 190℃, the lamination pressure between 1.5MPa and 2.5MPa, and the holding time between 60min and 90min. Furthermore, to reduce interlayer displacement caused by uneven resin flow, this embodiment preferably controls the lamination heating rate to 1.5℃ / min to 2.5℃ / min and the cooling rate to 1.0℃ / min to 2.0℃ / min, allowing the resin to gradually soften and flow uniformly, thereby reducing lamination stress and improving the bonding quality between the core layers. After the first pin-positioning lamination is completed, each core layer cures to form a sub-board with high overall rigidity.

[0053] It should be noted that the purpose of forming the sub-board in this disclosure is not only to complete local lamination, but more importantly, to establish an intermediate manufacturing unit with relatively stable dimensions. Since multiple core boards have already completed local curing, the positional relationship between their internal layers remains basically stable. Therefore, subsequent repositioning only requires repositioning the sub-boards, without having to reposition each core board individually. This significantly reduces the cumulative interlayer error during the manufacturing of high-layer PCBs and improves the overall interlayer alignment accuracy.

[0054] With the above settings, this disclosure first uses the first positioning hole to establish an initial positioning reference, then uses the first slot hole to achieve precise positioning of the pin, and completes local lamination to form a sub-board. This not only reduces the relative displacement between the core boards of each layer during the first lamination process, but also improves the dimensional stability of the local stacked structure. This provides reliable conditions for re-establishing the second positioning reference according to the actual expansion and contraction of the sub-board, thereby further improving the interlayer positioning accuracy and manufacturing reliability in the entire high-multilayer server printed circuit board manufacturing process.

[0055] If the first positioning hole made in the first production is used as the positioning reference for the second lamination, the position of the first positioning hole can no longer accurately reflect the actual size of the current sub-board. This can easily lead to new positioning errors between different sub-boards, causing the errors to accumulate further and ultimately affecting the interlayer alignment accuracy of the entire high-multilayer server printed circuit board.

[0056] Therefore, after the first lamination is completed, this disclosure does not continue to use the first positioning reference, but instead re-establishes the second positioning reference on each sub-board. By re-fabricating the second positioning holes and the second slots, the second lamination can be re-positioned according to the actual size of each sub-board, thereby reducing the cumulative dimensional error caused by the first lamination.

[0057] In some embodiments, step S300 further includes steps S310 to S330.

[0058] In step S310, before making the second positioning hole, this embodiment preferably first measures the expansion and contraction of each sub-plate.

[0059] It should be noted that the expansion and contraction in this disclosure refers to the changes in length, width or local position of the sub-board relative to the design dimensions after the first lamination. This includes both overall thermal shrinkage and anisotropic dimensional changes caused by uneven resin flow, inconsistent copper layer distribution, and different glass fiber weaving directions.

[0060] Step S311: X-ray inspection equipment, CCD optical measurement equipment, automatic target measurement equipment or high-precision coordinate measurement equipment can be used to measure the multiple positioning targets set on the sub-board.

[0061] Step S312: By comparing the difference between the theoretical position and the actual position of each target, the expansion and contraction rate of the sub-plate in the X-axis direction and the Y-axis direction is calculated.

[0062] Preferably, a least-squares fitting algorithm can be used to establish an overall expansion and contraction model of the sub-board, or an interpolation fitting method for each measurement point can be used to establish a local compensation model to obtain more accurate dimensional compensation data. Of course, for different types of server PCBs, other methods that can obtain dimensional deviations can also be used, and this disclosure does not limit this.

[0063] Based on the above measurement results, the compensation amount corresponding to each sub-board was further determined. The compensation amount refers to the positional compensation value that needs to be added or subtracted to correct the position of the second positioning hole in order to restore multiple sub-boards to their designed positions during the second lamination.

[0064] It should be noted that due to differences in copper area distribution, layer structure, and resin flow, the expansion and contraction amounts of different sub-boards are usually not completely consistent. Therefore, this disclosure prefers to establish corresponding compensation amounts for each sub-board rather than using a uniform compensation value, thereby further improving the accuracy of the second positioning.

[0065] Step S313: Using the theoretical coordinate system of the sub-plate as the reference coordinate system, calculate the positional deviation of each measurement target in the X and Y directions respectively: ΔX = X_measured Theory X; Actual measurement of ΔY=Y Y-theory; based on the positional deviations of all measured targets, the least squares method is used to establish the overall size compensation model of the sub-plate, and the corresponding processing compensation amounts Cx and Cy are calculated.

[0066] Preferably, Cx = -ΔX; Cy = -ΔY; that is, the machining position of the second positioning hole is compensated in the opposite direction of the actual deviation relative to the theoretical position, so as to reduce the dimensional error caused by the first lamination. For sub-boards with local non-uniform expansion and contraction, a regional compensation method can be used to establish local compensation models to further improve the positioning accuracy.

[0067] Step S320: Re-fabricate the second positioning hole according to the compensation amount. The second positioning hole is fabricated using a punching machine or a laser drilling machine. When using a punching method, the positioning hole can be directly processed based on the compensated coordinates; when using a laser processing method, the processing coordinates can be automatically adjusted by a CNC program to complete the fabrication of the compensated positioning hole.

[0068] It should be noted that, in this disclosure, the second positioning hole is preferably located closer to the effective circuit area than the first positioning hole. This is because, in high-multilayer server printed circuit boards, what is ultimately required to ensure is the interlayer overlap accuracy between the effective circuit areas, rather than the positional accuracy of the process edge area. If the positioning hole is far from the effective circuit area, there may still be some dimensional variation between the process edge area and the circuit area, resulting in positioning errors in the circuit area.

[0069] Therefore, this disclosure moves the second positioning hole further into the effective graphic area, making the second positioning reference closer to the actual line area, which can more accurately reflect the actual expansion and contraction of the line area and improve the interlayer alignment accuracy between the final lines.

[0070] After determining the compensation amount, the machining program for the second positioning hole is automatically updated by the CAM software. Its machining coordinates can be generated according to the following formula: X machining = X design + Cx; Y machining = Y design + Cy. Subsequently, the punching equipment or laser processing equipment completes the machining of the second positioning hole according to the compensated coordinates, so that the second positioning hole can truly reflect the size state of the sub-board after the first lamination.

[0071] In some embodiments, a second slot is made according to the second positioning hole. It should be noted that the second slot serves as a positioning structure during the second pin positioning lamination, and its manufacturing method can be the same as that of the first slot, or it can be made in different sizes or shapes according to the requirements of the second lamination equipment.

[0072] For example, the second slot can be a circular slot, an oblong slot, an elliptical slot, or other slot-shaped structures suitable for pin positioning. After the second slot is machined, its position is also checked to ensure that the positional deviation of the second slot relative to the second positioning hole meets the requirements for the second lamination.

[0073] In step S330, on the other hand, this disclosure provides an impedance compensation layer between each sub-board. It should be noted that the impedance compensation layer in this disclosure is not a conventional prepreg for lamination, but a functional dielectric layer designed according to the target impedance. Preferably, this impedance compensation layer is made using a prepreg having a predetermined dielectric constant and a predetermined thickness.

[0074] In some embodiments, the dielectric constant of the prepreg is determined based on the target impedance of the adjacent circuit layers. For example, when the design impedance of the adjacent circuit is high, the dielectric constant of the prepreg can be appropriately reduced; when the target impedance is low, the dielectric constant can be appropriately increased, so that the impedance after lamination is closer to the design value.

[0075] On the other hand, the thickness of the prepreg is determined based on the thickness of the dielectric layer after lamination. Since the circuit impedance is affected not only by the dielectric constant but also by the dielectric thickness, this disclosure controls both the prepreg thickness and the dielectric constant so that the laminated dielectric layer can simultaneously meet the impedance and thickness requirements.

[0076] Preferably, a dielectric parameter design model is established based on the target line impedance value. For a high-speed signal layer with a target single-ended impedance of 45Ω~55Ω, a prepreg with a dielectric constant of 3.4~3.9 is selected; for a high-speed differential line with a target differential impedance of 85Ω~100Ω, impedance compensation is preferably achieved by adjusting both the prepreg thickness and the dielectric constant.

[0077] More preferably, impedance simulation software can be used to establish a circuit model, calculate the target impedance based on the circuit width, copper thickness, dielectric thickness, and dielectric constant, and determine the parameters of the impedance compensation layer accordingly. For example, when the target impedance is 50Ω, a prepreg with a dielectric constant of approximately 3.7 and a thickness of approximately 100μm can be used as the impedance compensation layer.

[0078] Furthermore, in this embodiment, a prepreg with a resin content of 45% to 65% and a flowability of 15 mm to 30 mm is preferably used. The higher resin content ensures that the gaps between the circuits are fully filled during lamination, improving the quality of interlayer bonding; while proper control of the resin flowability avoids excessive resin flow leading to variations in dielectric thickness, thus ensuring overall impedance consistency.

[0079] In some embodiments, the prepreg includes a first adhesive layer, a dielectric control core layer, and a second adhesive layer. The adhesive layers on both sides are mainly used to achieve reliable bonding between adjacent sub-boards, while the dielectric control core layer is mainly used to adjust the interlayer dielectric properties. The resin content of the first and second adhesive layers is 62%~68%, and the flowability is 25mm~32mm; the resin content of the dielectric control core layer is 42%~48%, and the flowability is 12mm~16mm. The dielectric control core layer contains a composite dielectric filler composed of barium titanate and molten silica in a mass ratio of 1:(2.5~4), and the composite dielectric filler accounts for 20%~35% of the total mass of the dielectric control core layer; the thickness of the dielectric control core layer accounts for 65%~80% of the total thickness of the prepreg; the curing temperature of the first and second adhesive layers is lower than the curing temperature of the dielectric control core layer.

[0080] Preferably, a composite dielectric filler composed of barium titanate and fused silica is dispersed within the dielectric control core layer. It should be noted that barium titanate has a high dielectric constant, while fused silica has a low dielectric loss; barium titanate is used to increase the dielectric constant, thereby improving the impedance regulation capability of high-speed lines; fused silica has low dielectric loss and good thermal stability, which can reduce high-frequency signal transmission loss.

[0081] When combined, these two components can balance dielectric constant adjustment, high-frequency signal integrity, and lamination dimensional stability. As a composite filler, they can adjust the dielectric constant and reduce dielectric loss during high-speed signal transmission, thereby improving signal integrity on high-speed server PCBs.

[0082] In some embodiments, the thickness of the dielectric control core layer preferably accounts for 65% to 80% of the total thickness of the prepreg, so that impedance regulation is mainly concentrated in the dielectric control core layer, while the adhesive layers on both sides mainly ensure the interlayer bonding strength and avoid the dielectric layer thickness being affected by resin flow.

[0083] Through the above settings, this disclosure re-establishes a second positioning reference after the first lamination is completed, and re-fabricates the second positioning holes and second slots based on the actual expansion and contraction of each sub-board, so that the second lamination can be repositioned based on the actual size of the sub-board, effectively reducing the cumulative positioning error in multiple lamination processes; at the same time, by setting an impedance compensation layer with a predetermined dielectric constant and thickness between adjacent sub-boards, the dielectric layer thickness change and impedance deviation generated during the lamination process are compensated, so that the final high-multilayer server printed circuit board has more stable interlayer alignment accuracy and impedance consistency, improving high-speed signal transmission performance and product manufacturing reliability.

[0084] In step S400, the sub-boards stacked in the stacking order are subjected to a second pin positioning lamination through the second slot to form the mother board.

[0085] In some embodiments, step S400 further includes steps S410 to S440.

[0086] It should be noted that this step belongs to the overall lamination stage in the entire high-multilayer server printed circuit board manufacturing process, and is also an important process for the various sub-boards to form a complete high-multilayer server printed circuit board lamination structure. After the second positioning reference is established in step S300, each sub-board has completed positioning compensation according to the actual expansion and contraction. Therefore, this step no longer positions the single-layer core board, but uses the sub-board as the overall positioning object to perform a second pin positioning lamination, in order to further reduce the cumulative error in the overall stacking process.

[0087] Before the second lamination, this embodiment preferably classifies the multiple sub-boards according to the compensation amount of each sub-board. Specifically, the multiple sub-boards can be divided into several expansion and contraction level groups based on the expansion and contraction rate and compensation amount of each sub-board obtained in step S300. Preferably, the difference in expansion and contraction rate of each sub-board within the same expansion and contraction level group does not exceed a preset threshold, for example, 0.02% to 0.05%.

[0088] It should be noted that although dimensional compensation has been completed for all sub-boards, differences in board batches, copper area distribution, fiberglass weave direction, and resin curing degree may still result in variations in their actual dimensional change trends. If sub-boards with significantly different expansion and contraction trends are directly laminated together, new relative displacements may still occur during the second heating process.

[0089] Therefore, this disclosure preferably first groups the components according to their expansion and contraction characteristics, and then prioritizes selecting sub-plates with similar expansion and contraction trends to form an overall laminated structure, thereby further reducing new errors generated during the lamination process and improving overall dimensional stability.

[0090] Preferably, the sub-boards are divided into multiple grades according to their expansion and contraction rates. For example: Grade A, expansion and contraction rate ≤ 0.02%; Grade B, 0.02% < expansion and contraction rate ≤ 0.05%; Grade C, expansion and contraction rate > 0.05%. By selecting sub-boards belonging to the same grade or adjacent grades to form an overall laminated structure, the relative dimensional changes during re-lamination are reduced.

[0091] In some embodiments, multiple sub-boards belonging to the same expansion / contraction level group are pre-stacked sequentially according to the stacking order determined in step S100. It should be noted that, in this disclosure, pre-stacking refers to the pre-positioning and pre-assembly of the sub-boards before formal lamination.

[0092] During the pre-stacking process, the second positioning hole is used as the positioning reference to ensure that the second positioning holes on each sub-board are coaxially aligned in the vertical direction. The positioning pins are then used to pass through the corresponding second slots on each sub-board in sequence to ensure that the sub-boards maintain a consistent positional relationship in the X and Y directions.

[0093] In some embodiments, pre-stacking can be performed using automated stacking equipment or manual stacking. For server PCBs with a high number of layers or large dimensions, automated stacking equipment is used to improve stacking efficiency and positioning accuracy. After pre-stacking is completed, the impedance compensation layer described in step S300 is placed sequentially between adjacent sub-boards.

[0094] It should be noted that the impedance compensation layer set in this step, in addition to its impedance adjustment function, also serves as the resin bonding medium during the lamination process. Therefore, during placement, it is essential to ensure that the impedance compensation layer is fully bonded to the adjacent sub-boards to avoid wrinkles, misalignment, or localized gaps.

[0095] In some embodiments, the pre-stacked overall laminated structure is pre-compressed before formal lamination. The pre-compression pressure is controlled between 0.5 MPa and 1.0 MPa, and the holding time is between 5 min and 10 min.

[0096] It should be noted that pre-compression is mainly used to remove residual air between layers and to allow the resin in the impedance compensation layer to begin flowing, thus creating a better initial bond between adjacent sub-boards. If formal lamination is performed directly, air bubbles can easily form between layers during the heating process, leading to localized voids or uneven resin distribution, which affects the overall lamination quality and impedance consistency. Therefore, pre-compression effectively reduces interlayer voids and improves the uniformity of resin flow during subsequent formal lamination.

[0097] In some embodiments, the pre-compressed integral laminated structure is fed into a laminating machine for a second pin-positioning lamination. The lamination temperature is controlled between 180°C and 200°C, the lamination pressure is controlled between 2.0 MPa and 3.0 MPa, and the holding time is controlled between 80 min and 120 min.

[0098] It should be noted that, compared to the first lamination, the lamination object in this step has changed from multiple core boards to multiple sub-boards, and the overall thickness has increased significantly. It is necessary to appropriately increase the lamination pressure and extend the holding time to ensure that the resin in the impedance compensation layer can flow fully and complete curing, so that each sub-board can form a reliable bond.

[0099] To further improve lamination quality, this embodiment preferably controls the lamination heating rate to 1.0℃ / min to 2.0℃ / min and the cooling rate to 0.5℃ / min to 1.5℃ / min. The slower heating process ensures that the resin in the impedance compensation layer melts uniformly and gradually penetrates between layers, reducing localized resin buildup; the slower cooling process reduces thermal stress generated during cooling, preventing warping or interlayer delamination of the motherboard.

[0100] Furthermore, during the lamination process, it is preferable to control the vacuum level of the laminator cavity below 10 Pa. It should be noted that a vacuum environment can effectively eliminate interlayer air and volatile gases, reduce the possibility of air bubbles forming during resin curing, and prevent local bulging caused by the thermal expansion of air, thereby improving the overall density of the motherboard and the interlayer bonding strength.

[0101] On the other hand, vacuum lamination can also improve the resin wetting effect of the impedance compensation layer, making the dielectric layer thickness more uniform, thereby further improving the overall impedance consistency.

[0102] After the second lamination is completed, the sub-boards cure to form a unified motherboard. It should be noted that, in this disclosure, the motherboard refers to the overall laminated board that has completed all inner layer laminations but has not yet completed drilling, electroplating, and outer layer circuit fabrication. Since the sub-boards have formed a unified whole in this step, all subsequent processes are performed on the motherboard.

[0103] Furthermore, after lamination is completed, the motherboard is allowed to cool naturally or through a programmed cooling process. Once the motherboard temperature has dropped to near room temperature, the locating pins are removed and subsequent inspections are performed to prevent new dimensional changes from occurring due to external forces at high temperatures.

[0104] After the motherboard is formed, interlayer alignment and impedance are tested. Interlayer alignment can be measured by X-ray inspection equipment to measure the target offset of each layer, or by slicing inspection to observe the overlap between layers. Impedance can be tested by TDR (Time Domain Reflectometry) equipment to check the test circuit to confirm whether the overall impedance meets the design requirements.

[0105] If the test results meet the preset requirements, proceed to step S500 to continue drilling, electroplating, and outer layer circuit fabrication. If the test results show interlayer misalignment, impedance abnormalities, or local lamination defects, the second positioning compensation parameters, lamination temperature, lamination pressure, heating / cooling rate, or impedance compensation layer parameters can be adjusted according to the test results, and the process can be optimized again to form a closed-loop manufacturing process, thereby improving consistency and product yield in mass production.

[0106] Preferably, the interlayer alignment error is controlled within 50 μm, and the impedance detection is preferably performed using a TDR testing device, with the allowable deviation of the target impedance preferably controlled within ±5% of the design value. When the interlayer alignment error or impedance deviation exceeds the above range, the second positioning compensation parameters, lamination process parameters, or impedance compensation layer parameters are revised, and the process is verified again.

[0107] Through the above settings, this disclosure utilizes the second positioning hole to re-establish the overall positioning reference, and combines expansion and contraction grouping, pre-stacking, pre-pressing, vacuum lamination and second pin positioning lamination processes to enable multiple sub-boards to complete overall lamination based on actual dimensions. This not only further reduces the accumulation of positioning errors during multiple lamination processes, but also ensures that the impedance compensation layer can be uniformly cured, improving the overall interlayer bonding quality, impedance consistency and dimensional stability, thereby forming a high-multilayer server printed circuit board motherboard that meets the requirements of high-speed server applications, providing a stable and reliable foundation for subsequent drilling, electroplating and outer layer circuit fabrication.

[0108] In step S500, drilling, electroplating, and outer layer circuitry are performed on the motherboard to obtain a high-multilayer server printed circuit board. The drilling, outer layer patterning, and subsequent processing all utilize coordinate data established by the second positioning datum as a processing reference, ensuring that the entire subsequent manufacturing process is based on the second positioning system, thereby maintaining the correspondence between the drilling positions and the circuitry of each layer.

[0109] It should be noted that this step belongs to the subsequent processing stage of the high-multilayer server printed circuit board manufacturing process. After the second pin positioning lamination is completed in step S400, each sub-board has formed an integral motherboard, and its interlayer positional relationship is basically fixed and has good dimensional stability. Therefore, subsequent drilling, electroplating and outer layer circuit fabrication processes can be completed on the motherboard.

[0110] Specifically, the motherboard is CNC drilled according to the product design documents to form through holes, mounting holes, and other functional holes. Preferably, the drilling process uses the second positioning datum established in step S300 as a processing reference to ensure that the drilling position accurately corresponds to the circuitry of each layer, thereby improving the interlayer conductivity.

[0111] After drilling is completed, the motherboard undergoes hole wall cleaning and hole metallization treatment, followed by chemical copper plating and electrolytic copper plating processes to form a continuous conductive layer on the hole wall, enabling electrical connection between the circuits of each layer.

[0112] Subsequently, the outer layer circuitry is fabricated on the motherboard. Preferably, the outer layer circuitry is formed through processes such as outer layer pattern transfer, pattern electroplating, and etching, and solder mask, character printing, and surface treatment processes are completed according to product requirements. The surface treatment can employ mature processes such as electroless nickel-gold plating, immersion silver plating, immersion tin plating, or OSP, and this disclosure does not limit the specific application to these methods.

[0113] In some embodiments, after completing the above processes, the high-multilayer server printed circuit board undergoes finished product inspection. Inspection items include interlayer alignment inspection, conductivity inspection, impedance inspection, and appearance inspection. When the inspection results meet the design requirements, the high-multilayer server printed circuit board is obtained; if the inspection results do not meet the preset requirements, the parameters of the aforementioned lamination process or subsequent processing processes are adjusted based on the inspection results to improve product manufacturing consistency and production yield.

[0114] With the above setup, this disclosure uses the motherboard formed by two pin-positioning laminations as a unified processing object to complete drilling, electroplating, and outer layer circuit fabrication, so that the drilling position can accurately correspond to the circuit of each layer, improving the reliability of interlayer conductivity; at the same time, combined with the stable dielectric structure formed by the impedance compensation layer, the final multilayer server printed circuit board has high interlayer alignment accuracy and stable impedance consistency, meeting the application requirements of high-speed signal transmission and high reliability of servers.

[0115] For example, this embodiment uses a 16-layer server printed circuit board as an example to illustrate the process disclosed herein.

[0116] First, the 16-layer PCB is divided into four 4-layer lamination units. Each lamination unit completes the inner layer circuit fabrication and the first pin positioning lamination to form four sub-boards.

[0117] The first lamination process conditions were: lamination temperature 180℃, lamination pressure 2.0MPa, holding time 80min, heating rate 2℃ / min, and cooling rate 1.5℃ / min. After the first lamination, the expansion and contraction of the four sub-boards were measured. The measured expansion and contraction rates in the X direction for each sub-board were approximately 0.035%~0.046%, and in the Y direction, approximately 0.021%~0.038%.

[0118] Compensation models were established based on the measurement results of each sub-board, and the second positioning hole was re-machined.

[0119] Subsequently, an impedance compensation layer with a dielectric constant of approximately 3.7 and a thickness of approximately 100 μm was placed between adjacent sub-boards, and the second pin positioning lamination was completed.

[0120] The conditions for the second lamination were: lamination temperature 190℃, lamination pressure 2.5MPa, holding pressure for 100min, and vacuum degree controlled below 10Pa.

[0121] After drilling, electroplating, and outer layer circuit fabrication are completed, the resulting server printed circuit board is inspected.

[0122] The test results show that the interlayer alignment error is about 32μm, the single-ended impedance deviation is controlled within ±4%, the board thickness uniformity meets the design requirements, and the product meets the requirements of high-speed signal transmission for servers.

[0123] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0124] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A manufacturing process for a high-multilayer server printed circuit board, characterized in that, include: Step S100: The server printed circuit board to be manufactured is divided into multiple lamination units according to a preset number of layers. Each lamination unit includes at least one core board, and the stacking order of each lamination unit is determined. Step S200: Transfer the inner layer pattern of the core board in each of the pressing units, make the first positioning hole, make the first slot based on the first positioning hole, and perform the first pin positioning lamination on each of the core boards stacked in the stacking order through the first slot to form multiple sub-boards. Step S300: A second positioning hole is made on each of the sub-boards, and a second slot is made according to the second positioning hole. At the same time, a prepreg is provided between adjacent sub-boards as an impedance compensation layer. The prepreg has a predetermined dielectric constant and thickness and is used to compensate for the deviation of the overall impedance after lamination. Step S400: The sub-boards stacked in the stacking order are subjected to a second pin positioning lamination through the second slot to form a mother board; Step S500: Drilling, electroplating and outer layer circuitry are performed on the motherboard to obtain a high-multilayer server printed circuit board.

2. The high-multilayer server printed circuit board manufacturing process according to claim 1, characterized in that, Step S300 includes: Step S310: Perform expansion and contraction measurements on each of the sub-boards, and determine the compensation amount for each of the sub-boards based on the expansion and contraction measurement results; Step S320: According to the compensation amount, a second positioning hole is made on each of the sub-boards using a punching machine or laser drilling method, and a second slot is made according to the second positioning hole. The second positioning hole is closer to the effective graphic area of ​​the sub-board than the first positioning hole. In step S330, before each of the sub-boards is stacked, a prepreg is provided between adjacent sub-boards as an impedance compensation layer.

3. The high-multilayer server printed circuit board manufacturing process according to claim 2, characterized in that, Step S310 includes: Step S311: Use an X-ray inspection device or a CCD optical measurement device to measure the position offset of multiple targets on each of the sub-plates; Step S312: Based on the difference between the actual position and the theoretical position of each target, calculate the expansion and contraction rate of each sub-plate in the X-axis and Y-axis directions; Step S313: Determine the compensation amount of each sub-plate according to the expansion and contraction rate of each sub-plate, so that the second positioning holes of each sub-plate are aligned with each other when stacked.

4. The high-multilayer server printed circuit board manufacturing process according to claim 1, characterized in that, In step S300, the dielectric constant of the prepreg is selected based on the target impedance value of the circuit layer of the adjacent sub-board, the thickness of the prepreg is determined based on the target thickness of the dielectric layer after lamination, the resin content of the prepreg is 45%~65%, and the flowability of the prepreg is 15mm~30mm.

5. The high-multilayer server printed circuit board manufacturing process according to claim 1 or 4, characterized in that, The prepreg includes a first adhesive layer, a dielectric modulating core layer, and a second adhesive layer stacked sequentially. The resin content of the first adhesive layer and the second adhesive layer is 62%~68%, and the flowability is 25mm~32mm; the resin content of the dielectric control core layer is 42%~48%, and the flowability is 12mm~16mm. The dielectric control core layer contains a composite dielectric filler composed of barium titanate and molten silica in a mass ratio of 1:(2.5~4), and the composite dielectric filler accounts for 20%~35% of the total mass of the dielectric control core layer. The thickness of the dielectric control core layer accounts for 65% to 80% of the total thickness of the prepreg; the curing temperature of the first adhesive layer and the second adhesive layer is lower than the curing temperature of the dielectric control core layer.

6. The high-multilayer server printed circuit board manufacturing process according to claim 1, characterized in that, Step S200 includes: Step S210: Perform a stacking and matching check on each core board layer in each pressing unit, and select a matching prepreg according to the expansion and contraction characteristics of each core board layer. Step S220: A first positioning hole is made in the process edge area of ​​each layer of the core board. The first positioning hole includes an inner ring positioning hole and an outer ring positioning hole. The inner ring positioning hole is set close to the effective graphic area of ​​the core board. Step S230: Using the inner ring positioning hole as a reference, a first slot is made by punching, and the positional deviation of the first slot in each core board is measured after the first slot is made; if the positional deviation of the first slot exceeds a preset threshold, the core board is scrapped or reworked. Step S240: After the core boards and the corresponding prepregs are stacked alternately, the first pin positioning lamination is performed under the conditions of a lamination temperature of 170℃~190℃ and a lamination pressure of 1.5MPa~2.5MPa for 60 minutes~90 minutes to form multiple sub-boards.

7. The high-multilayer server printed circuit board manufacturing process according to claim 6, characterized in that, In step S240, the heating rate during the lamination process is 1.5℃ / min to 2.5℃ / min, and the cooling rate is 1.0℃ / min to 2.0℃ / min.

8. The high-multilayer server printed circuit board manufacturing process according to claim 1, characterized in that, Step S400 includes: Step S410: Divide the multiple sub-boards into several expansion and contraction level groups according to the compensation amount of each sub-board, pair the sub-boards belonging to the same expansion and contraction level group, and pre-stack them according to the stacking order determined in step S100, so that the second positioning holes of each sub-board are aligned with each other in the vertical direction. Step S420: A prepreg as an impedance compensation layer is placed between the adjacent sub-boards after pre-stacking, and a pre-compression pressure of 0.5MPa to 1.0MPa is applied to the pre-stacking stacked structure and maintained for 5 to 10 minutes to remove interlayer air bubbles and make the prepreg adhere tightly to the adjacent sub-boards. Step S430: Transfer the pre-compressed laminated structure to a laminator and perform a second pin-positioning lamination under the conditions of a pressing temperature of 180℃~200℃ and a pressing pressure of 2.0MPa~3.0MPa for 80 minutes~120 minutes to form a mother board; Step S440: After lamination is completed, the motherboard is cooled and the interlayer alignment and overall impedance of the motherboard are tested; if the test results do not meet the preset requirements, the process parameters are adjusted accordingly.

9. The high-multilayer server printed circuit board manufacturing process according to claim 8, characterized in that, In step S430, the heating rate during the lamination process is 1.0℃ / min to 2.0℃ / min, the cooling rate is 0.5℃ / min to 1.5℃ / min, and the vacuum degree of the laminator cavity during the lamination process is controlled below 10Pa.

10. The high-multilayer server printed circuit board manufacturing process according to claim 1, characterized in that, The number of the pressing units is 2 to 4, each pressing unit contains 2 to 6 core board layers, and the number of mother board layers is 16 or more.

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