Semiconductor structure and method of manufacturing the same, storage system

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof and a storage system, and relates to the technical field of semiconductor chips, aiming to improve the coupling between adjacent bit lines. The semiconductor structure comprises a connection structure and a plurality of bit lines arranged at intervals along a first direction, wherein the first direction is perpendicular to the extension direction of the bit lines. The connection structure penetrates the plurality of bit lines along the first direction and comprises insulating columns and conductive columns arranged along the first direction, wherein the insulating columns are in contact with the conductive columns, and the conductive columns are connected with one of the plurality of bit lines. Through the above arrangement, each bit line is penetrated by the connection structure, so that each bit line reduces the area, further reduces the opposite area between the adjacent two bit lines, thereby improving the coupling between the adjacent two bit lines and improving the storage performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] With the continuous evolution of Dynamic Random Access Memory (DRAM), the storage density of planar DRAM has gradually approached the limits of process technology. In order to further improve the storage density of DRAM, memory with 3D stacked memory cells has been developed. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and a memory system.

[0004] The embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a semiconductor structure is provided, the semiconductor structure comprising: a connection structure and a plurality of bit lines spaced apart along a first direction, the first direction being perpendicular to the extension direction of the bit lines; the connection structure extends through the plurality of bit lines along the first direction and includes insulating pillars and conductive pillars arranged along the first direction, the insulating pillars being in contact with the conductive pillars, and the conductive pillars being connected to one of the plurality of bit lines.

[0006] In some embodiments, the insulating post has a first end and a second end along the first direction, the first end being closer to the conductive post than the second end, and the dimension of the first end in the second direction being greater than the dimension of the second end in the second direction; the second direction is perpendicular to the first direction.

[0007] In some embodiments, the insulating post has a first end face, the conductive post has a second end face, the first end face is in contact with the second end face, and the edge of the first end face coincides with the edge of the second end face.

[0008] In some embodiments, the conductive post includes a first sub-post and a second sub-post connected together, the first sub-post being located between the second sub-post and the insulating post, the first sub-post being connected to one of the plurality of bit lines, and the second sub-post being spaced apart from the plurality of bit lines.

[0009] In some embodiments, the dimension of the first sub-post in the second direction is greater than the dimension of the second sub-post in the second direction; the second direction is perpendicular to the first direction.

[0010] In some embodiments, the second sub-post has a third end and a fourth end along the first direction, the third end being further away from the first sub-post than the fourth end, and the dimension of the third end in the second direction being greater than the dimension of the fourth end in the second direction; the second direction is perpendicular to the first direction.

[0011] In some embodiments, the connection structure further includes an isolation layer disposed around the second sub-post and located between the bit line penetrated by the second sub-post and the second sub-post.

[0012] In some embodiments, the bit line connected to the first sub-post is a first bit line, the first bit line having a first surface and a second surface disposed opposite to each other, the direction of the first surface pointing to the second surface being the direction of the insulating post pointing to the conductive post; in the first direction, the contact surface between the insulating post and the conductive post is located between the first surface and the second surface; or, in the first direction, the contact surface between the insulating post and the conductive post is located on the side of the first surface away from the second surface.

[0013] In some embodiments, the first sub-post is recessed within the second surface in the direction from the first surface to the second surface; or, the first sub-post protrudes from the second surface in the direction from the first surface to the second surface.

[0014] In some embodiments, the plurality of bit lines includes a second bit line, which is adjacent to the first bit line, and the minimum spacing between the first sub-pillar and the second bit line is greater than 5 nm.

[0015] In some embodiments, the bit line extends along a second direction; the semiconductor structure further includes: a gate layer and a plurality of channel structures arranged in a row along the first direction, one of the channel structures being connected to one of the bit lines, the channel structures extending along a third direction; the third direction intersects the plane containing the first direction and the second direction; the gate layer extends along the first direction and is located on at least one side of a row of channel structures along the second direction.

[0016] On the other hand, a method for fabricating a semiconductor structure is also provided, comprising: forming a plurality of bit lines, the plurality of bit lines being spaced apart along a first direction, the first direction being the thickness direction of the bit lines; forming a connection structure, the connection structure penetrating the plurality of bit lines along the first direction, the connection structure including insulating pillars and conductive pillars arranged along the first direction, the insulating pillars being in contact with the conductive pillars, and the conductive pillars being connected to one of the plurality of bit lines.

[0017] In some embodiments, forming a plurality of bit lines includes: forming a stacked structure, the stacked structure including a plurality of dielectric layers and a plurality of bit lines alternately disposed along the first direction; forming a connection structure includes: forming a first via through the stacked structure; filling the first via with an insulating material to form a first insulating pillar; removing a portion of the first insulating pillar to form a second insulating pillar and a second via; forming an isolation layer covering the wall of the second via; removing a portion of the second insulating pillar to expose at least a portion of the bit lines to form an insulating pillar; and filling the second via with a conductive material to form the conductive pillar.

[0018] In another aspect, a storage system is provided, comprising: a semiconductor structure as described above and a controller, the controller being coupled to the semiconductor device to control the semiconductor device to store data. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0020] Figure 1 A block diagram of an electronic device according to some embodiments;

[0021] Figure 2 A block diagram of a memory according to some embodiments;

[0022] Figure 3 This is a top view of a semiconductor structure according to some embodiments;

[0023] Figure 4 for Figure 3 A cross-sectional view of AA in the diagram;

[0024] Figure 5 This is a structural schematic diagram of a connection structure according to some embodiments;

[0025] Figure 6 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 1 ;

[0026] Figure 7 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 2 ;

[0027] Figure 8 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 3 ;

[0028] Figure 9 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 4 ;

[0029] Figure 10 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 5 ;

[0030] Figure 11 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 6 ;

[0031] Figure 12 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0032] Figure 13 This is a schematic diagram of the structure after the stacked structure is formed according to some embodiments;

[0033] Figure 14 This is a schematic diagram of the structure after the first through hole is formed according to some embodiments;

[0034] Figure 15 This is a schematic diagram of the structure after the formation of the first insulating pillar according to some embodiments;

[0035] Figure 16 This is a schematic diagram of the structure after removing part of the first insulating post according to some embodiments. Figure 1 ;

[0036] Figure 17 This is a schematic diagram of the structure after removing part of the first insulating post according to some embodiments. Figure 2 ;

[0037] Figure 18 This is a schematic diagram of the structure after removing part of the first insulating post according to some embodiments. Figure 3 ;

[0038] Figure 19 This is a schematic diagram of the structure after the formation of the second insulating pillar according to some embodiments;

[0039] Figure 20 This is a schematic diagram of the structure after the isolation layer is formed according to some embodiments;

[0040] Figure 21 This is a schematic diagram of the structure after removing part of the isolation layer according to some embodiments;

[0041] Figure 22This is a schematic diagram of the structure after the conductive pillars are formed, according to some embodiments.

[0042] Reference numerals: 9000, Electronic device; 910, Storage system; 911, Memory; 912, Controller; 920, Motherboard; X, First direction; Y, Second direction; Z, Third direction; BL, Bit line; BL-1, First bit line; BL-2, Second bit line; WL, Word line; C, Capacitor; 1000, Semiconductor structure; 10, Connection structure; 11, Insulating post; 111, First terminal; 112, Second terminal; 113, First terminal 12. Conductive pillar; 121. First sub-pillar; 122. Second sub-pillar; 1221. Third end; 1222. Fourth end; 123. Second end face; 13. Isolation layer; 21. First surface; 22. Second surface; 30. Channel structure; 40. Gate layer; 50. Stacked structure; 51. Dielectric layer; 52. First via; 53. First insulating pillar; 54. Mask layer; 55. Second insulating pillar; 56. Second via; 60. Capacitor structure. Detailed Implementation

[0043] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0044] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0045] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0046] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0047] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0048] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0049] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0050] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0051] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0052] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0053] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, the difference between the two equalities being less than or equal to 5% of either one.

[0054] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0055] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0056] Figure 1 This is a block diagram of an electronic device according to some embodiments. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, server, in-vehicle equipment, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0057] like Figure 1As shown, the electronic device 9000 may include a storage system 910 and a motherboard 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0058] The motherboard 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The motherboard 920 may be configured to send data to or receive data from memory.

[0059] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the memory 911 and the motherboard 920 and is configured to control the memory 911 to store data while also communicating with external devices (e.g., a host computer).

[0060] The number of memories 911 in the storage system 910 can be one or more. Figure 1The diagram uses three memories 911 as an example. The controller 912 manages the data stored in each memory 911 and communicates with the motherboard 920. The controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management.

[0061] In some implementations, controller 912 is also configured to determine the maximum memory capacity available to the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Controller 912 may also perform any other suitable functions. Controller 912 can communicate with external devices (e.g., motherboard 920) according to a specific communication protocol. For example, controller 912 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0062] The controller 912 mentioned above may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0063] In this embodiment, the storage system 910 can be integrated into various types of storage devices, and is not limited to the electronic device 9000 in the above embodiment.

[0064] Figure 2 This is a block diagram of a memory according to some embodiments. Figure 2 As shown, memory 911 includes a memory cell array 913 and peripheral circuitry 914 for controlling the memory cell array 913. Peripheral circuitry 914 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 913. For example, peripheral circuitry 914 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0065] For example, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0066] The memory cell array 913 and the peripheral circuitry 914 can be arranged side-by-side in the same plane, for example, on the same wafer; that is, the memory cell array 913 and the peripheral circuitry 914 can be located in the same semiconductor device. Alternatively, the memory cell array 913 and the peripheral circuitry 914 can be formed on different wafers and bonded together face-to-face. Figure 2 As shown, when the memory cell array 913 and the peripheral circuitry 914 are formed on different wafers and bonded together face-to-face, the memory 911 may include a first semiconductor structure 901 and a second semiconductor structure 902, as well as a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. The first semiconductor structure 901 may include the memory cell array 913, and the second semiconductor structure 902 may include the peripheral circuitry 914.

[0067] The memory cell array 913 may be an array of memory cells that use vertical transistors as switching and selection devices. In some embodiments, the memory cell array 913 may be a dynamic random access memory (DRAM) cell array. For ease of description, DRAM cell array may be used to describe an example of the memory cell array 913 in this disclosure. However, it should be understood that the memory cell array 913 is not limited to DRAM cell arrays, and may include any other suitable type of memory cell array 913 that can use vertical transistors as switching and selection devices, such as PCM cell arrays, static random-access memory (SRAM) cell arrays, FRAM cell arrays, resistive memory cell arrays, magnetic memory cell arrays, spin transfer torque (STT) memory cell arrays, etc.

[0068] When the memory cell array 913 is a DRAM cell array, the memory cells therein are DRAM cells. A DRAM cell includes a capacitor and one or more transistors. The capacitor stores data as positive or negative charge, and the one or more transistors (also called transfer transistors) control (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor and a capacitor (1T1C) cell. According to some embodiments, the DRAM cell can be refreshed by peripheral circuitry 914 to retain data.

[0069] As DRAM technology continues to evolve, the storage density of DRAM cells on a plane has gradually approached the limits of the manufacturing process. In order to further improve the storage density of DRAM cells, some embodiments of this disclosure provide a memory with 3D stacked DRAM cells. In the memory with 3D stacked DRAM cells, multiple storage cells are arranged into a storage array in the XY plane, and multiple storage arrays are also spaced apart along the Z direction.

[0070] In this embodiment, the first direction X intersects with the second direction Y, and the third direction Z intersects with the plane containing the first direction X and the second direction Y. For ease of understanding, in the embodiments of this disclosure, the first direction X, the second direction Y, and the third direction Z are set to be mutually perpendicular.

[0071] A memory cell includes a transistor T and a capacitor C. The transistor T can be formed by a channel structure formed by a semiconductor layer and a gate layer adjacent to the channel structure. A gate dielectric layer is also disposed between the semiconductor layer and the corresponding gate layer.

[0072] The semiconductor layer may include semiconductor materials, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The semiconductor layer may have source and drain electrodes, and the source and drain electrodes may be semiconductor materials doped with P-type or N-type dopants. P-type dopants include boron or gallium. N-type dopants include phosphorus or arsenic.

[0073] The gate layer of transistor T can be connected to word line WL. Word line WL can extend along a first direction X. The drain of transistor T can be connected to bit line BL, which can extend along a second direction Y. The source of transistor T is connected to one plate of capacitor C, and the other plate of capacitor C can be connected to a reference voltage, which can be ground or another voltage. The capacitor C can represent logical 1 and 0 by the amount of charge stored in it, or the high or low voltage difference across the capacitor C. With the above settings, the memory can control the transistor T to be turned on or off by applying a voltage to word line WL. When transistor T is turned on, bit line BL performs read or write operations on capacitor C.

[0074] This disclosure provides a semiconductor structure 1000 in some embodiments. The semiconductor structure 1000 can be part of the memory 911 in some of the above embodiments. For example, the semiconductor structure 1000 can be the first semiconductor structure 901; or, if the semiconductor structure 1000 can be the memory 911, the semiconductor structure 1000 can also include peripheral circuitry 914, which is not limited in this respect.

[0075] refer to Figure 3 and Figure 4 This disclosure provides a semiconductor structure 1000, which includes a connection structure 10 and a plurality of bit lines BL spaced apart along a first direction X. The first direction X is perpendicular to the extension direction of the bit lines BL; for example, the bit lines BL may extend along a second direction Y.

[0076] Since multiple bit lines BL are spaced apart along the first direction X, and since the constituent materials of the bit lines BL include conductive materials, two adjacent bit lines BL are similar to two opposing electrode plates. Adjacent bit lines BL may form a "capacitive structure," which can also be understood as a coupling problem between adjacent bit lines BL. This can affect the reading or writing of data by the semiconductor structure 1000, for example, causing the semiconductor structure 1000 to misinterpret data, thus affecting the storage performance of the semiconductor structure 1000. Furthermore, as the size of the semiconductor structure 1000 is reduced, the spacing between the bit lines BL is also reduced, further exacerbating the degree of coupling between adjacent bit lines BL, which is detrimental to the reading or writing of data by the semiconductor structure 1000.

[0077] Based on this, in this embodiment, the connection structure 10 extends through multiple bit lines BL along the first direction X. The connection structure 10 includes insulating posts 11 and conductive posts 12 arranged along the first direction X. The insulating posts 11 and conductive posts 12 are in contact and connected, and the conductive posts 12 are connected to one of the multiple bit lines BL.

[0078] The insulating pillar 11 is composed of insulating materials. The insulating materials may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials.

[0079] The conductive pillar 12 is composed of conductive materials. Conductive materials include, but are not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or other suitable conductive materials.

[0080] In this embodiment, reference Figure 4 The insulating post 11 and the conductive post 12 are arranged along the first direction X, and the insulating post 11 and the conductive post 12 are in contact with each other. For example, the insulating post 11 can extend along the first direction X, the conductive post 12 can extend along the first direction X, and one end of the insulating post 11 along the first direction X is in contact with one end of the conductive post 12 along the first direction X.

[0081] In this embodiment, a conductive post 12 is connected to one of a plurality of bit lines BL. The bit line BL to which the conductive post 12 is to be drawn is designated as the target bit line BL. The conductive post 12 can penetrate a portion of the bit line BL to the target bit line BL, and the conductive post 12 is connected to the target bit line BL. For example, the conductive post 12 can be in contact with the bit line BL.

[0082] The conductive post 12 is connected to one of the multiple bit lines BL, that is, one conductive post 12 is connected to one bit line BL. By analogy, the semiconductor structure 1000 can be configured with multiple connection structures 10, each of which is connected to one bit line BL in a one-to-one correspondence, thereby enabling the multiple bit lines BL to be led out and connected to the peripheral circuit.

[0083] The conductive post 12 penetrates part of the bit line BL, and the insulating post 11 also penetrates part of the bit line BL, so that the connection structure 10, which is formed by the conductive post 12 and the insulating post 11, penetrates multiple bit lines BL along the first direction X. At this time, the connection structure 10 penetrates a row of bit lines BL that are spaced apart along the first direction X.

[0084] With the above configuration, each bit line BL is penetrated by the connecting structure 10, thus reducing the area of ​​each bit line BL. Here, the area refers to the area of ​​the bit line BL in the YZ plane. Furthermore, the area between two adjacent bit lines BL is reduced, which helps to reduce the coupling between two adjacent bit lines BL and improve the storage performance of the semiconductor structure 1000.

[0085] Furthermore, the connection structure 10 extends through a column of bit lines BL arranged along the first direction X. In this column of bit lines BL arranged along the first direction X, the area lost by each bit line BL is the same or approximately the same, and the positions of the lost areas of each bit line are correspondingly arranged along the first direction X. Therefore, the coupling capacitance between adjacent bit lines BL along the first direction X is uniformly distributed, and the values ​​of the coupling capacitance between adjacent bit lines BL along the first direction X are also relatively uniform. The uniformity of the coupling capacitance between adjacent bit lines BL along the first direction X also helps to improve the stability of the semiconductor structure 1000.

[0086] In addition, the insulating pillar 11 and the conductive pillar 12 are arranged along the first direction X, and the insulating pillar 11 and the conductive pillar 12 are in contact and connected. The insulating pillar 11 can be located at the bottom of the conductive pillar 12. For example, the insulating pillar 11 is formed first and the conductive pillar 12 is formed later. Through the above arrangement, the insulating pillar 11 can also support the conductive pillar 12, which is beneficial to improving the stability of the semiconductor structure 1000.

[0087] In some embodiments, reference Figure 4 and Figure 5 The insulating post 11 has a first end 111 and a second end 112 along the first direction X. The first end 111 is closer to the conductive post 12 than the second end 112, and thus the first end 111 is in contact with the conductive post 12. Figure 5 In the connection structure 10 shown, the first end 111 is the top end of the insulating post 11, and the second end 112 is the bottom end of the insulating post 11.

[0088] like Figure 5 As shown, the dimension d1 of the first end 111 in the second direction Y is greater than the dimension d2 of the second end 112 in the second direction Y. Here, the dimension of the first end 111 in the second direction Y can be understood as the length of the first end 111 in the second direction Y. Similarly, the dimension of the second end 112 in the second direction Y can be understood as the length of the second end 112 in the second direction Y. When the insulating post 11 is cylindrical or frustum-shaped, the dimension of the first end 111 in the second direction Y is the radial length of the first end 111, and the dimension of the second end 112 in the second direction Y is the radial length of the second end 112. Since d1 is greater than d2, the shape of the insulating post 11 can be a frustum-shaped structure that is wider at the top and narrower at the bottom, and the XY cross-section of the insulating post 11 can be an inverted trapezoid.

[0089] With the above configuration, the end face area of ​​the first end 111 is larger than the end face area of ​​the second end 112, which helps to increase the contact area between the insulating post 11 and the conductive post 12, and further helps to increase the supporting force of the insulating post 11 on the conductive post 12, thereby helping to improve the stability of the semiconductor structure 1000.

[0090] In some embodiments, reference Figure 4 and Figure 5 The insulating post 11 has a first end face 113, and the conductive post 12 has a second end face 123. The first end face 113 is in contact with the second end face 123, and the edge of the first end face 113 coincides with the edge of the second end face 123.

[0091] It should be noted that, here, the first end face 113 refers to the end face of the first end 111 in some of the previous embodiments, while the second end face 123 is not the end face of the second end 112 in some of the previous embodiments. The second end face 123 refers to the end face of the end where the conductive post 12 contacts the insulating post 11.

[0092] If the edge of the first end face 113 coincides with the edge of the second end face 123, then the orthographic projection of the first end face 113 in the first direction X coincides with the orthographic projection of the second end face 123 in the first direction X. This arrangement helps to improve the supporting force of the insulating pillar 11 on the conductive pillar 12, thereby improving the stability of the semiconductor structure 1000.

[0093] In some embodiments, such as Figure 4 and Figure 5 As shown, the conductive post 12 includes a first sub-post 121 and a second sub-post 122 connected along the first direction X. The first sub-post 121 is located between the second sub-post 122 and the insulating post 11, and the first sub-post 121 is in contact with the insulating post 11. The first sub-post 121 has a second end face 123 in the above embodiment.

[0094] Furthermore, the first sub-post 121 is connected to one of the multiple bit lines BL, and the second sub-post 122 is spaced apart from the multiple bit lines BL. It should be noted that while the first sub-post 121 is connected to one of the multiple bit lines BL, and the second sub-post 122 is connected to the first sub-post 121 through the connection to one of the multiple bit lines BL, if the bit line BL connected to the first sub-post 121 is designated as the target bit line BL, then the second sub-post 122 is only electrically connected to the target bit line BL, and the second sub-post 122 is insulated from all other bit lines BL except the target bit line BL. For example, in some examples, the connection structure 10 also includes an isolation layer 13, which may be disposed around the second sub-post 122, and the isolation layer 13 is located between the bit line BL penetrated by the second sub-post 122 and the second sub-post 122. The isolation layer 13 is composed of an insulating material, such as silicon oxide.

[0095] With the above configuration, the second sub-pillar 122 is spaced apart and insulated from multiple bit lines BL. The first sub-pillar 121 is connected to one of the multiple bit lines BL, so that a connection structure 10 is connected to a corresponding bit line BL. This makes it easier for the semiconductor structure 1000 to select a specific bit line BL for reading / writing data, which helps improve the storage stability of the semiconductor structure 1000.

[0096] In some embodiments, reference Figure 4 and Figure 5 The dimension d3 of the first sub-pillar 121 in the second direction Y is greater than the dimension d4 of the second sub-pillar 122 in the second direction Y. The dimension d3 of the first sub-pillar 121 in the second direction Y can be understood as the length of the first sub-pillar 121 in the second direction Y. Similarly, the dimension d4 of the second sub-pillar 122 in the second direction Y can be understood as the length of the second sub-pillar 122 in the second direction Y. When the first sub-pillar 121 / second sub-pillar 122 is cylindrical or frustum-shaped, the dimension of the first sub-pillar 121 in the second direction Y is its radial length, and the dimension of the second sub-pillar 122 in the second direction Y is its radial length. Since d3 is greater than d4, the orthographic projection of the second sub-pillar 122 in the first direction X can be located within the edge of the orthographic projection of the first sub-pillar 121 in the first direction X.

[0097] Furthermore, the first sub-post 121 has many dimensions in the second direction Y, and the second sub-post 122 also has many dimensions in the second direction Y. Any dimension of the first sub-post 121 in the second direction Y is greater than any dimension of the second sub-post 122 in the second direction Y; that is, the minimum dimension of the first sub-post 121 in the second direction Y is greater than the maximum dimension of the second sub-post 122 in the second direction Y.

[0098] With the above configuration, in the second direction Y, the first sub-pillar 121 can protrude from the second sub-pillar 122, so that the first sub-pillar 121 and the bit line BL can be contacted and connected in the second direction Y, and the second sub-pillar 122 can be spaced apart from the bit line BL. It also facilitates the setting of an isolation layer 13 around the second sub-pillar 122, thereby improving the storage stability of the semiconductor structure 1000.

[0099] In some embodiments, reference Figure 4 and Figure 5 The second sub-post 122 has a third end 1221 and a fourth end 1222 along the first direction X, that is, the two ends of the second sub-post 122 along the first direction X are the third end 1221 and the fourth end 1222, respectively. Among them, the third end 1221 is farther away from the first sub-post 121 than the fourth end 1222, that is, the fourth end 1222 is in contact with the first sub-post 121.

[0100] like Figure 5 As shown, the dimension d5 of the third end 1221 in the second direction Y is greater than the dimension d6 of the fourth end 1222 in the second direction Y. Here, the dimension d5 of the third end 1221 in the second direction Y can be understood as the length of the third end 1221 in the second direction Y. Similarly, the dimension d6 of the fourth end 1222 in the second direction Y can be understood as the length of the fourth end 1222 in the second direction Y. When the second sub-post 122 is cylindrical or frustum-shaped, the dimension d5 of the third end 1221 in the second direction Y is the radial length of the third end 1221, and the dimension d6 of the fourth end 1222 in the second direction Y is the radial length of the fourth end 1222. Since d5 is greater than d6, the shape of the second sub-post 122 can be a frustum-shaped structure that is wider at the top and narrower at the bottom, and the XY cross-section of the second sub-post 122 can be an inverted trapezoid.

[0101] In some embodiments, reference Figure 4 The bit line BL connected to the first sub-post 121 is the first bit line BL-1. The first bit line BL-1 has a first surface 21 and a second surface 22 that are arranged opposite to each other. The direction from the first surface 21 to the second surface 22 is the same as the direction from the insulating post 11 to the conductive post 12. Figure 4 In the diagram, the first surface 21 is the lower surface of the first line BL-1, and the second surface 22 is the upper surface of the first line BL-1.

[0102] In some examples, reference Figure 4 , Figure 6 and Figure 7 In the first direction X, the contact surfaces (first end face 113 and second end face 123) of the insulating post 11 and the conductive post 12 are located between the first surface 21 and the second surface 22. It should be noted that since the connecting structure 10 penetrates the first line BL-1 along the first direction X, both the first surface 21 and the second surface 22 are penetrated by the connecting structure 10. Therefore, the contact surfaces of the insulating post 11 and the conductive post 12 are not covered by the first surface 21 / second surface 22 in the first direction X. Exemplarily, in the first direction X, the contact surfaces of the insulating post 11 and the conductive post 12 can also be flush with the first surface 21.

[0103] Here, it can be understood that, in the first direction X, the contact surface between the insulating post 11 and the conductive post 12 is located between the plane containing the first surface 21 and the plane containing the second surface 22, which will not be elaborated further below. It can also be understood that the orthographic projection of the contact surface between the insulating post 11 and the conductive post 12 in the second direction Y is located within the edge of the orthographic projection of the first line BL-1 in the second direction Y; or, the orthographic projection of the contact surface between the insulating post 11 and the conductive post 12 in the second direction Y coincides with the edge of the orthographic projection of the first line BL-1 in the second direction Y.

[0104] With the above configuration, in the first direction X, the contact surface between the insulating post 11 and the conductive post 12 can be positioned at the location of the first line BL-1, facilitating the connection between the conductive post 12 and the first line BL-1. Furthermore, in the first direction X, the contact surface between the insulating post 11 and the conductive post 12 is located between the first surface 21 and the second surface 22, ensuring the connection between the conductive post 12 and the first line BL-1, which improves the process window for forming the first sub-post 121 and the second sub-post 122.

[0105] In some examples, reference Figure 4 In the first direction X, the contact surface between the insulating post 11 and the conductive post 12 is flush with the first surface 21. In the direction from the first surface 21 to the second surface 22, the first sub-post 121 is recessed within the second surface 22. At this time, in the first direction X, the first sub-post 121 is located between the first surface 21 and the second surface 22, and the second end face 123 (reference) Figure 5 The first sub-pillar 121 is flush with the first surface 21 in the first direction X. Similarly, this can be understood as the first sub-pillar 121 being located between the plane containing the first surface 21 and the plane containing the second surface 22 in the first direction X.

[0106] With the above configuration, the sidewalls of the first sub-post 121 are all in contact with the first line BL-1, improving the connection stability between the first sub-post 121 and the first line BL-1. Furthermore, in the direction from the first surface 21 to the second surface 22, the first sub-post 121 is recessed within the second surface 22, which helps to save conductive material and reduce production costs.

[0107] In other examples, refer to Figure 6 In the first direction X, the contact surface between the insulating post 11 and the conductive post 12 is located between the first surface 21 and the second surface 22. In the direction from the first surface 21 to the second surface 22, the first sub-post 121 is recessed within the second surface 22. At this time, in the first direction X, the first sub-post 121 is located between the first surface 21 and the second surface 22.

[0108] With the above configuration, the sidewalls of the first sub-post 121 are all in contact with the first line BL-1, improving the connection stability between the first sub-post 121 and the first line BL-1. Furthermore, in the direction from the first surface 21 to the second surface 22, the first sub-post 121 is recessed within the second surface 22, which helps to save conductive material and reduce production costs.

[0109] In other examples, refer to Figure 7In the first direction X, the contact surface between the insulating post 11 and the conductive post 12 is located between the first surface 21 and the second surface 22. In the direction from the first surface 21 to the second surface 22, the first sub-post 121 protrudes from the second surface 22. At this time, with the first surface 21 as the lowest plane, the first sub-post 121 protrudes from the second surface 22, that is, the top surface of the first sub-post 121 is higher than the second surface 22.

[0110] In this example, the sidewall of the first sub-pillar 121 is in contact with the first bit line BL-1. This arrangement helps to increase the contact area between the first sub-pillar 121 and the first bit line BL-1, thereby reducing the contact resistance between the first sub-pillar 121 and the first bit line BL-1. It also helps to improve the connection stability between the first sub-pillar 121 and the first bit line BL-1 and optimize the storage performance of the semiconductor structure 1000.

[0111] In other examples, refer to Figure 8 In the first direction X, the contact surface between the insulating post 11 and the conductive post 12 is located on the side of the first surface 21 that is away from the second surface 22. At this time, taking the contact surface between the insulating post 11 and the conductive post 12 as the lowest plane, the first surface 21 is higher than the contact surface between the insulating post 11 and the conductive post 12, and the second surface 22 is higher than the first surface 21.

[0112] With the above settings, when forming the insulating post 11, it is not necessary to make the first end face 113 (reference) of the insulating post 11. Figure 5 The position of the first sub-pillar 121 between the first surface 21 and the second surface 22 helps to expand the process window. Furthermore, it helps to increase the contact area between the first sub-pillar 121 and the first first line BL-1, thereby reducing the contact resistance between the first sub-pillar 121 and the first first line BL-1. It also helps to improve the connection stability between the first sub-pillar 121 and the first first line BL-1 and optimize the storage performance of the semiconductor structure 1000.

[0113] In other examples, refer to Figure 8 In the first direction X, the contact surface between the insulating post 11 and the conductive post 12 is located on the side of the first surface 21 away from the second surface 22. Furthermore, in the direction from the first surface 21 to the second surface 22, the first sub-post 121 is recessed within the second surface 22.

[0114] At this point, taking the contact surface between the insulating post 11 and the conductive post 12 as the lowest plane, the first surface 21 is higher than the contact surface between the insulating post 11 and the conductive post 12, the top surface of the first sub-post 121 is higher than the first surface 21, and the second surface 22 is higher than the top surface of the first sub-post 121. In the first direction X, the top surface of the first sub-post 121 is located between the first surface 21 and the second surface 22.

[0115] With the above settings, when forming the insulating post 11, it is not necessary to make the first end face 113 (reference) of the insulating post 11. Figure 5 The first sub-post 121 is positioned between the first surface 21 and the second surface 22, which helps to expand the process window. In the first direction X, the top surface of the first sub-post 121 is located between the first surface 21 and the second surface 22, so that the first sub-post 121 can contact and connect with the first line BL-1.

[0116] In other examples, refer to Figure 9 In the first direction X, the contact surface between the insulating post 11 and the conductive post 12 is located on the side of the first surface 21 facing away from the second surface 22. Furthermore, in the direction from the first surface 21 to the second surface 22, the first sub-post 121 protrudes from the second surface 22. Taking the contact surface between the insulating post 11 and the conductive post 12 as the lowest plane, the first surface 21 is higher than the contact surface between the insulating post 11 and the conductive post 12, the second surface 22 is higher than the first surface 21, and the top surface of the first sub-post 121 is higher than the second surface 22. In the first direction X, the first line BL-1 is located between the two end faces of the first sub-post 121 along the first direction X. This can also be understood as the orthographic projection of the first line BL-1 in the second direction Y being located between the edges of the orthographic projection of the first sub-post 121 in the second direction Y.

[0117] At this time, the thickness of the first sub-column 121 in the first direction X is greater than the thickness of the first line BL-1 in the first direction X.

[0118] The above configuration helps to increase the contact area between the first sub-pillar 121 and the first bit line BL-1, thereby reducing the contact resistance between the first sub-pillar 121 and the first bit line BL-1. It also helps to improve the connection stability between the first sub-pillar 121 and the first bit line BL-1 and optimize the storage performance of the semiconductor structure 1000.

[0119] In some embodiments, reference Figure 4 Among the multiple bit lines BL, there is a second bit line BL-2, which is adjacent to the first bit line BL-1. The minimum spacing d7 between the first sub-pillar 121 and the second bit line BL-2 is greater than 5nm. This arrangement maintains a safe distance between the first sub-pillar 121 and the second bit line BL-2, preventing coupling between them and improving the storage stability of the semiconductor structure 1000.

[0120] In some embodiments, reference Figure 10 and Figure 11 The bit line BL extends along the second direction Y. The semiconductor structure 1000 also includes a gate layer 40 and a plurality of channel structures 30 arranged in a row along the first direction X.

[0121] For example, the constituent material of the channel structure 30 may include a semiconductor material. Semiconductor materials include monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0122] For example, the constituent material of the gate layer 40 may include a conductive material. The conductive material may be, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or other suitable conductive materials.

[0123] In this configuration, the channel structure 30 extends along a third direction Z. Multiple channel structures 30 can be arranged in a column along a first direction X. In a column of channel structures 30, one channel structure 30 is connected to one bit line BL. Multiple channel structures 30 can also be arranged in multiple rows and columns along a second direction Y and the first direction X. If the bit line BL extends along the second direction Y, then one bit line BL can be connected to a row of channel structures 30. One end of the channel structure 30 along the third direction Z is connected to the bit line BL, and the other end of the channel structure 30 along the third direction Z is connected to the capacitor structure 60.

[0124] The gate layer 40 extends along a first direction X and is located on at least one side of a channel structure 30 along a second direction Y. For example, when the channel structure 30 and the gate layer 40 form a single-gate transistor, the channel structure 30 is coupled to one gate layer 40, and that gate layer 40 is located on one side of the channel structure 30 along the second direction Y. When the channel structure 30 and the gate layer 40 form a dual-gate transistor, the channel structure 30 is coupled to two gate layers 40, and the two gate layers 40 are respectively located on both sides of the channel structure 30 along the second direction Y.

[0125] For example, multiple channel structures 30 may be symmetrically arranged with respect to capacitor structure 60. Correspondingly, multiple bit lines BL may be symmetrically arranged with respect to capacitor structure 60, and multiple gate layers 40 may be symmetrically arranged with respect to capacitor structure 60, thereby forming a 3D stacked memory array.

[0126] The above setup enables the formation of a 3D stacked memory array, which is beneficial for improving the memory density and capacity of the semiconductor structure 1000 and for achieving miniaturization of device integration.

[0127] This disclosure also provides a method for fabricating a semiconductor structure 1000, which is described below in conjunction with some embodiments. Figures 12 to 22 The fabrication method of semiconductor structure 1000 is explained.

[0128] Figure 12 This is a flowchart illustrating a method for fabricating a semiconductor structure 1000 according to some embodiments. For example... Figure 12As shown, the method for fabricating the semiconductor structure 1000 includes: S1 to S2.

[0129] S1. Multiple bit lines are formed, and the multiple bit lines are spaced apart along a first direction, which is the thickness direction of the bit lines.

[0130] In this step, refer to Figure 13 The stacked structure 50 can be formed using a thin-film deposition process. The stacked structure 50 includes a plurality of dielectric layers 51 and a plurality of bit lines BL that are alternately arranged along a first direction X. For example, bit lines BL and dielectric layers 51 are alternately formed along the first direction X, and stacked to form a plurality of bit lines BL and a plurality of dielectric layers 51 that are spaced apart from each other.

[0131] The thin film deposition process includes any one of the following: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD).

[0132] For example, the dielectric layer 51 is composed of an insulating material. The bit line BL is composed of a conductive material. The insulating and conductive materials can be found in some of the embodiments described above, and will not be repeated here.

[0133] S2. A connection structure is formed, which extends through multiple bit lines along a first direction. The connection structure includes insulating pillars and conductive pillars arranged along the first direction. The insulating pillars and conductive pillars are in contact and connected, and the conductive pillars are connected to one of the multiple bit lines.

[0134] In this step, refer to Figure 13 and Figure 14 An etching process can be used to form a first through-hole 52, which penetrates the stacked structure 50. The etching process can include wet etching or dry etching.

[0135] The first via 52 can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed over the stacked structure 50. The patterned photoresist layer can expose the portion of the stacked structure 50 used to form the first via 52. A suitable etching process can be performed to remove the portion of the stacked structure 50 used to form the first via 52. For example, the etching process includes a dry etching process.

[0136] refer to Figure 14 and Figure 15 The first insulating pillar 53 can be formed by filling the first via 52 with an insulating material, such as silicon oxide, using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD.

[0137] refer to Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 A portion of the first insulating post 53 can be removed to form the second insulating post 55 and the second through hole 56.

[0138] In this step, refer to Figure 16 , Figure 17 , Figure 18 and Figure 19 A mask layer 54 can be formed on the stacked structure 50, and then a portion of the mask layer 54 can be removed multiple times using photolithography. Furthermore, each removal of a portion of the mask layer 54 increases the number of exposed first insulating pillars 53, and a dry etching process is used to remove the exposed first insulating pillars 53, thereby reducing the height of the first insulating pillars 53 in the first direction X. After performing the above steps multiple times, refer to... Figure 19 Multiple second insulating pillars 55 can be formed along the second direction Y, with their heights increasing or decreasing sequentially.

[0139] Through the above steps, multiple second insulating pillars 55 with increasing / decreasing height along the second direction Y, and multiple second vias 56 with increasing / decreasing depth along the second direction Y, can be formed. In some other embodiments, a portion of the first insulating pillars 53 can be removed in a single etching process to form the second insulating pillars 55 and the second vias 56. However, when etching other first insulating pillars 53 subsequently, sacrificial material needs to be filled into the second vias 56 to protect the second insulating pillars 55 from etching. In this embodiment, in the above steps, multiple first insulating pillars 53 are etched together by sequentially opening the mask layer 54, and multiple second insulating pillars 55 and multiple second vias 56 are formed together in the final etching step. There is no need to fill with sacrificial material, which helps to reduce the production cost of the semiconductor structure 1000 and reduces the steps of filling and removing sacrificial material, which helps to simplify the process steps and improve the fabrication efficiency of the semiconductor structure 1000.

[0140] After forming the second insulating pillar 55 and the second through hole 56, refer to Figure 19 and Figure 20 The isolation layer 13 can be formed by employing one or more thin-film deposition processes, including but not limited to PVD, CVD, and ALD, and the isolation layer 13 covers the wall of the second via 56. Exemplarily, the material of the isolation layer 13 includes an insulating material, such as silicon oxide.

[0141] After the formation of isolation layer 13, refer to Figure 20 and Figure 21An etching process can be used, for example, by injecting etching solution into the second via 56 to remove a portion of the second insulating pillar 55, exposing at least a portion of the bit line BL to form the insulating pillar 11. In this step, a portion of the bit line BL is exposed in the second via 56 so that the bit line BL can be led out. The remaining second insulating pillar 55 constitutes the insulating pillar 11.

[0142] After exposing part of the bit line BL in the second via 56, refer to Figure 21 and Figure 22 Conductive pillars 12 can be formed by filling the second via 56 with a conductive material, such as a metallic material, using one or more thin-film deposition processes, including but not limited to PVD, CVD, and ALD. An isolation layer 13 is disposed around a portion of the conductive pillar 12 to connect the conductive pillar 12 to one of a plurality of bit lines BL.

[0143] In the semiconductor structure 1000 prepared by the above method, each bit line BL of the semiconductor structure 1000 is penetrated by the connecting structure 10, thus reducing the area of ​​each bit line BL. Here, the area refers to the area of ​​the bit line BL in the YZ plane. Furthermore, the area between two adjacent bit lines BL is reduced, which helps to reduce the coupling between two adjacent bit lines BL and improve the storage performance of the semiconductor structure 1000.

[0144] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A plurality of bit lines are spaced apart along a first direction, wherein the first direction is perpendicular to the extension direction of the bit lines; The connection structure extends through the plurality of bit lines along the first direction and includes insulating posts and conductive posts arranged along the first direction. The insulating posts are in contact with the conductive posts, and the conductive posts are connected to one of the plurality of bit lines.

2. The semiconductor structure according to claim 1, characterized in that, The insulating post has a first end and a second end along the first direction, the first end being closer to the conductive post than the second end, and the dimension of the first end in the second direction being greater than the dimension of the second end in the second direction; the second direction is perpendicular to the first direction.

3. The semiconductor structure according to claim 1, characterized in that, The insulating post has a first end face, and the conductive post has a second end face. The first end face is in contact with the second end face, and the edge of the first end face coincides with the edge of the second end face.

4. The semiconductor structure according to claim 1, characterized in that, The conductive post includes a first sub-post and a second sub-post connected to each other. The first sub-post is located between the second sub-post and the insulating post. The first sub-post is connected to one of the plurality of bit lines, and the second sub-post is spaced apart from the plurality of bit lines.

5. The semiconductor structure according to claim 4, characterized in that, The dimension of the first sub-post in the second direction is greater than the dimension of the second sub-post in the second direction; the second direction is perpendicular to the first direction.

6. The semiconductor structure according to claim 4, characterized in that, The second sub-post has a third end and a fourth end along the first direction, the third end being farther away from the first sub-post than the fourth end, and the dimension of the third end in the second direction being greater than the dimension of the fourth end in the second direction; the second direction is perpendicular to the first direction.

7. The semiconductor structure according to claim 4, characterized in that, The connection structure further includes an isolation layer, which is disposed around the second sub-post and is located between the bit line penetrated by the second sub-post and the second sub-post.

8. The semiconductor structure according to claim 4, characterized in that, The bit line connected to the first sub-post is the first bit line. The first bit line has a first surface and a second surface that are disposed opposite to each other. The direction from the first surface to the second surface is the direction from the insulating post to the conductive post. In the first direction, the contact surface between the insulating post and the conductive post is located between the first surface and the second surface; or, In the first direction, the contact surface between the insulating post and the conductive post is located on the side of the first surface away from the second surface.

9. The semiconductor structure according to claim 8, characterized in that, In the direction from the first surface to the second surface, the first sub-pillar is recessed within the second surface; or, In the direction from the first surface to the second surface, the first sub-post protrudes from the second surface.

10. The semiconductor structure according to any one of claims 4-9, characterized in that, The plurality of bit lines includes a second bit line, which is adjacent to the first bit line, and the minimum spacing between the first sub-pillar and the second bit line is greater than 5 nm.

11. The semiconductor structure according to claim 1, characterized in that, The bit line extends along a second direction; the semiconductor structure further includes: A plurality of channel structures are arranged in a row along the first direction, each channel structure is connected to a bit line, and the channel structure extends along a third direction; the third direction intersects the plane containing the first direction and the second direction; A gate layer, extending along the first direction, is located on at least one side of a series of channel structures along the second direction.

12. A method for fabricating a semiconductor structure, characterized in that, include: Multiple bit lines are formed, and the multiple bit lines are spaced apart along a first direction, the first direction being the thickness direction of the bit lines; A connection structure is formed, which extends through the plurality of bit lines along the first direction. The connection structure includes insulating pillars and conductive pillars arranged along the first direction. The insulating pillars are in contact with the conductive pillars, and the conductive pillars are connected to one of the plurality of bit lines.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The formation of multiple bit lines includes: A stacked structure is formed, the stacked structure comprising a plurality of dielectric layers and a plurality of bit lines alternately arranged along the first direction; The formation of the connection structure includes: A first through-hole is formed, which penetrates the stacked structure; The first through hole is filled with insulating material to form a first insulating pillar; A portion of the first insulating post is removed to form a second insulating post and a second through hole; An isolation layer is formed, which covers the wall of the second through hole; Remove a portion of the second insulating post to expose at least a portion of the bit line to form an insulating post; The second through hole is filled with conductive material to form the conductive pillar.

14. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-11; A controller, the control being coupled to the semiconductor structure, to control the semiconductor structure to store data.

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