Semiconductor structure and method of manufacturing the same, storage system

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof and a storage system, and relates to the technical field of semiconductor chips, aiming to improve the coupling between adjacent connection structures. The semiconductor structure comprises a connection structure, a first isolation structure and a plurality of bit lines arranged at intervals along a first direction. The bit lines extend along a second direction, and the first direction is perpendicular to the second direction; the connection structure extends along the first direction and is connected with one of the plurality of bit lines; the first isolation structure is located on at least one side of the connection structure along the second direction, and the first isolation structure and the connection structure overlap in the second direction. By arranging the first isolation structure on at least one side of the connection structure along the second direction, the connection structure is isolated from other conductive structures in the second direction, which is conducive to improving the coupling between adjacent connection structures in the second direction, optimizing the accuracy of reading or writing data of the semiconductor structure, and improving the storage performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] With the continuous evolution of Dynamic Random Access Memory (DRAM), the storage density of planar DRAM has gradually approached the limits of process technology. In order to further improve the storage density of DRAM, memory with 3D stacked memory cells has been developed. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and a memory system.

[0004] The embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a semiconductor structure is provided, comprising: a plurality of bit lines spaced apart along a first direction, a connection structure, and a first isolation structure. The bit lines extend along a second direction, the first direction being perpendicular to the second direction; the connection structure extends along the first direction and is connected to one of the plurality of bit lines; the first isolation structure is located on at least one side of the connection structure along the second direction, and the first isolation structure overlaps the connection structure in the second direction.

[0006] In some embodiments, the first isolation structure extends through the plurality of bit lines along the first direction.

[0007] In some embodiments, the first isolation structure has a first gap, which overlaps with the connecting structure in the second direction.

[0008] In some embodiments, the first isolation structure includes: a first conductive post and a first isolation layer, the first conductive post extending along the first direction, the first isolation layer surrounding the first conductive post, and the first isolation layer being located between the first conductive post and the bit line.

[0009] In some embodiments, the first conductive post has a first end face and a second end face arranged along the first direction, and the area of ​​the first end face is greater than the area of ​​the second end face.

[0010] In some embodiments, the first conductive post includes: a first portion and a second portion stacked along the first direction, the first portion having the first end face, the second portion having the second end face, and the width of the first portion in the second direction being greater than the width of the second portion in the second direction.

[0011] In some embodiments, the semiconductor structure further includes a second isolation structure located between adjacent bit lines, wherein the connection structure extends through the second isolation structure.

[0012] In some embodiments, the second isolation structure has a second gap.

[0013] In some embodiments, the second isolation structure includes a conductive layer and a second isolation layer, the conductive layer extending along the second direction, the second isolation layer being located between the conductive layer and the bit line, and the second isolation layer also being located between the conductive layer and the connection structure.

[0014] In some embodiments, when the first isolation structure includes a first conductive post and a first isolation layer, the conductive layer is connected to the first conductive post, and the material of the conductive layer is the same as the material of the first conductive post.

[0015] In some embodiments, the bit line connected to the connection structure is a first bit line. The connection structure includes a second conductive post and a third isolation layer. The second conductive post extends through the first bit line and is connected to the first bit line. The third isolation layer is disposed around the second conductive post.

[0016] In some embodiments, the semiconductor structure further includes a support structure extending through the plurality of bit lines along the first direction and located on the other side of the connection structure along the second direction, wherein the material of the support structure is different from the material of the first isolation structure.

[0017] In some embodiments, the connection structure extends through the plurality of bit lines, and the connection structure includes an insulating post and a third conductive post stacked along the first direction, the insulating post being in contact with the conductive post, and the conductive post being connected to one of the plurality of bit lines.

[0018] In some embodiments, the system further includes: a gate layer and a plurality of channel structures arranged in a row along the first direction, one of the channel structures being connected to a bit line, the channel structures extending along a third direction; the third direction intersecting the plane containing the first direction and the second direction; the gate layer extending along the first direction and located on at least one side of a row of channel structures along the second direction.

[0019] On the other hand, a method for fabricating a semiconductor structure is also provided, comprising: forming a plurality of bit lines, the plurality of bit lines being spaced apart along a first direction, the bit lines extending along a second direction, the first direction being perpendicular to the second direction; forming a connection structure, the connection structure extending along the first direction, the connection structure being connected to one of the plurality of bit lines; and forming a first isolation structure, the first isolation structure being located on one side of the connection structure along the second direction, and the first isolation structure overlapping the connection structure in the second direction.

[0020] In some embodiments, forming a plurality of bit lines includes: forming a stacked structure, the stacked structure including a plurality of dielectric layers and a plurality of bit lines alternately disposed along the first direction; forming a first isolation structure includes: forming a first via, the first via penetrating the stacked structure; and replacing the dielectric layer with the second isolation structure through the first via.

[0021] In some embodiments, forming the first isolation structure further includes: filling the first through-hole with a sacrificial material to form a sacrificial pillar; removing a portion of the sacrificial pillar to form a second through-hole; depositing a dielectric material on the sidewall of the second through-hole; and removing the sacrificial pillar.

[0022] In some embodiments, forming the first isolation structure further includes: forming the first isolation structure in the first through hole by a vapor deposition process, the first isolation structure having a first gap, the first gap overlapping the connecting structure in the second direction.

[0023] In some embodiments, forming the first isolation structure further includes: sequentially forming a first isolation layer and a first conductive post in the first through hole, wherein the first conductive post extends along the first direction, the first isolation layer is disposed around the first conductive post, and the first isolation layer is located between the first conductive post and the bit line.

[0024] In some embodiments, replacing the dielectric layer with the second isolation structure includes: removing the dielectric layer through the first through-hole to form a first filling space, the first filling space being in communication with the first through-hole; and forming the second isolation structure within the first filling space by a vapor deposition process, the second isolation structure having a second gap.

[0025] In some embodiments, replacing the dielectric layer with the second isolation structure includes: removing the dielectric layer through the first via to form a first filling space; and sequentially forming a second isolation layer and a conductive layer in the first filling space to form the second isolation structure.

[0026] In some embodiments, forming the first isolation structure includes: sequentially forming a first isolation layer and a first conductive pillar in the first through hole, wherein the first isolation layer and the second isolation layer are formed in one process, and the first conductive pillar and the conductive layer are formed in one process.

[0027] In some embodiments, forming a connection structure includes: sequentially forming a third isolation layer and a second conductive post, the second conductive post extending through to and connecting to the first bit line, the third isolation layer surrounding the second conductive post, and the first bit line being one of the plurality of bit lines; forming a support structure that extends through the stacked structure.

[0028] In some embodiments, forming a connection structure includes: forming an insulating post and a third conductive post stacked along the first direction, the insulating post being in contact with the third conductive post, and the third conductive post being connected to one of the plurality of bit lines.

[0029] In another aspect, a storage system is provided, comprising: a semiconductor structure as described above and a controller, the controller being coupled to the semiconductor device to control the semiconductor device to store data. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0031] Figure 1 A block diagram of an electronic device according to some embodiments;

[0032] Figure 2 A block diagram of a memory according to some embodiments;

[0033] Figure 3 A top view of a semiconductor structure according to some embodiments Figure 1 ;

[0034] Figure 4 for Figure 3 A cross-sectional view of AA in the diagram;

[0035] Figure 5 A top view of a semiconductor structure according to some embodiments Figure 2 ;

[0036] Figure 6 for Figure 5 A cross-sectional view of BB in the image;

[0037] Figure 7 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 1 ;

[0038] Figure 8 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 2 ;

[0039] Figure 9 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 3 ;

[0040] Figure 10 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 4 ;

[0041] Figure 11 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 5 ;

[0042] Figure 12 A top view of a semiconductor structure according to some embodiments Figure 3 ;

[0043] Figure 13 This is a schematic diagram of a semiconductor structure according to some embodiments. Figure 6 ;

[0044] Figure 14 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0045] Figures 15a-15f This is a schematic diagram of the semiconductor structure during the fabrication process according to some embodiments;

[0046] Figures 16a-16e This is a schematic diagram of the semiconductor structure during the fabrication process according to some other embodiments;

[0047] Figures 17a-17d This is a schematic diagram of the semiconductor structure during the fabrication process according to some of the embodiments.

[0048] Reference numerals: 9000, Electronic device; 910, Storage system; 911, Memory; 912, Controller; 920, Motherboard; X, First direction; Y, Second direction; Z, Third direction; BL, Bit line; BL-1, First bit line; 1000, Semiconductor structure; 10, Connection structure; 11, Second conductive post; 12, Third isolation layer; 13, Insulating post; 14, Third conductive post; 20, First isolation structure; 201, First gap; 21, First conductor... 211. Electrostatic post; 212. First end face; 213. Second end face; 214. First portion; 215. Second portion; 22. First isolation layer; 30. Second isolation structure; 301. Second gap; 31. Conductive layer; 32. Second isolation layer; 40. Support structure; 50. Channel structure; 60. Gate layer; 70. Capacitor structure; 80. Stacked structure; 81. Dielectric layer; 82. First via; 83. Sacrificial post; 84. Second via; 85. First fill space. Detailed Implementation

[0049] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0050] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0051] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0052] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0053] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0054] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0055] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0056] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0057] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0058] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0059] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, the difference between the two equalities being less than or equal to 5% of either one.

[0060] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0061] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0062] Figure 1 This is a block diagram of an electronic device according to some embodiments. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, server, in-vehicle equipment, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0063] like Figure 1As shown, the electronic device 9000 may include a storage system 910 and a motherboard 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0064] The motherboard 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The motherboard 920 may be configured to send data to or receive data from memory.

[0065] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the memory 911 and the motherboard 920 and is configured to control the memory 911 to store data while also communicating with external devices (e.g., a host computer).

[0066] The number of memories 911 in the storage system 910 can be one or more. Figure 1The diagram uses three memories 911 as an example. The controller 912 manages the data stored in each memory 911 and communicates with the motherboard 920. The controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management.

[0067] In some implementations, controller 912 is also configured to determine the maximum memory capacity available to the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Controller 912 may also perform any other suitable functions. Controller 912 can communicate with external devices (e.g., motherboard 920) according to a specific communication protocol. For example, controller 912 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0068] The controller 912 mentioned above may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0069] In this embodiment, the storage system 910 can be integrated into various types of storage devices, and is not limited to the electronic device 9000 in the above embodiment.

[0070] Figure 2 This is a block diagram of a memory according to some embodiments. For example... Figure 2 As shown, memory 911 includes a memory cell array 913 and peripheral circuitry 914 for controlling the memory cell array 913. Peripheral circuitry 914 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 913. For example, peripheral circuitry 914 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0071] For example, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0072] The memory cell array 913 and the peripheral circuitry 914 can be arranged side-by-side in the same plane, for example, on the same wafer; that is, the memory cell array 913 and the peripheral circuitry 914 can be located in the same semiconductor device. Alternatively, the memory cell array 913 and the peripheral circuitry 914 can be formed on different wafers and bonded together face-to-face. Figure 2 As shown, when the memory cell array 913 and the peripheral circuitry 914 are formed on different wafers and bonded together face-to-face, the memory 911 may include a first semiconductor structure 901 and a second semiconductor structure 902, as well as a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. The first semiconductor structure 901 may include the memory cell array 913, and the second semiconductor structure 902 may include the peripheral circuitry 914.

[0073] The memory cell array 913 may be an array of memory cells that use vertical transistors as switching and selection devices. In some embodiments, the memory cell array 913 may be a dynamic random access memory (DRAM) cell array. For ease of description, DRAM cell array may be used to describe an example of the memory cell array 913 in this disclosure. However, it should be understood that the memory cell array 913 is not limited to DRAM cell arrays, and may include any other suitable type of memory cell array 913 that can use vertical transistors as switching and selection devices, such as PCM cell arrays, static random-access memory (SRAM) cell arrays, FRAM cell arrays, resistive memory cell arrays, magnetic memory cell arrays, spin transfer torque (STT) memory cell arrays, etc.

[0074] When the memory cell array 913 is a DRAM cell array, the memory cells therein are DRAM cells. A DRAM cell includes a capacitor and one or more transistors. The capacitor stores data as positive or negative charge, and the one or more transistors (also called transfer transistors) control (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor and a capacitor (1T1C) cell. According to some embodiments, the DRAM cell can be refreshed by peripheral circuitry 914 to retain data.

[0075] As DRAM technology continues to evolve, the storage density of DRAM cells on a plane has gradually approached the limits of the manufacturing process. In order to further improve the storage density of DRAM cells, some embodiments of this disclosure provide a memory with 3D stacked DRAM cells. In the memory with 3D stacked DRAM cells, multiple storage cells are arranged into a storage array in the XY plane, and multiple storage arrays are also spaced apart along the Z direction.

[0076] In this embodiment, the first direction X intersects with the second direction Y, and the third direction Z intersects with the plane containing the first direction X and the second direction Y. For ease of understanding, in the embodiments of this disclosure, the first direction X, the second direction Y, and the third direction Z are set to be mutually perpendicular.

[0077] A memory cell includes a transistor T and a capacitor C. The transistor T can be formed by a channel structure formed by a semiconductor layer and a gate layer adjacent to the channel structure. A gate dielectric layer is also disposed between the semiconductor layer and the corresponding gate layer.

[0078] The semiconductor layer may include semiconductor materials, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The semiconductor layer may have source and drain electrodes, and the source and drain electrodes may be semiconductor materials doped with P-type or N-type dopants. P-type dopants include boron or gallium. N-type dopants include phosphorus or arsenic.

[0079] The gate layer of transistor T can be connected to word line WL. Word line WL can extend along a first direction X. The drain of transistor T can be connected to bit line BL, which can extend along a second direction Y. The source of transistor T is connected to one plate of capacitor C, and the other plate of capacitor C can be connected to a reference voltage, which can be ground or another voltage. The capacitor C can represent logical 1 and 0 by the amount of charge stored in it, or the high or low voltage difference across the capacitor C. With the above settings, the memory can control the transistor T to be turned on or off by applying a voltage to word line WL. When transistor T is turned on, bit line BL performs read or write operations on capacitor C.

[0080] This disclosure provides a semiconductor structure 1000 in some embodiments. The semiconductor structure 1000 can be part of the memory 911 in some of the above embodiments. For example, the semiconductor structure 1000 can be the first semiconductor structure 901; or, if the semiconductor structure 1000 can be the memory 911, the semiconductor structure 1000 can also include peripheral circuitry 914, which is not limited in this respect.

[0081] refer to Figure 3 and Figure 4 This disclosure provides a semiconductor structure 1000, comprising: a connection structure 10 and a plurality of bit lines BL spaced apart along a first direction X. The bit lines BL extend along a second direction Y, and the first direction X is perpendicular to the second direction Y.

[0082] The connection structure 10 extends along a first direction X and is connected to one of a plurality of bit lines BL. The connection structure 10 is used to lead one of the plurality of bit lines BL to an external circuit. For example, the semiconductor structure 1000 may include a plurality of connection structures 10, which can be connected one-to-one with a plurality of bit lines BL, thereby leading the plurality of bit lines BL to an external circuit respectively.

[0083] Since the connection structure 10 is used to lead out the bit line BL, the constituent materials of the connection structure 10 include conductive materials. Conductive materials include, but are not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or other suitable conductive materials.

[0084] However, other conductive structures adjacent to the connection structure 10 in the second direction Y are prone to coupling with the connection structure 10. For example, coupling can easily occur between two adjacent connection structures 10 along the second direction Y, affecting the reading or writing of data by the semiconductor structure 1000.

[0085] Based on this, the semiconductor structure 1000 in this embodiment further includes a first isolation structure 20. The first isolation structure 20 is located on at least one side of the connection structure 10 along the second direction Y. In some examples, the first isolation structure 20 is located only on one side of the connection structure 10 along the second direction Y. In other examples, the semiconductor structure 1000 may include multiple first isolation structures 20, in which case the first isolation structure 20 may be provided on both sides of the connection structure 10 along the second direction Y.

[0086] Furthermore, the first isolation structure 20 overlaps with the connecting structure 10 in the second direction Y. Here, the overlap of the first isolation structure 20 and the connecting structure 10 in the second direction Y can be understood as the orthographic projection of the first isolation structure 20 in the second direction Y overlapping with the orthographic projection of the connecting structure 10 in the second direction Y. It is worth noting that the orthographic projections of the first isolation structure 20 and the connecting structure 10 in the second direction Y only need to overlap; for example, they can partially overlap without being completely identical.

[0087] For example, the constituent materials of the first isolation structure 20 may include an insulating material. The insulating material may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or may be other suitable insulating materials.

[0088] By placing the first isolation structure 20 on at least one side of the connection structure 10 along the second direction Y, the connection structure 10 is isolated from other conductive structures in the second direction Y. This helps to improve the coupling between the connection structure 10 and other conductive structures adjacent to the connection structure 10 in the second direction Y. For example, it improves the coupling between adjacent connection structures 10 along the second direction Y. This helps to optimize the accuracy of reading or writing data in the semiconductor structure 1000 and improve the storage performance of the semiconductor structure 1000.

[0089] Since multiple bit lines BL are spaced apart along the first direction X, and since the constituent materials of the bit lines BL include conductive materials, two adjacent bit lines BL are similar to two opposing electrode plates. Two adjacent bit lines BL may form a "capacitive structure 70," which can also be understood as a coupling problem between adjacent bit lines BL. This can affect the semiconductor structure 1000's ability to read or write data, for example, causing the semiconductor structure 1000 to misinterpret data, thus affecting the storage performance of the semiconductor structure 1000. Furthermore, as the size of the semiconductor structure 1000 is compressed, the spacing between the bit lines BL is also compressed, further exacerbating the degree of coupling between adjacent bit lines BL, which is detrimental to the semiconductor structure 1000's ability to read or write data.

[0090] Based on this, in some embodiments, reference is made to Figure 3 and Figure 4 The first isolation structure 20 extends along the first direction X, and the first isolation structure 20 passes through multiple bit lines BL along the first direction X.

[0091] It should be noted that although the first isolation structure 20 penetrates multiple bit lines BL along the first direction X, the first isolation structure 20 does not sever the continuity of the bit lines BL along the second direction Y; the bit lines BL still extend along the second direction Y without being broken. For example, at the position where the first isolation structure 20 penetrates the bit lines BL, on the YZ plane, the bit lines BL can be arranged around the first isolation structure 20.

[0092] With the above configuration, each bit line BL is penetrated by the connecting structure 10, thus reducing the area of ​​each bit line BL. Here, the area refers to the area of ​​the bit line BL in the YZ plane. Furthermore, the area between two adjacent bit lines BL is reduced, which helps to reduce the coupling between two adjacent bit lines BL and improve the storage performance of the semiconductor structure 1000.

[0093] In some embodiments, reference Figure 4 The first isolation structure 20 has a first gap 201, which overlaps with the connecting structure 10 in the second direction Y. Here, it can be understood that the orthographic projection of the connecting structure 10 in the second direction Y overlaps with the orthographic projection of the first gap 201 in the second direction Y, for example, it may partially overlap. The orthographic projection of the first gap 201 in the second direction Y refers to the orthographic projection of the closed shape enclosed by the edge of the first gap 201 in the second direction Y.

[0094] The first gap 201 can be filled with air. The dielectric constant of air is less than that of the dielectric material (e.g., silicon oxide). Therefore, setting the first gap 201 inside the first isolation structure 20 is beneficial to improving the isolation capability of the first isolation structure 20, further improving the coupling between adjacent connection structures 10 along the second direction Y, optimizing the accuracy of reading or writing data in the semiconductor structure 1000, and improving the storage performance of the semiconductor structure 1000.

[0095] In other embodiments, reference is made to... Figure 5 and Figure 6 The first isolation structure 20 may include a first conductive post 21 and a first isolation layer 22. The first conductive post 21 extends along a first direction X, and the first isolation layer 22 is disposed around the first conductive post 21 and is located between the first conductive post 21 and the bit line BL.

[0096] For example, the first insulating layer 22 is composed of an insulating material. The first conductive pillar 21 may be composed of a conductive material. The insulating / conductive materials can be referred to in some of the preceding embodiments, and will not be repeated here.

[0097] With the above settings, the first conductive post 21 can be connected to a low potential, thereby improving the isolation capability of the first isolation structure 20, better shielding the connection structure 10, preventing coupling of adjacent connection structures 10 along the second direction Y, and optimizing the accuracy of reading / writing data of the semiconductor structure 1000.

[0098] Furthermore, by setting the first isolation layer 22 between the first conductive post 21 and the bit line BL, the first conductive post 21 and the bit line BL are isolated, preventing short circuit between the first conductive post 21 and the bit line BL, thereby improving the storage stability of the semiconductor structure 1000.

[0099] In some embodiments, reference Figure 6 The first conductive post 21 has a first end face 211 and a second end face 212 arranged along the first direction X, and the area of ​​the first end face 211 is larger than the area of ​​the second end face 212.

[0100] For example, the first conductive post 21 can be a frustum-shaped structure. The first end face 211 and the second end face 212 arranged along the first direction X are the two bottom surfaces of the first conductive post 21, and the area of ​​the first end face 211 is greater than the area of ​​the second end face 212.

[0101] With the above configuration, the first conductive post 21 can be connected to a low potential through the first end face 211. The area of ​​the first end face 211 is larger than that of the second end face 212, which is beneficial to expanding the process window, facilitating connection to a low potential, and also helps to reduce contact resistance.

[0102] In other embodiments, reference is made to... Figure 6 The first conductive post 21 includes a first portion 213 and a second portion 214 stacked along a first direction X. Exemplarily, the shape of the first portion 213 / second portion 214 may include a cylindrical shape or a frustum shape. The central axis of the first portion 213 may coincide with the central axis of the second portion 214 so that the second portion 214 can support the first portion 213.

[0103] The first part 213 has a first end face 211, and the second part 214 has a second end face 212. The width of the first part 213 in the second direction Y is greater than the width of the second part 214 in the second direction Y. The width of the first part 213 in the second direction Y can be understood as the radial width of the first part 213. The width of the second part 214 in the second direction Y can be understood as the radial width of the second part 214.

[0104] Since the first portion 213 has a first end face 211, it can be used to connect to peripheral circuits, which helps to expand the process window and facilitates connecting the first conductive post 21 to a fixed low potential. The first portion 213 is used for connection to peripheral circuits, and the second portion 214 is used to shield adjacent connection structures 10 along the second direction Y. Therefore, the length of the first portion 213 in the first direction X does not need to be large; the length of the first portion 213 in the first direction X is less than the length of the second portion 214 in the first direction X. The second portion 214 can extend along the first direction X and penetrate multiple bit lines BL. An isolation layer can be disposed around the second portion 214 to shield adjacent connection structures 10 along the second direction Y, which helps to prevent coupling of adjacent connection structures 10 along the second direction Y and optimizes the accuracy of reading / writing data in the semiconductor structure 1000.

[0105] In some embodiments provided in this disclosure, the semiconductor structure 1000 further includes a second isolation structure 30, which is described below in conjunction with... Figures 7-11 Some feasible embodiments of the second isolation structure 30 will be explained and described below. Furthermore, embodiments of the semiconductor structure 1000 including the second isolation structure 30 can also be combined with some of the embodiments described above.

[0106] In some embodiments, reference Figure 7 The semiconductor structure 1000 also includes a second isolation structure 30. The second isolation structure 30 is located between adjacent bit lines BL, and the connection structure 10 passes through the second isolation structure 30.

[0107] For example, the constituent materials of the second isolation structure 30 may include insulating materials.

[0108] Since coupling can easily occur between adjacent bit lines BL, affecting the accuracy of reading / writing data in the semiconductor structure 1000, a second isolation structure 30 is provided between two adjacent bit lines BL along the first direction X to isolate the two adjacent bit lines BL, thereby improving the coupling between adjacent bit lines BL and enhancing the accuracy of reading / writing data in the semiconductor structure 1000.

[0109] It is worth noting that, since the connection structure 10 is connected to one of the multiple bit lines BL, and the target bit line BL to be extended is different, the penetration of the connection structure 10 will also be different. For example, as Figure 7 As shown, when the connection structure 10 needs to be connected to the topmost bit line BL among multiple bit lines BL, the connection structure 10 does not need to penetrate the second isolation structure 30. For example, as Figure 7 As shown, when the connection structure 10 is to be connected to the bottommost bit line BL among multiple bit lines BL, the connection structure 10 passes through part of the bit line BL, and the connection structure 10 also passes through the second isolation structure 30, thereby leading out the bottommost bit line BL to the peripheral circuit.

[0110] In some embodiments, reference Figure 7 The second isolation structure 30 has a second gap 301. Since the second isolation structure 30 is located between adjacent bit lines BL, and the second gap 301 is present within the second isolation structure 30, the second gap 301 overlaps with the bit line BL in the first direction X. Here, it can be understood that the orthographic projection of the bit line BL in the first direction X overlaps with the orthographic projection of the second gap 301 in the first direction X. For example, the orthographic projection of the second gap 301 in the first direction X can be located within the edge of the orthographic projection of the bit line BL in the first direction X. The orthographic projection of the second gap 301 in the first direction X refers to the orthographic projection of the closed shape enclosed by the edge of the second gap 301 in the first direction X.

[0111] The second gap 301 can be filled with air. The dielectric constant of air is less than that of the dielectric material (e.g., silicon oxide). Therefore, setting the second gap 301 inside the second isolation structure 30 is beneficial to improving the isolation capability of the second isolation structure 30, further improving the coupling between adjacent bit lines BL along the first direction X, and optimizing the accuracy of reading or writing data in the semiconductor structure 1000, thereby improving the storage performance of the semiconductor structure 1000.

[0112] It should be noted that when the first isolation structure 20 has a first gap 201, the first gap 201 and the second gap 301 are not connected.

[0113] In other embodiments, reference is made to... Figure 8The second isolation structure 30 includes a conductive layer 31 and a second isolation layer 32. The conductive layer 31 extends along the second direction Y, and the second isolation layer 32 is located between the conductive layer 31 and the bit line BL. The second isolation layer 32 is also located between the conductive layer 31 and the connection structure 10.

[0114] For example, the conductive layer 31 is composed of a conductive material, and the material of the second insulating layer 32 may include an insulating material.

[0115] In this embodiment, the conductive layer 31 can be connected to a fixed low potential, thereby shielding the electrical interference between adjacent bit lines BL along the first direction X, improving the coupling between adjacent bit lines BL along the first direction X, which is beneficial to optimizing the accuracy of reading or writing data in the semiconductor structure 1000 and improving the storage performance of the semiconductor structure 1000.

[0116] Furthermore, by setting the second isolation layer 32 between the conductive layer 31 and the bit line BL, and further, by setting the second isolation layer 32 around the conductive layer 31, it is beneficial to isolate the bit line BL from the conductive layer 31, prevent the bit line BL from short-circuiting with the conductive layer 31, and improve the storage stability of the semiconductor structure 1000.

[0117] In this embodiment, when the first isolation structure 20 includes a first conductive post 21 and a first isolation layer 22, the conductive layer 31 is connected to the first conductive post 21. With this configuration, by connecting one end of the first conductive post 21 to a low potential, the conductive layer 31 can also be connected to a low potential. This configuration makes it more convenient to connect the conductive layer 31 to a low potential, which helps to simplify the internal circuit configuration of the semiconductor structure 1000.

[0118] Furthermore, the material of the conductive layer 31 can be the same as that of the first conductive pillar 21, for example, both including tungsten (W). The composition of the second isolation layer 32 can also be the same as that of the first isolation layer 22, for example, both including silicon oxide. This arrangement combines the steps of forming the first conductive pillar 21 with the steps of forming the second conductive pillar 11, and also combines the steps of forming the first isolation layer 22 with the steps of forming the second isolation layer 32, thereby simplifying the fabrication steps of the semiconductor structure 1000 and improving the production efficiency of the semiconductor structure 1000.

[0119] Some embodiments provided in this disclosure offer two connection structures 10, which are described below in conjunction with... Figure 7 and Figure 8 The features of the first connection structure 10 will be explained. It should also be noted that both connection structures 10 can be applied to the embodiments described above.

[0120] In some embodiments, reference Figure 8The bit line BL connected to the connection structure 10 is the first bit line BL-1. The connection structure 10 includes a second conductive post 11 and a third isolation layer 12. The second conductive post 11 extends through to the first bit line BL-1 and is connected to the first bit line BL-1. The third isolation layer 12 is disposed around the second conductive post 11 and is located between the bit line BL penetrated by the connection structure 10 and the connection structure 10.

[0121] In this embodiment, reference Figure 8 If the first bit line BL-1 is the topmost bit line among multiple bit lines BL, then the connecting structure 10 can penetrate a portion of the dielectric layer 81 to the first bit line BL-1. If the first bit line BL-1 is the bottommost bit line among multiple bit lines BL, then the connecting structure 10 can penetrate a portion of the bit line BL to the first bit line BL-1. The third isolation structure surrounding the second conductive post 11 can isolate the second conductive post 11 from the bit lines BL penetrated by the second conductive post 11, so that the second conductive post 11 is only connected to the first bit line BL-1 among multiple bit lines BL, thereby improving the storage stability of the semiconductor structure 1000.

[0122] For example, multiple connection structures 10 can be set up to bring out multiple bit lines BL one by one.

[0123] In some embodiments, reference Figure 7 and Figure 8 The semiconductor structure 1000 further includes a support structure 40. The support structure 40 can extend along a first direction X and passes through multiple bit lines BL along the first direction X. The first isolation structure 20 is located on one side of the connection structure 10 along the second direction Y, and the support structure 40 is located on the other side of the connection structure 10 along the second direction Y.

[0124] The supporting structure 40 is composed of insulating materials; however, the material of the supporting structure 40 is different from that of the first insulating structure 20. For example, the material of the supporting structure 40 may be silicon nitride, while the material of the first insulating structure 20 may be silicon oxide.

[0125] In this embodiment, if a second isolation structure 30 is provided between adjacent bit lines BL, the support structure 40 also penetrates multiple second isolation structures 30 along the first direction X.

[0126] It should be noted that the support structure 40 runs through multiple bit lines BL, but the support structure 40 does not affect the continuity of the bit lines BL along the second direction Y. The bit lines BL still extend along the second direction Y. At the location of the support structure 40, on the YZ plane, the bit lines BL can be set around the support structure 40.

[0127] With the above configuration, the support structure 40 can provide support for multiple bit lines BL, which helps to improve the structural stability of the semiconductor structure 1000. In addition, since the support structure 40 extends through multiple bit lines BL, the area of ​​the bit lines BL on the YZ plane is further reduced, which helps to improve the coupling between two adjacent bit lines BL along the first direction X, thereby improving the accuracy of data reading / writing of the semiconductor structure 1000.

[0128] The following text combines Figures 9-11 The features of the second connection structure 10 will be explained.

[0129] In some embodiments, reference Figure 9 The connection structure 10 extends through multiple bit lines BL. The connection structure 10 may include an insulating post 13 and a third conductive post 14 stacked along a first direction X. The insulating post 13 is in contact with the conductive post, and the conductive post is connected to one of the multiple bit lines BL. For example, the first bit line BL-1 of the multiple bit lines BL is connected to the conductive post. The conductive post may extend through a portion of the bit line BL or the dielectric layer 81 to the first bit line BL-1, and the conductive post may be in contact with the first bit line BL-1.

[0130] For example, the insulating pillar 13 is composed of an insulating material. The conductive pillar is composed of a conductive material.

[0131] The insulating post 13 can extend along the first direction X, and the third conductive post 14 can also extend along the first direction X. One end of the insulating post 13 along the first direction X can be in contact with one end of the third conductive post 14 along the first direction X. The insulating post 13 can be located at the bottom of the conductive post, for example, the insulating post 13 can be formed first, and then the conductive post can be formed. With the above arrangement, the insulating post 13 can support the conductive post, improve the accuracy of reading / writing data of the semiconductor structure 1000, and help improve the stability of the semiconductor structure 1000.

[0132] In this embodiment, the connection structure 10 penetrates a row of bit lines BL that are spaced apart along the first direction X. With this arrangement, each bit line BL is penetrated by the connection structure 10, thus reducing the area of ​​each bit line BL. Here, the area refers to the area of ​​the bit line BL in the YZ plane. Furthermore, it reduces the area directly opposite each other between two adjacent bit lines BL, thereby reducing the coupling between adjacent bit lines BL and improving the storage performance of the semiconductor structure 1000.

[0133] In addition, the connection structure 10 in this embodiment passes through multiple bit lines BL and can also provide support for multiple bit lines BL. Therefore, in this embodiment, there is no need to set up a support structure 40.

[0134] In some embodiments, reference Figure 10When the connection structure 10 includes an insulating pillar 13 and a third conductive pillar 14 stacked along the first direction X, and when the semiconductor structure 1000 also includes a second isolation structure 30, the insulating pillar 13 may penetrate a portion of the second isolation structure 30, and / or the third conductive pillar 14 may also penetrate a portion of the second isolation structure 30.

[0135] In this embodiment, reference Figure 11 When the second isolation structure 30 includes a conductive layer 31 and a second isolation layer 32, in order to avoid a short circuit between the conductive layer 31 and the third conductive pillar 14, when the third conductive pillar 14 penetrates a portion of the second isolation structure 30, the second isolation layer 32 is still located between the third conductive pillar 14 and the conductive layer 31, thereby isolating the third conductive pillar 14 and the conductive layer 31, preventing a short circuit between the third conductive pillar 14 and the conductive layer 31, which is beneficial to improving the storage stability of the semiconductor structure 1000.

[0136] In some embodiments, reference Figure 12 and Figure 13 The semiconductor structure 1000 further includes a gate layer 60 and a plurality of channel structures 50 arranged in a row along a first direction X. Each channel structure 50 is connected to a bit line BL and extends along a third direction Z. The gate layer 60 extends along the first direction X and is located on at least one side of a row of channel structures 50 along a second direction Y.

[0137] For example, the constituent material of the channel structure 50 may include a semiconductor material. Semiconductor materials include monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0138] For example, the constituent material of the gate layer 60 may include a conductive material. The conductive material may be, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or other suitable conductive materials.

[0139] In this configuration, the channel structure 50 extends along a third direction Z. Multiple channel structures 50 can be arranged in a column along a first direction X. In a column of channel structures 50, one channel structure 50 is connected to a bit line BL. Multiple channel structures 50 can also be arranged in multiple rows and columns along a second direction Y and the first direction X. If the bit line BL extends along the second direction Y, then one bit line BL can be connected to a row of channel structures 50. One end of the channel structure 50 along the third direction Z is connected to the bit line BL, and the other end of the channel structure 50 along the third direction Z is connected to the capacitor structure 70.

[0140] The gate layer 60 extends along a first direction X and is located on at least one side of a channel structure 50 along a second direction Y. For example, when the channel structure 50 and the gate layer 60 form a single-gate transistor, the channel structure 50 is coupled to one gate layer 60, and that gate layer 60 is located on one side of the channel structure 50 along the second direction Y. When the channel structure 50 and the gate layer 60 form a dual-gate transistor, the channel structure 50 is coupled to two gate layers 60, and the two gate layers 60 are respectively located on both sides of the channel structure 50 along the second direction YY.

[0141] For example, multiple channel structures 50 may be symmetrically arranged with respect to capacitor structure 70. Correspondingly, multiple bit lines BL may be symmetrically arranged with respect to capacitor structure 70, and multiple gate layers 60 may be symmetrically arranged with respect to capacitor structure 70, thereby forming a 3D stacked memory array.

[0142] The above setup enables the formation of a 3D stacked memory array, which is beneficial for improving the memory density and capacity of the semiconductor structure 1000 and for achieving miniaturization of device integration.

[0143] This disclosure also provides a method for fabricating a semiconductor structure 1000, which is described below in conjunction with some embodiments. Figures 14 to 17d The fabrication method of semiconductor structure 1000 is explained.

[0144] Figure 14 This is a flowchart illustrating a method for fabricating a semiconductor structure 1000 according to some embodiments. For example... Figure 14 As shown, the method for fabricating the semiconductor structure 1000 includes: S1 to S3.

[0145] S1. Multiple bit lines are formed, and the multiple bit lines are spaced apart along a first direction. The bit lines extend along a second direction, and the first direction is perpendicular to the second direction.

[0146] In this step, refer to Figure 15a , Figure 16a and Figure 17a A stacked structure 80 can be formed using a thin-film deposition process. The stacked structure 80 includes a plurality of dielectric layers 81 and a plurality of bit lines 81 alternately arranged along a first direction X. For example, bit lines 81 and dielectric layers 81 are alternately formed along the first direction X, and stacked to form a plurality of spaced-apart bit lines 81 and a plurality of spaced-apart dielectric layers 81.

[0147] The thin film deposition process includes any one of the following: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD).

[0148] For example, the dielectric layer 81 is composed of an insulating material, such as silicon oxide. The bit line BL is composed of a conductive material, such as tungsten. The insulating and conductive materials can be found in some of the embodiments described above, and will not be repeated here.

[0149] S2. Form a connection structure, the connection structure extends along a first direction, and the connection structure is connected to one of the multiple bit lines.

[0150] In this step, refer to Figure 15a , Figure 16a and Figure 17a The connection structure 10 can be formed by means of etching and deposition processes, including but not limited to etching and deposition processes.

[0151] In some embodiments, reference Figure 15a and Figure 16a The connection structure 10 is formed by using etching and deposition processes, including but not limited to forming a third isolation layer 12 and a second conductive pillar 11 in sequence. The second conductive pillar 11 extends through to and is connected to the first bit line BL-1. The third isolation layer 12 is arranged around the second conductive pillar 11. The first bit line BL-1 is one of a plurality of bit lines BL.

[0152] In this step, multiple connection structures 10 can be formed. The multiple connection structures 10 can be arranged along the second direction Y. Along the second direction Y, the number of bit lines BL that each connection structure 10 passes through increases / decreases sequentially, thereby forming multiple connection structures 10 arranged in a stepped manner. These structures are then connected one-to-one with multiple bit lines BL and the bit lines BL are connected to the peripheral circuit, making it easier to control each bit line BL individually.

[0153] If a second isolation structure 30 needs to be formed in subsequent steps, refer to the following after forming the connection structure 10: Figure 16b The support structure 40 can be formed by etching and deposition processes, and the support structure 40 penetrates the stacked structure 80. This disclosure does not limit the number of support structures 40; there can be one or more support structures 40.

[0154] If it is not necessary to form a second isolation structure 30 in subsequent steps, a support structure 40 can be formed to reinforce the semiconductor structure 1000. Alternatively, the support structure 40 can be omitted to save the preparation steps of the semiconductor structure 1000.

[0155] In other embodiments, reference is made to... Figure 17aThe connection structure 10 is formed by using etching and deposition processes, including but not limited to forming an insulating pillar 13 and a third conductive pillar 14 stacked along a first direction X. The insulating pillar 13 and the third conductive pillar 14 are in contact and connected, and the third conductive pillar 14 is connected to one of a plurality of bit lines BL.

[0156] For example, an etching process can be used to remove part of the stacked structure 80 to form a through-hole. The etching process can include wet etching or dry etching.

[0157] An insulating material, such as silicon oxide, can be filled into the via using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, and then a portion of the insulating material can be etched back to form a plurality of insulating pillars 13 with sequentially increasing / decreasing heights along the second direction Y.

[0158] An insulating layer can be formed in the via using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, and the insulating layer can cover the sidewalls of the via. After the insulating layer is formed, an etching solution can be injected into the via to remove part of the insulating pillar 13, exposing part of the bit line BL in the via so that the bit line BL can be led out.

[0159] After exposing a portion of the bit line BL in the via, a conductive material can be deposited in the via using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a third conductive pillar 14. An insulating layer is disposed around a portion of the third conductive pillar 14, and the third conductive pillar 14 is in contact with the bit line BL exposed in the via.

[0160] Through the above steps, insulating pillars 13 and third conductive pillars 14 can be stacked along the first direction X, and the insulating pillars 13 and third conductive pillars 14 are in contact connection, with the insulating pillars 13 providing support for the third conductive pillars 14. Additionally, in this step, an insulating layer is formed, and this insulating layer surrounds a portion of the third conductive pillars 14, which helps to isolate the third conductive pillars 14 so that the third conductive pillars 14 are connected to only one of the multiple bit lines BL.

[0161] In this embodiment, the connecting structure 10 can penetrate the stacked structure 80, so there is no need to form an additional support structure 40, which helps to save the preparation steps of the semiconductor structure 1000, simplify the preparation process, and improve the preparation efficiency of the semiconductor structure 1000.

[0162] S3. A first isolation structure is formed, which is located on one side of the connecting structure along the second direction, and the first isolation structure overlaps with the connecting structure in the second direction.

[0163] In some embodiments, reference Figure 15a and Figure 15bThis step may include: forming a first through hole 82, the first through hole 82 penetrating the stacked structure 80.

[0164] The first via 82 can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed over the stacked structure 80. The patterned photoresist layer can expose the portion of the stacked structure 80 used to form the first via 82. A suitable etching process can be performed to remove the portion of the stacked structure 80 used to form the first via 82. For example, the etching process includes a dry etching process.

[0165] refer to Figure 15b and Figure 15c After the first via 82 is formed, a sacrificial pillar 83 can be formed by filling the first via 82 with sacrificial material using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD.

[0166] Continue to refer to Figure 15b and Figure 15c After the sacrificial pillar 83 is formed, a portion of the sacrificial pillar 83 can be removed by a wet etching process to form the second through hole 84.

[0167] refer to Figure 15c and Figure 15d After the second via 84 is formed, a dielectric material can be deposited on the sidewall of the second via 84 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. It should be noted that since the dielectric layer 81 covers the sidewall of the second via 84, the aperture of the second via 84 is reduced, facilitating the formation of a first isolation structure 20 with a first gap 201 in subsequent process steps.

[0168] refer to Figure 15d and Figure 15e After depositing the dielectric material on the sidewall of the second through-hole 84, the sacrificial pillars 83 can be removed through the second through-hole 84, for example, by injecting etching solution into the second through-hole 84 to remove all the sacrificial pillars 83. At this time, the first through-hole 82 is connected to the second through-hole 84, which can also be understood as the second through-hole 84 being part of the first through-hole 82. At this time, the aperture at the top opening of the first through-hole 82 is reduced.

[0169] refer to Figure 15e and Figure 15f A first isolation structure 20 can be formed in the first through hole 82 by vapor deposition process. By adjusting the process parameters, the first isolation structure 20 can have a first gap 201, which overlaps with the connecting structure 10 in the second direction Y.

[0170] In this step, because the aperture at the top opening of the first through hole 82 is reduced, the insulating material fills the top opening of the first through hole 82 more quickly, which is more conducive to forming the first isolation structure 20 with the first gap 201.

[0171] In other embodiments, reference is made to... Figure 16a , Figure 16b and Figure 16c During the formation of the connection structure 10, a third isolation layer 12 and a second conductive post 11 are formed sequentially. The second conductive post 11 extends through to and connects to the first bit line BL-1. The third isolation layer 12 is arranged around the second conductive post 11. The first bit line BL-1 is one of multiple bit lines BL. Furthermore, after the connection structure 10 is formed, a support structure 40 is formed, which extends through the stacked structure 80.

[0172] Continue to refer to Figure 16b and Figure 16c This step also includes forming a first through hole 82, which penetrates the stacked structure 80.

[0173] The first via 82 can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed over the stacked structure 80. The patterned photoresist layer can expose the portion of the stacked structure 80 used to form the first via 82. A suitable etching process can be performed to remove the portion of the stacked structure 80 used to form the first via 82. For example, the etching process includes a dry etching process.

[0174] refer to Figure 16c and Figure 16d After the first through hole 82 is formed, the dielectric layer 81 can be replaced with the second isolation structure 30 through the first through hole 82.

[0175] For example, refer to Figure 16b and Figure 16c The dielectric layer 81 can be removed using a wet etching process through the first via 82 to form a first filling space 85, which is connected to the first via 82. It should be noted that in this step, only the dielectric layer 81 located between adjacent bit lines BL is removed.

[0176] refer to Figure 16c and Figure 16d An insulating material, such as silicon oxide, can be deposited in the first filled space 85 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a second isolation structure 30, the second isolation structure 30 having a second gap 301.

[0177] Because silicon oxide has poor pore-filling ability, it is easy to form a second isolation structure 30 with a second gap 301. Other insulating materials with poor pore-filling ability can also be used, and this disclosure does not limit this.

[0178] It is worth noting that since the dielectric layer 81 is removed in this step, the support structure 40 can provide support for multiple bit lines BL, and the stacked structure 80 will not collapse. Therefore, the material of the support structure 40 needs to be different from the material of the dielectric layer 81 to prevent the support structure 40 from being damaged in this step. For example, the dielectric layer 81 can be made of silicon oxide, and the support structure 40 can be made of silicon nitride.

[0179] The second isolation structure 30 prepared by the above steps is located between adjacent bit lines BL. The second isolation structure 30 has a second gap 301, which is beneficial to isolate adjacent bit lines BL, reduce coupling between adjacent bit lines BL, and improve the accuracy of reading / writing data of semiconductor structure 1000.

[0180] Continue to refer to Figure 16c and Figure 16d After the second isolation structure 30 is formed, an insulating material can be filled in the first through hole 82 by using one or more thin film deposition processes including but not limited to PVD, CVD, and ALD to form the first isolation structure 20. The first isolation structure 20 is located on one side of the connecting structure 10 along the second direction Y, and the first isolation structure 20 overlaps with the connecting structure 10 in the second direction Y.

[0181] The first isolation structure 20 prepared by the above steps can be used to isolate the adjacent connection structures 10 along the second direction Y, thereby improving the coupling problem of adjacent connection structures 10 and improving the accuracy of reading / writing data of semiconductor structure 1000.

[0182] In some embodiments, replacing the dielectric layer 81 with the second isolation structure 30 includes: forming the second isolation structure 30 by sequentially forming a second isolation layer 32 and a conductive layer 31 in the first filled space 85 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The second isolation layer 32 is disposed around the conductive layer 31.

[0183] In some embodiments, forming the first isolation structure 20 further includes: forming a first isolation layer 22 and a first conductive pillar 21 sequentially in the first via 82 by employing one or more thin film deposition processes including but not limited to PVD, CVD, and ALD, wherein the first conductive pillar 21 extends along a first direction X, the first isolation layer 22 is disposed around the first conductive pillar 21, and the first isolation layer 22 is located between the first conductive pillar 21 and the bit line BL.

[0184] In other embodiments, reference continues. Figure 16a , Figure 16b , Figure 16c and Figure 16e After forming the first filling space 85, the step of forming the first isolation structure 20 further includes: forming a second isolation layer 32 and a conductive layer 31 in the first filling space 85 to form the second isolation structure 30; forming a first isolation layer 22 and a first conductive post 21 in the first through hole 82; the first conductive post 21 extends along the first direction X; the first isolation layer 22 is disposed around the first conductive post 21; and the first isolation layer 22 is located between the first conductive post 21 and the bit line BL.

[0185] In this step, the first isolation layer 22 and the second isolation layer 32 are formed in one process, and the first conductive pillar 21 and the conductive layer 31 are formed in one process. For example, an insulating material, such as silicon oxide, is deposited in the first filled space 85 and the first via 82 using one or more thin film deposition processes such as PVD, CVD, and ALD to form the second isolation layer 32 and the first isolation layer 22, wherein the second isolation layer 32 covers the sidewall of the first filled space 85, and the first isolation layer 22 covers the sidewall of the first via 82.

[0186] Continue to refer to Figure 16c and Figure 16e After forming the second isolation layer 32 and the first isolation layer 22, one or more thin film deposition processes, such as PVD, CVD, and ALD, can be used to deposit conductive material, such as tungsten, in the first filled space 85 and the first via 82 to form a conductive layer 31 and a conductive pillar. The conductive layer 31 is connected to the conductive pillar, which can then be connected to an external circuit, allowing both the conductive pillar and the conductive layer 31 to achieve a low potential.

[0187] In other embodiments, reference is made to... Figure 17a , Figure 17b and Figure 17c After the first filling space 85 is formed, an insulating material, such as silicon oxide, can be deposited in the first filling space 85 using one or more thin film deposition processes such as PVD, CVD, and ALD to form a second isolation structure 30. The second isolation structure 30 may have a second gap 301. At this time, a portion of the second isolation structure 30 also covers the insulating pillar 13.

[0188] After the second isolation structure 30 is formed, one or more thin film deposition processes, such as PVD, CVD, and ALD, can be used to fill the first via 82 with an insulating material, such as silicon oxide, to form the first isolation structure 20.

[0189] In other embodiments, reference is made to... Figure 17a , Figure 17b and Figure 17dAfter the first filling space 85 is formed, an insulating material, such as silicon oxide, can be deposited in the first filling space 85 and the first via 82 using one or more thin film deposition processes such as PVD, CVD, and ALD to form the second isolation layer 32 and the first isolation layer 22. The second isolation layer 32 also covers the sidewalls of the insulating pillar 13 and the conductive pillar.

[0190] After forming the second isolation layer 32 and the first isolation layer 22, a conductive material, such as tungsten, can be deposited in the first filled space 85 and the first via 82 using one or more thin film deposition processes such as PVD, CVD, and ALD to form a conductive layer 31 and a first conductive pillar 21. The conductive layer 31 is connected to the first conductive pillar 21.

[0191] The semiconductor structure 1000 prepared by the above method isolates the connection structure 10 from other conductive structures in the second direction Y by setting the first isolation structure 20 on at least one side of the connection structure 10 along the second direction Y. This is beneficial to improving the coupling between the connection structure 10 and other conductive structures adjacent to the connection structure 10 in the second direction Y, such as improving the coupling between adjacent connection structures 10 along the second direction Y. This is beneficial to optimizing the accuracy of reading or writing data in the semiconductor structure 1000 and improving the storage performance of the semiconductor structure 1000.

[0192] Furthermore, some fabrication methods can form a second isolation structure 30 between adjacent bit lines BL, which is beneficial to improve the coupling between adjacent bit lines BL, optimize the accuracy of reading or writing data in the semiconductor structure 1000, and improve the storage performance of the semiconductor structure 1000.

[0193] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A plurality of bit lines are spaced apart along a first direction, the bit lines extending along a second direction, the first direction being perpendicular to the second direction; A connection structure extends along the first direction and is connected to one of the plurality of bit lines; A first isolation structure is located on at least one side of the connecting structure along the second direction, and the first isolation structure overlaps with the connecting structure in the second direction.

2. The semiconductor structure according to claim 1, characterized in that, The first isolation structure extends through the plurality of bit lines along the first direction.

3. The semiconductor structure according to claim 1, characterized in that, The first isolation structure has a first gap, which overlaps with the connecting structure in the second direction.

4. The semiconductor structure according to claim 1, characterized in that, The first isolation structure includes: a first conductive post and a first isolation layer, the first conductive post extending along the first direction, the first isolation layer surrounding the first conductive post, and the first isolation layer located between the first conductive post and the bit line.

5. The semiconductor structure according to claim 4, characterized in that, The first conductive post has a first end face and a second end face arranged along the first direction, and the area of ​​the first end face is greater than the area of ​​the second end face.

6. The semiconductor structure according to claim 5, characterized in that, The first conductive post includes a first portion and a second portion stacked along the first direction, the first portion having the first end face, the second portion having the second end face, and the width of the first portion in the second direction being greater than the width of the second portion in the second direction.

7. The semiconductor structure according to any one of claims 1-6, characterized in that, The semiconductor structure further includes a second isolation structure located between adjacent bit lines, and the connection structure extends through the second isolation structure.

8. The semiconductor structure according to claim 7, characterized in that, The second isolation structure has a second gap.

9. The semiconductor structure according to claim 7, characterized in that, The second isolation structure includes a conductive layer and a second isolation layer. The conductive layer extends along the second direction, and the second isolation layer is located between the conductive layer and the bit line. The second isolation layer is also located between the conductive layer and the connection structure.

10. The semiconductor structure according to claim 9, characterized in that, When the first isolation structure includes a first conductive pillar and a first isolation layer, the conductive layer is connected to the first conductive pillar, and the material of the conductive layer is the same as the material of the first conductive pillar.

11. The semiconductor structure according to claim 1, characterized in that, The bit line connected to the connection structure is the first bit line. The connection structure includes a second conductive post and a third isolation layer. The second conductive post extends through the first bit line and is connected to the first bit line. The third isolation layer is arranged around the second conductive post.

12. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure further includes a support structure that extends through the plurality of bit lines along the first direction and is located on the other side of the connection structure along the second direction, wherein the material of the support structure is different from the material of the first isolation structure.

13. The semiconductor structure according to claim 1, characterized in that, The connection structure extends through the plurality of bit lines. The connection structure includes an insulating post and a third conductive post stacked along the first direction. The insulating post is in contact with the third conductive post, and the third conductive post is connected to one of the plurality of bit lines.

14. The semiconductor structure according to claim 1, characterized in that, Also includes: A plurality of channel structures arranged in a row along the first direction, one of the channel structures being connected to one of the bit lines, the channel structures extending along a third direction; The third direction intersects the plane containing the first direction and the second direction; A gate layer, extending along the first direction, is located on at least one side of a series of channel structures along the second direction.

15. A method for fabricating a semiconductor structure, characterized in that, include: Multiple bit lines are formed, the multiple bit lines are spaced apart along a first direction, the bit lines extend along a second direction, and the first direction is perpendicular to the second direction; A connection structure is formed, the connection structure extending along the first direction, and the connection structure is connected to one of the plurality of bit lines; A first isolation structure is formed, which is located on one side of the connecting structure along the second direction, and the first isolation structure overlaps with the connecting structure in the second direction.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, The formation of multiple bit lines includes: A stacked structure is formed, the stacked structure comprising a plurality of dielectric layers and a plurality of bit lines alternately arranged along the first direction; The formation of the first isolation structure includes: A first through-hole is formed, which penetrates the stacked structure; The dielectric layer is replaced with a second isolation structure through the first through-hole.

17. The method for preparing a semiconductor structure according to claim 16, characterized in that, The formation of the first isolation structure further includes: The first through-hole is filled with sacrificial material to form a sacrificial column; Remove part of the sacrificial column to form a second through hole; Deposit a medium material on the sidewall of the second through hole; Remove the sacrificial column.

18. The method for preparing a semiconductor structure according to claim 17, characterized in that, The formation of the first isolation structure further includes: The first isolation structure is formed in the first through-hole by a vapor deposition process. The first isolation structure has a first gap, and the first gap overlaps with the connecting structure in the second direction.

19. The method for preparing a semiconductor structure according to claim 16, characterized in that, The formation of the first isolation structure further includes: A first isolation layer and a first conductive post are sequentially formed in the first through hole. The first conductive post extends along the first direction. The first isolation layer is disposed around the first conductive post and is located between the first conductive post and the bit line.

20. The method for preparing a semiconductor structure according to any one of claims 16-19, characterized in that, The step of replacing the dielectric layer with the second isolation structure includes: The dielectric layer is removed through the first through hole to form a first filling space, which is connected to the first through hole. The second isolation structure is formed within the first filling space by a vapor deposition process, and the second isolation structure has a second gap.

21. The method for preparing a semiconductor structure according to any one of claims 16-19, characterized in that, The step of replacing the dielectric layer with the second isolation structure includes: The dielectric layer is removed through the first through-hole to form a first filling space; A second isolation layer and a conductive layer are sequentially formed in the first filling space to form the second isolation structure.

22. The method for preparing a semiconductor structure according to claim 21, characterized in that, When the first isolation structure is formed, it includes: sequentially forming a first isolation layer and a first conductive pillar in the first through hole. The first isolation layer and the second isolation layer are formed in one process, and the first conductive pillar and the conductive layer are formed in one process.

23. The method for preparing a semiconductor structure according to claim 15, characterized in that, Forming a connection structure, including: A third isolation layer and a second conductive pillar are formed sequentially. The second conductive pillar extends through to the first bit line and is connected to the first bit line. The third isolation layer is arranged around the second conductive pillar. The first bit line is one of the plurality of bit lines. A support structure is formed, which extends through the plurality of bit lines.

24. The method for preparing a semiconductor structure according to claim 15, characterized in that, Forming a connection structure, including: An insulating pillar and a third conductive pillar are formed and stacked along the first direction. The insulating pillar and the third conductive pillar are in contact and connected. The third conductive pillar is connected to one of the plurality of bit lines.

25. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-14; A controller, the control being coupled to the semiconductor structure, to control the semiconductor structure to store data.

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