Semiconductor device and method of manufacturing the same, memory, storage system, and electronic device

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, a memory, a storage system and an electronic device, and relates to the technical field of semiconductor technology, aiming to improve the electrical performance and reliability of the semiconductor device and realize miniaturization of the semiconductor device. The semiconductor device comprises a semiconductor body and a bit line. The semiconductor body comprises a first end and a second end oppositely arranged in a first direction, and the first direction is the thickness direction of the semiconductor device. A gate layer is arranged around the semiconductor body in the circumferential direction of the semiconductor body. The bit line is located on one side of the semiconductor body along the first direction and is coupled to the first end. The bit line comprises a main body part, and at least part of the main body part is located on one side of the first end away from the second end. The size of one end of the main body part away from the semiconductor body along the second direction is smaller than the size of the other end of the main body part close to the semiconductor body along the second direction. The above semiconductor device is applied in the memory to realize data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a memory, a storage system, and an electronic device. Background Technology

[0002] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly, and the memory density for planar memory cells approaches its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. 3D memory architectures include semiconductor devices.

[0004] It should be noted that the information disclosed in the background section is only used to enhance the understanding of the background art of the technology described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] Embodiments of this disclosure provide a semiconductor device and a method for fabricating the same, a memory, a storage system, and an electronic device.

[0006] On the one hand, a method for fabricating a semiconductor device is provided. The method for fabricating a semiconductor device includes the following steps:

[0007] An initial stacked structure is formed on one side of the substrate. The initial stacked structure includes a first insulating layer, a gate layer, and a second insulating layer sequentially disposed in a direction away from the substrate.

[0008] A semiconductor body is formed that extends through the initial stacked structure. The semiconductor body includes a first end and a second end disposed opposite to each other in a first direction, the first direction being the thickness direction of the substrate.

[0009] Remove the substrate to expose the first end.

[0010] A bit line is formed. The bit line is located on one side of the semiconductor body along a first direction and coupled to a first end.

[0011] In the above-mentioned semiconductor device fabrication method, a semiconductor body penetrating the initial stacked structure is first formed within the initial stacked structure, and then the substrate is removed to expose the first end of the semiconductor body. Finally, a bit line coupled to the first end of the semiconductor body is formed. Compared with forming a bit line between the initial stacked structure and the substrate first, and then forming a semiconductor body penetrating the initial stacked structure and coupling the first end of the semiconductor body to the bit line, forming a semiconductor body penetrating the initial stacked structure first, then exposing the first end of the semiconductor body, and finally forming a bit line coupled to the first end of the semiconductor body, allows for more precise control of the position and size of the bit line. It avoids alignment errors that may occur when processing the semiconductor body after the bit line is formed, which is beneficial for optimizing the semiconductor device fabrication process and reducing the complexity of the semiconductor device fabrication process. On the other hand, forming bit lines coupled to the first end of the semiconductor body after its first end is exposed allows for a cleaner and tighter contact interface between the first end of the semiconductor body and the bit lines. This helps reduce or eliminate defects at the contact interface and lowers the contact resistance between the first end of the semiconductor body and the bit lines, thereby improving the electrical performance between them and ultimately enhancing the reliability of the semiconductor device. Furthermore, removing the substrate first to expose the first end of the semiconductor body before forming the bit lines allows for a wider range of material selection during bit line formation, without needing to consider the compatibility between the bit line material and the substrate material. This improves the design flexibility of the semiconductor device.

[0012] In some embodiments, before forming a semiconductor body that extends through the initial stacked structure, the method for fabricating a semiconductor device further includes the following steps:

[0013] A through-hole is formed that penetrates the initial stacked structure.

[0014] An initial gate dielectric layer is formed inside the via, covering the sidewalls and bottom of the via.

[0015] In some embodiments, removing the substrate to expose the first end includes the following steps:

[0016] Remove the substrate to expose the initial gate dielectric layer located at the bottom of the via.

[0017] The initial gate dielectric layer located at the bottom of the via is removed to expose the first end of the semiconductor body, and the remaining initial gate dielectric layer forms the gate dielectric layer.

[0018] In the aforementioned semiconductor device fabrication method, after forming a semiconductor body penetrating the initial stacked structure, the substrate is first removed to expose the initial gate dielectric layer located at the bottom of the via. Then, the initial gate dielectric layer at the bottom of the via is removed to expose the first end of the semiconductor body. The remaining initial gate dielectric layer forms the gate dielectric layer. This method avoids damage to the initial gate dielectric layer located on the sidewalls of the via during the removal of the initial gate dielectric layer at the bottom of the via, thereby improving the insulation performance of the finally formed gate dielectric layer and reducing the risk of short circuits between the semiconductor body and the gate layer. This, in turn, improves the electrical performance of the semiconductor device. Furthermore, since the removal of the initial gate dielectric layer at the bottom of the via does not require passing through the via, the size of the via is not limited by the process of removing the initial gate dielectric layer at the bottom of the via, which helps to reduce the size of the via and thus the size of the semiconductor device. This facilitates the miniaturization of semiconductor devices.

[0019] In some embodiments, before forming an initial stacked structure on one side of the substrate, the method for fabricating the semiconductor device further includes the following steps:

[0020] A sacrificial layer is formed on one side of the substrate.

[0021] The sacrificial layer is located between the substrate and the initial stack structure. When forming a via through the initial stack structure, the bottom of the via stops inside the sacrificial layer or on the surface of the sacrificial layer away from the substrate.

[0022] After removing the substrate, the sacrificial layer is also removed to expose the initial gate dielectric layer located at the bottom of the via.

[0023] In some embodiments, before forming an initial stacked structure on one side of the substrate, the method for fabricating the semiconductor device further includes the following steps:

[0024] A third insulating layer is formed on one side of the substrate, and a sacrificial portion is embedded in the third insulating layer. The sacrificial portion penetrates the third insulating layer along a first direction.

[0025] The third insulating layer is located between the substrate and the initial stacked structure. When forming a via through the initial stacked structure, the bottom of the via stops inside the sacrificial portion or on the surface of the sacrificial portion away from the substrate.

[0026] After removing the substrate, the sacrificial portion is also removed to expose the initial gate dielectric layer located at the bottom of the via.

[0027] In some embodiments, forming a bit line includes the following steps:

[0028] An initial bit line layer is formed. The initial bit line layer is located at least on the side of the first insulating layer away from the gate layer.

[0029] The initial bitline layer in a certain region is removed, and the remaining initial bitline layer forms a bitline and is coupled to the first end.

[0030] The bit line includes a main body portion, at least a portion of which is located on the side of the first end away from the second end. The dimension of the main body portion away from the semiconductor body along the second direction is smaller than the dimension of the main body portion near the semiconductor body along the second direction, and the second direction is perpendicular to the first direction and perpendicular to the extension direction of the bit line.

[0031] In some embodiments, the initial bit line layer further fills the gap between the first insulating layer and the semiconductor body, and the side surface of the gate dielectric layer near the body portion contacts the side surface of the initial bit line layer near the second end. The bit line also includes an extension located on the side of the body portion near the second end and connected to the body portion. The extension is disposed around the semiconductor body and contacts the side surface of the semiconductor body.

[0032] On the other hand, a semiconductor device is provided. The semiconductor device includes a semiconductor body, a gate layer, and a bit line. The semiconductor body includes a first end and a second end disposed opposite each other in a first direction, the first direction being the thickness direction of the semiconductor device. The gate layer is disposed around the semiconductor body circumferentially. The bit line is located on one side of the semiconductor body along the first direction and coupled to the first end. The bit line includes a body portion, at least a portion of which is located on the side of the first end away from the second end.

[0033] The dimension of the end of the main body away from the semiconductor body along the second direction is smaller than the dimension of the end of the main body close to the semiconductor body along the second direction. The second direction is perpendicular to the first direction and perpendicular to the extension direction of the bit line.

[0034] In some embodiments, the size of the main body gradually increases along the second direction from the end of the main body away from the semiconductor body to the end of the main body close to the semiconductor body.

[0035] In some embodiments, the main body of the bit line is an isosceles trapezoid in a first cross-section. The first cross-section is a cross-section obtained by cutting the bit line along a first direction and perpendicular to the extension direction of the bit line.

[0036] In some embodiments, the semiconductor device further includes a first insulating layer. The first insulating layer is disposed around the semiconductor body circumferentially. Along a first direction, the first insulating layer is located between the gate layer and the body portion.

[0037] In some embodiments, the first end is flush with the surface of the first insulating layer away from the gate layer. Alternatively, along the first direction, the first end is located between the surface of the first insulating layer away from the gate layer and the surface of the body portion away from the semiconductor body.

[0038] In some embodiments, the bit line further includes an extension. The extension is located on the side of the body portion near the second end and is connected to the body portion. The extension is disposed around the semiconductor body and contacts the side of the semiconductor body.

[0039] In some embodiments, the extension is located between the semiconductor body and the first insulating layer.

[0040] In some embodiments, the dimension of the extension in the second direction is smaller than the dimension of the main body in the second direction.

[0041] In some embodiments, the semiconductor device further includes a gate dielectric layer. The gate dielectric layer is located at least between the semiconductor body and the gate layer, and is disposed around the semiconductor body. The side surface of the gate dielectric layer near the body portion is in contact with the side surface of the extension portion away from the body portion.

[0042] In some embodiments, along the first direction, the side surface of the gate dielectric layer near the bit line is located between the side surface of the first insulating layer near the gate layer and the side surface away from the gate layer.

[0043] In some embodiments, the dimension of the semiconductor body along the first direction is larger than the dimension of the gate dielectric layer along the first direction.

[0044] In some embodiments, the semiconductor device further includes a third insulating layer. The third insulating layer is located on the side of the first insulating layer away from the gate layer. The material of the third insulating layer is different from the material of the first insulating layer. The main body portion is embedded within the third insulating layer.

[0045] In some embodiments, the size of the semiconductor body gradually increases along a second direction from the first end to the second end.

[0046] In another aspect, a memory is provided. The memory includes a semiconductor device and a peripheral device layer as described in any of the above embodiments. The peripheral device layer is coupled to the semiconductor device.

[0047] In another aspect, a storage system is provided. The storage system includes a memory and a controller as described in the above embodiments. The controller is electrically connected to the memory.

[0048] In another aspect, an electronic device is provided. The electronic device includes a processor and a storage system as described in the above embodiments. The processor is coupled to the storage system.

[0049] It is understood that the beneficial effects of the semiconductor devices, memories, storage systems and electronic devices provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor device preparation method described above, and will not be repeated here. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0051] Figure 1 This is a structural diagram of an electronic device provided according to some embodiments;

[0052] Figure 2 This is a structural diagram of a storage system provided according to some embodiments;

[0053] Figure 3 This is a structural diagram of a memory provided according to some embodiments;

[0054] Figure 4 This is a structural diagram of a partial region of a storage array layer within a memory according to some embodiments;

[0055] Figure 5 This is a structural diagram of a partial region of a semiconductor device according to some embodiments;

[0056] Figure 6 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0057] Figure 7 This is another flowchart illustrating a method for fabricating a semiconductor device according to some embodiments;

[0058] Figure 8 This is yet another flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0059] Figure 9 for Figure 6 and Figure 7 The flowchart of the semiconductor device fabrication method includes steps S0 and S1, and... Figure 7 A structural diagram of a semiconductor device corresponding to step S7 in the flowchart of the semiconductor device fabrication method;

[0060] Figure 10 for Figure 6 and Figure 8 The flowchart of the semiconductor device fabrication method includes steps S0 and S1, and... Figure 8 A structural diagram of a semiconductor device corresponding to step S8 in the flowchart of the semiconductor device fabrication method;

[0061] Figure 11 for Figure 6 and Figure 7 A structural diagram of a semiconductor device corresponding to steps S2, S5, and S6 in the flowchart of the semiconductor device fabrication method.

[0062] Figure 12 for Figure 6 and Figure 8 A structural diagram of a semiconductor device corresponding to steps S2, S5, and S6 in the flowchart of the semiconductor device fabrication method.

[0063] Figure 13 for Figure 6 and Figure 7 A structural diagram of a semiconductor device corresponding to step S3 in the flowchart of the semiconductor device fabrication method;

[0064] Figure 14 for Figure 6 and Figure 8 A structural diagram of a semiconductor device corresponding to step S3 in the flowchart of the semiconductor device fabrication method;

[0065] Figure 15 for Figure 6 and Figure 7 A structural diagram of a semiconductor device corresponding to step S4 in the flowchart of the semiconductor device fabrication method;

[0066] Figure 16 for Figure 6 and Figure 8 A structural diagram of a semiconductor device corresponding to step S4 in the flowchart of the semiconductor device fabrication method;

[0067] Figure 17 for Figure 6 and Figure 7 A structural diagram of a semiconductor device corresponding to step S4 in the flowchart of the semiconductor device fabrication method;

[0068] Figure 18 for Figure 8 A structural diagram of a semiconductor device corresponding to step S8 in the flowchart of the semiconductor device fabrication method;

[0069] Figure 19 This is a structural diagram of a partial region of a semiconductor device according to some embodiments. Detailed Implementation

[0070] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0071] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0072] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0073] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0074] In this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned, or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0075] In this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias (vias) are formed) and one or more dielectric layers.

[0076] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0077] It should be noted that, for example, G / WL in the accompanying drawings of this disclosure indicates that the component is both G and WL. Other similar reference numerals appearing in the drawings also follow the above description.

[0078] like Figure 1 As shown, this application provides an electronic device 1000. The electronic device 1000 may include a mobile phone, a tablet computer, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, etc. This application does not impose any special limitations on the specific form of the aforementioned electronic device 1000.

[0079] In some embodiments, please continue reading Figure 1 The aforementioned electronic device 1000 may include a storage system 100 and a processor 200. The processor 200 is coupled to the storage system 100 to interact with the storage system 100.

[0080] For example, the processor 200 within the electronic device 1000 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0081] The storage system 100 described above will be described in detail below.

[0082] In some embodiments, such as Figure 2 As shown, Figure 2 This is a structural diagram of a storage system 100 provided according to some embodiments. The storage system 100 may include a memory 10 and a controller 20. The controller 20 is electrically connected to the memory 10 and can control the memory 10 to store data.

[0083] For example, the storage system 100 described above can be integrated into a memory card. Memory cards include, for example, any of the following: PC card (Personal Computer Memory Card International Association, PCMCIA), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0084] The aforementioned storage system 100 can also be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 100 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0085] The aforementioned storage system 100 can also be integrated into a solid state drive (SSD).

[0086] For example, the controller 20 within the storage system 100 can be configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0087] The controller 20 within the storage system 100 can also be configured to operate in high duty cycle environments using SSDs or eMMCs, which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0088] For example, the controller 20 within the storage system 100 can be configured to manage data stored in the memory 10 and communicate with external devices (e.g., a host).

[0089] The controller 20 within the storage system 100 can also be configured to control the operation of the memory 10, such as read, erase, and program operations.

[0090] The controller 20 within the storage system 100 can also be configured to manage various functions related to data stored or to be stored in the memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling.

[0091] The controller 20 within the storage system 100 can also be configured to process error correction codes for data read from or written to the memory 10.

[0092] Of course, the controller 20 within the storage system 100 can also perform any other suitable functions. For example, the controller 20 within the storage system 100 can format the memory 10. As another example, the controller 20 within the storage system 100 can communicate with external devices (e.g., a host) via at least one of various interface protocols.

[0093] It should be noted that the aforementioned interface protocols may include at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0094] For example, the memory 10 within the storage system 100 may be one of the following: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Resistive Random Access Memory (RRAM), Magnetic Random Access Memory (MRAM), Phase Change Memory (PCM), and Static Random-Access Memory (SRAM).

[0095] The following illustration uses the memory 10 in the storage system 100 as a dynamic random access memory as an example, but the type of memory 10 in this disclosure is not limited to this. The memory 10 in the storage system 100 can be any suitable type of memory.

[0096] The structure of the memory 10 described above will be explained in detail below.

[0097] In some embodiments, such as Figure 3 As shown, Figure 3 This is a structural diagram of a memory 10 provided according to some embodiments. The memory 10 may include a memory array layer 101 and a peripheral device layer 102. The peripheral device layer 102 is coupled to the memory array layer 101.

[0098] By coupling the peripheral device layer 102 within the memory 10 to the memory array layer 101, the peripheral device layer 102 can be configured to operate on the memory array layer 101 (e.g., the peripheral device layer 102 can be configured to perform write or read operations on the memory array layer 101).

[0099] For example, please continue reading Figure 3 In the case where the memory 10 includes a memory array layer 101 and a peripheral device layer 102, the memory array layer 101 and the peripheral device layer 102 in the memory 10 can be fabricated separately (and in some embodiments, the memory array layer 101 and the peripheral device layer 102 in the memory 10 can be fabricated in parallel), so that the thermal budget of one of the memory array layer 101 and the peripheral device layer 102 in the memory 10 does not limit the process of fabricating the other.

[0100] For example, please continue reading Figure 3 The peripheral device layer 102 within the memory 10 may include peripheral circuitry 102a.

[0101] The peripheral circuitry 102a within the peripheral device layer 102 can be any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory array layer 101 within the memory 10. The peripheral circuitry 102a within the peripheral device layer 102 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0102] For example, please continue reading Figure 3 In the case where the peripheral device layer 102 within the memory 10 includes peripheral circuitry 102a, the peripheral circuitry 102a within the peripheral device layer 102 can utilize complementary metal-oxide-semiconductor (CMOS) technology. The peripheral circuitry 102a within the peripheral device layer 102 can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0103] For example, please continue reading Figure 3 The memory 10 can be a semiconductor device D.

[0104] Or, such as Figure 4 As shown, Figure 4 This is a structural diagram of a partial region of a memory array layer 101 within a memory 10 provided according to some embodiments. The semiconductor device D may be part of the memory 10.

[0105] For example, please continue reading Figure 4 When the semiconductor device D is part of the memory 10, the semiconductor device D can be the memory array layer 101 within the memory 10.

[0106] Please continue reading. Figure 4 and combined Figure 3 When the semiconductor device D is the memory array layer 101 within the memory 10, the peripheral device layer 102 within the memory 10 can be coupled to the semiconductor device D.

[0107] The semiconductor device D described above will be explained in detail below.

[0108] In some embodiments, such as Figure 5 As shown, Figure 5 This is a structural diagram of a partial region of a semiconductor device D according to some embodiments. The semiconductor device D may include a capacitor C. The capacitor C may be used to store data bits as positive or negative charges.

[0109] For example, the capacitor C within the semiconductor device D can be set to a charged state or a discharged state, using these two states to represent two values ​​of the data bit, which are typically referred to as zero and one.

[0110] For example, the capacitor C within the semiconductor device D may include one or more of the following: a pillar structure capacitor and a cup structure capacitor.

[0111] For example, the capacitor C within a semiconductor device D may include a Pillar structure capacitor. A Pillar structure capacitor has a columnar shape, which can be formed by alternating layers of metal and dielectric. Pillar structure capacitors exhibit high capacitance density and excellent electrical performance.

[0112] For example, the capacitor C within a semiconductor device D may include a CUP structure capacitor. A CUP structure capacitor has a cup-shaped metal electrode and dielectric layer structure. CUP structure capacitors offer high capacitance density, excellent electrical performance, and strong process compatibility.

[0113] For example, please continue reading Figure 5 The capacitor C in the semiconductor device D may include a first plate C1 and a second plate C2, as well as a dielectric layer 6 located between the first plate C1 and the second plate C2.

[0114] In some embodiments, please continue reading Figure 5 The semiconductor device D may also include a transmission transistor T1.

[0115] For example, please continue reading Figure 5 In the case where the semiconductor device D includes a capacitor C, the transmission transistor T1 can be electrically connected to the capacitor C within the semiconductor device D to control (e.g., switch and select) access to the capacitor C.

[0116] For example, please continue reading Figure 5 The number of transmission transistors T1 in semiconductor device D can be one.

[0117] Alternatively, the number of transfer transistors T1 within the semiconductor device D can be multiple (greater than or equal to two).

[0118] For example, please continue reading Figure 5 The transfer transistor T1 within the semiconductor device D can be a vertical transistor. For example, the transfer transistor T1 within the semiconductor device D can be a vertical metal-oxide-semiconductor field-effect transistor (MOSFET).

[0119] Using a vertical transistor as the transmission transistor T1 within the semiconductor device D can reduce the area occupied by the transmission transistor T1, the coupling capacitance, and the complexity of the interconnect wiring.

[0120] The following uses a vertical transistor as an example to illustrate some embodiments of the present disclosure. However, the type of the transmission transistor T1 in the semiconductor device D is not limited to this. The type of the transmission transistor T1 in the semiconductor device D can also be other suitable transistor types.

[0121] For example, please continue reading Figure 5 The transmission transistor T1 within the semiconductor device D may include a semiconductor body 1. The semiconductor body 1 may include a first end 1a and a second end 1b disposed opposite each other in a first direction Z, where the first direction Z is the thickness direction of the semiconductor device D.

[0122] Please continue reading. Figure 5 The semiconductor body 1 within the transmission transistor T1 can have any suitable 3D shape. For example, the semiconductor body 1 within the transmission transistor T1 can have a polyhedral shape or a cylindrical shape, etc.

[0123] Please continue reading. Figure 5The semiconductor body 1 within the transmission transistor T1 may be made of at least one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (ITO), zinc tin oxide (ZTO), and gallium zinc oxide (GZO). Indium gallium zinc oxide, indium zinc oxide, indium tin oxide, zinc tin oxide, and gallium zinc oxide are all transparent oxide semiconductor materials. Indium gallium zinc oxide is composed of indium (In), gallium (Ga), zinc (Zn), and oxygen (O). Indium zinc oxide is composed of indium (In), zinc (Zn), and oxygen (O). Indium tin oxide is composed of indium (In), tin (Sn), and oxygen (O). Zinc tin oxide is composed of zinc (Zn), tin (Sn), and oxygen (O). Gallium zinc oxide is composed of gallium (Ga), zinc (Zn), and oxygen (O).

[0124] It is understood that if the material of the semiconductor body 1 within the transmission transistor T1 includes indium gallium zinc oxide (IGNOW), then the transmission transistor T1 can be an IGNOW transistor. If the material of the semiconductor body 1 within the transmission transistor T1 includes IGNOW, then the transmission transistor T1 can be an IGNOW transistor. If the material of the semiconductor body 1 within the transmission transistor T1 includes IGNOW, then the transmission transistor T1 can be an IGNOW transistor. If the material of the semiconductor body 1 within the transmission transistor T1 includes zinc tin oxide (ZTI), then the transmission transistor T1 can be a ZTI transistor. If the material of the semiconductor body 1 within the transmission transistor T1 includes gallium zinc oxide (GZNOW), then the transmission transistor T1 can be a gallium zinc oxide (GZNOW) transistor.

[0125] For example, please continue reading Figure 5 In the case where the transmission transistor T1 in the semiconductor device D includes a semiconductor body 1, the semiconductor body 1 may include a first electrode 11, a channel 13 and a second electrode 12 arranged sequentially along the first direction Z.

[0126] For example, please continue reading Figure 5 The first electrode 11 of the semiconductor body 1 can be located on the side of the channel 13 near the first end 1a of the semiconductor body 1, and the second electrode 12 of the semiconductor body 1 can be located on the side of the channel 13 near the second end 1b of the semiconductor body 1.

[0127] For example, please continue reading Figure 5The transfer transistor T1 within the semiconductor device D may also include a gate layer G. When the transfer transistor T1 within the semiconductor device D includes a semiconductor body 1, the gate layer G may be disposed around the semiconductor body 1 circumferentially.

[0128] Please continue reading. Figure 5 When the semiconductor body 1 includes a first electrode 11, a channel 13 and a second electrode 12 arranged sequentially along the first direction Z, the gate layer G can be opposite to the channel 13 in the semiconductor body 1.

[0129] Understandably, when the gate layer G within the transmission transistor T1 surrounds the semiconductor body 1 and is opposite to the channel 13 within the semiconductor body 1, the transmission transistor T1 can be a gate-all-around (GAA) transistor. A GAA transistor can have a larger gate control area, thereby achieving better channel 13 control with a smaller subthreshold swing. Since the channel 13 within the semiconductor body 1 is completely depleted, the leakage current of the GAA transistor can also be significantly reduced.

[0130] The gate layer G of the transmission transistor T1 is made of a conductive material. For example, the gate layer G of the transmission transistor T1 may be made of polysilicon, metal, metal compound, or silicide.

[0131] The gate layer G of the transmission transistor T1 may include one or more conductive layers. For example, if the gate layer G of the transmission transistor T1 includes multiple conductive layers, the gate layer G may include a titanium nitride (TiN) layer and a tungsten (W) layer stacked together.

[0132] For example, please continue reading Figure 5 In the case where the transfer transistor T1 in the semiconductor device D includes a semiconductor body 1 and a gate layer G, the transfer transistor T1 in the semiconductor device D may further include a gate dielectric layer 4. The gate dielectric layer 4 is located at least between the semiconductor body 1 and the gate layer G, and is disposed around the semiconductor body 1.

[0133] For example, please continue reading Figure 5 In the case where the semiconductor body 1 includes a first electrode 11, a channel 13 and a second electrode 12 arranged sequentially along the first direction Z, the gate dielectric layer 4 may be located between the semiconductor body 1 and the gate layer G, and may be arranged around the channel 13 of the semiconductor body 1.

[0134] For example, please continue reading Figure 5 The gate dielectric layer 4 can also be disposed around the second electrode 12 of the semiconductor body 1.

[0135] For example, please continue reading Figure 5The gate dielectric layer 4 can also be disposed around the first electrode 11 of the semiconductor body 1.

[0136] In some embodiments, please continue reading Figure 5 The semiconductor device D may also include a word line WL. The word line WL may be coupled to the gate layer G of the transmission transistor T1 within the semiconductor device D to control the transmission transistor T1 to turn on or off.

[0137] For example, please continue reading Figure 5 In semiconductor device D, the word line WL and the gate layer G of transmission transistor T1 can be a continuous conductive structure. That is, the gate layer G of transmission transistor T1 can be regarded as a part forming the word line WL, or the word line WL can be regarded as an extension of the gate layer G of transmission transistor T1.

[0138] For example, please continue reading Figure 3 and combined Figure 5 In the case where the peripheral circuit 102a in the peripheral device layer 102 includes a line decoder, the line decoder can be coupled to the word line WL in the semiconductor device D and can be configured to control the conduction or cutoff of the transmission transistor T1 in the semiconductor device D.

[0139] In some embodiments, please continue reading Figure 5 The semiconductor device D may also include bit lines BL.

[0140] For example, please continue reading Figure 5 In the case where the semiconductor device D includes a transmission transistor T1 and the transmission transistor T1 includes a semiconductor body 1, the bit line BL can be located on one side of the semiconductor body 1 of the transmission transistor T1 along the first direction Z (i.e. the thickness direction of the semiconductor device D) and coupled to the first end 1a of the semiconductor body 1.

[0141] For example, please continue reading Figure 5 In the case where the semiconductor body 1 includes a first electrode 11, a channel 13 and a second electrode 12 arranged sequentially along the first direction Z, and the first electrode 11 of the semiconductor body 1 is located on the side of the channel 13 near the first end 1a of the semiconductor body 1, the bit line BL can also be coupled to the first electrode 11 of the semiconductor body 1.

[0142] Please continue reading. Figure 5 When the semiconductor device D includes a capacitor C, and the transmission transistor T1 is electrically connected to the capacitor C in the semiconductor device D, the capacitor C in the semiconductor device D can be charged or discharged by coupling the bit line BL to the first electrode 11 of the semiconductor body 1 in the transmission transistor T1.

[0143] For example, please continue reading Figure 3 and combined Figure 5 In the case where the peripheral circuit 102a in the peripheral device layer 102 includes a column decoder, the column decoder can be coupled to the bit line BL in the semiconductor device D and can be configured to perform write or read operations on the semiconductor device D in the memory array layer 101.

[0144] For example, please continue reading Figure 3 and combined Figure 5 In the case where the peripheral circuit 102a within the peripheral device layer 102 includes a sense amplifier, the sense amplifier can be configured to sense a low-power signal from the bit line BL within the semiconductor device D, representing a data bit (zero or one) stored in the semiconductor device D, and amplify a small voltage swing to a recognizable logic level.

[0145] For example, the material of the bit line BL within the semiconductor device D may include a conductive material.

[0146] For example, the material of the bit line BL in the semiconductor device D may include one or more (two or more) of copper (Cu), tungsten (W) and aluminum (Al).

[0147] For example, please continue reading Figure 5 In a semiconductor device D comprising a semiconductor body 1, and the semiconductor body 1 comprising a first end 1a and a second end 1b disposed opposite each other in a first direction Z (i.e., the thickness direction of the semiconductor device D), the dimension L1 of the semiconductor body 1 gradually increases along the second direction X from the first end 1a to the second end 1b, where the second direction X is perpendicular to the first direction Z and perpendicular to the extension direction of the bit line BL (i.e., the third direction Y). That is, the dimension L1 of the first end 1a of the semiconductor body 1 along the second direction X is smaller than the dimension L1 of the second end 1b of the semiconductor body 1 along the second direction X.

[0148] In other words, when the semiconductor device D includes a semiconductor body 1, and the semiconductor body 1 includes a first electrode 11, a channel 13, and a second electrode 12 arranged sequentially along the first direction Z, the dimension L1 of the semiconductor body 1 along the second direction X gradually increases from the first electrode 11 to the second electrode 12. That is, the dimension L1 of the first electrode 11 of the semiconductor body 1 along the second direction X is smaller than the dimension L1 of the second electrode 12 of the semiconductor body 1 along the second direction X.

[0149] For example, please continue reading Figure 5 In the cross section of semiconductor device D perpendicular to the extension direction of bit line BL (i.e., the third direction Y), the semiconductor body 1 inside semiconductor device D can be an isosceles trapezoid.

[0150] It should be noted that the statement "in the cross-section of semiconductor device D perpendicular to the extension direction of bit line BL, the semiconductor body 1 within semiconductor device D is an isosceles trapezoid" means that in the cross-section of semiconductor device D perpendicular to the extension direction of bit line BL, the shape of the boundary of semiconductor body 1 is generally an isosceles trapezoid, but it is not limited to a standard isosceles trapezoid. That is, "isosceles trapezoid" here includes not only the shape of a standard isosceles trapezoid, but also shapes similar to isosceles trapezoids, considering process conditions. For example, due to deviations in etching processes (e.g., photolithography) or deposition processes during fabrication, the boundary of semiconductor body 1 in the cross-section of semiconductor device D perpendicular to the extension direction of bit line BL may have slight curvature, asymmetry, or local deformation, but these deviations do not affect the overall isosceles trapezoidal shape of the boundary of semiconductor body 1. Furthermore, in the cross-section of semiconductor device D perpendicular to the extension direction of bit line BL, parameters such as the ratio of the lengths of the upper and lower bases of semiconductor body 1 and the inclination angle of the waist may vary due to process conditions or design requirements. However, these variations still fall within the broad category of "isosceles trapezoid". Therefore, the "isosceles trapezoid" described in this article not only covers the strict geometric definition but also includes the approximate isosceles trapezoid shape that may appear in the actual manufacturing process.

[0151] In some embodiments, please continue reading Figure 5 The semiconductor device D may also include a first insulating layer 31.

[0152] For example, please continue reading Figure 5 In the case where the semiconductor device D includes a transmission transistor T1 and the transmission transistor T1 includes a semiconductor body 1, the first insulating layer 31 may be disposed around the semiconductor body 1 in the circumferential direction.

[0153] For example, please continue reading Figure 5 In the case where the semiconductor device D includes a transmission transistor T1, the transmission transistor T1 includes a semiconductor body 1 and a gate layer G, and the semiconductor body 1 includes a first electrode 11, a channel 13 and a second electrode 12 arranged sequentially along the first direction Z, the first insulating layer 31 can be stacked on one side of the gate layer G, the first insulating layer 31 surrounds the semiconductor body 1 and is opposite to the first electrode 11 of the semiconductor body 1.

[0154] Please continue reading. Figure 5 In the case where the semiconductor device D includes a gate dielectric layer 4 and a bit line BL, and the gate dielectric layer 4 is disposed around the semiconductor body 1, along the first direction Z, the side surface 41 of the gate dielectric layer 4 near the bit line BL can be located between the side surface 31a of the first insulating layer 31 near the gate layer G and the side surface 31b away from the gate layer G.

[0155] In some embodiments, please continue reading Figure 5 The semiconductor device D may also include a second insulating layer 32.

[0156] For example, please continue reading Figure 5 In the case where the semiconductor device D includes a transmission transistor T1 and the transmission transistor T1 includes a semiconductor body 1, the second insulating layer 32 may be disposed around the semiconductor body 1 in the circumferential direction.

[0157] For example, please continue reading Figure 5 In the case where the semiconductor device D includes a transmission transistor T1, the transmission transistor T1 includes a semiconductor body 1 and a gate layer G, and the semiconductor body 1 includes a first electrode 11, a channel 13 and a second electrode 12 arranged sequentially along the first direction Z, the second insulating layer 32 can be stacked on one side of the gate layer G, the second insulating layer 32 surrounds the semiconductor body 1 and is opposite to the second electrode 12 of the semiconductor body 1.

[0158] For example, please continue reading Figure 5 In the case where the semiconductor device D includes a first insulating layer 31, the material of the second insulating layer 32 can be the same as the material of the first insulating layer 31.

[0159] Alternatively, the material of the second insulating layer 32 may be different from the material of the first insulating layer 31.

[0160] For example, the materials of the second insulating layer 32 and the first insulating layer 31 may include one or more (two or more) of silicon dioxide (SiO2) and silicon nitride (Si3N4).

[0161] In some embodiments, please continue reading Figure 5 The semiconductor device D may also include a third insulating layer 33.

[0162] For example, please continue Figure 5 In the case where the semiconductor device D includes a first insulating layer 31 and a gate layer G, the third insulating layer 33 may be located on the side of the first insulating layer 31 away from the gate layer G.

[0163] For example, please continue reading Figure 5 In the case where the semiconductor device D includes a bit line BL, the bit line BL can penetrate the third insulating layer 33 along the first direction Z.

[0164] For example, please continue reading Figure 5 In the case where the semiconductor device D includes a first insulating layer 31, the material of the third insulating layer 33 can be the same as the material of the first insulating layer 31.

[0165] It is understandable that when the material of the third insulating layer 33 is the same as that of the first insulating layer 31, and the third insulating layer 33 and the first insulating layer 31 are in contact, the physical and chemical properties of the third insulating layer 33 and the first insulating layer 31 may be highly consistent in the contact area between them, resulting in a very smooth transition area without a clear boundary. In other words, when the material of the third insulating layer 33 is the same as that of the first insulating layer 31, and the third insulating layer 33 and the first insulating layer 31 are in contact, there may not be a clear connection interface between the third insulating layer 33 and the first insulating layer 31.

[0166] Alternatively, the material of the third insulating layer 33 may be different from the material of the first insulating layer 31.

[0167] For example, the materials of the third insulating layer 33 and the first insulating layer 31 may include one or more (two or more) of silicon dioxide (SiO2) and silicon nitride (Si3N4).

[0168] The following provides a detailed description of the fabrication method of the aforementioned semiconductor device D.

[0169] In some embodiments, such as Figure 6 , Figure 7 and Figure 8 As shown, Figure 6 , Figure 7 and Figure 8 All of these are flowcharts illustrating methods for fabricating semiconductor device D according to some embodiments. It should be noted that... Figure 6 , Figure 7 and Figure 8 The method for fabricating semiconductor device D shown is not exclusive and can also be used in... Figure 6 , Figure 7 and Figure 8 Other steps are performed before, after, or between any step in the fabrication method of the semiconductor device D shown.

[0170] The method for fabricating semiconductor device D may include steps S1 to S4.

[0171] S1: As Figure 9 and Figure 10 As shown, Figure 9 for Figure 6 and Figure 7 The flowchart of the method for fabricating semiconductor device D in the diagram includes steps S0 and S1, and... Figure 7 The flowchart of the fabrication method of semiconductor device D shows a structural diagram of semiconductor device D corresponding to step S7. Figure 10 for Figure 6 and Figure 8 The flowchart of the method for fabricating semiconductor device D in the diagram includes steps S0 and S1, and... Figure 8 The flowchart of the method for fabricating semiconductor device D shows a structural diagram of semiconductor device D corresponding to step S8. An initial stacked structure 3a is formed on one side of substrate 8. The initial stacked structure 3a includes a first insulating layer 31, a gate layer G, and a second insulating layer 32 sequentially disposed along a direction away from substrate 8.

[0172] S2: As Figure 11 and Figure 12 As shown, and in combination Figure 9 and Figure 10 , Figure 11 for Figure 6 and Figure 7 The flowchart of the fabrication method of semiconductor device D shows a structural diagram of semiconductor device D corresponding to steps S2, S5, and S6. Figure 12 for Figure 6 and Figure 8 The flowchart of the method for fabricating semiconductor device D shows a structural diagram of semiconductor device D corresponding to steps S2, S5, and S6. A semiconductor body 1 is formed that penetrates the initial stacked structure 3a. The semiconductor body 1 includes a first end 1a and a second end 1b disposed opposite each other in a first direction Z, where the first direction Z is the thickness direction of the substrate 8.

[0173] S3: As Figure 13 and Figure 14 As shown, Figure 13 for Figure 6 and Figure 7 The flowchart of the fabrication method of semiconductor device D shows a structural diagram of semiconductor device D corresponding to step S3. Figure 14 for Figure 6 and Figure 8 The flowchart of the fabrication method of semiconductor device D shows a structural diagram of semiconductor device D corresponding to step S3. The substrate 8 is removed to expose the first end 1a.

[0174] S4: As Figure 15 and Figure 16 As shown, Figure 15 for Figure 6 and Figure 7 The flowchart of the fabrication method of semiconductor device D shows a structural diagram of semiconductor device D corresponding to step S4. Figure 16 for Figure 6 and Figure 8 The flowchart of the method for fabricating semiconductor device D shows a structural diagram of semiconductor device D corresponding to step S4. A bit line BL is formed. The bit line BL is located on one side of the semiconductor body 1 along the first direction Z and coupled to the first end 1a.

[0175] In the above-mentioned method for fabricating semiconductor device D, a semiconductor body 1 penetrating the initial stacked structure 3a is first formed within the initial stacked structure 3a, then the substrate 8 is removed to expose the first end 1a of the semiconductor body 1, and finally a bit line BL coupled to the first end 1a of the semiconductor body 1 is formed. Compared with forming the bit line BL between the initial stacked structure 3a and the substrate 8 first, and then forming the semiconductor body 1 penetrating the initial stacked structure 3a and coupling the first end 1a of the semiconductor body 1 to the bit line BL, forming the semiconductor body 1 penetrating the initial stacked structure 3a first, then exposing the first end 1a of the semiconductor body 1, and finally forming the bit line BL coupled to the first end 1a of the semiconductor body 1, allows for more precise control of the position and size of the bit line BL. This avoids alignment errors that may occur when processing the semiconductor body 1 after the bit line BL is formed, which is beneficial for optimizing the fabrication process of semiconductor device D and reducing the complexity of the fabrication process of semiconductor device D.

[0176] On the other hand, after the first end 1a of the semiconductor body 1 is exposed, a bit line BL is formed that is coupled to the first end 1a of the semiconductor body 1. This makes the contact interface between the first end 1a of the semiconductor body 1 and the bit line BL cleaner and tighter. This helps to reduce or eliminate defects in the contact interface between the first end 1a of the semiconductor body 1 and the bit line BL, and also helps to reduce the contact resistance between the first end 1a of the semiconductor body 1 and the bit line BL. This, in turn, helps to improve the electrical performance between the first end 1a of the semiconductor body 1 and the bit line BL, thereby improving the reliability of the semiconductor device D.

[0177] On the other hand, by first removing the substrate 8 to expose the first end 1a of the semiconductor body 1, and then forming the bit line BL coupled to the first end 1a of the semiconductor body 1, a wider range of materials can be selected when forming the bit line BL, without having to consider the compatibility between the material used to form the bit line BL and the material of the substrate 8, which is beneficial to improving the design flexibility of the semiconductor device D.

[0178] For example, please continue reading Figure 6 , Figure 7 and Figure 8 Before step S2 (i.e., forming the semiconductor body 1 through the initial stacked structure 3a) in the flowchart of the method for fabricating semiconductor device D, the method for fabricating semiconductor device D may also include steps S5 and S6.

[0179] S5: Please continue reading Figure 11 and Figure 12 This forms a through-hole K that penetrates the initial stacked structure 3a.

[0180] For example, please continue reading Figure 11 and Figure 12 The initial stacked structure 3a can be etched using a dry etching process to form a through-hole K that penetrates the initial stacked structure 3a.

[0181] S6: Please continue reading Figure 11 and Figure 12 An initial gate dielectric layer 4a is formed inside the via K, and the initial gate dielectric layer 4a covers the sidewalls and bottom of the via K.

[0182] For example, please continue reading Figure 11 and Figure 12 The material used to form the initial gate dielectric layer 4a can be deposited on the sidewalls and bottom of the via K through one or more processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD), thereby forming the initial gate dielectric layer 4a covering the sidewalls and bottom of the via K.

[0183] For example, please continue reading Figure 6 , Figure 7 and Figure 8 In the case where the method for fabricating semiconductor device D includes step S5 (i.e., forming a via K through the initial stacked structure 3a) and step S6 (i.e., forming an initial gate dielectric layer 4a within the via K), step S3 (i.e., removing the substrate 8 to expose the first end 1a) in the flowchart of the method for fabricating semiconductor device D may include steps S31 and S32.

[0184] S31: Please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 Remove substrate 8 to expose initial gate dielectric layer 4a located at the bottom of via K.

[0185] S32: Please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 The initial gate dielectric layer 4a located at the bottom of the via K is removed to expose the first end 1a of the semiconductor body 1, and the remaining initial gate dielectric layer 4a forms the gate dielectric layer 4.

[0186] In the above-mentioned method for fabricating semiconductor device D, a via K penetrating the initial stacked structure 3a is first formed within the initial stacked structure 3a. Then, an initial gate dielectric layer 4a is formed within the via K, covering the sidewalls and bottom of the via K. Next, a semiconductor body 1 penetrating the initial stacked structure 3a is formed within the initial stacked structure 3a, with the initial gate dielectric layer 4a covering the sidewalls and bottom of the semiconductor body 1. Then, the substrate 8 and the initial gate dielectric layer 4a located at the bottom of the via K are sequentially removed to expose the first end 1a of the semiconductor body 1. Finally, a bit line BL coupled to the first end 1a of the semiconductor body 1 is formed. This method is superior to first forming a bit line BL between the initial stacked structure 3a and the substrate 8, then forming a via K penetrating the initial stacked structure 3a within the initial stacked structure 3a, then forming an initial gate dielectric layer 4a within the via K, covering the sidewalls and bottom of the via K, and then removing the initial gate dielectric layer 4a located at the bottom of the via K. A gate dielectric layer 4a is formed to expose the bit line BL, and finally a semiconductor body 1 is formed that penetrates the initial stacked structure 3a. The first end 1a of the semiconductor body 1 is coupled to the bit line BL. On the one hand, after the semiconductor body 1 that penetrates the initial stacked structure 3a is formed in the initial stacked structure 3a, the substrate 8 is removed first to expose the initial gate dielectric layer 4a located at the bottom of the via K. Then, the initial gate dielectric layer 4a located at the bottom of the via K is removed to expose the first end 1a of the semiconductor body 1. The remaining initial gate dielectric layer 4a forms the gate dielectric layer 4. This way, when removing the initial gate dielectric layer 4a located at the bottom of the via K, it is not necessary to go through the via K. This can avoid damage to the initial gate dielectric layer 4a located on the sidewall of the via K when removing the initial gate dielectric layer 4a located at the bottom of the via K. This is beneficial to improving the insulation performance of the finally formed gate dielectric layer 4, reducing the risk of short circuit between the semiconductor body 1 and the gate layer G, and thus improving the electrical performance of the semiconductor device D.

[0187] On the other hand, since the initial gate dielectric layer 4a located at the bottom of the via K does not need to be removed through the via K, the size of the via K is not limited by the process of removing the initial gate dielectric layer 4a located at the bottom of the via K. This is beneficial for reducing the size of the via K, and thus for reducing the size of the semiconductor device D. This is conducive to realizing the miniaturization of the semiconductor device D.

[0188] For example, please continue reading Figure 6 , Figure 7 and Figure 8 Before step S1 (i.e., forming an initial stacked structure 3a on one side of the substrate 8) in the flowchart of the method for fabricating semiconductor device D, the method for fabricating semiconductor device D may also include step S0.

[0189] S0: Please continue reading Figure 9 and Figure 10A buffer layer m2 is formed on one side of the substrate 8.

[0190] Please continue reading. Figure 6 , Figure 7 and Figure 8 and combined Figure 9 and Figure 10 Since step S0 in the flowchart of the method for fabricating semiconductor device D is before step S1 (i.e., forming the initial stacked structure 3a on one side of the substrate 8), that is, before the initial stacked structure 3a is formed, the buffer layer m2 is located between the substrate 8 and the initial stacked structure 3a.

[0191] Please continue reading. Figure 6 , Figure 7 and Figure 8 In the flowchart of the method for fabricating semiconductor device D, step S3 (i.e., removing substrate 8 to expose the first end 1a) includes steps S31 (i.e., removing substrate 8 to expose the initial gate dielectric layer 4a located at the bottom of via K) and step S32 (i.e., removing the initial gate dielectric layer 4a located at the bottom of via K to expose the first end 1a of semiconductor body 1, with the remaining initial gate dielectric layer 4a forming the gate dielectric layer 4). After step S31 (i.e., removing substrate 8) in the flowchart of the method for fabricating semiconductor device D, step S3 in the flowchart of the method for fabricating semiconductor device D may also include step S33.

[0192] S33: Please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 Remove the buffer layer m2 to expose the initial gate dielectric layer 4a located at the bottom of the via K.

[0193] For example, please continue reading Figure 13 and Figure 14 and combined Figure 11 and Figure 12 , Figure 6 , Figure 7 and Figure 8 After step S2 (i.e., forming a semiconductor body 1 that penetrates the initial stacked structure 3a) in the flowchart of the method for fabricating semiconductor device D, and before step S3 (i.e., removing the substrate 8 to expose the first end 1a), a capacitor C and a carrier layer located on the side of the capacitor C away from the semiconductor body 1, and a connection layer N1 located between the carrier layer and the capacitor C can be formed by back end of line (BEOL) and carry bonding processes.

[0194] In some embodiments, please continue reading Figure 7Before step S1 (i.e., forming an initial stacked structure 3a on one side of the substrate 8) in the flowchart of the method for fabricating semiconductor device D, the method for fabricating semiconductor device D may also include step S7.

[0195] S7: Please continue reading Figure 9 A sacrificial layer m1 is formed on one side of the substrate 8.

[0196] Please continue reading. Figure 7 and Figure 9 Since step S7 in the flowchart of the semiconductor device D fabrication method is before step S1 (i.e., forming the initial stacked structure 3a on one side of the substrate 8), that is, the sacrificial layer m1 is formed before the initial stacked structure 3a, the sacrificial layer m1 is located between the substrate 8 and the initial stacked structure 3a.

[0197] For example, please continue reading Figure 11 and combined Figure 7 In the case where the method for fabricating semiconductor device D includes step S5 (i.e., forming a via K that penetrates the initial stacked structure 3a), when forming the via K that penetrates the initial stacked structure 3a, the bottom of the via K can stop inside the sacrificial layer m1.

[0198] Alternatively, when forming a via K that penetrates the initial stacked structure 3a, the bottom of the via K may stop at the surface m11 of the sacrificial layer m1 away from the substrate 8.

[0199] For example, please continue reading Figure 7 In the case where step S3 (i.e., removing the substrate 8 to expose the first end 1a) in the flowchart of the method for fabricating semiconductor device D includes step S31 (i.e., removing the substrate 8 to expose the initial gate dielectric layer 4a located at the bottom of the via K) and step S32 (i.e., removing the initial gate dielectric layer 4a located at the bottom of the via K to expose the first end 1a of the semiconductor body 1, with the remaining initial gate dielectric layer 4a forming the gate dielectric layer 4), after step S31 (i.e., removing the substrate 8) in the flowchart of the method for fabricating semiconductor device D, step S3 in the flowchart of the method for fabricating semiconductor device D may also include step S34.

[0200] S34: Please continue reading Figure 13 and combined Figure 11 Remove the sacrificial layer m1 to expose the initial gate dielectric layer 4a located at the bottom of the via K.

[0201] For example, please continue reading Figure 7In the case where the method for fabricating semiconductor device D includes step S0 (i.e., forming a buffer layer m2 on one side of substrate 8), step S7 (i.e., forming a sacrificial layer m1 on one side of substrate 8) in the flowchart of the method for fabricating semiconductor device D can be after step S0 and before step S1 (i.e., forming an initial stacked structure 3a on one side of substrate 8).

[0202] Please continue reading. Figure 7 and Figure 9 Since the semiconductor device D fabrication method includes steps S0, S1 and S7, step S7 in the flowchart of the semiconductor device D fabrication method is after step S0 and before step S1. That is, the sacrificial layer m1 is formed after the buffer layer m2 and before the initial stacked structure 3a. Therefore, the sacrificial layer m1 is located between the buffer layer m2 and the initial stacked structure 3a.

[0203] For example, such as Figure 17 As shown, and in combination Figure 6 , Figure 7 , Figure 9 and Figure 13 , Figure 17 for Figure 6 and Figure 7 The flowchart of the fabrication method of semiconductor device D shows a structural diagram of semiconductor device D corresponding to step S4. It should be noted that... Figure 17 The structural diagram of semiconductor device D shows only the stacked structure 3, semiconductor body 1, gate dielectric layer 4, bit line BL and third insulating layer 33 within semiconductor device D, omitting other structures within semiconductor device D (e.g., capacitor C within semiconductor device D).

[0204] In the case where the method for fabricating semiconductor device D includes step S7 (i.e., forming a sacrificial layer m1 on one side of substrate 8), and step S3 (i.e., removing substrate 8 to expose first end 1a) in the flowchart of the method for fabricating semiconductor device D includes step S34 (i.e., removing sacrificial layer m1 to expose initial gate dielectric layer 4a located at the bottom of via K), step S4 (i.e. forming bit line BL) in the flowchart of the method for fabricating semiconductor device D may include steps S41 and S42.

[0205] S41: Please continue reading Figure 17 An initial bit line layer BL1 is formed. The initial bit line layer BL1 is located at least on the side of the first insulating layer 31 away from the gate layer G.

[0206] S42: Please continue reading Figure 17 Remove a portion of the initial bit line layer BL1, and the remaining initial bit line layer BL1 forms a bit line BL, which is coupled to the first end 1a.

[0207] For example, please continue reading Figure 13 and Figure 17 and combined Figure 6 and Figure 7 In the flowchart of the method for fabricating semiconductor device D, step S3 (i.e., removing the substrate 8 to expose the first end 1a) includes steps S31 (i.e., removing the substrate 8 to expose the initial gate dielectric layer 4a located at the bottom of the via K), step S34 (i.e., removing the sacrificial layer m1 to expose the initial gate dielectric layer 4a located at the bottom of the via K), and step S32 (i.e., removing the initial gate dielectric layer 4a located at the bottom of the via K to expose the first end 1a of the semiconductor body 1, with the remaining initial gate dielectric layer 4a forming the gate dielectric layer 4). In the above-mentioned method for fabricating semiconductor device D, the steps... In S41 (i.e., forming the initial bit line layer BL1), based on the initial bit line layer BL1 being located on the side of the first insulating layer 31 away from the gate layer G, the initial bit line layer BL1 can also fill the gap between the first insulating layer 31 and the semiconductor body 1, and the side surface 41 of the gate dielectric layer 4 near the first end 1a of the semiconductor body 1 (i.e., the side surface 41 of the gate dielectric layer 4 near the main body portion 21 of the bit line BL, where the main body portion 21 of the bit line BL will be described in detail below) and the side surface BL11 of the initial bit line layer BL1 near the second end 1b of the semiconductor body 1 are in contact.

[0208] For example, please continue reading Figure 17 Step S42 in the above-mentioned method for fabricating semiconductor device D (i.e., removing a portion of the initial bit line layer BL1, with the remaining initial bit line layer BL1 forming a bit line BL and coupled to the first end 1a) can specifically be: etching a portion of the initial bit line layer BL1 via the side of the initial bit line layer BL1 away from the first insulating layer 31 to form a plurality of first openings E1, with the remaining initial bit line layer BL1 forming a bit line BL and coupled to the first end 1a of the semiconductor body 1.

[0209] Please continue reading. Figure 17 After step S42 (i.e., removing a portion of the initial bit line layer BL1, with the remaining initial bit line layer BL1 forming a bit line BL and coupled to the first end 1a) in the method for fabricating semiconductor device D, step S4 (i.e., forming the bit line BL) in the flowchart of the method for fabricating semiconductor device D may include step S43.

[0210] S43: Please continue reading Figure 17 A third insulating layer 33 is formed within the first opening E1.

[0211] The material of the third insulating layer 33 can be the same as the material of the first insulating layer 31. Alternatively, the material of the third insulating layer 33 can be different from the material of the first insulating layer 31.

[0212] In other embodiments, please continue to refer to Figure 8 Before step S1 (i.e., forming an initial stacked structure 3a on one side of the substrate 8) in the flowchart of the method for fabricating semiconductor device D, the method for fabricating semiconductor device D may also include step S8.

[0213] S8: Please continue reading Figure 10 A third insulating layer 33 is formed on one side of the substrate 8, and a sacrificial portion 7 is embedded in the third insulating layer 33. The sacrificial portion 7 penetrates the third insulating layer 33 along the first direction Z.

[0214] Please continue reading. Figure 8 and Figure 10 Since step S8 in the flowchart of the method for fabricating semiconductor device D is before step S1 (i.e., forming an initial stacked structure 3a on one side of substrate 8), that is, before the initial stacked structure 3a is formed, the third insulating layer 33 is located between substrate 8 and the initial stacked structure 3a.

[0215] For example, please continue reading Figure 12 and combined Figure 8 In the case where the method for fabricating semiconductor device D includes step S5 (i.e., forming a via K that penetrates the initial stacked structure 3a), when forming the via K that penetrates the initial stacked structure 3a, the bottom of the via K can stop inside the sacrificial portion 7.

[0216] Alternatively, when forming a through-hole K that penetrates the initial stacked structure 3a, the bottom of the through-hole K may stop at the surface 71 of the sacrificial portion 7 away from the substrate 8.

[0217] For example, please continue reading Figure 8 In the flowchart of the method for fabricating semiconductor device D, step S3 (i.e., removing substrate 8 to expose the first end 1a) includes steps S31 (i.e., removing substrate 8 to expose the initial gate dielectric layer 4a located at the bottom of via K) and step S32 (i.e., removing the initial gate dielectric layer 4a located at the bottom of via K to expose the first end 1a of semiconductor body 1, with the remaining initial gate dielectric layer 4a forming the gate dielectric layer 4). After step S31 (i.e., removing substrate 8) in the flowchart of the method for fabricating semiconductor device D, step S3 in the flowchart of the method for fabricating semiconductor device D may also include step S35.

[0218] S35: Please continue reading Figure 14 and combined Figure 12 Remove the sacrificial portion 7 to expose the initial gate dielectric layer 4a located at the bottom of the via K.

[0219] For example, please continue reading Figure 8When the method for fabricating semiconductor device D includes step S0 (i.e., forming a buffer layer m2 on one side of substrate 8), step S8 (i.e., forming a third insulating layer 33 on one side of substrate 8 and a sacrificial portion 7 embedded in the third insulating layer 33) in the flowchart of the method for fabricating semiconductor device D can be after step S0 and before step S1 (i.e., forming an initial stacked structure 3a on one side of substrate 8).

[0220] Please continue reading. Figure 8 and Figure 10 Since the semiconductor device D fabrication method includes steps S0, S1 and S8, step S8 in the flowchart of the semiconductor device D fabrication method is after step S0 and before step S1. That is, the third insulating layer 33 is formed after the buffer layer m2 and before the initial stacked structure 3a. Therefore, the third insulating layer 33 is located between the buffer layer m2 and the initial stacked structure 3a.

[0221] Please continue reading. Figure 12 and Figure 14 and combined Figure 8 In the flowchart of the method for fabricating semiconductor device D, step S3 (i.e., removing substrate 8 to expose the first end 1a) includes step S31 (i.e., removing substrate 8 to expose the initial gate dielectric layer 4a located at the bottom of via K), step S33 (i.e., removing buffer layer m2 to expose the initial gate dielectric layer 4a located at the bottom of via K), step S35 (i.e., removing sacrificial portion 7 to expose the initial gate dielectric layer 4a located at the bottom of via K), and step S32 (i.e., removing the initial gate dielectric layer 4a located at the bottom of via K to expose the first end 1a of semiconductor body 1, with the remaining initial gate dielectric layer 4a forming the gate dielectric layer 4), the materials of buffer layer m2 and third insulating layer 33 are different.

[0222] In the above-mentioned method for fabricating semiconductor device D, the materials of buffer layer m2 and third insulating layer 33 are different, so that when buffer layer m2 is removed by etching process (e.g., wet etching process), etching stops at third insulating layer 33 to avoid removal of third insulating layer 33.

[0223] For example, such as Figure 18 As shown, and in combination Figure 8 and Figure 10 , Figure 18 for Figure 8The flowchart of the method for fabricating semiconductor device D shows a structural diagram of semiconductor device D corresponding to step S8. Step S8 in the flowchart of the method for fabricating semiconductor device D (i.e., forming a third insulating layer 33 on one side of substrate 8, and a sacrificial portion 7 embedded in the third insulating layer 33) can be specifically described as follows: First, an initial third insulating layer 331 is formed on one side of substrate 8 within semiconductor device D. Then, a portion of the initial third insulating layer 331 is etched through a surface 331a away from substrate 8 to form multiple second openings E2. The remaining portion of the initial third insulating layer 331 forms the third insulating layer 33. Finally, a sacrificial portion 7 is formed within the second openings E2. The sacrificial portion 7 penetrates the third insulating layer 33 along the first direction Z.

[0224] For example, the material of the sacrificial part 7 may include at least one of titanium nitride (TiN) and polysilicon.

[0225] For example, the material of the sacrificial part 7 may include one of titanium nitride and polycrystalline silicon.

[0226] For example, the material of the sacrificial part 7 may include multiple (two or more) materials such as titanium nitride and polycrystalline silicon.

[0227] For example, the material of the third insulating layer 33 can be the same as the material of the first insulating layer 31. Alternatively, the material of the third insulating layer 33 can be different from the material of the first insulating layer 31.

[0228] For example, the materials of the third insulating layer 33 and the first insulating layer 31 may include one or more (two or more) of silicon dioxide (SiO2) and silicon nitride (Si3N4).

[0229] The bit line BL within the semiconductor device D formed by the above-described method is described in detail below.

[0230] In some embodiments, such as Figure 19 As shown, Figure 19 This is a structural diagram of a partial region of a semiconductor device D according to some embodiments. A bit line BL within the semiconductor device D may include a body portion 21. At least a portion of the body portion 21 of the bit line BL is located on the side of the first end 1a of the semiconductor body 1 away from the second end 1b.

[0231] Please continue reading. Figure 19 The dimension L21a of the main body portion 21 of the bit line BL away from the semiconductor body 1 along the second direction X can be smaller than the dimension L21b of the main body portion 21 near the semiconductor body 1 along the second direction X. The second direction X is perpendicular to the first direction Z and perpendicular to the extension direction of the bit line BL.

[0232] For example, please continue reading Figure 19 From the end 21a of the main body portion 21 away from the semiconductor body 1 to the end 21b of the main body portion 21 close to the semiconductor body 1, the size L21 of the main body portion 21 along the second direction X can gradually increase.

[0233] For example, please continue reading Figure 19 In the first cross-section of the bit line BL within the semiconductor device D, if the size L21 of the main body portion 21 gradually increases along the second direction X from the end 21a away from the semiconductor body 1 to the end 21b closer to the semiconductor body 1, the main body portion 21 within the bit line BL can be an isosceles trapezoid. The first cross-section is obtained by cutting the bit line BL along the first direction Z and perpendicular to the extension direction of the bit line BL (i.e., the third direction Y).

[0234] It should be noted that the statement "in the first cross-section of bitline BL, the main body 21 within bitline BL is an isosceles trapezoid" means that the shape of the boundary of the main body 21 within bitline BL in the first cross-section of bitline BL is generally an isosceles trapezoid, but it is not limited to a standard isosceles trapezoid. That is, "isosceles trapezoid" here includes not only the shape of a standard isosceles trapezoid, but also shapes similar to isosceles trapezoids, taking into account process conditions. For example, due to deviations in etching processes (e.g., photolithography) or deposition processes during fabrication, the boundary of the main body 21 within bitline BL in the first cross-section of bitline BL may have slight curvature, asymmetry, or local deformation, but these deviations do not affect the fact that the boundary of the main body 21 within bitline BL generally presents an isosceles trapezoidal shape. In addition, parameters such as the ratio of the lengths of the upper and lower bases and the inclination angle of the waist sides of the main body 21 within bitline BL in the first cross-section of bitline BL may also vary due to process conditions or design requirements, but these variations still fall within the broad category of "isosceles trapezoid". Therefore, the term "isosceles trapezoid" as used in this article not only encompasses the strict geometric definition but also includes the approximate isosceles trapezoid shape that may appear during actual manufacturing.

[0235] For example, please continue reading Figure 19 In the case where the semiconductor device D includes a first insulating layer 31 and a gate layer G, and both the first insulating layer 31 and the gate layer G are disposed around the semiconductor body 1 in the circumferential direction, the first insulating layer 31 may be located between the gate layer G in the semiconductor device D and the body portion 21 in the bit line BL in the first direction Z.

[0236] For example, please continue reading Figure 19 The main body portion 21 within the bit line BL can contact the side surface of the first insulating layer 31 that is close to the first insulating layer 31 and away from the gate layer G.

[0237] For example, when the semiconductor device D includes a first insulating layer 31 and a gate layer G, and both the first insulating layer 31 and the gate layer G are disposed around the semiconductor body 1 in the circumferential direction, the first end 1a of the semiconductor body 1 can be flush with the side surface of the first insulating layer 31 away from the gate layer G.

[0238] Alternatively, please continue reading Figure 19 Along the first direction Z, the first end 1a of the semiconductor body 1 can be located between the surface of the first insulating layer 31 away from the gate layer G and the surface of the main body portion 21 in the bit line BL away from the semiconductor body 1. That is, the first end 1a of the semiconductor body 1 can be embedded in the main body portion 21 of the bit line BL.

[0239] For example, please continue reading Figure 19 In the case where the semiconductor device D includes a third insulating layer 33, the main body portion 21 in the bit line BL can be embedded in the third insulating layer 33.

[0240] In some embodiments, please continue reading Figure 19 The bit line BL within the semiconductor device D may also include an extension 22. The extension 22 is located on the side of the main body 21 within the bit line BL near the second end 1b of the semiconductor body 1 and is connected to the main body 21.

[0241] For example, please continue reading Figure 19 The extension 22 within the bit line BL can be disposed around the semiconductor body 1 and contact the side of the semiconductor body 1.

[0242] For example, please continue reading Figure 19 When the semiconductor body 1 includes a first electrode 11, a channel 13 and a second electrode 12 arranged sequentially along the first direction Z, the extension 22 in the bit line BL can be arranged around the first electrode 11 of the semiconductor body 1 and contact the side of the first electrode 11 of the semiconductor body 1.

[0243] For example, please continue reading Figure 19 When the semiconductor device D includes a first insulating layer 31 and the first insulating layer 31 is disposed around the semiconductor body 1 in the circumferential direction, the extension 22 in the bit line BL can be located between the semiconductor body 1 and the first insulating layer 31.

[0244] Please continue reading. Figure 19In the case where the semiconductor device D includes a gate dielectric layer 4, which is located at least between the semiconductor body 1 and the gate layer G and is disposed around the semiconductor body 1, the side surface 41 of the gate dielectric layer 4 near the body portion 21 in the bit line BL can contact the side surface 22a of the extension portion 22 in the bit line BL away from the body portion 21.

[0245] For example, please continue reading Figure 19 The dimension H1 of the semiconductor body 1 along the first direction Z can be larger than the dimension H4 of the gate dielectric layer 4 along the first direction Z.

[0246] For example, please continue reading Figure 19 When the extension 22 within the bit line BL is located between the semiconductor body 1 and the first insulating layer 31, the dimension H1 of the semiconductor body 1 along the first direction Z can be larger than the dimension H4 of the gate dielectric layer 4 along the first direction Z.

[0247] For example, please continue reading Figure 19 The dimension L22 of the extension portion 22 within the bit line BL along the second direction X is smaller than the dimension L21 of the main body portion 21 within the bit line BL along the second direction X.

[0248] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: The semiconductor body includes a first end and a second end disposed opposite to each other in a first direction; the first direction is the thickness direction of the semiconductor device. A gate layer is disposed around the semiconductor body in the circumferential direction; Bit line, located on one side of the semiconductor body along the first direction and coupled to the first end; the bit line includes a body portion, at least a portion of which is located on the side of the first end away from the second end; Wherein, the dimension of the end of the main body portion away from the semiconductor body along the second direction is smaller than the dimension of the end of the main body portion near the semiconductor body along the second direction; the second direction is perpendicular to the first direction and perpendicular to the extension direction of the bit line.

2. The semiconductor device according to claim 1, characterized in that, From the end of the main body portion away from the semiconductor body to the end of the main body portion closer to the semiconductor body, the size of the main body portion gradually increases along the second direction.

3. The semiconductor device according to claim 2, characterized in that, In the first cross-section of the bit line, the main body is an isosceles trapezoid; the first cross-section is a cross-section obtained by cutting the bit line along the first direction and perpendicular to the extension direction of the bit line.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a first insulating layer disposed around the semiconductor body in the circumferential direction; Along the first direction, the first insulating layer is located between the gate layer and the body portion.

5. The semiconductor device according to claim 4, characterized in that, The first end and the surface of the first insulating layer away from the gate layer are flush; or... Along the first direction, the first end is located between the side surface of the first insulating layer away from the gate layer and the side surface of the main body away from the semiconductor body.

6. The semiconductor device according to claim 4, characterized in that, The bit line also includes an extension located on the side of the main body portion near the second end and connected to the main body portion; The extension is disposed around the semiconductor body and contacts the side of the semiconductor body.

7. The semiconductor device according to claim 6, characterized in that, The extension is located between the semiconductor body and the first insulating layer.

8. The semiconductor device according to claim 6, characterized in that, The dimension of the extension portion along the second direction is smaller than the dimension of the main body portion along the second direction.

9. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes a gate dielectric layer, which is located at least between the semiconductor body and the gate layer and is disposed around the semiconductor body; The side surface of the gate dielectric layer near the main body is in contact with the side surface of the extension away from the main body.

10. The semiconductor device according to claim 9, characterized in that, Along the first direction, the side surface of the gate dielectric layer near the bit line is located between the side surface of the first insulating layer near the gate layer and the side surface away from the gate layer.

11. The semiconductor device according to claim 9, characterized in that, The dimension of the semiconductor body along the first direction is greater than the dimension of the gate dielectric layer along the first direction.

12. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes a third insulating layer located on the side of the first insulating layer away from the gate layer; the material of the third insulating layer is different from the material of the first insulating layer. The main body is embedded in the third insulating layer.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that, From the first end to the second end of the semiconductor body, the size of the semiconductor body gradually increases along the second direction.

14. A method for fabricating a semiconductor device, characterized in that, include: An initial stacked structure is formed on one side of a substrate; the initial stacked structure includes a first insulating layer, a gate layer, and a second insulating layer sequentially disposed in a direction away from the substrate; A semiconductor body is formed that extends through the initial stacked structure; the semiconductor body includes a first end and a second end disposed opposite to each other in a first direction, the first direction being the thickness direction of the substrate; Remove the substrate to expose the first end; Form bit lines; The bit line is located on one side of the semiconductor body along the first direction and is coupled to the first end.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, Prior to forming the semiconductor body that extends through the initial stacked structure, the method further includes: Forming a through-hole that penetrates the initial stacked structure; An initial gate dielectric layer is formed within the via, the initial gate dielectric layer covering the sidewalls and bottom of the via.

16. The method for fabricating a semiconductor device according to claim 15, characterized in that, The removal of the substrate to expose the first end includes: Remove the substrate to expose the initial gate dielectric layer located at the bottom of the via; The initial gate dielectric layer located at the bottom of the via is removed to expose the first end of the semiconductor body, and the remaining initial gate dielectric layer forms the gate dielectric layer.

17. The method for fabricating a semiconductor device according to claim 16, characterized in that, Before forming the initial stacked structure on one side of the substrate, the method further includes: forming a sacrificial layer on one side of the substrate; The sacrificial layer is located between the substrate and the initial stacked structure; when forming a via through the initial stacked structure, the bottom of the via stops inside the sacrificial layer or on the surface of the sacrificial layer away from the substrate; After removing the substrate, the sacrificial layer is also removed to expose the initial gate dielectric layer located at the bottom of the via.

18. The method for fabricating a semiconductor device according to claim 16, characterized in that, Before forming the initial stacked structure on one side of the substrate, the method further includes: forming a third insulating layer on one side of the substrate, and a sacrificial portion embedded in the third insulating layer; the sacrificial portion penetrates the third insulating layer along the first direction. The third insulating layer is located between the substrate and the initial stacked structure; when forming a via through the initial stacked structure, the bottom of the via stops inside the sacrificial portion or on the surface of the sacrificial portion away from the substrate; After removing the substrate, the sacrificial portion is also removed to expose the initial gate dielectric layer located at the bottom of the via.

19. The method for fabricating a semiconductor device according to claim 17, characterized in that, The formation of bit lines includes: An initial bit line layer is formed; the initial bit line layer is located at least on the side of the first insulating layer away from the gate layer; The initial bit line layer in a certain region is removed, and the remaining initial bit line layer forms a bit line and is coupled to the first end; The bit line includes a main body portion, at least a portion of which is located on the side of the first end away from the second end; the dimension of the main body portion away from the semiconductor body along the second direction is smaller than the dimension of the main body portion near the semiconductor body along the second direction; the second direction is perpendicular to the first direction and perpendicular to the extension direction of the bit line.

20. The method for fabricating a semiconductor device according to claim 19, characterized in that, The initial bit line layer also fills the gap between the first insulating layer and the semiconductor body, and the side surface of the gate dielectric layer near the body portion is in contact with the side surface of the initial bit line layer near the second end; The bit line further includes an extension located on the side of the main body near the second end and connected to the main body; the extension is disposed around the semiconductor body and contacts the side of the semiconductor body.

21. A memory, characterized in that, include: The semiconductor device as described in any one of claims 1 to 13; The peripheral device layer is coupled to the semiconductor device.

22. A storage system, characterized in that, include: The memory as described in claim 21; The controller is electrically connected to the memory.

23. An electronic device, characterized in that, include: The processor, and the storage system as claimed in claim 22, wherein the processor is coupled to the storage system.

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