Semiconductor device and method of manufacturing the same, storage system

Abstract

The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a storage system, wherein the semiconductor device comprises: a first semiconductor structure comprising a first bonding layer, a peripheral circuit layer comprising a logic circuit, and an interconnection layer; a second semiconductor structure comprising a storage array layer comprising a DRAM storage unit, and a second bonding layer; the second bonding layer is bonded to the first bonding layer; wherein the first semiconductor structure further comprises: a first interconnection structure between the logic circuit and the first bonding layer; a contact structure penetrating through a semiconductor layer where the logic circuit is located; and a second interconnection structure and a pad in the interconnection layer; the logic circuit is connected to the pad through the first interconnection structure, the contact structure, and the second interconnection structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a method for manufacturing the same, and a memory system. Background Technology

[0002] Semiconductor devices, such as Dynamic Random Access Memory (DRAM), are among the most important storage components in electronic systems. They typically employ a 1T1C structure, consisting of a transistor (T) and a capacitor (C), as a storage cell. This 1T1C structure allows DRAM to achieve high integration density and low cost, giving it an irreplaceable position in computer storage devices. With the rapid development of semiconductor technology, DRAM is rapidly evolving towards higher density and higher quality. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a first semiconductor structure including a first bonding layer, a peripheral circuit layer containing logic circuitry, and an interconnect layer; a second semiconductor structure including a memory array layer containing DRAM memory cells and a second bonding layer; the second bonding layer being bonded to the first bonding layer; wherein the first semiconductor structure further comprises: a first interconnect structure located between the logic circuitry and the first bonding layer; a contact structure penetrating the semiconductor layer containing the logic circuitry; and a second interconnect structure and a pad located in the interconnect layer; the logic circuitry being connected to the pads via the first interconnect structure, the contact structure, and the second interconnect structure.

[0004] In some embodiments, the first interconnect structure includes a plurality of first connection structures extending along a first direction and at least one first metal layer extending along a second direction and / or a third direction; the at least one first metal layer and the plurality of first connection structures are alternately arranged along the first direction; the first direction is the stacking direction of the first semiconductor structure and the second semiconductor structure; the second direction intersects with the third direction and is perpendicular to the first direction.

[0005] In some embodiments, the logic circuit includes a decoding circuit, a driving circuit, a sensing amplification circuit, and a horizontal hammer refresh circuit; the first interconnect structure includes multiple layers of the first metal layer; wherein the decoding circuit, the driving circuit, the sensing amplification circuit, and the horizontal hammer refresh circuit are respectively connected to different first metal layers.

[0006] In some embodiments, the second interconnect structure includes a plurality of second connection structures extending along the first direction and at least one second metal layer extending along the second direction and / or the third direction; the at least one second metal layer and the plurality of second connection structures are alternately arranged along the first direction.

[0007] In some embodiments, the number of contact structures includes a plurality; the plurality of contact structures are arranged at intervals in the second direction and / or the third direction upward.

[0008] In some embodiments, the materials comprising the pads, the first connection structure, the second connection structure, the first metal layer, the second metal layer, and the contact structure are all conductive materials.

[0009] In some embodiments, a plurality of the second connection structures, spaced apart along the second direction and / or the third direction, are connected to the same pad.

[0010] In some embodiments, the first semiconductor structure further includes a dielectric layer; the dielectric layer extends through the semiconductor layer along the first direction and surrounds the sidewall of the contact structure.

[0011] In some embodiments, the first bonding layer includes a first bonding contact and a first insulating layer that isolates the first bonding contact; the second bonding layer includes a second bonding contact and a second insulating layer that isolates the second bonding contact; the first bonding contact and the second bonding contact are bonded, and the first insulating layer and the second insulating layer are bonded.

[0012] According to one aspect of this disclosure, a storage system is provided, comprising: a semiconductor device as described in the above embodiments of this disclosure; and a memory controller connected to the semiconductor device and configured to control the semiconductor device.

[0013] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a first semiconductor structure, the first semiconductor structure including a first bonding layer, a peripheral circuit layer containing logic circuitry, and an interconnect layer; forming a second semiconductor structure, the second semiconductor structure including a memory array layer containing DRAM memory cells and a second bonding layer; and bonding the first bonding layer to the second bonding layer; wherein the method further comprises: forming a first interconnect structure between the first bonding layer and the logic circuitry; forming a contact structure penetrating the semiconductor layer containing the logic circuitry; and forming a second interconnect structure and pads in the interconnect layer, and connecting the logic circuitry to the pads through the first interconnect structure, the contact structure, and the second interconnect structure.

[0014] In some embodiments, forming a first interconnect structure between the first bonding layer and the logic circuit includes: forming a first connection structure extending along a first direction between the first bonding layer and the logic circuit, and at least one first metal layer extending along a second direction and / or a third direction, such that the at least one first metal layer and a plurality of the first connection structures are alternately arranged along the first direction; the first direction is the stacking direction of the first semiconductor structure and the second semiconductor structure; the second direction intersects with the third direction and is perpendicular to the first direction.

[0015] In some embodiments, the method further includes: forming a decoding circuit, a driving circuit, an amplification circuit, and a horizontal hammer refresh circuit in the peripheral circuit layer to form the logic circuit; and forming multiple layers of the first metal layer, such that the decoding circuit, the driving circuit, the sensing amplification circuit, and the horizontal hammer refresh circuit are respectively connected to different first metal layers.

[0016] In some embodiments, forming a second interconnect structure in the interconnect layer includes: forming a plurality of second connection structures extending along the first direction in the interconnect layer, and at least one second metal layer extending along the second direction and / or the third direction, such that the at least one second metal layer and the plurality of second connection structures are alternately arranged along the first direction.

[0017] In some embodiments, forming a contact structure penetrating the semiconductor layer containing the logic circuit includes: forming a plurality of contact structures penetrating the semiconductor layer containing the logic circuit, wherein the plurality of contact structures are spaced apart in the second direction and / or the third direction upward.

[0018] In some embodiments, forming a contact structure penetrating the semiconductor layer containing the logic circuit includes: forming a via penetrating the semiconductor layer containing the logic circuit along the first direction; forming a dielectric layer on the sidewall of the via; and forming a contact structure in the via in which the dielectric layer is formed.

[0019] In some embodiments, bonding the second bonding layer to the first bonding layer includes: forming a first bonding contact and a first insulating layer that isolates the first bonding contact in the first bonding layer; forming a second bonding contact and a second insulating layer that isolates the second bonding contact in the second bonding layer; and bonding the first bonding contact and the second bonding contact, and bonding the first insulating layer and the second insulating layer, so that the first bonding layer is bonded to the second bonding layer.

[0020] In this embodiment, the peripheral circuit layer and the memory array layer are bonded together via a bonding layer. Pads are provided on the side of the peripheral circuit layer furthest from the memory array layer on both sides. A first interconnect structure and a contact structure are provided in the peripheral circuit layer, and a second interconnect structure is provided in the interconnect layer on the side of the peripheral circuit layer furthest from the memory array layer on both sides. This allows the logic circuit located in the peripheral circuit layer to be connected to the pads via the first interconnect structure, the contact structure, and the second interconnect structure, thereby achieving connection between the logic circuit and external devices. In other words, this configuration allows the connection structures (such as the first interconnect structure, the contact structure, and the second interconnect structure) used to connect the logic circuit to external devices to avoid penetrating the memory array layer during signal communication. Instead, the signal is led out through the connection structure in a direction away from the memory array layer, avoiding the winding effect between the connection structure and the bonding contacts in the bonding layer. This saves winding resources for the bonding contacts, reduces process difficulty, improves device reliability, and can further reduce device size and increase memory density. Attached Figure Description

[0021] Figure 1 A schematic block diagram of an exemplary electronic device provided in an embodiment of this disclosure;

[0022] Figure 2 A schematic diagram illustrating the composition of an exemplary electronic device provided in an embodiment of this disclosure;

[0023] Figure 3 This is a schematic block diagram illustrating the composition of an exemplary solid-state drive provided in an embodiment of the present disclosure;

[0024] Figure 4 A schematic block diagram illustrating the composition of an exemplary memory according to an embodiment of this disclosure;

[0025] Figure 5 A schematic diagram of the structure of a dynamic random access memory provided in an embodiment of this disclosure;

[0026] Figure 6 A top view of a bonding contact and a metal layer provided in an embodiment of this disclosure;

[0027] Figure 7 A cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0028] Figure 8 A three-dimensional schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0029] Figure 9 for Figure 8 A schematic cross-sectional view of the semiconductor device in the XZ plane is shown.

[0030] Figure 10 A top view of a first metal layer located on the back side of a first semiconductor structure in the XY plane, provided as an embodiment of this disclosure;

[0031] Figure 11 A schematic flowchart of a semiconductor device manufacturing method provided in this disclosure embodiment;

[0032] Figures 12 to 14 This is a schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure.

[0033] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0034] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0035] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0036] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0037] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0040] The semiconductor devices disclosed herein are at least a portion of those to be used in subsequent processes to form the final device structure. Here, the final device may include memory, including but not limited to Dynamic Random Access Memory (DRAM). The following description uses DRAM as an example only. However, it should be noted that the following descriptions of DRAM are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0041] Figure 1 A schematic block diagram of an exemplary electronic device according to an embodiment of the present disclosure is shown. The electronic device 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, electronic device 1 may include a host 10 and a storage system 20. The storage system 20 includes a memory controller 30 and one or more memory devices 40. The host 10 may be a processor of the electronic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The host 10 may be configured to send data to or receive data from the memory device 40. The memory controller 30 is coupled to the memory device 40 and the host 10 and is configured to control the memory device 40. The memory controller 30 may manage the data stored in the memory device 40 and communicate with the host 10.

[0042] The memory controller 30 can be configured to control the operation of the memory device 40, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 30 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory device 40. The memory controller 30 can also perform any other suitable functions, such as formatting the memory device 40.

[0043] In some specific embodiments, the memory controller 30 and one or more memory devices 40 can be integrated into various types of electronic devices. For example, the memory controller 30 can be integrated into the northbridge chipset of a computer motherboard or directly into the computer CPU; multiple memory devices 40 can be integrated into a memory module. In other words, the storage system 20 can be implemented and packaged into different types of terminal electronic products.

[0044] The memory controller 30 can send data to / receive data from the host 10, and can send commands (CMD) and addresses (ADDR) to the memory device 40. The memory controller 30 may include a command generator 11, an address generator 12, a device interface 13, and a host interface 14. The host interface 14 can receive commands (CMD) and addresses (ADDR) from the host 10. The command generator 11 can generate access commands by decoding the commands (CMD) received from the host 10, and can provide access commands to the memory device 40 through the device interface 13. The access command may be a signal instructing the memory device 40 to write or read data by accessing a row of the memory cell array 22 corresponding to the address (ADDR). The address generator 12 in the memory controller 30 can generate the row address and column address to be accessed in the memory cell array 22 by decoding the address (ADDR) received from the host interface 14. Furthermore, the memory device 40 can generate the address of the memory bank to be accessed when the memory cell array 22 includes multiple memory banks.

[0045] Furthermore, the memory controller 30 can control memory operations such as writing and reading by providing various signals to the memory device 40 via the device interface 13. For example, the memory controller 30 can provide a write command to the memory device 40. The write command is used to instruct the memory device 40 to perform a write operation to store data in the memory device 40.

[0046] In some embodiments, the memory device 40 includes a memory cell array 22 and peripheral circuitry 21. The memory cell array 22 includes multiple banks, each bank including multiple blocks, each block including multiple rows and columns of memory cells, each row of memory cells coupled to a corresponding word line, and each column of memory cells coupled to a corresponding bit line. The peripheral circuitry 21 can write data to or read data from the memory cell array 22 based on commands CMD and addresses ADDR received from the memory controller 30, or it can provide control signals CTRL to the row decoding and column decoding circuits for refreshing the memory cells included in the memory cell array 22. In other words, the peripheral circuitry 21 can perform all operations to process the data in the memory cell array 22. The peripheral circuit 21 may include: control circuits corresponding to each memory bank, such as a sense amplifier circuit and a word-line driver (WLD) circuit, control circuits corresponding to each memory bank, such as a row decoding circuit and a column decoding circuit, and control circuits corresponding to all memory banks, such as a command buffer, a command decoder, an address buffer, an input / output buffer, and a mode register.

[0047] The memory device 40 can be random access memory (RAM), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, etc. The following explanation uses DRAM as an example only.

[0048] Figure 2 A schematic diagram of the composition of an exemplary electronic device according to an embodiment of the present disclosure is shown. In some specific embodiments, the DRAM may be a structure outside the storage system 20, which may be directly connected to the host 10 to serve as main memory during the operation of the host 10. It may also be connected to the storage system 20 to be used as a buffer memory. In other specific embodiments, the DRAM may also be part of a controller within the storage system 20, such as a DRAM controller, for controlling the memory device 40 to perform operations such as writing and reading. In still other embodiments, a plurality of DRAM stacks may be applied to a high-bandwidth memory (HBM) architecture for use as a storage medium.

[0049] For example, refer to Figure 3 , Figure 3 This is a schematic block diagram illustrating the composition of an exemplary solid-state drive (SSD) according to an embodiment of this disclosure. Here, SSD can be understood as the aforementioned... Figure 1 and Figure 2 One type of storage system 20, in this example, DRAM can be used as a buffer memory.

[0050] like Figure 3As shown, SSD 50 may include SSD controller 51, buffer memory 52, and non-volatile memory 53. SSD controller 51 provides the physical connection between host 10 and SSD 50. That is, SSD controller 51 can provide an interface between host 10 and SSD 50 according to the bus format of host 10. SSD controller 51 can decode instructions provided from host 10. SSD controller 51 can access non-volatile memory 53 based on the decoding result. Buffer memory 52 can temporarily store write data provided from host 10 or data read from non-volatile memory 53. When host 10 issues a read request, if the data present in non-volatile memory 53 is cached, buffer memory 52 can support caching functionality for directly providing cached data to the host. The data transfer rate through the host's bus format (e.g., SATA or SAS) is much higher than the data transfer rate of the SSD 50's memory channel. That is, when the host's interface speed is significantly higher, the performance degradation caused by the speed difference can be minimized by providing a high-capacity buffer memory 52. Additionally, buffer memory 52 may store the address mapping table of non-volatile memory 53. Buffer memory 52 may include, but is not limited to, DRAM. Non-volatile memory 53 may be configured as a storage medium for SSD 50. Non-volatile memory 53 may include, but is not limited to, NAND flash memory.

[0051] Figure 4 This is a schematic block diagram illustrating the composition of an exemplary memory according to an embodiment of the present disclosure. Here, memory can be understood as the aforementioned... Figure 1 and Figure 2 One type of storage system 20, in this example, DRAM can be used as a storage medium.

[0052] like Figure 4 As shown, memory 60 can be easily attached to or installed in an electronic device or removed from electronic setup 1 via the illustrated interface. Memory 60 may include a plurality of volatile memories 62 (e.g., DRAM) and a memory controller 61. Memory 60 can be used to write data, store data, retrieve (or read) data, and / or erase data under the control of a computer's processor. In some embodiments, memory controller 61 may communicate with DRAM using at least one communication protocol or technology standard typically associated with, for example, dual in-line memory modules (DIMMs), register-equipped DIMMs (RDIMMs), low-load DIMMs (LRDIMMs), and registerless DIMMs (UDIMMs).

[0053] It should be noted that, Figure 3 Medium buffer memory 52 and Figure 4 62 medium volatile memory are all Figure 1 or Figure 2One application scenario of the memory device 40.

[0054] With the development of dynamic random access memory technology, the size of DRAM memory cells is getting smaller and smaller, and their array architecture has evolved from 8F... 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements of dynamic random access memory for ions and leakage current, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0055] In some embodiments of this disclosure, whether planar transistors or buried transistors, the dynamic random access memory is composed of multiple DRAM memory cells. Each DRAM memory cell consists of a transistor and a capacitor controlled by the transistor. That is, the dynamic random access memory includes a (1T1C) architecture of 1 transistor and 1 capacitor. Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0056] The following is combined with Figure 5 One architecture of dynamic random access memory is described in detail. In the introduction... Figure 5 Before illustrating the semiconductor device, we first define the various directions that may be used in the following description. The extension direction of the semiconductor body is defined as the first direction (i.e., the Z-axis direction). In a plane perpendicular to the Z-axis direction, we define the intersecting second direction (i.e., the X-axis direction) and the third direction (i.e., the Y-axis direction). In some embodiments, the X-axis direction, the Y-axis direction, and the Z-axis direction can be mutually perpendicular.

[0057] refer to Figure 5 , Figure 5 This is a cross-sectional view of a three-dimensional (3D) dynamic random access memory 100 including vertical transistors provided in an embodiment of this disclosure; as shown... Figure 5As shown, the dynamic random access memory 100 includes a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102 along the Z-axis direction. The first semiconductor structure 102 and the second semiconductor structure 104 are connected through a bonding interface 106. The first semiconductor structure 102 and the second semiconductor structure 104 can be connected by hybrid bonding or other methods. In some embodiments, the second semiconductor structure 104 can be bonded to the top of the first semiconductor structure 102 in a face-to-face manner at the bonding interface 106.

[0058] The first semiconductor structure 102 may include a first substrate 1010, a peripheral circuit 1012 located on one side of the first substrate 1010, and a first interconnect layer 1016 located on the side of the peripheral circuit 1012 away from the first substrate 1010. The first interconnect layer 1016 is used to transmit electrical signals of the peripheral circuit 1012. The peripheral circuit 1012 may include a plurality of transistors 1014. In some embodiments, trench isolation (such as shallow trench isolation, STI) and doped regions (such as the well, source, and drain of the transistor 1014) may also be formed on or in the first substrate 1010.

[0059] The first semiconductor structure 102 may further include a first bonding layer 1018 located at the bonding interface 106 and on the side of the first interconnect layer 1016 away from the peripheral circuit 1012. The first bonding layer 1018 may include a plurality of first bonding contacts 1019 and a dielectric material electrically isolating the first bonding contacts 1019. The first bonding contacts 1019 in the first bonding layer 1018 and the surrounding dielectric material can be used for mixed bonding. Conversely, the second semiconductor structure 104 may also include a second bonding layer 1020 located at the bonding interface 106 and on the side of the first bonding layer 1018 away from the first interconnect layer 1016. The second bonding layer 1020 may include a plurality of second bonding contacts 1021 and a dielectric material electrically isolating the second bonding contacts 1021. The second bonding contacts 1021 in the second bonding layer 1020 and the surrounding dielectric material can be used for mixed bonding. Here, the second bonding contact 1021 contacts the first bonding contact 1019 at the bonding interface 106.

[0060] In some embodiments, the peripheral circuitry 1012 may further include word lines (WL) and word line drivers / row decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. In other embodiments, the peripheral circuitry 1012 may further include bit lines 1023 (BL) and bit line drivers / column decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. Here, the second interconnect layer 1022 includes bit lines 1023 above the second bonding layer 1020, and the bit lines 1023 are used to transmit electrical signals.

[0061] In other embodiments, the stacked first semiconductor structure 102 and the second semiconductor structure 104 may not be connected by bonding, but rather integrated on the same substrate (only the first substrate, no second substrate), and directly connected through one or more interconnect layers between the first semiconductor structure 102 and the second semiconductor structure 104. In this case, the first semiconductor structure 102 does not have a first bonding layer 1018 and a first bonding contact 1019; the second semiconductor structure 104 does not have a second bonding layer 1020 and a second bonding contact 1021; and the bonding interface 106 between the first semiconductor structure 102 and the second semiconductor structure 104 also does not exist.

[0062] refer to Figure 5 The second semiconductor structure 104 also includes a memory cell array 1024 located on the second interconnect layer 1022. The memory cell array 1024 may include a plurality of memory cells, a second substrate 1048 located on the memory cell array 1024, and a third interconnect layer 1050 located on the second substrate 1048. Figure 5 The cross section of the dynamic random access memory 100 can be cut along the bit line direction (X-axis direction), and a bit line 1023 in the second interconnect layer 1022 extending laterally in the X-axis direction can be coupled to a column of memory cells.

[0063] Here, each memory cell may include a vertical transistor 1026 and a capacitor structure 1028 coupled to the vertical transistor 1026; the vertical transistor 1026 includes a semiconductor body 1030 extending vertically (in the Z-axis direction) and a gate structure 1036 contacting one side of the semiconductor body 1030 in the bit line direction (X-axis direction); in other embodiments, the gate structure may also completely surround the semiconductor body, partially surround the semiconductor body, or be located on two opposite sides of the semiconductor body, etc., which will not be elaborated here. Here, the gate structure 1036 includes a gate electrode 1034 and a gate dielectric 1032 located between the gate electrode 1034 and the semiconductor body 1030 in the bit line direction (X-axis direction). In some embodiments, the gate dielectric 1032 is adjacent to one side of the semiconductor body 1030, and the gate electrode 1034 is adjacent to the gate dielectric 1032.

[0064] In some embodiments, the semiconductor body 1030 has two ends (an upper end and a lower end) in the vertical direction (Z-axis direction), and one end (such as...) Figure 5 The lower end of the semiconductor body 1030 extends in the vertical direction (Z-axis direction) beyond the gate dielectric 1032 into the interlayer dielectric (ILD) layer, while the other end of the semiconductor body 1030 (such as...) Figure 5 The upper end of the semiconductor body 1030 is flush with the corresponding end of the gate dielectric 1032. In other embodiments, the two ends (upper and lower) of the semiconductor body 1030 extend in the vertical direction (Z-axis direction) beyond the gate electrode 1034 into the ILD layer. In other words, the semiconductor body 1030 may have a larger vertical dimension than the vertical dimension (e.g., depth in the Z-axis direction) of the gate electrode 1034, and neither the upper nor lower end of the semiconductor body 1030 is flush with the corresponding end of the gate electrode 1034. This avoids short circuits between the bit line 1023 and the gate electrode 1034 or between the gate electrode 1034 and the capacitor structure 1028.

[0065] The vertical transistor 1026 may further include a source 1038 and a drain 1040 respectively disposed at two ends (upper end and lower end) of the semiconductor body 1030 in the vertical direction (Z-axis direction). (The positions of the source and drain can be interchanged; here and below, the upper end is the source 1038 and the lower end is the drain 1040 as an example.) In some embodiments, the source 1038 is coupled to the capacitor structure 1028, and the drain 1040 is coupled to the bit line 1023.

[0066] Since the gate electrode 1034 can be a portion of a word line or extend as a word line in the word line direction, the second semiconductor structure 104 of the dynamic random access memory 100 can also include multiple word lines, each extending in the word line direction (Y-axis direction). Here, each word line can be coupled to a row of memory cells.

[0067] Vertical transistor 1026 extends vertically through and contacts the word line, and its drain 1040 at its lower end contacts the bit line 1023. Therefore, due to the vertical arrangement of the vertical transistor 1026, the word line and bit line 1023 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line and bit line 1023. Here, the vertical transistor 1026 can be arranged in a mirror-symmetric manner to increase the density of memory cells in the bit line direction (X-axis direction). Two adjacent vertical transistors 1026 in the bit line direction are mirror-symmetric with respect to trench isolation 1060; that is, the second semiconductor structure 104 may include a plurality of trench isolations 1060, each trench isolation 1060 extending parallel to the word line in the word line direction (Y-axis direction) and disposed between the semiconductor bodies 1030 of two adjacent rows of vertical transistors 1026. In some embodiments, rows of vertical transistors 1026 separated by trench isolations 1060 are mirror-symmetric with respect to trench isolations 1060. It should be understood that the trench isolation 1060 may include air gaps, each air gap being laterally disposed between adjacent semiconductor bodies 1030. The second semiconductor structure 104 also includes a plurality of gate isolations 1062, each gate isolation 1062 extending parallel to the word line in the word line direction (Y-axis direction) and disposed between word lines of two adjacent rows of vertical transistors 1026. It should be understood that the dimensions of the gate isolations 1062 and word lines in the bit line direction (X-axis direction) may be the same as or different from the dimensions of the trench isolation 1060 in the bit line direction (X-axis direction); when their dimensions in the bit line direction (X-axis direction) are different, the spacing between the plurality of semiconductor bodies 1030 arranged along the bit line direction (X-axis direction) is different, that is, the plurality of semiconductor bodies 1030 arranged along the bit line direction (X-axis direction) are non-uniformly arranged.

[0068] like Figure 5 As shown, capacitor structure 1028 can be a vertical capacitor. In some embodiments, a conductive structure 1064 is formed between the vertical transistor 1026 (further, for example, source 1038) and capacitor structure 1028 to reduce contact resistance.

[0069] like Figure 5As shown, the second semiconductor structure 104 may further include capacitor contacts 1047 that contact the common plate of the capacitor structure 1028 for coupling the capacitor structure 1028 to the peripheral circuit 1012 or directly to ground. In some embodiments, the ILD layer forming the capacitor structure 1028 has the same dielectric material, such as silicon oxide, as the two ILD layers into which the semiconductor body 1030 extends. The construction of the capacitor structure 1028 may include any suitable structure and construction, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-planar capacitor.

[0070] like Figure 5 As shown, the vertical transistor 1026 extends vertically through and contacts the word line. The drain 1040 at its lower end contacts the bit line 1023, and the source 1038 at its upper end contacts the capacitor structure 1028. That is, due to the vertical arrangement of the vertical transistor 1026, the bit line 1023 and the capacitor structure 1028 can be arranged in different planes in the vertical direction and coupled vertically to opposite ends of the vertical transistor 1026 of the memory cell. In some embodiments, the bit line 1023 and the capacitor structure 1028 are arranged on opposite sides of the vertical transistor 1026 in the vertical direction. Compared to conventional memory cells where the bit line and capacitor structure are arranged on the same side of a planar transistor, this simplifies the wiring of the bit line 1023 and reduces the coupling capacitance between the bit line 1023 and the capacitor structure 1028.

[0071] In some embodiments, the vertical transistor 1026 is vertically disposed between the capacitor structure 1028 and the bonding interface 106. That is, the vertical transistor 1026 can be arranged closer to the peripheral circuitry 1012 / bonding interface 106 of the first semiconductor structure 102 than the capacitor structure 1028. Since the bit line 1023 and the capacitor structure 1028 are coupled to opposite ends of the vertical transistor 1026, the bit line 1023 (as part of the second interconnect layer 1022) is vertically disposed between the vertical transistor 1026 and the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0072] In some embodiments, the second semiconductor structure 104 further includes a second substrate 1048 disposed above the memory cell array 1024, and a third interconnect layer 1050 with pads disposed above the memory cell array 1024. The third interconnect layer 1050 with pads may include interconnects in one or more ILD layers, such as contact pads 1054.

[0073] In some embodiments, the second semiconductor structure 104 further includes one or more contacts 1052 extending through pads to lead out the third interconnect layer 1050 and the second substrate 1048, so as to lead out the third interconnect layer 1050 through the pads and couple to the memory cell and the second interconnect layer 1022. Thus, the peripheral circuit 1012 can be coupled to the memory cell through the first interconnect layer 1016 and the second interconnect layer 1022, as well as the second bonding layer 1020 and the first bonding layer 1018, and the peripheral circuit 1012 and the memory cell array 1024 can be led out through the contacts 1052 and the pads to the third interconnect layer 1050 and coupled to external circuitry.

[0074] However, with the development of semiconductor technology, the storage density of memory is gradually increasing, the number of first and second bonding contacts is gradually increasing, and the number of metal layers used to couple peripheral circuits to the pads is also gradually increasing. This makes the wiring between the bonding contacts and the metal layers more complex. In other words, the wiring channel resources between the two are affected. Under these circumstances, the area saved in the memory cell array by stacking cannot be effectively utilized.

[0075] For example, refer to Figure 6 , Figure 6 This is a top view of the bonding contacts and the metal layer; where... Figure 6 The bonding contact 201 shown can be a top view of the first bonding contact and the second bonding contact in the above embodiments on the XY plane; as shown Figure 6 As shown, both the metal layer 202 extending along the X-axis and the metal layer 203 extending along the Y-axis need to bypass the bonding contact 201, which makes the winding resources of the metal layers limited and more complex.

[0076] It should be noted that the metal layer 202 extending along the X-axis and the metal layer 203 extending along the Y-axis can be connected to the same circuit or to different circuits. When they are connected to the same circuit, i.e., when they transmit the same electrical signals, at least one end of them is connected, and their heights in the Z-axis direction can be the same. When they are connected to different circuits, i.e., when they transmit different electrical signals, they need to be electrically isolated; for example, they can achieve electrical isolation by having different heights in the Z-axis direction. In other words, the memory can achieve the transmission of electrical signals between different circuits by setting multiple metal layers at different heights in the Z-axis direction and connecting these multiple metal layers to different circuits.

[0077] However, while increasing the number of metal layers in the Z-axis direction enables the transmission of electrical signals for more circuits, the efficiency is low due to limitations in the bonding contacts. This, in turn, makes the requirements for metal pitch and sheet resistance more stringent in the areas where the metal layers are located, increasing the manufacturing complexity. Furthermore, with advancements in process technology, the size of some components, such as sense amplifier circuits (SA) and word line driver circuits (WL Drv), will further decrease, leading to an increase in the density of bonding contacts. This results in a larger free area within the memory block, placing even higher demands on the spacing and sheet resistance between metal layers, making the effect of process technology improvements on reducing the overall memory die size less significant.

[0078] In view of the above, and based on one or more of the aforementioned problems, this disclosure provides a semiconductor device comprising: a first semiconductor structure and a second semiconductor structure; the first semiconductor structure comprising a first bonding layer, a peripheral circuit layer containing logic circuits, and an interconnect layer; the second semiconductor structure comprising a memory cell layer containing DRAM memory cells and a second bonding layer; the second bonding layer being bonded to the first bonding layer; wherein the first semiconductor structure further comprises: a first interconnect structure located between the logic circuits and the first bonding layer; a contact structure penetrating the semiconductor layer containing the logic circuits; and a second interconnect structure and a pad located in the interconnect layer; the logic circuits being connected to the pads through the first interconnect structure, the contact structure, and the second interconnect structure.

[0079] Thus, by setting pads on the side of the peripheral circuit layer furthest from the memory array layer on opposite sides, and by setting a first interconnect structure, a contact structure in the peripheral circuit layer, and a second interconnect structure in the interconnect layer on the side of the peripheral circuit layer furthest from the memory array layer on opposite sides, the logic circuit located in the peripheral circuit layer is connected to the pads through the first interconnect structure, the contact structure, and the second interconnect structure, thereby realizing the connection between the logic circuit and external devices. In other words, this configuration allows the connection structures (such as the first interconnect structure, the contact structure, and the second interconnect structure) used to connect the logic circuit to external devices to avoid penetrating the memory array layer during signal communication between the logic circuit and external devices. Instead, the signal is led out through the connection structure in a direction away from the memory array layer, avoiding the winding effect between the connection structure and the bonding contacts in the bonding layer, saving the winding resources of the bonding contacts, reducing the process difficulty, improving device reliability, and further reducing device size and increasing memory density.

[0080] The specific structure of the semiconductor device described above will be described in detail below with reference to the accompanying drawings. In the following description, the first direction is the Z-axis direction, and the second direction intersects with the third direction and is perpendicular to the first direction. For example, the second direction is the X-axis direction, and the third direction is the Y-axis direction; the X-axis, Y-axis, and Z-axis directions can be mutually perpendicular.

[0081] refer to Figure 7 , Figure 7 A schematic cross-sectional view of a semiconductor device 300 in the XZ plane is shown. The semiconductor device 300 includes a first semiconductor structure 301 and a second semiconductor structure 302, which are stacked along the Z-axis. It should be understood that... Figure 7 The example shows a second semiconductor structure 302 located above a first semiconductor structure 301. In other embodiments, the first semiconductor structure 301 may also be located above the second semiconductor structure 302.

[0082] Here, the first semiconductor structure 301 includes a first bonding layer 3012, a peripheral circuit layer 3014, and an interconnect layer 3016 stacked sequentially along the Z-axis; the second semiconductor structure 302 includes a second bonding layer 3022 and a memory array layer 3024 stacked along the Z-axis, the memory array layer 3024 including DRAM memory cells 4080. Here, the DRAM memory cell 4080 includes a transistor 4081 and a capacitor structure 4082; in other embodiments, the DRAM memory cell may also be other architectures, such as 2TOC, etc., which are not limited in this disclosure.

[0083] The first semiconductor structure 301 and the second semiconductor structure 302 are bonded together via a bonding interface 401. Specifically, the first bonding layer 3012 may include a first bonding contact 4011 and a first insulating layer 4012 that isolates the first bonding contact 4011; the second bonding layer 3022 may include a second bonding contact 4021 and a second insulating layer 4022 that isolates the second bonding contact 4021; the first bonding contact 4011 and the second bonding contact 4021 are joined, and the first insulating layer 4012 and the second insulating layer 4022 are joined, so that the first bonding layer 3012 and the second bonding layer 3022 are bonded together and a bonding interface 401 is formed at the bonding point. The first bonding contact 4011 and the second bonding contact 4021 are composed of conductive materials. Here, the conductive material can be one of the following: metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride (TiN), tantalum nitride, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0084] Continue to refer to Figure 7 The peripheral circuit layer 3014 includes a semiconductor layer 4013, the constituent material of which is not limited to silicon (Si). At least a portion of the logic circuit 4014 is formed in the semiconductor layer 4013; for example, the logic circuit 4014 may include a decoding circuit, a driving circuit, a sensing amplification circuit, and a horizontal hammer refresh circuit, etc.

[0085] The peripheral circuit layer 3014 also includes a first interconnect structure 4015 and a contact structure 4016. The first interconnect structure 4015 is located between the logic circuit 4014 and the first bonding layer 3012, and the contact structure 4016 penetrates the semiconductor layer 4013 along the Z-axis. One end of the first interconnect structure 4015 is connected to the logic circuit 4014, and the other end is connected to the contact structure 4016. In this way, the electrical signals of the logic circuit 4014 can be led out from the front side (the side closer to the second semiconductor structure) of the logic circuit 4014 and transmitted to the back side (the side away from the second semiconductor structure) of the logic circuit 4014. Here, the first interconnect structure 4015 and the contact structure 4016 are made of conductive materials.

[0086] In some embodiments, reference Figure 7 The first interconnect structure 4015 includes multiple first connection structures 501 extending along the Z-axis direction and at least one first metal layer 502 extending along a direction perpendicular to the Z-axis direction (such as the X-axis direction and / or the Y-axis direction). The first connection structures 501 are connected to the first metal layer 502, and the multiple first metal layers 502 and the multiple first connection structures 501 are arranged alternately along the Z-axis direction. Multiple first connection structures 501 can also be provided between two adjacent first metal layers 502. The shapes of the first connection structures 501 and the first metal layers 502 can be selected according to actual needs. Both the first connection structures 501 and the first metal layers 502 are used for electrical signal transmission, and their constituent materials are all conductive materials.

[0087] In some embodiments, the logic circuit may include multiple different circuits, such as a decoding circuit, a driving circuit, a sensing amplification circuit, and a horizontal hammer refresh circuit. The first interconnect structure 4015 includes multiple first metal layers 502. The decoding circuit, the driving circuit, the sensing amplification circuit, and the horizontal hammer refresh circuit may be connected to different first metal layers 502 respectively, so as to transmit different circuit signals to the pads through different first metal layers.

[0088] In some embodiments, the contact structure 4016 may extend to both ends along the Z-axis. Here, the first end of the contact structure 4016 is connected to the first metal layer 502 in the first interconnect structure; the second end of the contact structure 4016 is connected to the second interconnect structure 4018. However, it should be understood that in other embodiments, the first end of the contact structure 4016 may also be connected to the first connection structure 501 in the first interconnect structure.

[0089] In some embodiments, the number of contact structures 4016 may include multiple contact structures 4016; the multiple contact structures 4016 are arranged at intervals in a direction perpendicular to the Z-axis direction (such as the X-axis direction and / or the Y-axis direction). For example, the multiple contact structures 4016 may be arranged at intervals along the X-axis direction, or at intervals along the Y-axis direction, or arranged in an array along both the X-axis and Y-axis directions. It should be noted that the multiple first metal layers 502 can be connected to the same contact structure 4016 through the first connection structure 501, or they can be connected to different contact structures 4016.

[0090] In some embodiments, the first semiconductor structure further includes a dielectric layer 4017; the dielectric layer 4017 extends through the semiconductor layer 4013 along the Z-axis and surrounds the sidewall of the contact structure 4016 to isolate the contact structure 4016 from the semiconductor layer 4013 and prevent electrical short circuits. The dielectric layer 4017 is composed of an insulating material, such as silicon oxide (SiO2), silicon nitride (Si3N4), etc.

[0091] Continue to refer to Figure 7 An interconnect layer 3016 is provided on one side of the peripheral circuit layer 3014 away from the first bonding layer 3012 along the Z-axis. The interconnect layer 3016 is provided with a second interconnect structure 4018 and a pad 4019.

[0092] Here, the second interconnect structure 4018 includes multiple second connection structures 503 extending along the Z-axis direction and at least one second metal layer 504 extending in a direction perpendicular to the Z-axis direction. The second connection structures 503 are connected to the second metal layer 504, and the multiple second metal layers 504 and the multiple second connection structures 503 are arranged alternately along the Z-axis direction. Multiple second connection structures 503 can also be provided between two adjacent second metal layers 504. The shapes of the second connection structures 503 and the second metal layers 504 can be selected according to actual needs. Both the second connection structures 503 and the second metal layers 504 are used for electrical signal transmission, and their constituent materials are both conductive materials.

[0093] In some embodiments, when the number of second metal layers includes multiple layers, the arrangement of the multiple second metal layers and the multiple second connection structures can be selected and set according to actual needs. For example, refer to... Figure 8 and Figure 9, Figure 8 This is a three-dimensional schematic diagram of a semiconductor device; Figure 9 for Figure 8 The diagram shows a cross-sectional view of the semiconductor device in the XZ plane. The second connection structure includes a first sub-connection structure 503-1 and a second sub-connection structure 503-2. The second metal layer 504 includes a first second metal layer 504-1 and a second second metal layer 504-2. The first sub-connection structure 503-1, the first second metal layer 504-1, the second sub-connection structure 503-2, and the second second metal layer 504-2 are arranged sequentially along the Z-axis.

[0094] Similarly, in order to transmit electrical signals from different circuits, different second metal layers can be connected to different circuits through different contact structures, and different second connection structures can also be connected to different circuits through different contact structures. In this way, the parallelism of electrical signal transmission can be improved, thereby improving the operating performance of semiconductor devices.

[0095] refer to Figure 7 , Figure 8 and Figure 9 The second end of the contact structure 4016 is connected to the second metal layer 504 (such as the first second metal layer 504-2); in other embodiments, the second end of the contact structure 4016 may also be connected to the second connecting structure 503 (such as the second sub-connecting structure 503-2). The first end and the second end of the contact structure 4016 are the two opposite ends of the contact structure 4016 in the Z-axis direction.

[0096] Return to reference Figure 7 The pads 4019 in the interconnect layer 3016 are connected to the second interconnect structure 4018. Specifically, the pads 4019 are connected to the second connection structure 503 within the second interconnect structure. The pads 4019 can be used to enable electrical signal communication between logic circuits and external devices. In this embodiment, the number of pads 4019 can be one or more. The shape of the pads 4019 can be selected according to actual needs. The constituent materials of the pads 4019 include, but are not limited to, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), or other conductive composite materials.

[0097] In some specific embodiments, multiple second connection structures 503 can be connected to the same pad 4019 or to different pads 4019 respectively. In this way, the electrical signals of the logic circuit 4014 can be transmitted to the pads 4019 through the first metal layer 502, the first connection structure 501, the contact structure 4016, the second metal layer 504, and the second connection structure 507, thereby realizing the electrical signal communication between the logic circuit 4014 and external devices.

[0098] In some embodiments, reference Figure 7 , Figure 8 and Figure 9 Interconnect layer 3016 also includes a redistribution layer (RDL) 4040, located between the second interconnect structure 4018 and the pad 4019. The redistribution layer 4040 is used to redistribute I / O electrical signal connections, thereby achieving higher-density signal connections to meet the miniaturization requirements of high-performance computing and mobile devices. The redistribution layer 4040 may be composed of copper, aluminum, or other suitable conductive materials. It should be noted that... Figure 8 and Figure 9 The example only shows partial structures of the metal layer, connection structure, and redistribution layer. Figure 7 Some structures, such as pads and circuits, are not illustrated.

[0099] In some embodiments, reference Figure 7 The peripheral circuit layer 3014 also includes a third interconnect structure 4020. One end of the third interconnect structure 4020 is connected to the first bonding contact 4011, and the other end is connected to a portion of the peripheral circuitry. The memory array layer 3024 includes a fourth interconnect structure 4030. One end of the fourth interconnect structure 4030 is connected to the second bonding contact 4021, and the other end is connected to the DRAM memory cell 4080 via a bit line 4060. This connection enables electrical connection between a portion of the peripheral circuitry and the DRAM memory cell 4080.

[0100] For example, in conjunction with the reference Figure 8 and Figure 9 The third interconnect structure 4020 includes interconnected third connection structures 601 and third metal layers 602. The number of third connection structures 601 may include one (see reference). Figure 8 ) or more (references) Figure 9 The third metal layer 602 may include one layer (see reference). Figure 8 ) or multiple layers (reference) Figure 9 In this configuration, multiple third connection structures 601 and multiple layers of third metal layers 602 are arranged alternately along the Z-axis. The constituent materials of the third connection structures 601 and the third metal layers 602 both include conductive materials.

[0101] It should be noted that the logic circuits connected by the third interconnect structure can be different from those connected by the first interconnect structure. For example, the logic circuits connected by the third interconnect structure are used to realize the internal signal interaction of the semiconductor device, while the logic circuits connected by the first interconnect structure are used to realize the signal interaction with external devices, thereby improving the operating performance and reliability of the semiconductor device.

[0102] In this embodiment, on the one hand, only the related wiring (e.g., the third interconnect structure) connected to the second bonding contact of the second semiconductor structure and short interconnects inside the device are retained on the front side of the first semiconductor structure (i.e., the side bonded to the second semiconductor structure), which can reduce the wiring difficulty between the first and second semiconductor structures; at the same time, it can also reduce the bit line coupling (BL Couple) generated between the first semiconductor structure and the bit line 4060, thereby improving the reliability of the semiconductor device. On the other hand, the first interconnect structure, the second interconnect structure, the contact structure, and the pad are provided on the back side of the first semiconductor structure to be used for long interconnects inside the device, such as global signals and power meshes. In this way, since there is no limitation on the wiring resources on the back side of the first semiconductor structure, the requirements for metal layer spacing and connection structure spacing can be reduced, thereby reducing the process difficulty and manufacturing cost. Furthermore, the increase in wiring resources inside the device makes it easier to make full use of the free area inside the device. As the process iterates towards smaller dimensions, the effect of reducing the die size of the semiconductor device becomes more obvious.

[0103] For example, refer to Figure 10 , Figure 10 This is a top view of a first metal layer on the back side of the first semiconductor structure in the XY plane, wherein the spacing of the metal layer 603 extending along the X-axis and the spacing of the metal layer 604 extending along the Y-axis have a higher degree of freedom in selection.

[0104] Based on the above-described semiconductor device, this disclosure also provides a method for manufacturing a semiconductor device. The semiconductor device includes a semiconductor structure, as shown in the reference... Figure 11 , Figure 11 This is a schematic flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure; the method includes:

[0105] Step S701: Form a first semiconductor structure, the first semiconductor structure including a first bonding layer, a peripheral circuit layer containing logic circuits, and an interconnect layer.

[0106] Step S702: Form a second semiconductor structure, the second semiconductor structure including a memory array layer containing DRAM memory cells and a second bonding layer.

[0107] Step S703: Bond the second bonding layer to the first bonding layer.

[0108] Step S704: A first interconnect structure is formed between the first bonding layer and the logic circuit; a contact structure is formed through the semiconductor layer where the logic circuit is located; and a second interconnect structure and a pad are formed in the interconnect layer, and the logic circuit is connected to the pad through the first interconnect structure, the contact structure and the second interconnect structure.

[0109] It should be understood that Figure 11 The steps shown are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Figure 11 The steps shown can be adjusted in order according to actual needs; for example, step S704 can be completed before step S703. The formation process of the semiconductor structure is described in detail below with reference to the accompanying drawings.

[0110] In some embodiments, steps S701 and S704 are performed, referring to Figure 12 A first semiconductor structure 800 is formed. The method includes: forming a first bonding layer 801, a peripheral circuit layer 802, and an interconnect layer 803 sequentially stacked along the Z-axis direction; and forming a first bonding contact 8011 and a first insulating layer 8012 isolating the first bonding contact 8011 in the first bonding layer 801. The constituent material of the first bonding contact 8011 includes a conductive material. The preparation method of the first bonding contact 8011 includes, but is not limited to, etching processes and deposition processes. Deposition processes include, but are not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0111] The method further includes: forming a semiconductor layer 8013 in the peripheral circuit layer 802, and forming at least a portion of a logic circuit 8014 in the semiconductor layer 8013. The semiconductor layer 8013 is composed of silicon. The logic circuit 8014 includes transistors. The method for forming transistors is well-established and will not be described in detail here. A first interconnect structure 8015 is formed in the peripheral circuit layer 802 and between the logic circuit 8014 and the first bonding layer 801.

[0112] In some embodiments, a first interconnect structure 8015 is formed between the first bonding layer 801 and the logic circuit 8014, including: forming a first connection structure 505 extending along the Z-axis direction between the first bonding layer and the logic circuit, and at least one first metal layer 506 extending along the X-axis direction and / or the Y-axis direction, such that the first connection structure 505 is connected to the first metal layer 506. When the first metal layer 506 comprises multiple layers, the multiple first metal layers 506 and the plurality of first connection structures 505 are alternately arranged along the Z-axis direction. It should be noted that the number of first connection structures 505 located between two first metal layers 506 may include one or more. Both the first connection structure 505 and the first metal layer 506 are used for electrical signal transmission, and their materials are both conductive materials. The first connection structure 505 may be formed, for example, using through silicon via (TSV) technology, wherein TSV technology includes etching processes, deposition processes, electroplating processes, chemical mechanical polishing (CMP) processes, etc. Here, the etching process includes, for example, deep reactive ion etching (DRIE). The first metal layer 506 can be formed, for example, by a deposition process.

[0113] In some embodiments, the method further includes: forming a decoding circuit, a driving circuit, an amplification circuit, and a horizontal hammer refresh circuit in the peripheral circuit layer 802 to form a logic circuit 8014; and forming multiple first metal layers 506, and connecting the decoding circuit, the driving circuit, the sensing amplification circuit, and the horizontal hammer refresh circuit to different first metal layers respectively, so as to realize the electrical signal transmission of different circuits, improve the parallelism of electrical signal transmission, and improve the operating performance of semiconductor devices.

[0114] In some embodiments, the method further includes: forming a plurality of contact structures 8016 penetrating the semiconductor layer containing the logic circuit, wherein the contact structures 8016 extend along the Z-axis direction, and the number of contact structures 8016 may include one or more; wherein the plurality of contact structures 8016 are spaced apart in the X-axis direction and / or the Y-axis direction. The constituent material of the contact structures 8016 includes conductive materials. Methods for forming the contact structures 8016 include, but are not limited to, etching processes, deposition processes, etc.

[0115] In some embodiments, a specific method for forming the contact structure 8016 may include: forming a via through the semiconductor layer 8013 containing the logic circuit along the Z-axis direction; forming a dielectric layer 8017 on the sidewall of the via; and forming the contact structure 8016 in the via where the dielectric layer 8017 is formed. This allows the dielectric layer 8017 to surround the sidewall of the contact structure 8016, isolating the contact structure 8016 from the semiconductor layer 8013 and preventing electrical short circuits. The dielectric layer 8017 is composed of an insulating material, such as silicon oxide (SiO2) or silicon nitride (Si3N4). Methods for forming the dielectric layer 8017 include, but are not limited to, deposition processes.

[0116] In some embodiments, the method further includes forming a second interconnect structure 8018 in the interconnect layer 803. The specific method for forming the second interconnect structure 8018 includes forming a plurality of second connection structures 507 extending along the Z-axis direction, and at least one second metal layer 508 extending along the X-axis direction and / or the Y-axis direction, connecting the second connection structures 507 to the second metal layer 508. Here, the second metal layer 508 may include multiple layers, and the multiple second metal layers 508 and the plurality of second connection structures 507 are alternately arranged along the Z-axis direction; the number of second connection structures 507 between two second metal layers 508 may include one or more, thereby improving the parallelism of signal transmission. The method for forming the second connection structure is the same as that for the first connection structure, and the method for forming the second metal layer is the same as that for the first metal layer.

[0117] In some embodiments, the method further includes forming a third interconnect structure 8020 in the peripheral circuit layer 802. One end of the third interconnect structure 8020 is connected to a logic circuit, and the other end is connected to a first bonding contact, for realizing an electrical connection between the logic circuit and the second semiconductor structure. It should be noted that the logic circuit connected to the third interconnect structure 8020 may be different from the logic circuit connected to the first interconnect structure 8015. For example, the third interconnect structure 8020 connects circuits in the logic circuit used for internal signal interaction within the semiconductor device, while the first interconnect structure 8015 connects circuits in the logic circuit used for signal interaction with external devices. This can improve the reliability and operational performance of the semiconductor device.

[0118] In some embodiments, the method further includes forming pads 8019 in the interconnect layer 803. This allows logic circuitry 8014 to be connected to pads 8019 via a first interconnect structure 8015, a contact structure 8016, and a second interconnect structure 8018, thereby enabling electrical signal connection between the logic circuitry and external devices.

[0119] In some embodiments, the method further includes forming a redistribution layer 8040 between the second interconnect structure 8018 and the pad 8019 in the interconnect layer 803. The redistribution layer 8040 is used to redistribute I / O electrical signal connections, thereby achieving higher-density signal connections to meet the miniaturization requirements of high-performance computing and mobile devices. The constituent materials of the redistribution layer 8040 may include copper or aluminum or other suitable conductive materials. The methods for forming the redistribution layer 8040 are well-established in related technologies and will not be elaborated upon here.

[0120] In some embodiments, step S702 is performed, referring to Figure 13 The method includes forming a second semiconductor structure 900. The method comprises forming a memory array layer 901 and a second bonding layer 902 stacked along the Z-axis direction.

[0121] The method specifically includes: forming a second bonding contact 9021 in a second bonding layer 902 and a second insulating layer 9022 to isolate the second bonding contact 9021. The number of second bonding contacts 9021 may include multiple contacts. The constituent material of the second bonding contact 9021 includes a conductive material. Methods for preparing the second bonding contact 9021 include, but are not limited to, etching processes and deposition processes.

[0122] In some embodiments, the method further includes forming a DRAM memory cell 9025 in the memory array layer 901, wherein the DRAM memory cell 9025 includes a transistor 9027 and a capacitor structure 9026; in other embodiments, the DRAM memory cell 9025 may also be other structures, such as 2TOC, etc. The method for forming the DRAM memory cell 9025 is relatively mature and will not be described in detail here.

[0123] In some embodiments, the method further includes: forming bit lines 9024 coupled to DRAM memory cells 9025 in the memory array layer 901, and forming a fourth interconnect structure 9023 connected to the bit lines 9024. The other end of the fourth interconnect structure 9023 is connected to a second bonding contact 9021.

[0124] In some embodiments, step S703 is performed, referring to Figure 14 The method involves bonding a first semiconductor structure 800 to a second semiconductor structure 900. This includes joining a first bonding contact 8011 and a second bonding contact 9021, and joining a first insulating layer 8012 and a second insulating layer 9022 to bond a first bonding layer 801 to a second bonding layer 902; wherein the first bonding layer 801 and the second bonding layer 902 form a bonding interface 903 at their bonding points.

[0125] This operation allows some circuits in the logic circuit to be connected to the DRAM memory cell through the third interconnect structure, while other circuits are connected to external devices through the first interconnect structure, contact structure, and second interconnect structure. On the one hand, the first interconnect structure, contact structure, and second interconnect structure do not need to penetrate the memory array layer, avoiding the influence of winding between them and the bonding contacts in the bonding layer, saving the winding resources of the bonding contacts, reducing the process difficulty, and improving the device reliability. On the other hand, it can also reduce the bit line coupling (BL couple) between the first semiconductor structure and the bit lines, improving the reliability of the semiconductor device. Furthermore, different transmission paths can be selected according to different circuits, improving the parallelism of signal transmission, while reducing the requirements for metal layer spacing and connection structure spacing, thereby reducing the process difficulty, reducing manufacturing costs, and improving device reliability. Moreover, the increase in winding resources inside the semiconductor device allows for full utilization of the idle area inside the device, thereby increasing the storage density.

[0126] According to one aspect of this disclosure, a storage system is provided, comprising: a semiconductor device as described in the above embodiments of this disclosure; and a memory controller connected to the semiconductor device and configured to control the semiconductor device.

[0127] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: The first semiconductor structure includes a first bonding layer, a peripheral circuit layer containing logic circuits, and an interconnect layer; The second semiconductor structure includes a memory array layer containing DRAM memory cells and a second bonding layer; The second bonding layer is bonded to the first bonding layer; The first semiconductor structure further includes: a first interconnect structure located between the logic circuit and the first bonding layer; a contact structure penetrating the semiconductor layer containing the logic circuit; and a second interconnect structure and a pad located in the interconnect layer; the logic circuit is connected to the pad through the first interconnect structure, the contact structure and the second interconnect structure.

2. The semiconductor device according to claim 1, characterized in that, The first interconnect structure includes a plurality of first connection structures extending along a first direction and at least one first metal layer extending along a second direction and / or a third direction; the at least one first metal layer and the plurality of first connection structures are alternately arranged along the first direction; the first direction is the stacking direction of the first semiconductor structure and the second semiconductor structure; the second direction intersects with the third direction and is perpendicular to the first direction.

3. The semiconductor device according to claim 2, characterized in that, The logic circuit includes a decoding circuit, a driving circuit, a sensing amplification circuit, and a horizontal hammer refresh circuit; the first interconnect structure includes multiple layers of the first metal layer; The decoding circuit, the driving circuit, the sensing amplification circuit, and the horizontal hammer refresh circuit are respectively connected to different first metal layers.

4. The semiconductor device according to claim 2, characterized in that, The second interconnect structure includes a plurality of second connection structures extending along the first direction and at least one second metal layer extending along the second direction and / or the third direction; the at least one second metal layer and the plurality of second connection structures are arranged alternately along the first direction.

5. The semiconductor device according to claim 4, characterized in that, The number of contact structures includes multiple ones; the multiple contact structures are arranged at intervals in the second direction and / or the third direction upward.

6. The semiconductor device according to claim 5, characterized in that, The materials comprising the pads, the first connection structure, the second connection structure, the first metal layer, the second metal layer, and the contact structure all include conductive materials.

7. The semiconductor device according to claim 5, characterized in that, A plurality of the second connection structures, spaced apart along the second direction and / or the third direction, are connected to the same pad.

8. The semiconductor device according to claim 7, characterized in that, The first semiconductor structure further includes a dielectric layer; the dielectric layer extends through the semiconductor layer along the first direction and surrounds the sidewall of the contact structure.

9. The semiconductor device according to claim 1, characterized in that, The first bonding layer includes a first bonding contact and a first insulating layer that isolates the first bonding contact; the second bonding layer includes a second bonding contact and a second insulating layer that isolates the second bonding contact; the first bonding contact and the second bonding contact are bonded, and the first insulating layer and the second insulating layer are bonded.

10. A storage system, characterized in that, include: The semiconductor device as described in any one of claims 1-9; And a memory controller, connected to the semiconductor device and used to control the semiconductor device.

11. A method for manufacturing a semiconductor device, characterized in that, The method includes: A first semiconductor structure is formed, the first semiconductor structure including a first bonding layer, a peripheral circuit layer containing logic circuits, and an interconnect layer; A second semiconductor structure is formed, the second semiconductor structure including a memory array layer containing DRAM memory cells and a second bonding layer; The first bonding layer is bonded to the second bonding layer; The method further includes: forming a first interconnect structure between the first bonding layer and the logic circuit; forming a contact structure through the semiconductor layer containing the logic circuit; and forming a second interconnect structure and a pad in the interconnect layer, such that the logic circuit is connected to the pad through the first interconnect structure, the contact structure and the second interconnect structure.

12. The manufacturing method according to claim 11, characterized in that, The step of forming a first interconnect structure between the first bonding layer and the logic circuit includes: A first connection structure extending along a first direction is formed between the first bonding layer and the logic circuit, and at least one first metal layer extending along a second direction and / or a third direction, such that at least one first metal layer and a plurality of first connection structures are alternately arranged along the first direction; the first direction is the stacking direction of the first semiconductor structure and the second semiconductor structure; the second direction intersects with the third direction and is perpendicular to the first direction.

13. The manufacturing method according to claim 12, characterized in that, The method further includes: A decoding circuit, a driving circuit, a sensing amplification circuit, and a horizontal hammer refresh circuit are formed in the peripheral circuit layer to form the logic circuit; and, Multiple layers of the first metal layer are formed, and the decoding circuit, the driving circuit, the sensing amplification circuit and the horizontal hammer refresh circuit are respectively connected to different layers of the first metal layer.

14. The manufacturing method according to claim 12, characterized in that, The formation of the second interconnect structure in the interconnect layer includes: A plurality of second connection structures extending along the first direction are formed in the interconnect layer, and at least one second metal layer extends along the second direction and / or the third direction, such that the at least one second metal layer and the plurality of second connection structures are alternately arranged along the first direction.

15. The manufacturing method according to claim 12, characterized in that, The contact structure forming the semiconductor layer through which the logic circuit is located includes: Multiple contact structures are formed through the semiconductor layer where the logic circuit is located, and the multiple contact structures are spaced apart in the second direction and / or the third direction upward.

16. The manufacturing method according to claim 15, characterized in that, The contact structure forming the semiconductor layer through which the logic circuit is located includes: Forming a via through the semiconductor layer containing the logic circuit along the first direction; A dielectric layer is formed on the sidewall of the through hole; A contact structure is formed in the through-hole in which the dielectric layer is formed.

17. The manufacturing method according to claim 11, characterized in that, The step of bonding the second bonding layer to the first bonding layer includes: A first bonding contact and a first insulating layer are formed in the first bonding layer to isolate the first bonding contact; A second bonding contact and a second insulating layer are formed in the second bonding layer to isolate the second bonding contact; The first bonding contact and the second bonding contact are joined, and the first insulating layer and the second insulating layer are joined, so that the first bonding layer and the second bonding layer are bonded together.

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