Semiconductor device and method of manufacturing the same, electronic device

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and an electronic device. The manufacturing method of the semiconductor device comprises: manufacturing an initial stack structure on a substrate; forming a first via, a second via and a trench distributed in sequence; replacing the multilayer initial sacrificial layer on both sides of the trench with a multilayer bit line; replacing the multilayer initial insulating layer around the second via with a multilayer first sacrificial layer; removing the multilayer first sacrificial layer to form a multilayer first channel; forming a semiconductor layer conformally covering the second via and each first channel; using a remote plasma deposition process to form a fluorine-containing polymer layer covering the semiconductor layer at the sidewall of the second via; doping the semiconductor layer based on the fluorine-containing polymer layer; manufacturing a gate insulating layer and a word line in the first channel and the second via; removing the semiconductor layer on the sidewall of the first channel to obtain a multilayer transistor. The application can improve the doping uniformity of the multilayer semiconductor layer in the high aspect ratio device and is inexpensive and efficient.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect device performance.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] This application addresses the shortcomings of existing methods by proposing a semiconductor device and its manufacturing method, as well as an electronic device, to solve the technical problems of poor doping uniformity of multilayer semiconductor layers in complex devices with high aspect ratios, and the complexity and high cost of the process.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising: An initial insulating layer and an initial sacrificial layer are sequentially and alternately fabricated on one side of the substrate to obtain an initial stacked structure; A first through-hole, a second through-hole, and a trench are formed that penetrate the initial stacked structure and are sequentially distributed in a first direction; The initial sacrificial layers on both sides of the trench are replaced with multiple bit lines extending along a second direction; the second direction intersects the first direction and is parallel to the substrate. Replace the multiple layers of the initial insulating layer surrounding the second through hole with multiple layers of the first sacrificial layer; Based on the second via, a portion of each of the first sacrificial layers is laterally etched to form a plurality of first channels that communicate with the second via and are spaced apart along a third direction perpendicular to the substrate. A conformal semiconductor layer is formed covering the second via and each of the first channels, and the semiconductor layer at the sidewall of the second via is treated with fluorine using remote plasma. A gate insulating layer and word lines are sequentially formed to cover and fill the first channel and the second via; Based on the first via and the trench, the semiconductor layer located on the sidewall of the first channel is laterally etched to obtain a multilayer transistor.

[0006] Optionally, the semiconductor layer at the sidewall of the second via is doped with fluorine using remote plasma, including at least one of the following: The system filters out charged ions with physical bombardment capabilities from the remote plasma, and then performs fluorine doping on the semiconductor layer during the contact process between the filtered remote plasma and the semiconductor layer at the sidewall of the second via. A fluoropolymer layer is formed covering the semiconductor layer at the sidewall of the second via using a remote plasma doping process; fluorine is doped onto the covered semiconductor layer using an annealing process based on the fluoropolymer layer; and the residual fluoropolymer layer is removed.

[0007] Optionally, the material of the fluoropolymer layer includes a fluorocarbon polymer, and the fluoropolymer layer does not contain hydrogen.

[0008] Optionally, a first through-hole, a second through-hole, and a trench are formed that penetrate the initial stacked structure and are sequentially distributed in a first direction, including: A plurality of first through holes and a plurality of second through holes are formed through the initial stacked structure and are respectively arranged in an array; at least one first through hole and at least one second through hole are arranged alternately in pairs in the first direction, and the plurality of second through holes and the plurality of first through holes are arranged sequentially at intervals along the second direction; A first isolation layer is formed to conformally cover the first through-hole and the second through-hole; a second sacrificial layer is formed to fill the first through-hole and the second through-hole; and a first protective layer is formed to cover the first isolation layer, the second sacrificial layer and the initial stacked structure. A plurality of grooves are formed that penetrate the initial stacked structure and are distributed sequentially at intervals in the first direction and each extends along the second direction, the grooves being located between two adjacent second through holes in the first direction.

[0009] Optionally, the multiple initial sacrificial layers exposed on the trench sidewalls are replaced with multiple bit lines, each extending along a second direction, including: Based on the lateral etching of the initial sacrificial layer in the trench, a multi-layered second channel is formed, which is spaced apart along the third direction and extends along the second direction. Multiple bit lines are formed to fill the second channel, the bit lines at least covering the first isolation layer and the portion of the initial insulating layer exposed in the second channel.

[0010] Optionally, after replacing the multiple initial sacrificial layers exposed on the trench sidewalls with multiple bit lines each extending along the second direction, and before replacing the multiple initial insulating layers surrounding the second via with multiple first sacrificial layers, the process includes: The multilayer initial sacrificial layer surrounding the first through hole is replaced with a multilayer first electrode plate.

[0011] Optionally, the multiple initial sacrificial layers surrounding the first through-hole are replaced with multiple first electrode plates, including: Based on dry etching, a portion of the second sacrificial layer located within the first via is removed; Based on wet etching, the second sacrificial layer remaining in the first via and the first isolation layer located on the sidewall of the first via are removed; Based on the first via, the initial sacrificial layer is laterally etched until the first isolation layer located in the second via is exposed, forming a multilayer third channel spaced apart along the third direction; A first electrode plate is formed to conformally cover the third channel, and a capacitor sacrificial layer is formed to fill the third channel.

[0012] Optionally, the multiple layers of the initial insulating layer surrounding the second via are replaced with multiple layers of the first sacrificial layer, including: Based on dry etching, a portion of the second sacrificial layer located within the second via is removed; Based on wet etching, the second sacrificial layer remaining in the second via and the first isolation layer located on the sidewall of the second via are removed; Based on the second through-hole, the initial insulating layer is laterally etched to form a multilayer fourth channel arranged at intervals; A conformal layer is formed covering the sidewall of the second through-hole and the first sacrificial layer filling the fourth channel.

[0013] Optionally, based on the first via and the trench, the semiconductor layer located on the sidewall of the first channel is laterally etched to obtain a multilayer transistor, including: Through the first via and the trench, multiple layers of the first sacrificial layer are laterally etched until the semiconductor layer in the fourth channel is exposed. The semiconductor layer in the fourth channel is etched laterally to obtain the multilayer transistor.

[0014] Optionally, after laterally etching the semiconductor layer located on the sidewall of the first channel based on the first via and the trench to obtain a multilayer transistor, the process includes: The capacitor sacrificial layer located within the multilayer third channel and the initial insulating layer located on the substrate-facing side and the substrate-removing side of the multilayer third channel are removed based on the first via. A capacitor dielectric material, a conductive material, and a filling material are deposited sequentially to form a capacitor dielectric layer and a second electrode that sequentially conformally cover and fill the third channel and the first through hole; the first electrode, the capacitor dielectric layer, and the second electrode form a capacitor.

[0015] Secondly, embodiments of this application provide a semiconductor device, including: Word lines, disposed on one side of the substrate, include gates of multilayer transistors spaced apart along a third direction perpendicular to the substrate and connection lines located between any two adjacent gates; A gate insulating layer is disposed around the periphery of the gate; A multilayer semiconductor layer, wherein each semiconductor layer corresponds to a gate and is wound around the periphery of the gate insulating layer, and the semiconductor layer is doped with fluorine by remote plasma; Multiple bit lines, each extending along the second direction; A multilayer first electrode plate is located on the side of the semiconductor layer away from the bit line, and the bit line and the first electrode plate are electrically connected to both ends of the semiconductor layer of the transistor.

[0016] Optionally, each layer of transistors includes a plurality of transistors arranged in an array in a first direction and a second direction, wherein the plurality of transistors arranged sequentially in the second direction share a bit line; The semiconductor device further includes a capacitor dielectric layer and a second electrode that sequentially conformally cover the inner wall, i.e. part of the outer wall, of the first electrode. The first electrode, the capacitor dielectric layer, and the second electrode form a capacitor, and the plurality of capacitors correspond one-to-one with the plurality of transistors.

[0017] Thirdly, embodiments of this application provide an electronic device, including: A semiconductor device manufactured using the semiconductor device manufacturing method described above; or, Semiconductor devices as described above.

[0018] The beneficial technical effects of the technical solutions provided in this application include: In this embodiment, along a third direction perpendicular to the substrate, the sidewall of the second via is divided into multiple sidewall segments by multiple first channels. The semiconductor layers covering each sidewall segment belong to multiplex transistors. Remote plasma can penetrate deep into the second via, for example, up to several micrometers, to perform contact-type fluorine doping on the semiconductor layers of the multiplex transistors on its sidewalls, or to deposit a fluorinated polymer layer followed by annealing for fluorine doping. This results in a high depth-to-width ratio and relatively uniform doping concentration in the semiconductor layers of each transistor, sufficient to meet the doping requirements of complex devices such as multilayer stacked devices. Furthermore, remote plasma technology is more cost-effective and efficient than traditional iCVD technology.

[0019] When depositing a fluoropolymer within a second via using remote plasma deposition (RPD), due to the wafer loading effect, the fluoropolymer is primarily deposited within the second via and covers the semiconductor layer on its sidewalls, with little or no deposit entering the first channel. This allows for uniform doping of the semiconductor layer on the second via sidewalls based on the fluoropolymer, preventing the parasitic semiconductor layer covering the first channel from being doped, or ensuring that the doping concentration gradually decreases from the inside to the outside of the first channel. This results in an etching rate for the parasitic semiconductor layer in the first channel (including the outer sidewall along a third direction and between any two bit lines) that is greater than the etching rate of the fluoropolymer-doped semiconductor layer on the second via sidewalls. This makes the parasitic semiconductor layer in the first channel easier to remove in subsequent etching steps, reducing the manufacturing difficulty and complexity of semiconductor devices and improving their manufacturing efficiency.

[0020] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0021] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application; Figures 2 to 45 This is a schematic diagram of the structure of a semiconductor device manufacturing method provided in this application at different processes. Explanation of reference numerals in the attached figures: 10-Substrate; 20 - Initial stacked structure; 21 - Initial insulating layer; 22 - Initial sacrificial layer; 31-Transistor; 311-Semiconductor layer; 312-Gate insulating layer; 313-Word line; 3131-Gate; 3132-Connection line; 42-Capacitor; 421-First plate; 422-Capacitor dielectric layer; 423-Second plate; 424-Capacitor sacrificial layer; 425-Fill layer; 51 - Fluoropolymer layer; 52 - Insulating cover layer; 61-First through hole; 62-Second through hole; 63-Third through hole; 64-Fourth through hole; 65-Fifth through hole; 66-First through groove; 70-groove; 81 - First isolation layer; 82 - Second isolation layer; 83 - Third isolation layer; 84 - Fourth isolation layer; 91 - First sacrificial layer; 92 - Second sacrificial layer; 93 - Third sacrificial layer; 94 - Fourth sacrificial layer; 95 - Fifth sacrificial layer; 101 - First protective layer; 102 - Second protective layer; 103 - Third protective layer; 104 - Fourth protective layer; 111 - First Channel; 112 - Second Channel; 113 - Third Channel; 114 - Fourth Channel; 120-bit line; 130 - Layered structure; 131 - Insulating layer; 132 - Sacrificial layer. Detailed Implementation

[0022] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0023] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connections or wireless coupling. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0025] The relevant technologies are explained below: By constructing ring-channel transistors based on IGZO (Indium Gallium Zinc Oxide), high on / off ratio transistors can be fabricated on multilayer stacked structures without doping processes. However, IGZO materials are quite sensitive to subsequent processing conditions and have certain requirements for the contact film layer. Fluorine doping can effectively improve the stability of IGZO materials, optimize the CV characteristic curve (capacitance-voltage characteristic curve) of the transistor, and improve the device on / off ratio.

[0026] However, fluorine doping of IGZO is quite difficult. Conventional plasma treatment can lead to inconsistent doping concentrations in localized areas due to direct ion bombardment, and can also damage the device, making it difficult to achieve uniform doping between multilayer semiconductors in complex devices with high aspect ratios. Conventional iCVD (analytical initiation chemical vapor deposition) methods are also complex and costly.

[0027] The semiconductor devices, manufacturing methods, and electronic devices provided in this application are intended to solve the aforementioned technical problems in related technologies.

[0028] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0029] This application provides a method for manufacturing a semiconductor device, and the flowchart of the method is shown below. Figure 1 As shown, the structural schematic diagrams of the semiconductor device manufacturing method at different processes are as follows: Figures 2 to 45 As shown, the method for manufacturing this semiconductor device includes: S101: Initial insulating layer 21 and initial sacrificial layer 22 are sequentially and alternately fabricated on one side of substrate 10 to obtain initial stacked structure 20.

[0030] S102: Form a first through hole 61, a second through hole 62 and a trench 70 that penetrate the initial stacked structure 20 and are distributed sequentially in the first direction.

[0031] S103: Replace the multilayer initial sacrificial layers 22 on both sides of the trench 70 with multilayer bit lines 120 extending along the second direction; the second direction intersects the first direction and is parallel to the substrate 10.

[0032] S104: Replace the multilayer initial insulating layer 21 around the second through hole 62 with a multilayer first sacrificial layer 91.

[0033] S105: Based on the second via 62, a portion of each first sacrificial layer 91 is laterally etched to form a plurality of first channels 111 that are connected to the second via 62 and spaced apart along a third direction perpendicular to the substrate 10.

[0034] S106: Form a semiconductor layer 311 that conformally covers the second via 62 and each of the first channels 111, and apply fluorine to the semiconductor layer 311 at the sidewall of the second via 62 using remote plasma.

[0035] S107: Sequentially form a gate insulating layer 312 and word line 313 that conformally cover and fill the first channel 111 and the second via 62.

[0036] S108: Based on the first via 61 and the trench 70, the semiconductor layer 311 located on the sidewall of the first channel 111 is etched laterally to obtain the multilayer transistor 31.

[0037] This application addresses the problem that conventional plasma processing in related technologies can lead to inconsistent doping concentrations in localized areas due to direct ion bombardment, and can damage devices, making it difficult to achieve uniform doping between multilayer semiconductors in complex devices with high aspect ratios. To address the technical issues of the complexity and high cost of conventional iCVD methods, a novel semiconductor device fabrication method is proposed.

[0038] In this embodiment, using a remote plasma deposition process along a third direction perpendicular to the substrate 10, the sidewall of the second via 62 is divided into multiple sidewall segments by multiple first channels 111. The semiconductor layers 311 covering each of these sidewall segments belong to multiplex transistors 31. The remote plasma can penetrate deep into the second via 62, for example, up to several micrometers, to perform contact-type fluorine doping on the semiconductor layers 311 of the multiplex transistors 31 on its sidewalls, or to deposit a fluoropolymer layer 51 followed by annealing for fluorine doping. This results in a high depth-to-width ratio, and the doping concentration of the semiconductor layers 311 of each transistor layer is relatively uniform, sufficient to meet the doping requirements of complex devices such as multilayer stacked devices. Furthermore, the remote plasma deposition process is more cost-effective and efficient than traditional iCVD processes.

[0039] When a fluoropolymer is uniformly deposited in the second via 62 using a remote plasma deposition process, due to the wafer loading effect, the fluoropolymer is mainly deposited inside the second via 62, and only a small portion enters the first channel 111. This prevents the semiconductor layer 311 covering the sidewall of the first channel 111 from being doped, or the doping concentration of the semiconductor layer 311 gradually decreases from the inside to the outside of the first channel 111. This results in the etching rate of the semiconductor layer 311 parasitic in the first channel 111 (including the outer sidewall of the first channel 111 along a third direction and between any two bit lines 120) being greater than the etching rate of the semiconductor layer 311 doped with the fluoropolymer on the sidewall of the second via 62. This makes it easier to remove the parasitic semiconductor layer 311 in the first channel 111 in subsequent etching steps, thereby reducing the manufacturing difficulty of semiconductor devices and improving the manufacturing efficiency of semiconductor devices.

[0040] In some optional embodiments of this application, in step S101, an initial insulating layer 21 and an initial sacrificial layer 22 are sequentially and alternately fabricated on one side of the substrate 10 to obtain an initial stacked structure 20, including: Insulating materials and dielectric materials are sequentially and alternately deposited on substrate 10 to form multiple layers of initial insulating layers 21 and multiple layers of initial sacrificial layers 22, thereby obtaining an initial stacked structure 20, as shown in the figure. Figure 2 The diagram shows a schematic of the membrane structure.

[0041] Optionally, in the embodiments of this application, the material of the substrate 10 includes, but is not limited to, silicon; the material of the initial insulating layer 21 includes, but is not limited to, silicon oxide (SiO or SiO2); and the material of the initial sacrificial layer 22 includes, but is not limited to, silicon nitride (SiN).

[0042] Optionally, in this embodiment, the initial insulating layer 21 made of SiO or SiO2 and the initial sacrificial layer 22 made of SiN form an ON layer, and the initial stacked structure 20 includes multiple ON layers stacked sequentially along a third direction perpendicular to the substrate 10. Six tiers of ON layers are fabricated on the substrate 10, meaning the initial stacked structure 20 includes six ON layers. Of course, in other optional embodiments of this application, other multiple ON layers besides six layers can be fabricated according to actual needs, such as five or seven layers.

[0043] In this embodiment of the application, the a-a' direction is parallel to the first direction, and the b-b' and c-c' directions are parallel to the second direction.

[0044] In some optional embodiments of this application, such as Figures 2-9 As shown, where Figure 4 for Figure 3 Sectional view along direction aa, Figure 5 for Figure 3 A cross-sectional view along the bb direction. In step S102, a first through hole 61, a second through hole 62, and a trench 70 are formed, penetrating the initial stacked structure 20 and sequentially distributed in the first direction, including: Multiple first through holes 61 and multiple second through holes 62 are formed, penetrating the initial stacked structure 20 and respectively arranged in an array, to obtain the following: Figure 4 The diagram shows a schematic of the membrane structure. Figures 2-5 As shown, at least one first through hole 61 and at least one second through hole 62 are arranged alternately in a first direction, and a plurality of second through holes 62 and a plurality of first through holes 61 are arranged sequentially at intervals along a second direction.

[0045] In this embodiment, the second via 62 defines the location of the transistor 31 to be formed, and the first via 61 defines the location of the capacitor 42 to be formed.

[0046] Next, a first insulating layer 81 is formed to conformally cover the first through-hole 61 and the second through-hole 62; a second sacrificial layer 92 is formed to fill the first through-hole 61 and the second through-hole 62; and a first protective layer 101 is formed to cover the first insulating layer 81, the second sacrificial layer 92, and the initial stacked structure 20, resulting in the following: Figure 6 The diagram shows a schematic of the membrane structure.

[0047] Optionally, in the embodiments of this application, the material of the first isolation layer 81 includes, but is not limited to, oxide (such as SiO or SiO2), the material of the second sacrificial layer 92 includes polysilicon, and the material of the first protective layer 101 includes oxide (such as SiO or SiO2).

[0048] Optionally, in this embodiment, Oxide and Poly can be deposited sequentially to form a first isolation layer 81 and a second sacrificial layer 92 that sequentially conformally cover and fill the second through-hole 62 and the first through-hole 61; then, planarization is performed by CMP (Chemical Mechanical Polishing) process to grind the surface Poly flat, so that the surfaces of the second sacrificial layer 92, the first isolation layer 81 and the outermost initial sacrificial layer 22 are flush; then, Oxide is deposited and CMP is performed to form a first protective layer 101.

[0049] Figure 8 The second through hole 62 and the first through hole 61 are indicated by dashed lines, and the first protective layer 101 is made semi-transparent. On the one hand, it can show the positions of the second through hole 62, the first through hole 61, the first isolation layer 81 and the second sacrificial layer 92. On the other hand, it can show that the second through hole 62, the first through hole 61, the first isolation layer 81 and the second sacrificial layer 92 are blocked by the first protective layer 101.

[0050] Next, as Figures 8-9 As shown, the first protective layer 101 and the initial stacked structure 20 are etched to form a plurality of trenches 70 that penetrate the initial stacked structure 20 and are sequentially spaced in a first direction, each extending along a second direction. The trenches 70 are located between two adjacent second vias 62 in the first direction. Fabricating the trenches 70 facilitates the subsequent fabrication of bit lines 120. The trenches 70 being located between the two second vias 62 allows transistors 31 subsequently fabricated within the two second vias 62 to share the bit lines 120.

[0051] Optionally, in step S103, such as Figure 8-12 As shown, the multilayer initial sacrificial layers 22 on both sides of the trench 70 are replaced with multilayer bit lines 120 extending along a second direction, which intersects the first direction and is parallel to the substrate 10, including: Based on the transverse etching of the initial sacrificial layers 22 in the trench 70, a multilayer second channel 112 is formed, which is spaced apart along the third direction and extends along the second direction, resulting in... Figure 10 The diagram shows a schematic of the membrane structure.

[0052] like Figure 8 As shown in this embodiment, the multilayer second channels 112 are sequentially spaced along a third direction. Each second channel 112 extends along a second direction. The upper and lower parts of the second channel 112 along the third direction expose the initial insulating layer 21, and the side parts expose the first isolation layer 81 located within the second via 62 and the initial sacrificial layer 22 located between two adjacent second vias 62 in the second direction. The second channel 112 defines the position of the bit line 120 to be formed.

[0053] Next, multiple bit lines 120 are formed to fill the second channel 112, the bit lines 120 at least covering the first isolation layer 81 and the exposed portion of the initial insulating layer 21 of the second channel 112, resulting in the following: Figure 11 The diagram shows a schematic of the membrane structure.

[0054] Multiple bit lines 120 correspond one-to-one with multiple second channels 112. The multiple bit lines 120 are arranged sequentially at intervals along a third direction, and each bit line 120 extends along a second direction. One bit line 120 covers the first isolation layer 81 in the second vias 62 spaced apart in the second direction, the initial sacrificial layer 22 between two adjacent second vias 62 in the second direction, and the partial initial insulating layer 21 located above and below the second channel 112.

[0055] Optionally, in this embodiment, the material of bit line 120 includes a conductive material, which includes, but is not limited to, TiN.

[0056] Optionally, in this embodiment, fabricating the bit line 120 includes: depositing a conductive material to at least fill the second channel 112; performing wet etching on the conductive material; then depositing another conductive material; performing another wet etching on the conductive material; and the remaining unetched conductive material forming the bit line 120. By performing two depositions and two etchings, the morphology of the bit line 120 can be improved, thereby enhancing performance.

[0057] It should be noted that, in some alternative embodiments of this application, the above-mentioned steps of "depositing conductive material" and "wet etching of conductive material" may be performed once or twice more as needed to fabricate bit line 120.

[0058] Optionally, after fabricating bit line 120 and before replacing the multilayer initial insulating layer 21 surrounding the second via 62 with the multilayer first sacrificial layer 91, the process includes: A second isolation layer 82 is formed to conformally cover the second channel 112 and the bit line 120, and a third sacrificial layer 93 is formed to fill the second channel 112 and the trench 70, resulting in... Figure 12 The diagram shows a schematic of the membrane structure.

[0059] Optionally, in this embodiment, the material of the second isolation layer 82 includes, but is not limited to, SiN, and the material of the third sacrificial layer 93 includes, but is not limited to, Poly.

[0060] Next, planarization is performed using CMP process to make the surfaces of the second isolation layer 82, the third sacrificial layer 93 and the first protective layer 101 flush.

[0061] Next, a second protective layer 102 is formed, covering the second isolation layer 82, the third sacrificial layer 93, and the first protective layer 101, resulting in the following: Figure 12 The diagram shows a schematic of the membrane structure.

[0062] Optionally, in this embodiment, the material of the second protective layer 102 includes, but is not limited to, oxides (such as SiO or SiO2). Optionally, such as Figure 13-25 As shown, after fabricating bit line 120, and before replacing the multilayer initial insulating layer 21 around the second through hole 62 with the multilayer first sacrificial layer 91, the process further includes replacing the multilayer initial sacrificial layer 22 around the first through hole 61 with the multilayer first electrode plate 421.

[0063] Optionally, after fabricating the second protective layer 102, it is patterned using a hard mask (HM) to form a third via 63 penetrating the second protective layer 102 and the first protective layer 101. The orthographic projection of the third via 63 onto the substrate 10 intersects with the orthographic projection of the first via 61 onto the substrate 10. The bottom of the third via 63 exposes the first isolation layer 81 and the second sacrificial layer 92 located within the first via 61, thereby opening the area where the capacitor 42 is to be formed, resulting in... Figure 13 and 14 The diagram shows a schematic of the membrane structure.

[0064] Optionally, the multilayer initial sacrificial layer 22 surrounding the first through-hole 61 is replaced with a multilayer first electrode plate 421, including: Based on dry etching, a portion of the second sacrificial layer 92 located within the first via 61 is removed, resulting in the following: Figure 15 The diagram shows a schematic of the membrane structure.

[0065] Dry etching is performed on the second sacrificial layer 92 located in the first via 61 through the third via 63 to remove most of the second sacrificial layer 92 in the first via 61, avoiding etching to the bottom of the first via 61, thereby avoiding damage to the first isolation layer 81 and the substrate 10.

[0066] Next, based on wet etching, the second sacrificial layer 92 remaining in the first via 61 and the first isolation layer 81 located on the sidewall of the first via 61 are removed, resulting in the following: Figure 16 and 17 The schematic diagram of the membrane structure shown is as follows, in which Figure 16 for Figure 13 Sectional view along line a-a' Figure 17 for Figure 13 The b-b' sectional view.

[0067] Based on the exposed portion of the first via 61, the remaining portion of the second sacrificial layer 92 is wet-etched to expose the first via 61. Then, the first isolation layer 81 on the sidewall of the first via 61 is removed by wet etching.

[0068] Next, the initial sacrificial layer 22 is etched laterally based on the first via 61 until the first isolation layer 81 located in the second via 62 is exposed, forming a multilayer third channel 113 spaced apart along the third direction, resulting in... Figure 18 and 19 The schematic diagram of the membrane structure shown is as follows, in which Figure 18 for Figure 13 Sectional view along line a-a' Figure 19 for Figure 13 The b-b' sectional view.

[0069] In this embodiment, the multilayer third channels 113 are sequentially spaced in the third direction, and the initial insulating layer 21 is exposed at the upper and lower parts of the third channels 113 along the third direction, respectively. Figure 18 The initial sacrificial layer 22 is exposed on one side, as shown in the figure. Figure 18 The other side shown exposes the first isolation layer 81 located within the second through-hole 62.

[0070] Next, a first electrode plate 421 conformally covering the third channel 113 and a capacitor sacrificial layer 424 filling the third channel 113 are formed, resulting in the following: Figure 20 and 21 The schematic diagram of the membrane structure shown is as follows, in which Figure 20 for Figure 13 Sectional view along line a-a' Figure 21 for Figure 13 The b-b' sectional view.

[0071] Optionally, in this embodiment of the application, fabricating the first electrode plate 421 and the capacitor sacrificial layer 424 includes: Conductive material and dielectric material are deposited sequentially. The conductive material at least covers the inner wall of the third channel 113, and the dielectric material covers the conductive material and fills the third channel 113 and the first through hole 61.

[0072] Next, etching is performed to remove the dielectric material or dielectric and conductive material in the first through hole 61. The remaining conductive material on the inner wall of the third channel 113 forms the first electrode plate 421, and the remaining dielectric material in the third channel 113 forms the capacitor sacrificial layer 424.

[0073] Optionally, in this embodiment, the material of the first electrode 421 includes, but is not limited to, titanium nitride (TiN), which can be deposited by ALD (Atomic Layer Deposition) process. The material of the capacitor sacrificial layer 424 includes, but is not limited to, oxide (such as SiO or SiO2).

[0074] Optionally, after fabricating the first electrode plate 421 and the capacitor sacrificial layer 424, and before fabricating the first sacrificial layer 91, the method further includes: A third isolation layer 83 is formed to cover the first through hole 61 and the third through hole 63 in a conformal shape.

[0075] Next, a fourth sacrificial layer 94 is formed to fill the first through-hole 61 and the third through-hole 63, resulting in the following: Figure 22 and 23 The schematic diagram of the membrane structure shown is as follows, in which Figure 22 for Figure 13 Sectional view along line a-a' Figure 23 for Figure 13 The b-b' sectional view.

[0076] In this embodiment, a third isolation layer 83 can be formed by depositing SiN using an ALD process, and a fourth sacrificial layer 94 can be formed by depositing Poly.

[0077] Next, planarization is performed using CMP process to make the surfaces of the third isolation layer 83, the fourth sacrificial layer 94, and the second protective layer 102 flush.

[0078] Next, a third protective layer 103 is formed, covering the third isolation layer 83, the fourth sacrificial layer 94, and the second protective layer 102, resulting in the following: Figure 22 and 23 The diagram shows a schematic of the membrane structure.

[0079] Optionally, in this embodiment, a third protective layer 103 is formed by depositing a dielectric material and then planarizing it using a CMP process. The material of the third protective layer 103 includes, but is not limited to, nitrides (such as SiN). Optionally, such as Figure 24-26As shown, after fabricating the third protective layer 103, it can be patterned using a hard mask (HM) to form a fourth via 64 penetrating the third protective layer 103, the second protective layer 102, and the first protective layer 101. The orthographic projection of the fourth via 64 onto the substrate 10 intersects with the orthographic projection of the second via 62 onto the substrate 10. The bottom of the fourth via 64 exposes the first isolation layer 81 and the second sacrificial layer 92 located within the second via 62, thereby opening the area where the transistor 31 is to be formed, resulting in... Figure 24 The diagram shows a schematic of the membrane structure.

[0080] Optionally, in step S104, the multilayer initial insulating layer 21 surrounding the second through-hole 62 is replaced with a multilayer first sacrificial layer 91, including: Based on dry etching, a portion of the second sacrificial layer 92 located within the second via 62 is removed, resulting in the following: Figure 25 The diagram shows a schematic of the membrane structure.

[0081] Dry etching is performed on the second sacrificial layer 92 located in the second via 62 through the fourth via 64 to remove most of the second sacrificial layer 92 in the second via 62, avoiding etching to the bottom of the second via 62, thereby avoiding damage to the first isolation layer 81 and the substrate 10.

[0082] Next, based on wet etching, the second sacrificial layer 92 remaining in the second via 62 and the first isolation layer 81 located on the sidewall of the second via 62 are removed, resulting in the following: Figure 26 The diagram shows a schematic of the membrane structure.

[0083] Based on the exposed portion of the second via 62, the remaining portion of the second sacrificial layer 92 is wet-etched to expose the second via 62. Then, the first isolation layer 81 on the sidewall of the second via 62 is removed by wet etching to fully expose the second via 62 and the fourth via 64.

[0084] Next, based on the fourth via 64 and the second via 62, a multilayer initial insulating layer 21 is wet-etched laterally to form a multilayer fourth channel 114 arranged at intervals, resulting in the following... Figure 27 The diagram shows a schematic of the membrane structure.

[0085] In this embodiment, since the materials of the first protective layer 101 and the second protective layer 102 are the same as the initial insulating layer 21, the top portions of the first protective layer 101 and the second protective layer 102 are also etched laterally, forming fourth channels 114 between the third protective layer 103 and the first electrode plate 421, and between the third protective layer 103 and the bit line 120. The multiple layers of fourth channels 114 are distributed sequentially at intervals in the third direction, with the upper and lower portions of the fourth channels 114 exposing the first electrode plate 421 and the bit line 120, respectively. Figure 27The third isolation layer 83 is exposed on one side, as shown. Figure 27 The other side, as shown, exposes the second isolation layer 82 located within the second through-hole 62.

[0086] Next, a first sacrificial layer 91 is formed to conformally cover the sidewall of the second through-hole 62 and fill the fourth channel 114, resulting in the following: Figure 28 The diagram shows a schematic of the membrane structure.

[0087] Optionally, in this embodiment of the application, Poly is deposited inside the fourth channel 114 and the sidewalls of the second through hole 62 and the fourth through hole 64 using an ALD process to form a first sacrificial layer 91.

[0088] In step S105, a portion of each first sacrificial layer 91 is laterally etched based on the second via 62 to form a plurality of first channels 111 that communicate with the second via 62 and are spaced apart along a third direction perpendicular to the substrate 10, including: Based on a wet etching process, the first sacrificial layer 91 located on the sidewalls of the second via 62 and the fourth via 64, as well as a portion of the first sacrificial layer 91 located within the multilayer first channel 111, are etched to form a multilayer first channel 111 spaced apart along a third direction. The projections of the first channel 111 and the fourth channel 114 onto a vertical plane perpendicular to the substrate 10 intersect or extend continuously. The upper and lower parts of the first channel 111 along the third direction expose the first electrode plate 421 and the bit line 120, respectively, resulting in... Figure 29 The diagram shows a schematic of the membrane structure.

[0089] Optionally, in step S106, forming a conformal semiconductor layer 311 covering the second via 62 and each of the first channels 111 includes: A semiconductor layer 311 is deposited using an ALD process, so that the semiconductor layer 311 conformally covers the first channel 111, the first electrode 421, the bit line 120, the sidewalls of the third protective layer 103, and the surface of the third protective layer 103, to obtain the following: Figure 30 The diagram shows a schematic of the membrane structure.

[0090] In this embodiment, the material of the semiconductor layer 311 includes, but is not limited to, IGZO.

[0091] Next, using remote plasma, the semiconductor layer 311 on the sidewall of the second via 62 is doped with fluorine.

[0092] Optionally, in one alternative embodiment, fluorine doping is performed on the semiconductor layer 311 at the sidewall of the second via 62 using remote plasma, including: The semiconductor layer 311 is doped with fluorine during the contact process between the filtered remote plasma and the semiconductor layer 311 at the sidewall of the second via 62.

[0093] The remote plasma enters the second via 62 through a specially designed transmission system and comes into contact with the semiconductor layer 311 that conformally covers the sidewalls of the second via 62. Since the concentration of fluorine in the remote plasma is higher than that in the semiconductor layer 311, a small amount of fluorine will also be doped into the semiconductor layer 311. However, the doping depth generated during the deposition of the fluoropolymer is generally very shallow, typically limited to within 2 nm, and causes minimal damage to the IGZO material, which can be ignored. Of course, a higher degree of doping can also be achieved locally.

[0094] It should be noted that the doping depth mentioned in this application refers to the direction perpendicular to the surface of the semiconductor layer 311, that is, the lateral dimension parallel to the substrate. For example, it can be a thickness of 2nm (nanometer) doped from the side of the semiconductor layer 311 inward.

[0095] Alternatively, in another alternative embodiment, fluorine doping of the semiconductor layer at the sidewall of the second via using remote plasma may further include: Using a remote plasma doping process, a fluoropolymer layer 51 is formed covering the semiconductor layer 311 at the sidewall of the second via 62, resulting in... Figure 31 The diagram shows a schematic of the membrane structure.

[0096] Using an annealing process, fluorine is doped onto the covered semiconductor layer 311 based on the fluorinated polymer layer 51.

[0097] Removing the residual fluoropolymer layer 51 yields the following result: Figure 32 The diagram shows a schematic of the membrane structure.

[0098] Optionally, after forming the fluoropolymer layer 51 covering the semiconductor layer 311 at the sidewall of the second via 62 and the semiconductor layer 311 covering the top of the third protective layer 103, the method further includes: An insulating cover layer 52 is formed over the fluoropolymer layer 51 to obtain the following: Figure 31 The diagram shows a schematic of the membrane structure.

[0099] In this embodiment, the material of the insulating covering layer 52 includes, but is not limited to, aluminum oxide (Al2O3).

[0100] In this embodiment, by annealing the fluoropolymer layer 51 and the insulating cover layer 52, the semiconductor layer 311 can be further doped under heating conditions, thereby obtaining a deeper doping depth, which allows the fluorine doping to reach the source and drain portions of the transistor 31, so that the doped channels of the transistor 31 are connected into a path.

[0101] Optionally, in the manufacturing process of different semiconductor devices, different gases can be used in remote plasmas, and one of the two doping schemes mentioned above can be selectively used, or used in combination, to provide multiple selection modes according to the needs of the semiconductor devices, thereby improving the performance of the semiconductor devices.

[0102] During the deposition of the fluoropolymer, due to the wafer loading effect, the fluoropolymer layer 51 is mainly deposited on the sidewall of the second via 62, and will not or will enter the lateral first channel 111 in small quantities. This results in the semiconductor layer 311 that conformally covers the sidewall of the first channel 111 being undoped or having a low doping concentration. Furthermore, the doping concentration of the semiconductor layer 311 gradually decreases from the inside to the outside of the first channel 111, that is, from the side closer to the first via 61 to the side farther away from the first channel 111. This facilitates the removal of the semiconductor layer 311 parasitically located between any two bit lines 120 and between any two first electrode plates 421 in subsequent steps.

[0103] Optionally, in this embodiment, the material of the fluoropolymer layer 51 includes, but is not limited to, fluorocarbon polymers, such as C4F6 and C4F8. This ensures that the fluoropolymer layer 51 is entirely composed of carbon and fluorine elements, and contains no hydrogen elements. Using a hydrogen-free fluorocarbon polymer for doping can prevent hydrogen penetration, avoid damage to the semiconductor layer 311 by hydrogen elements, and ensure the stability of the electrical properties of the semiconductor layer 311.

[0104] The fluorine-containing plasmas (such as CF4 / O2 plasma) used in related technologies are difficult to etch IGZO, requiring the addition of gases with physical bombardment capabilities, such as Ar, and the use of accelerating voltage to enhance the plasma's bombardment power. However, even these fluorine-containing plasmas have relatively weak etching capabilities for IGZO. Furthermore, without the use of gases with physical bombardment capabilities and without accelerating voltage, the effect of plasma on nanoscale-thickness IGZO films in multilayer stacked structures is to improve channel material mobility and interfacial contact, without significantly negatively impacting the various properties of IGZO materials.

[0105] The remote plasma used in this paper filters out charged ions with physical bombardment capabilities, resulting in weaker etching ability. The C4F6 gas used has a weaker etching ability than CF4 / O2 plasma, and can only modify the surface of IGZO materials, unable to penetrate the atomic layer of the material surface. It then exhibits more deposition effects. Therefore, it can be judged that this type of plasma is less likely to damage IGZO.

[0106] Optionally, in step S107, a conformal gate insulating layer 312 and word line 313 are sequentially formed to cover and fill the first channel 111 and the second via 62, including: Based on the second via 62, a gate insulating material and a conductive material are sequentially deposited using an ALD process to form a conformal overlay semiconductor layer 311, a gate insulating layer 312, and a word line 313 filling the first channel 111, the second via 62, and the fourth via 64, resulting in... Figure 33 The diagram shows a schematic of the membrane structure.

[0107] Optionally, in this embodiment, the gate insulating material includes, but is not limited to, HK (High-K, a high dielectric constant material, which includes dielectrics with a dielectric constant k greater than or equal to 3.9) material. The word line 313 is not limited to, ITO.

[0108] Optionally, after fabricating the gate insulating layer 312 and the word line 313, the process includes: The semiconductor layer 311, gate insulating layer 312, and word line 313 are planarized using CMP process, so that the surfaces of the semiconductor layer 311, gate insulating layer 312, word line 313, and third protective layer 103 are flush.

[0109] Next, a fourth protective layer 104 is fabricated, which covers the semiconductor layer 311, the gate insulating layer 312, the word line 313, and the third protective layer 103, to obtain the following: Figure 33 The diagram shows a schematic of the membrane structure.

[0110] Optionally, in this embodiment, the material of the fourth protective layer 104 includes, but is not limited to, SiN, and the fourth protective layer 104 can be formed by depositing SiN.

[0111] Next, dry etching can be used to form a fifth via 65 and a first trench 66 penetrating the third protective layer 103 and the fourth protective layer 104. The fifth via 65 intersects with the orthographic projection of the first via 61 onto the substrate 10, and the first trench 66 intersects with the orthographic projection of the trench 70 onto the substrate 10, thereby exposing the third sacrificial layer 93 in the trench 70 and the fourth sacrificial layer 94 in the first via 61, resulting in... Figures 35-37 The schematic diagram of the membrane structure shown is as follows, in which Figure 35 for Figure 34Sectional view along line a-a' Figure 36 for Figure 34 The b-b' sectional view, Figure 37 for Figure 34 The c-c' sectional view.

[0112] Next, based on the fifth via 65, a wet etching process is used to remove the fourth sacrificial layer 94 and the third isolation layer 83 located in the third via 63 and the first via 61, exposing the walls of the third via 63 and the first via 61, resulting in the following... Figure 38 The diagram shows a schematic of the membrane structure.

[0113] Next, based on the first through-groove 66, a wet etching process is used to remove the third sacrificial layer 93 and the second isolation layer 82 located in the trench 70 and the multilayer first channel 111, exposing the bit line 120 and the walls of the trench 70 and the multilayer first channel 111, resulting in the following: Figures 39-40 The diagram shows a schematic of the membrane structure.

[0114] Next, based on the first via 61, the first sacrificial layer 91 between any two first electrode plates 421 is etched laterally, and based on the trench 70, the first sacrificial layer 91 between any two bit lines 120 is etched laterally, exposing the fourth channel 114, thereby exposing the semiconductor layer 311 parasitic between any two first electrode plates 421 and any two bit lines 120, to obtain the following... Figure 41 The diagram shows a schematic of the membrane structure.

[0115] Optionally, in step S108, based on the first via 61 and the trench 70, the semiconductor layer 311 located on the sidewall of the first channel 111 is laterally etched to obtain a multilayer transistor 31, including: By severing the semiconductor layer 311 parasitic between any two first electrode plates 421 and any two bit lines 120, multiple gate insulating layers 312 are exposed, forming a multilayer transistor 31, resulting in... Figure 42 The diagram shows a schematic of the membrane structure.

[0116] The semiconductor layer 311 parasitic between any two first electrode plates 421 and any two bit lines 120 is not doped with fluorine or is doped with very little fluorine, so it is relatively easy to remove, thus making the removal of the parasitic semiconductor layer 311 selective.

[0117] Optionally, after forming the multilayer transistor 31, the method further includes fabricating a capacitor dielectric layer 422 and a second electrode plate 423 within the first via 61 and the fourth channel 114, including: A fourth isolation layer 84 is formed, which conforms to the trench 70, the first through-slot 66, the first through-hole 61, the fifth through-hole 65, and the fourth channel 114; and a fifth sacrificial layer 95 is formed, which fills the trench 70, the first through-slot 66, the first through-hole 61, the fifth through-hole 65, and the fourth channel 114, to obtain the following: Figure 43 The diagram shows a schematic of the membrane structure.

[0118] Optionally, in the embodiments of this application, the material of the fourth isolation layer 84 includes, but is not limited to, Oxide (such as SiO or SiO2), and the material of the fifth sacrificial layer 95 includes, but is not limited to, Poly.

[0119] Next, based on the first via 61 and the fifth via 65, the fifth sacrificial layer 95 and the fourth isolation layer 84 located in the first via 61, the fifth via 65 and the fourth channel 114, as well as the initial insulating layer 21 on the side of the third channel 13 facing the substrate 10 and the side facing away from the substrate 10, are removed to obtain the following: Figure 44 The diagram shows a schematic of the membrane structure.

[0120] Next, dielectric material and conductive material are deposited sequentially to form a capacitor dielectric layer 422 that conformally covers the fourth channel 114, the first via 61, and the fifth via 65. Then, a second electrode 423 is formed to fill the fourth channel 114, the first via 61, and the fifth via 65. The first electrode 421, the capacitor dielectric layer 422, and the second electrode 423 form the capacitor 42, resulting in... Figure 45 The diagram shows a schematic of the membrane structure.

[0121] Optionally, after sequentially depositing the dielectric material and conductive material of capacitor 42, the process further includes: The dielectric and conductive materials of capacitor 42 are planarized by CMP until the fourth protective layer 104 is exposed.

[0122] Next, a filling layer 425 is formed in the fourth channel 114, the first through hole 61, and the fifth through hole 65, such that the filling layer 425 covers the fourth protective layer 104, resulting in the following: Figure 45 The diagram shows a schematic of the membrane structure.

[0123] Optionally, in this embodiment, the dielectric material of capacitor 42 includes, but is not limited to, HK material. The material of the second electrode 423 includes, but is not limited to, TiN. The filler layer 425 includes, but is not limited to, Poly.

[0124] In this embodiment, the initial insulating layer 21 is formed into an insulating layer 131 after the semiconductor device is manufactured by the semiconductor device manufacturing method, the initial sacrificial layer 22 is formed into a sacrificial layer 132 after the semiconductor device is manufactured by the semiconductor device manufacturing method, and correspondingly, the initial stacked structure 20 is formed into a stacked structure 130 after the semiconductor device is manufactured by the semiconductor device manufacturing method.

[0125] The semiconductor device manufacturing method provided in this application embodiment can be applied to the field of semiconductor devices for the preparation of three-dimensional memory devices. Furthermore, it can be used as a manufacturing process for 3D DRAM (3 Dimension Dynamic Random Access Memory) to manufacture 3D DRAM structures.

[0126] Based on the same inventive concept, this application provides a semiconductor device, the structural schematic diagram of which is shown below. Figure 45 As shown, The semiconductor device includes word lines 313, gate insulating layer 312, multilayer semiconductor layer 311, multilayer bit lines 120, multilayer first electrode 421, and stacked structure 130.

[0127] Word lines 313 are disposed on one side of the substrate 10 and include gates 3131 of multilayer transistors 31 arranged at intervals along a third direction perpendicular to the substrate 10, and connecting lines 3132 located between any two adjacent gates 3131. A gate insulating layer 312 is wound around the periphery of the gates 3131. Multilayer semiconductor layers 311 correspond one-to-one with the gates 3131 and are wound around the periphery of the gate insulating layer 312. The semiconductor layers 311 are doped with fluorine by remote plasma. Multilayer bit lines 120 each extend along a second direction and are arranged at intervals along a third direction. Each bit line 120 includes a first electrode region electrically connected to the semiconductor layer 311 of the transistors 31. A multilayer first electrode plate 421 is located on the side of the semiconductor layer 311 away from the bit lines 120. The first electrode plate 421 includes a second electrode region electrically connected to the semiconductor layer 311 of the transistors 31, such that the bit lines 120 and the first electrode plate 421 are electrically connected to the two ends of the semiconductor layer 311 of the transistors 31, respectively. The transistor 31 includes a gate 3131, a gate insulating layer 312 surrounding the gate 3131, and a semiconductor layer 311 surrounding the gate insulating layer 312.

[0128] This embodiment utilizes remote plasma to dope the semiconductor layer at the sidewall of the second via 62 with fluorine. The remote plasma can penetrate deep into the second via 62, for example, up to several micrometers, to perform contact-type fluorine doping on the semiconductor layer 311 of the multilayer transistors 31 on its sidewall, or to deposit a fluoropolymer layer 51 followed by annealing for fluorine doping. This results in a high depth-to-width ratio and relatively uniform doping concentration in the semiconductor layer 311 of each transistor layer 31, sufficient to meet the doping requirements of complex devices such as multilayer stacked devices. Furthermore, the remote plasma deposition process is more cost-effective and efficient than the traditional iCVD process.

[0129] Due to the wafer loading effect, the fluoropolymer is mainly deposited inside the second via 62, and only a small portion enters the first channel 111. This prevents the semiconductor layer 311 covering the sidewall of the first channel 111 from being doped, or the doping concentration of the semiconductor layer 311 gradually decreases from the inside to the outside of the first channel 111. This makes it easier to remove the parasitic semiconductor layer 311 at the first channel 111 in subsequent etching steps, thereby reducing the manufacturing difficulty of semiconductor devices and improving the manufacturing efficiency of semiconductor devices.

[0130] It should be noted that the semiconductor devices in the embodiments of this application can be manufactured using the manufacturing method of the semiconductor devices provided in the embodiments of this application. Therefore, the semiconductor devices in the embodiments of this application also have the above-mentioned beneficial effects of the manufacturing method of the semiconductor devices provided in the embodiments of this application, which will not be repeated here.

[0131] Optionally, each layer of transistors 31 includes a plurality of transistors 31 arranged in an array in a first direction and a second direction, with the plurality of transistors 31 arranged sequentially in the second direction sharing a single bit line 120. This reduces the number of bit lines 120, which is beneficial for layout design, increases structural density, and improves practicality.

[0132] Optionally, the first electrode plate 421 includes a top plate, a bottom plate, and a side plate. The top plate and the bottom plate are both annular, and the side plates are connected to the outer edges of the top plate and the bottom plate respectively to form an inner cavity.

[0133] Optionally, the semiconductor device of this application further includes a capacitor dielectric layer 422 and a second electrode 423 that sequentially conformally cover the inner wall and part of the outer wall of the first electrode 421. The first electrode 421, the capacitor dielectric layer 422, and the second electrode 423 form a capacitor 42, and multiple capacitors 42 correspond one-to-one with multiple transistors 31. The capacitors 42 and transistors 31 form a memory cell.

[0134] In some optional embodiments of this application, the semiconductor device can be a random access memory, specifically a static random access memory or a dynamic random access memory, or of course, flash memory, etc.

[0135] Based on the same inventive concept, embodiments of this application provide an electronic device, which includes: a semiconductor device manufactured using the semiconductor device manufacturing method described above; or, a semiconductor device as described above.

[0136] It should be noted that since the electronic devices in the embodiments of this application include semiconductor devices manufactured using the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, the electronic devices in the embodiments of this application also have the above-mentioned beneficial effects of the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, which will not be repeated here.

[0137] In some optional embodiments of this application, the electronic device includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include, for example, memory in a computer, and is not limited thereto.

[0138] By applying the embodiments of this application, at least the following beneficial effects can be achieved: remote plasma can penetrate deep into the second via 62, with a deposition depth of several micrometers and a corresponding high depth-to-width ratio, enabling uniform doping of different semiconductor layers 311, which is sufficient to meet the doping requirements of complex devices such as multilayer stacked devices. Furthermore, the remote plasma deposition process is more cost-effective and efficient compared to the traditional iCVD process.

[0139] During the deposition process of remote plasma, fluorine ions from the remote plasma gradually diffuse into the semiconductor layer 311 based on the concentration gradient, resulting in a small amount of fluorine doping into the semiconductor layer 311 and thus achieving a shallow doping depth. Subsequently, by annealing the fluoropolymer layer 51 and the insulating capping layer 52, the semiconductor layer 311 achieves a deeper doping depth, allowing the fluorine doping to reach the source and drain portions of the transistor 31, thus connecting the doped channels of the transistor 31. Based on different device requirements, one of the above two doping schemes can be selectively used, or they can be used in combination, providing multiple selection modes according to the needs of semiconductor devices, thereby improving the performance of semiconductor devices.

[0140] The fluoropolymer layer 51 is composed entirely of carbon and fluorine elements and contains no hydrogen. Using a hydrogen-free fluorocarbon polymer for doping can prevent hydrogen penetration, avoid damage to the semiconductor layer 311 by hydrogen, and ensure the stability of the electrical properties of the semiconductor layer 311.

[0141] Due to the wafer loading effect, the fluoropolymer layer 51 is mainly deposited on the sidewall of the second via 62 and will not or will enter the lateral first channel 111 in small quantities. This results in the semiconductor layer 311 covering the sidewall of the first channel 111 being undoped or having a low doping concentration, which facilitates the removal of the semiconductor layer 311 parasitizing between any two bit lines 120 and between any two first electrode plates 421 in subsequent steps.

[0142] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0143] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0144] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0145] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0146] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: An initial insulating layer and an initial sacrificial layer are sequentially and alternately fabricated on one side of the substrate to obtain an initial stacked structure; A first through-hole, a second through-hole, and a trench are formed that penetrate the initial stacked structure and are sequentially distributed in a first direction; The initial sacrificial layers on both sides of the trench are replaced with multiple bit lines extending along a second direction; the second direction intersects the first direction and is parallel to the substrate. Replace the multiple layers of the initial insulating layer surrounding the second through hole with multiple layers of the first sacrificial layer; Based on the second via, a portion of each of the first sacrificial layers is laterally etched to form a plurality of first channels that communicate with the second via and are spaced apart along a third direction perpendicular to the substrate. A conformal semiconductor layer is formed covering the second via and each of the first channels, and fluorine is doped at the sidewall of the second via using remote plasma. A gate insulating layer and word lines are sequentially formed to cover and fill the first channel and the second via; Based on the first via and the trench, the semiconductor layer located on the sidewall of the first channel is laterally etched to obtain a multilayer transistor.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Fluorine doping of the semiconductor layer at the sidewall of the second via using remote plasma includes at least one of the following: The system filters out charged ions with physical bombardment capabilities from the remote plasma, and then performs fluorine doping on the semiconductor layer during the contact process between the filtered remote plasma and the semiconductor layer at the sidewall of the second via. A fluoropolymer layer covering the semiconductor layer at the sidewall of the second via is formed using a remote plasma doping process. The semiconductor layer covered by the fluorinated polymer layer is doped with fluorine using an annealing process; the residual fluorinated polymer layer is then removed.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The fluoropolymer layer is made of fluorocarbon polymers and does not contain hydrogen.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Forming a first through-hole, a second through-hole, and a trench that penetrate the initial stacked structure and are sequentially distributed in a first direction, including: A plurality of first through holes and a plurality of second through holes are formed through the initial stacked structure and are respectively arranged in an array; at least one first through hole and at least one second through hole are arranged alternately in pairs in the first direction, and the plurality of second through holes and the plurality of first through holes are arranged sequentially at intervals along the second direction; A first isolation layer is formed to conformally cover the first through-hole and the second through-hole; a second sacrificial layer is formed to fill the first through-hole and the second through-hole; and a first protective layer is formed to cover the first isolation layer, the second sacrificial layer and the initial stacked structure. A plurality of grooves are formed that penetrate the initial stacked structure and are distributed sequentially at intervals in the first direction and each extends along the second direction, the grooves being located between two adjacent second through holes in the first direction.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The exposed initial sacrificial layers on the trench sidewalls are replaced with multiple bit lines, each extending along a second direction, including: Based on the lateral etching of the initial sacrificial layer in the trench, a multi-layered second channel is formed, which is spaced apart along the third direction and extends along the second direction. Multiple bit lines are formed to fill the second channel, the bit lines at least covering the first isolation layer and the portion of the initial insulating layer exposed in the second channel.

6. The method for manufacturing a semiconductor device according to claim 4, characterized in that, After replacing the multiple initial sacrificial layers exposed on the trench sidewalls with multiple bit lines extending along the second direction, and before replacing the multiple initial insulating layers surrounding the second via with multiple first sacrificial layers, the process includes: The multilayer initial sacrificial layer surrounding the first through hole is replaced with a multilayer first electrode plate.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The initial sacrificial layer surrounding the first through-hole is replaced with a multilayer first electrode plate, including: Based on dry etching, a portion of the second sacrificial layer located within the first via is removed; Based on wet etching, the second sacrificial layer remaining in the first via and the first isolation layer located on the sidewall of the first via are removed. Based on the first via, the initial sacrificial layer is laterally etched until the first isolation layer located in the second via is exposed, forming a multilayer third channel spaced apart along the third direction; A first electrode plate is formed to conformally cover the third channel, and a capacitor sacrificial layer is formed to fill the third channel.

8. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The multiple layers of initial insulating layer surrounding the second through-hole are replaced with multiple layers of first sacrificial layer, including: Based on dry etching, a portion of the second sacrificial layer located within the second via is removed; Based on wet etching, the second sacrificial layer remaining in the second via and the first isolation layer located on the sidewall of the second via are removed; Based on the second through-hole, the initial insulating layer is laterally etched to form a multilayer fourth channel arranged at intervals; A conformal layer is formed covering the sidewall of the second through-hole and the first sacrificial layer filling the fourth channel.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, Based on the first via and the trench, the semiconductor layer located on the sidewall of the first channel is laterally etched to obtain a multilayer transistor, including: Through the first via and the trench, multiple layers of the first sacrificial layer are laterally etched until the semiconductor layer in the fourth channel is exposed. The semiconductor layer in the fourth channel is etched laterally to obtain the multilayer transistor.

10. The method for manufacturing a semiconductor device according to claim 7, characterized in that, Based on the first via and the trench, the semiconductor layer located on the sidewall of the first channel is laterally etched to obtain a multilayer transistor, followed by: The capacitor sacrificial layer located within the multilayer third channel and the initial insulating layer located on the substrate-facing side and the substrate-removing side of the multilayer third channel are removed based on the first via. A capacitor dielectric material, a conductive material, and a filling material are deposited sequentially to form a capacitor dielectric layer and a second electrode that sequentially conformally cover and fill the third channel and the first through hole; the first electrode, the capacitor dielectric layer, and the second electrode form a capacitor.

11. A semiconductor device, characterized in that, include: Word lines, disposed on one side of the substrate, include gates of multilayer transistors spaced apart along a third direction perpendicular to the substrate and connection lines located between any two adjacent gates; A gate insulating layer is disposed around the periphery of the gate; A multilayer semiconductor layer, wherein each semiconductor layer corresponds to a gate and is wound around the periphery of the gate insulating layer, and the semiconductor layer is doped with fluorine by remote plasma; Multiple bit lines, each extending along the second direction; A multilayer first electrode plate is located on the side of the semiconductor layer away from the bit line, and the bit line and the first electrode plate are electrically connected to both ends of the semiconductor layer of the transistor.

12. The semiconductor device according to claim 11, characterized in that, Each layer of transistors includes a plurality of transistors arranged in an array in a first direction and a second direction, wherein the plurality of transistors arranged sequentially in the second direction share a bit line; The semiconductor device further includes a capacitor dielectric layer and a second electrode that sequentially conformally cover the inner wall and part of the outer wall of the first electrode. The first electrode, the capacitor dielectric layer and the second electrode form a capacitor, and the plurality of capacitors correspond one-to-one with the plurality of transistors.

13. An electronic device, characterized in that, include: Semiconductor devices manufactured using the manufacturing method as described in any one of claims 1 to 10; or, The semiconductor device as described in any one of claims 11 to 12.

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