Semiconductor device, method for manufacturing semiconductor device, and storage system

Abstract

The present disclosure relates to the technical field of semiconductor, and particularly relates to a semiconductor device, a manufacturing method of the semiconductor device and a storage system. The semiconductor device comprises a first gate structure, a second gate structure and a semiconductor column, the semiconductor column extends along a first direction, and the first gate structure and the second gate structure are respectively arranged on two sides of the semiconductor column along a second direction; the first gate structure comprises a first conductive layer and a second conductive layer located on at least one side of the first conductive layer along the first direction; wherein the first direction is perpendicular to the second direction. Since the first gate structure comprises the first conductive layer and the second conductive layer located on at least one side of the first conductive layer along the first direction, compared with the first gate structure of a single material, the off-state channel leakage current and the gate-induced drain-end leakage current can be simultaneously optimized, the risk of generating the leakage current is reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing a semiconductor device, and a memory system. Background Technology

[0002] Dynamic Random Access Memory (DRAM) consists of multiple memory cells. With the continuous optimization of DRAM manufacturing processes, the integration density is constantly increasing and the component size is constantly shrinking, the leakage current in DRAM needs to be further reduced. Summary of the Invention

[0003] The purpose of this disclosure is to provide a semiconductor device, a method for manufacturing a semiconductor device, and a storage system to reduce leakage current and improve the reliability of the semiconductor device.

[0004] To achieve the above objectives, this disclosure provides a semiconductor device including a first gate structure, a second gate structure, and a semiconductor pillar, wherein the semiconductor pillar extends along a first direction, and the first gate structure and the second gate structure are respectively disposed on both sides of the semiconductor pillar along a second direction; the first gate structure includes a first conductive layer and a second conductive layer located on at least one side of the first conductive layer along the first direction; wherein the first direction is perpendicular to the second direction.

[0005] In one embodiment of this disclosure, the work function of the second conductive layer is different from the work function of the first conductive layer.

[0006] In one embodiment of this disclosure, the number of semiconductor pillars is multiple; along the second direction, the first gate structure is located between two adjacent semiconductor pillars, or two second gate structures are disposed between two adjacent semiconductor pillars.

[0007] In one embodiment of this disclosure, a second conductive layer is disposed on both sides of the first conductive layer along the first direction, and the work function of the second conductive layer is less than the work function of the first conductive layer.

[0008] In one embodiment of this disclosure, the second conductive layer includes at least two sublayers, wherein, among two adjacent sublayers, the work function of the sublayer closer to the first conductive layer is greater than the work function of the sublayer farther from the first conductive layer.

[0009] In one embodiment of this disclosure, the material of the first conductive layer includes titanium nitride, and the material of the second conductive layer includes doped polycrystalline silicon.

[0010] In one embodiment of this disclosure, the thickness of the first conductive layer is greater than the thickness of the second conductive layer along the first direction.

[0011] In one embodiment of this disclosure, the semiconductor device further includes a capacitor and a conductive structure; along the first direction, the semiconductor pillar has opposing first and second ends, the first end of the semiconductor pillar being connected to the capacitor, and the second end of the semiconductor pillar being connected to the conductive structure.

[0012] In one embodiment of this disclosure, along a third direction, the length of the first gate structure is less than the length of the second gate structure; wherein, the third direction is perpendicular to both the first direction and the second direction.

[0013] In one embodiment of this disclosure, an oxide layer is disposed between the first gate structure and the semiconductor pillar.

[0014] To achieve the above objectives, this disclosure also provides a method for manufacturing a semiconductor device, comprising: forming a semiconductor pillar extending along a first direction; forming a first gate structure including a first conductive layer and a second conductive layer located on at least one side of the first conductive layer along the first direction; and forming a second gate structure along a second direction, wherein the second gate structure and the first gate structure are respectively located on opposite sides of the semiconductor pillar, wherein the second direction is perpendicular to the first direction.

[0015] In one embodiment of this disclosure, forming the first gate structure includes: providing a substrate;

[0016] A first groove is formed on one side of the substrate, the depth direction of the first groove being consistent with the first direction; a first conductive layer and a second conductive layer are formed in the first groove, wherein the work function of the first conductive layer is different from the work function of the second conductive layer.

[0017] In one embodiment of this disclosure, forming a first conductive layer and a second conductive layer within the first groove includes: forming the second conductive layer on the side of the first conductive layer near the bottom of the first groove, and / or forming the second conductive layer on the side of the first conductive layer away from the bottom of the first groove; wherein the work function of the second conductive layer is less than the work function of the first conductive layer.

[0018] In one embodiment of this disclosure, forming a first conductive layer and a second conductive layer within the first groove includes: forming a second conductive layer within the first groove, the second conductive layer being close to the bottom of the first groove; forming a first conductive layer on the side of the second conductive layer away from the bottom of the first groove; and forming a second conductive layer on the side of the first conductive layer away from the bottom of the first groove; wherein the second conductive layer close to the bottom of the first groove is a first sub-conductive layer, and the second conductive layer away from the bottom of the first groove is a second sub-conductive layer.

[0019] In one embodiment of this disclosure, forming the first sub-conductive layer includes: sequentially forming a plurality of first sub-layers within the first groove, wherein, among two adjacent first sub-layers, the work function of the first sub-layer farther from the bottom of the first groove is greater than the work function of the first sub-layer closer to the bottom of the first groove, wherein the plurality of first sub-layers form the first sub-conductive layer.

[0020] In one embodiment of this disclosure, forming the second sub-conductive layer includes: forming a plurality of second sub-layers on the side of the first conductive layer away from the bottom of the first groove, wherein in two adjacent second sub-layers, the work function of the second sub-layer away from the first conductive layer is less than the work function of the second sub-layer close to the first conductive layer, wherein the plurality of second sub-layers form the second sub-conductive layer.

[0021] In one embodiment of this disclosure, the method for manufacturing the semiconductor device further includes: forming a capacitor connected to a first end of the semiconductor pillar; and forming a conductive structure connected to a second end of the semiconductor pillar.

[0022] In view of the above objectives, this disclosure also provides a storage system including a controller and the semiconductor device, wherein the controller is coupled to the semiconductor device and controls the semiconductor device.

[0023] The main beneficial effects of this disclosure are:

[0024] The semiconductor device provided in this disclosure has a first gate structure and a second gate structure respectively disposed on both sides of a semiconductor pillar along a second direction. Since the first gate structure includes a first conductive layer and a second conductive layer located on at least one side of the first conductive layer along a first direction, compared with a first gate structure made of a single material, it can simultaneously optimize the off-state channel leakage current and the gate-induced drain current, reduce the risk of leakage current generation, and improve the performance of the semiconductor device.

[0025] The semiconductor device manufacturing method disclosed herein forms a first gate structure and a second gate structure on both sides of a semiconductor pillar along a second direction. The first gate structure includes a first conductive layer and a second conductive layer located on at least one side of the first conductive layer along a first direction. Compared with a first gate structure made of a single material, it can simultaneously optimize the off-state channel leakage current and the gate-induced drain current, reduce the risk of leakage current generation, and improve the performance of the semiconductor device. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0028] Figure 2 for Figure 1 A magnified view of a section at point A in the middle;

[0029] Figure 3 Another schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure;

[0030] Figure 4 for Figure 3 The E-direction view in the middle;

[0031] Figure 5 A schematic diagram of a third structure of a semiconductor device provided in this disclosure embodiment;

[0032] Figure 6 for Figure 5 A magnified view of a section at point B in the middle;

[0033] Figure 7 A fourth structural schematic diagram of a semiconductor device provided in this disclosure embodiment;

[0034] Figure 8 A fifth structural schematic diagram of a semiconductor device provided in this disclosure embodiment;

[0035] Figure 9 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0036] Figures 10 to 21 This is a partial structural schematic diagram of a semiconductor structure formed after performing certain steps in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0037] Figure 22 This is a block diagram of an exemplary system with a memory according to an embodiment of this disclosure;

[0038] Figure 23A An exemplary block diagram of a storage system is shown;

[0039] Figure 23B A block diagram of another storage system is shown as an example. Detailed Implementation

[0040] The technical solutions of this disclosure will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0041] Generally, terms can be understood, at least in part, based on their use in context. For example, the term "one or more," depending at least in part on the context, can be used to describe any feature, structure, or characteristic in the singular or in the plural form to describe a combination of features, structures, or characteristics. Similarly, terms such as "a" or "described" in this document can also be understood, at least in part on the context, to convey either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again, depending at least in part on the context.

[0042] It should be readily understood that, in the description of this disclosure, it is necessary to clarify that the meanings of “on,” “above,” and “above” should be interpreted in the broadest sense, such that “on” not only means “directly on” something, but also includes the meaning of being “on” something with an intermediate feature or layer between them. Furthermore, “above” or “above” not only means “on” or “above” something, but can also include it being “on” or “above” something without an intermediate feature or layer between them (i.e., directly on something).

[0043] Furthermore, for ease of description, this document uses spatially relative terms such as "below," "below," "lower layer," "above," "upper layer," etc., to describe the relationship between one element or feature and another element or feature as shown in the figure. Spatially related terms are intended to include different orientations of the device in use or process steps (in addition to the orientation shown in the figure). The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted accordingly.

[0044] In the description of this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. A substrate includes a front side and a back side. The front side of the substrate is typically where a semiconductor device is formed; unless otherwise stated, the semiconductor device is formed on the front side of the substrate, and the back side is opposite to the front side. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0045] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend integrally over the structure of a bottom or upper layer, or may have a range smaller than that of the bottom or upper layer. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect pathways are formed) and one or more dielectric layers.

[0046] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate.

[0047] See Figures 1 to 8 As shown, this embodiment provides a semiconductor device including a first gate structure 111, a second gate structure 112, and a semiconductor pillar 113. The semiconductor pillar 113 extends along a first direction, and the first gate structure 111 and the second gate structure 112 are respectively disposed on both sides of the semiconductor pillar 113 along a second direction. The first gate structure 111 includes a first conductive layer 1111 and a second conductive layer 1112 located on at least one side of the first conductive layer 1111 along the first direction. Figure 1 The arrow direction D1 indicates the direction of the second direction (indicated by the arrow in the image). Figure 1 The arrow in the image (D2) indicates that the direction is perpendicular.

[0048] The semiconductor device provided in this embodiment has a first gate structure and a second gate structure respectively disposed on both sides of a semiconductor pillar along a second direction. Since the first gate structure includes a first conductive layer and a second conductive layer located on at least one side of the first conductive layer along a first direction, compared with a first gate structure made of a single material, it can simultaneously optimize the off-state channel leakage current and the gate-induced drain current, reduce the risk of leakage current generation, and improve the performance of the semiconductor device.

[0049] For example, the semiconductor device can be a dynamic random access memory (DRAM), such as 4F. 2 DRAM, the cell area of ​​which is four times the feature size F; the semiconductor pillars may include the channel structure 1133 of the vertical transistor 11 and the source region 1131 and drain region 1132 located at both ends of the channel structure 1133, wherein the drain regions of two adjacent semiconductor pillars may be connected together, the first gate structure 111 may serve as the back gate of the vertical transistor, and the second gate structure 112 may serve as the positive gate of the vertical transistor.

[0050] The back gate modulation mainly affects two leakage mechanisms of vertical transistors: off-state channel leakage current and gate-induced drain current. For a conductive material with a certain work function, the work function has opposite effects on the two leakage mechanisms. That is, when a conductive material that is conducive to reducing gate-induced drain current is selected, the off-state channel leakage current will increase; when a conductive material that is conducive to reducing off-state channel leakage current is selected, the gate-induced drain current will increase.

[0051] In order to simultaneously optimize the off-state channel leakage current and the gate-induced drain current, the work function of the second conductive layer 1112 in this embodiment is different from the work function of the first conductive layer 1111.

[0052] For example, the work function of the second conductive layer 1112 is less than that of the first conductive layer 1111. When the second conductive layer 1112 is located on either side of the first conductive layer 1111, it effectively reduces the work function of the conductive material near the source region 1131 or drain region 1132 of the vertical transistor, thereby making it less likely to generate a high electric field and reducing leakage current. For example, see... Figure 7 As shown, within the field of view, the second conductive layer 1112 is located below the first conductive layer 1111, which effectively reduces the work function of the conductive material near the drain region 1132 of the vertical transistor; for example, see... Figure 8 As shown, within the field of view, the second conductive layer 1112 is located above the first conductive layer 1111, which is equivalent to reducing the work function of the conductive material near the source region 1131 of the vertical transistor.

[0053] When the second conductive layer 1112 is located on both sides of the first conductive layer 1111, it is equivalent to simultaneously reducing the work function of the conductive material near the source region 1131 and the drain region 1132 of the vertical transistor, thereby ensuring that high electric fields are not easily generated at both ends of the vertical transistor and reducing leakage current.

[0054] In one embodiment, see Figure 1 As shown, there are multiple semiconductor pillars 113; along the second direction, a first gate structure 111 is located between two adjacent semiconductor pillars 113, or two second gate structures 112 are disposed between two adjacent semiconductor pillars 113.

[0055] Figure 1 The diagram shows four semiconductor pillars arranged along the second direction. Taking the two middle semiconductor pillars as an example, along the second direction, the first gate structure 111 is located between two adjacent semiconductor pillars 113. Taking the two right semiconductor pillars as an example, two second gate structures 112 are provided between the two adjacent semiconductor pillars 113.

[0056] See Figure 2 As shown, Figure 2 for Figure 1 A magnified view of a portion of point A in the middle. Figure 2 The diagram shows the main structure of a vertical transistor 11, see [link / reference]. Figure 1 and Figure 2 As shown, the first gate structures 111 of two adjacent vertical transistors are connected together. In the process of fabrication, the first gate structures 111 of the two vertical transistors can be fabricated simultaneously.

[0057] In one embodiment, see Figure 2 As shown, along the first direction, a second conductive layer is provided on both sides of the first conductive layer 1111. Within the field of view, the second conductive layer located below the first conductive layer 1111 is named the first sub-conductive layer 1112a, and the second conductive layer located above the first conductive layer 1111 is named the second sub-conductive layer 1112b. The work functions of the first sub-conductive layer 1112a and the second sub-conductive layer 1112b are both less than the work function of the first conductive layer 1111. This can simultaneously reduce the work function of the conductive material near the source region 1131 and the drain region 1132 of the vertical transistor, thereby ensuring that high electric fields are not easily generated at both ends of the vertical transistor and reducing leakage current.

[0058] In one embodiment, the thickness of the first conductive layer is greater than the thickness of the second conductive layer along the first direction.

[0059] By using a thinner second conductive layer, the leakage current of the vertical transistor can be reduced without sacrificing the on-state current as much as possible.

[0060] It should be noted that when a second conductive layer is provided on both sides of the first conductive layer 1111, the thickness of the first sub-conductive layer 1112a and the thickness of the second sub-conductive layer 1112b can be the same or different.

[0061] In one embodiment, the material of the first conductive layer 1111 includes titanium nitride, and the material of the second conductive layer 1112 includes doped polycrystalline silicon.

[0062] For example, the doping element in the doped polycrystalline silicon can be one or more of phosphorus, boron, aluminum and titanium, among others.

[0063] In one embodiment, the second conductive layer includes at least two sublayers, wherein the work function of the sublayer closer to the first conductive layer 1111 is greater than that of the sublayer farther from the first conductive layer 1111. This allows the work function of the second conductive layer to form a gradient change along the first direction from the middle to both ends (source region and drain region), further reducing the impact on the on-state current.

[0064] For example, see Figure 5 and Figure 6 As shown, the first sub-conductive layer 1112a and the second sub-conductive layer 1112b each include two sub-layers. The two sub-layers of the first sub-conductive layer 1112a are named the first material layer 11121 and the second material layer 11122, respectively. The two sub-layers of the second sub-conductive layer 1112b are named the third material layer 11123 and the fourth material layer 11124, respectively. The first material layer 11121 is far from the first conductive layer 1111, and the second material layer 11122 is close to the first conductive layer 1111. That is, the second material layer 11122 is located between the first material layer 11121 and the first conductive layer 1111, and the work function of the second material layer 11122 is greater than the work function of the first material layer 11121. The third material layer 11123 is close to the first conductive layer, and the fourth material layer 11124 is far from the first conductive layer. That is, the third material layer 11123 is located between the fourth material layer 11124 and the first conductive layer 1111, and the work function of the third material layer 11123 is greater than the work function of the fourth material layer 11124.

[0065] It should be noted that the work function of the first material layer and the work function of the fourth material layer may be the same or different, and the work function of the second material layer and the work function of the third material layer may be the same or different.

[0066] It should also be noted that, along the first direction, the thickness of the first material layer and the thickness of the fourth material layer can be the same or different, and the thickness of the second material layer and the thickness of the third material layer can be the same or different.

[0067] In one embodiment, see Figure 3As shown, the semiconductor device also includes a capacitor 12 and a conductive structure 30; along the first direction, the semiconductor pillar 113 has a first end and a second end opposite to each other, the first end of the semiconductor pillar 113 is connected to the capacitor 12, and the second end of the semiconductor pillar 113 is connected to the conductive structure 30.

[0068] For example, the first end of the semiconductor pillar 113 can serve as the source and be connected to the capacitor 12, and the second end of the semiconductor pillar 113 can serve as the drain and be connected to the conductive structure 30 (e.g., a bit line).

[0069] For example, a capacitor 12 and a vertical transistor 11 together form a memory cell, and multiple memory cells can form a memory array 100.

[0070] See Figure 3 As shown, the semiconductor device also includes peripheral circuitry 40, which can be formed on a complementary metal-oxide-semiconductor wafer. The peripheral circuitry includes multiple transistors, such as horizontal transistors. Peripheral circuitry 40 is bonded to memory array 100 for bringing out a first gate structure 111 (e.g., a back gate), a second gate structure 112 (e.g., a positive gate), and conductive structures 30 (e.g., bit lines).

[0071] In one embodiment, see Figure 4 As shown, along the third direction (indicated by arrow direction D3), the length of the first gate structure 111 is less than the length of the second gate structure 112; wherein, the third direction is perpendicular to both the first and second directions.

[0072] In one embodiment, see Figure 1 As shown, an oxide layer 1113 is disposed between the first gate structure 111 and the semiconductor pillar 113.

[0073] It should be noted that, Figure 3 and Figure 4 The oxide layer between the first gate structure 111 and the semiconductor pillar 113 is not shown.

[0074] It should be understood that in the actual structure, due to the presence of the oxide layer, the first gate structure 111 and the second gate structure 112 will not appear simultaneously in the same cross-section. Therefore, Figure 4 It can be viewed as a perspective view rather than a cross-sectional view, in order to illustrate the length relationship of the first gate structure 111 and the second gate structure 112 in the third direction.

[0075] See Figure 9 As shown, this embodiment also provides a method for manufacturing a semiconductor device, which may include the following steps:

[0076] Step S902: Form semiconductor pillar 113, which extends along a first direction;

[0077] Step S904: A first gate structure 111 is formed. The first gate structure 111 includes a first conductive layer 1111 and a second conductive layer 1112 located on at least one side of the first conductive layer 1111 along a first direction.

[0078] In step S906, a second gate structure 112 is formed. Along the second direction, the second gate structure 112 and the first gate structure 111 are located on both sides of the semiconductor pillar 113, wherein the second direction is perpendicular to the first direction.

[0079] The semiconductor device manufacturing method provided in this embodiment forms a first gate structure and a second gate structure on both sides of a semiconductor pillar along a second direction. The first gate structure 111 includes a first conductive layer 1111 and a second conductive layer 1112 located on at least one side of the first conductive layer 1111 along a first direction. Compared with a first gate structure made of a single material, it can simultaneously optimize the off-state channel leakage current and the gate-induced drain current, reduce the risk of leakage current generation, and improve the performance of the semiconductor device.

[0080] It should be understood that, Figure 9 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 9 The steps shown can be adjusted in order according to actual needs. Figures 10 to 21 This is a partial structural schematic diagram of a semiconductor structure formed after performing certain steps in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. The following is in conjunction with... Figure 9 , Figures 10 to 21 The method for manufacturing a semiconductor device provided in the embodiments of this disclosure will be described in detail.

[0081] In step S902, the semiconductor pillar 113 is formed, including: providing a substrate 200; forming a channel structure 1133 and a source region 1131 and a drain region 1132 located at both ends of the channel structure.

[0082] In some embodiments, the material of the semiconductor pillar 113 may be the same as the material of the substrate, so there is no obvious interface between the semiconductor pillar and the substrate.

[0083] In other embodiments, the channel structure may also be made of indium gallium zinc oxide.

[0084] In some embodiments, the provided substrate 200 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0085] It should be understood that substrate 200 can be retained, removed, or thinned.

[0086] In one embodiment, step S904, forming a first gate structure 111, includes: providing a substrate 200; forming a first groove 1110 on one side of the substrate 200, the depth direction of the first groove 1110 being consistent with a first direction; forming a first conductive layer 1111 and a second conductive layer 1112 within the first groove 1110, wherein the work function of the first conductive layer 1111 is different from the work function of the second conductive layer 1112.

[0087] For example, the substrate 200 provided can be the substrate 200 in step S702 in which semiconductor pillars 113 are formed.

[0088] For example, see Figure 10 As shown, an etching process is used to form a first groove 1110 on one side of the substrate 200. The first groove 1110 is located between the two channel structures 1133. The method for forming the first conductive layer 1111 and the second conductive layer 1112 in the first groove 1110 can be one or a combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0089] In some exemplary processes prior to depositing the first conductive layer 1111 and the second conductive layer 1112 in the first groove 1110, an oxide material is deposited on the bottom and walls of the first groove to form an oxide layer 1113.

[0090] In some embodiments, forming a first conductive layer 1111 and a second conductive layer 1112 within a first groove 1110 includes: forming a second conductive layer 1112 within a first groove 1110, the second conductive layer 1112 being close to the bottom of the first groove 1110; forming a first conductive layer 1111 on the side of the second conductive layer 1112 away from the bottom of the first groove 1110; and forming a second conductive layer 1112 on the side of the first conductive layer 1111 away from the bottom of the first groove 1110; wherein the second conductive layer close to the bottom of the first groove 1110 is named a first sub-conductive layer 1112a, the second conductive layer away from the bottom of the first groove 1110 is named a second sub-conductive layer 1112b, and the work function of the second conductive layer is less than the work function of the first conductive layer 1111.

[0091] For example, see Figure 11As shown, a first conductive material is deposited in the first groove 1110, and the first conductive material fills the first groove 1110. Then, an etching process is used to etch the first conductive material back from the groove opening of the first groove. At this time, the retained first conductive material is located at the bottom of the first groove, serving as the first sub-conductive layer 1112a.

[0092] See Figure 12 As shown, a second conductive material is deposited on the side of the first sub-conductive layer 1112a away from the bottom of the first groove. The second conductive material fills the remaining space of the first groove. Then, an etching process is used to etch the second conductive material back from the groove opening of the first groove. At this time, the retained second conductive material serves as the first conductive layer 1111. The work function of the first conductive material is less than that of the second conductive material.

[0093] See Figure 13 As shown, a third conductive material is deposited on the side of the first conductive layer 1111 away from the first sub-conductive layer 1112a. The third conductive material fills the remaining space of the first groove. Then, an etching process is used to etch the third conductive material back from the groove opening of the first groove. At this time, the retained third conductive material serves as the second sub-conductive layer 1112b.

[0094] See Figure 14 As shown, oxide material is deposited in the remaining space of the first groove.

[0095] It should be understood that the third conductive material may be the same as or different from the first conductive material. Along the first direction, the thickness of the first sub-conductive layer 1112a and the thickness of the second sub-conductive layer 1112b may both be less than the thickness of the first conductive layer 1111, and the thickness of the first sub-conductive layer 1112a and the thickness of the second sub-conductive layer 1112b may be the same or different.

[0096] In other embodiments, a first conductive layer 1111 may be deposited in the first groove 1110 first, then a portion of the first conductive layer may be etched back, and then a second conductive layer 1112 may be deposited; or a second conductive layer 1112 may be deposited in the first groove 1110 first, then a portion of the second conductive layer may be etched back, and then a first conductive layer 1111 may be deposited.

[0097] In one embodiment, the first sub-conductive layer and the second sub-conductive layer may be made of a single material.

[0098] In other embodiments, the first sub-conductive layer and the second sub-conductive layer may also comprise at least two materials with different work functions.

[0099] Specifically, when the first sub-conductive layer 1112a includes at least two materials with different work functions, forming the first sub-conductive layer 1112a includes: sequentially forming a plurality of first sub-layers in the first groove 1110, wherein in two adjacent first sub-layers, the work function of the first sub-layer farther from the bottom of the first groove 1110 is greater than the work function of the first sub-layer closer to the bottom of the first groove 1110, wherein the plurality of first sub-layers form the first sub-conductive layer 1112a.

[0100] For example, see Figure 15 As shown, the first sub-conductive layer 1112a includes two first sub-layers, which are named the first material layer 11121 and the second material layer 11122, respectively. The first material layer 11121 is far away from the first conductive layer 1111, and the second material layer 11122 is close to the first conductive layer 1111. That is, the second material layer 11122 is located between the first material layer 11121 and the first conductive layer 1111. The work function of the second material layer 11122 is greater than the work function of the first material layer 11121.

[0101] See Figure 16 As shown, a first conductive layer 1111 is formed on the side of the second material layer away from the first material layer.

[0102] When the second sub-conductive layer 1112b comprises at least two materials with different work functions, the formation of the second sub-conductive layer 1112b includes: forming a plurality of second sub-layers on the side of the first conductive layer 1111 away from the bottom of the first groove 1110, wherein in two adjacent second sub-layers, the work function of the second sub-layer away from the first conductive layer 1111 is less than the work function of the second sub-layer close to the first conductive layer 1111, wherein the plurality of second sub-layers form the second sub-conductive layer 1112b.

[0103] For example, see Figure 17 As shown, the second sub-conductive layer 1112b includes two second sub-layers, named the third material layer 11123 and the fourth material layer 11124, respectively. The third material layer 11123 is close to the first conductive layer, and the fourth material layer 11124 is far from the first conductive layer. That is, the third material layer 11123 is located between the fourth material layer 11124 and the first conductive layer 1111. The work function of the third material layer 11123 is greater than that of the fourth material layer 11124. After the etching is completed, a remaining space is formed between the fourth material layer 11124 and the groove opening of the first groove.

[0104] See Figure 18 As shown, oxide material is deposited in the remaining space of the first groove.

[0105] In one embodiment, in step S906, forming a second gate structure 112 includes: forming a second groove on one side of the substrate 200, wherein the second groove and the first groove 1110 are respectively on both sides of the semiconductor pillar 113, wherein two second grooves are formed between two adjacent semiconductor pillars 113; and forming a second gate structure 112 in the second groove.

[0106] It should be understood that the first groove and the second groove are not located simultaneously between two adjacent semiconductor pillars.

[0107] For example, the second groove and the first groove can be formed in the same process. After forming the first groove and the second groove, see [link to documentation]. Figure 10 As shown, an oxide layer 1113 is deposited on the bottom and walls of the first groove 1110, and an oxide material is filled in the second groove.

[0108] After the first gate structure is fabricated, a portion of the oxide material in the second groove is removed, and conductive material is deposited on the groove walls and bottom of the second groove. The conductive material deposited on the bottom is then removed, thus forming the second gate structure on each of the two groove walls. (See [link to documentation]). Figure 1 As shown, oxide material is also formed between two adjacent second gate structures 112 and between the second gate structure 112 and the semiconductor pillar 113.

[0109] In one embodiment, see Figure 19 As shown, the method for manufacturing a semiconductor device further includes: forming a capacitor 12, the capacitor 12 being connected to a first end of a semiconductor pillar 113; and forming a conductive structure 30, the conductive structure 30 being connected to a second end of the semiconductor pillar 113.

[0110] For example, the first end of the semiconductor pillar 113 can serve as the source and be connected to the capacitor 12, and the second end of the semiconductor pillar 113 can serve as the drain and be connected to the conductive structure 30 (e.g., a bit line).

[0111] In some embodiments, when fabricating a transistor, the second ends of two adjacent semiconductor pillars 113 are connected together.

[0112] In one embodiment, see Figure 20 and Figure 21 As shown, the method for manufacturing a semiconductor device further includes: providing peripheral circuitry 40 and bonding peripheral circuitry 40 to memory array 100.

[0113] For example, peripheral circuitry can be formed on a complementary metal-oxide-semiconductor wafer. Peripheral circuitry includes multiple transistors, such as horizontal transistors. Peripheral circuitry 40 is bonded to memory array 100 to bring out a first gate structure 111 (e.g., a back gate), a second gate structure 112 (e.g., a positive gate), and conductive structures 30 (e.g., bit lines).

[0114] It should be noted that, Figures 19 to 21 The oxide layer between the first gate structure 111 and the semiconductor pillar 113 is not shown in the diagram.

[0115] It should be noted that the semiconductor device provided in this embodiment can be manufactured using the semiconductor device manufacturing method provided in this embodiment.

[0116] This embodiment also provides a storage system, including a controller and a semiconductor device provided in this embodiment. The controller is coupled to the semiconductor device and controls the semiconductor device.

[0117] Figure 22 The diagram shown is a block diagram of an exemplary system with a storage system according to this embodiment. System 300 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or any other suitable electronic device having memory therein.

[0118] See Figure 22 As shown, system 300 may include host 308 and storage system 302, storage system 302 having controller 306 and one or more memories 304. Memory 304 may be a semiconductor device as provided in this embodiment; host 308 may be a processor (e.g., central processing unit (CPU)) or system-on-a-chip (SoC) (e.g., application processor) of an electronic device. Host 308 may be configured to send data to memory 304, or receive data from memory 304.

[0119] In this embodiment, memory 304 can be any type of memory, such as volatile memory. Volatile memory can be dynamic random access memory (DRAM).

[0120] In some embodiments, controller 306 is coupled to memory 304 and host 308 and is configured to control memory 304. Controller 306 can manage data stored in memory 304 and communicate with host 308.

[0121] In some embodiments, the controller 306 is configured to send a command to the memory 304 to cause the memory 304 to perform a memory operation method.

[0122] In some embodiments, the controller 306 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0123] In some embodiments, controller 306 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which can be used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. Controller 306 can be configured to send commands to memory 304 to cause memory 304 to perform operations, such as read, erase, and program operations.

[0124] The controller 306 can also be configured to manage various functions related to data stored or to be stored in the memory 304, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0125] In some embodiments, controller 306 is also configured to process error correction codes (ECC) regarding data read from or written to memory 304. Controller 306 may also perform any other suitable functions, such as formatting memory 304. Controller 306 may communicate with external devices (e.g., host 308) according to specific communication protocols. For example, controller 306 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0126] The controller 306 and one or more memories 304 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 302 can be implemented and packaged into different types of end electronic products.

[0127] Figure 23A A block diagram of a memory system is shown as an example. See also Figure 23AAs shown, controller 306 and a single memory 304 can be integrated into memory card 232. Memory card 232 may include PC cards (also known as PCMCIA cards, Personal Computer Memory Card International Association cards), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (such as MMC cards, RS-MMC cards, MMCmicro cards, etc.), SD cards (such as SD cards, miniSD cards, microSD cards, SDHC cards, etc.), UFS cards, etc. Memory card 232 may also include a connector for connecting memory card 232 to a host computer (e.g., Figure 22 The memory card connector 234 is coupled to the host 308.

[0128] Figure 23B A block diagram of another memory system is shown as an example. See also Figure 23B As shown, controller 306 and multiple memories 304 can be integrated into SSD 236. SSD 236 may also include a connection between SSD 236 and a host (e.g., Figure 22 The SSD connector 238 is coupled to the host 308 in the memory card 232. In some embodiments, the storage capacity and / or operating speed of the SSD 236 is greater than the storage capacity and / or operating speed of the memory card 232.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor device, characterized in that, The device includes a first gate structure, a second gate structure, and a semiconductor pillar. The semiconductor pillar extends along a first direction, and the first gate structure and the second gate structure are respectively disposed on both sides of the semiconductor pillar along a second direction. The first gate structure includes a first conductive layer and a second conductive layer located on at least one side of the first conductive layer along the first direction. The first direction is perpendicular to the second direction.

2. The semiconductor device according to claim 1, characterized in that, The work function of the second conductive layer is different from that of the first conductive layer.

3. The semiconductor device according to claim 1, characterized in that, The number of semiconductor pillars is multiple; along the second direction, the first gate structure is located between two adjacent semiconductor pillars, or two second gate structures are disposed between two adjacent semiconductor pillars.

4. The semiconductor device according to claim 1, characterized in that, Along the first direction, a second conductive layer is disposed on both sides of the first conductive layer, and the work function of the second conductive layer is less than that of the first conductive layer.

5. The semiconductor device according to claim 1, characterized in that, The second conductive layer includes at least two sublayers, wherein, among two adjacent sublayers, the work function of the sublayer closer to the first conductive layer is greater than the work function of the sublayer farther from the first conductive layer.

6. The semiconductor device according to claim 1, characterized in that, The first conductive layer is made of titanium nitride, and the second conductive layer is made of doped polycrystalline silicon.

7. The semiconductor device according to claim 1, characterized in that, Along the first direction, the thickness of the first conductive layer is greater than the thickness of the second conductive layer.

8. The semiconductor device according to claim 1, characterized in that, It also includes a capacitor and a conductive structure; along the first direction, the semiconductor pillar has a first end and a second end opposite to each other, the first end of the semiconductor pillar being connected to the capacitor, and the second end of the semiconductor pillar being connected to the conductive structure.

9. The semiconductor device according to claim 1, characterized in that, Along a third direction, the length of the first gate structure is less than the length of the second gate structure; wherein, the third direction is perpendicular to both the first direction and the second direction.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, An oxide layer is disposed between the first gate structure and the semiconductor pillar.

11. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor pillar is formed, the semiconductor pillar extending along a first direction; A first gate structure is formed, the first gate structure including a first conductive layer and a second conductive layer located on at least one side of the first conductive layer along the first direction; A second gate structure is formed along a second direction, wherein the second gate structure and the first gate structure are respectively located on both sides of the semiconductor pillar, and the second direction is perpendicular to the first direction.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, Forming the first gate structure includes: Provide substrate; A first groove is formed on one side of the substrate, and the depth direction of the first groove is consistent with the first direction; A first conductive layer and a second conductive layer are formed in the first groove, wherein the work function of the first conductive layer is different from that of the second conductive layer.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, Forming a first conductive layer and a second conductive layer within the first groove includes: A second conductive layer is formed on the side of the first conductive layer near the bottom of the first groove, and / or a second conductive layer is formed on the side of the first conductive layer away from the bottom of the first groove; wherein the work function of the second conductive layer is less than the work function of the first conductive layer.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, Forming a first conductive layer and a second conductive layer within the first groove includes: A second conductive layer is formed in the first groove, and the second conductive layer is close to the bottom of the first groove; A first conductive layer is formed on the side of the second conductive layer away from the bottom of the first groove; A second conductive layer is formed on the side of the first conductive layer away from the bottom of the first groove; wherein the second conductive layer closer to the bottom of the first groove is the first sub-conductive layer, and the second conductive layer away from the bottom of the first groove is the second sub-conductive layer.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, Forming the first sub-conductive layer includes: Multiple first sub-layers are sequentially formed within the first groove. Among two adjacent first sub-layers, the work function of the first sub-layer farther from the bottom of the first groove is greater than that of the first sub-layer closer to the bottom of the first groove. The multiple first sub-layers form the first sub-conductive layer.

16. The method for manufacturing a semiconductor device according to claim 14, characterized in that, Forming the second sub-conductive layer includes: A plurality of second sub-layers are formed on the side of the first conductive layer away from the bottom of the first groove. In two adjacent second sub-layers, the work function of the second sub-layer away from the first conductive layer is less than the work function of the second sub-layer close to the first conductive layer. The plurality of second sub-layers form the second sub-conductive layer.

17. The method for manufacturing a semiconductor device according to any one of claims 11 to 16, characterized in that, Also includes: A capacitor is formed, and the capacitor is connected to the first end of the semiconductor pillar; A conductive structure is formed, which is connected to the second end of the semiconductor pillar.

18. A storage system, characterized in that, It includes a controller and a semiconductor device according to any one of claims 1 to 10, wherein the controller is coupled to the semiconductor device and controls the semiconductor device.

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