Memory array and method of making the same, memory, and electronic device

Abstract

The application provides a storage array and a preparation method thereof, a memory and an electronic device, relates to the technical field of semiconductors, and aims to solve the technical problem of how to conveniently increase the number of storage units stacked in the vertical direction of the storage array. The storage array comprises a dielectric column, a transistor and a capacitor, the channel layer, the gate structure and the first electrode of the transistor can be arranged around the dielectric column, the first electrode of the capacitor also surrounds the dielectric column, and the channel layer is connected with the first electrode and the first electrode. The storage array is used to increase the number of storage units that can be stacked.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory array and its fabrication method, a memory, and an electronic device. Background Technology

[0002] With the rapid development of computer systems, the demand for integrated density of dynamic random access memory (DRAM) is increasing. However, miniaturizing the critical dimensions of planar devices is becoming increasingly challenging, and designing three-dimensional device structures that can be vertically stacked has become a major driving force for improving integration density.

[0003] The memory cells of dynamic random access memory (DRAM) can include capacitors and transistors. In the prior art, the transistor channels are primarily made of silicon (Si) or silicon-germanium (SiGe). Silicon or silicon-germanium is mainly formed using epitaxial processes. During the three-dimensional stacking of silicon or silicon-germanium, the stacking height is limited by the epitaxial process, thus limiting the number of memory cells that can be stacked vertically. The transistor channels can also be made of oxide semiconductors, but due to the difficulty in achieving high aspect ratio etching on the stacked structure of oxide semiconductors and sacrificial layers, multiple photolithography and etching processes are required to form DRAMs with increased integration density by increasing the number of stacked layers. Furthermore, as the number of stacked layers increases, it negatively impacts both cost and yield. Summary of the Invention

[0004] This application discloses a storage array and its fabrication method, a memory, and an electronic device, which solves the technical problem of how to conveniently increase the number of storage cells stacked in the vertical direction of the storage array.

[0005] In a first aspect, this application provides a memory array including a dielectric pillar, a capacitor, and a transistor. The dielectric pillar extends along a first direction. The capacitor is disposed at a first end of the dielectric pillar and includes a first electrode that surrounds the first end of the dielectric pillar. The transistor is disposed adjacent to the capacitor and includes a channel layer, a first electrode, and a gate structure. The channel layer surrounds the dielectric pillar, with a first end of the channel layer connected to the first electrode, a second end of the channel layer connected to the first electrode of the capacitor, and a gate structure surrounding the channel layer.

[0006] Thus, during the fabrication of this memory array, multiple dielectric pillars arranged in an array can be formed in a plane perpendicular to the first direction. The dielectric pillars are made of dielectric material. Understandably, multiple dielectric pillars arranged in an array can be formed through a stacked structure, which includes alternately stacked dielectric layers and sacrificial layers. The sacrificial layer can be made of a dielectric material different from that of the dielectric pillars. Since both the sacrificial layer and the dielectric layer are made of dielectric material, alternating stacking is easily achieved. After forming the stacked structure, the stacked structure can be etched and the sacrificial layer removed to form multiple dielectric pillars. Similarly, since both the sacrificial layer and the dielectric layer are made of dielectric material, this stacked structure is also easy to etch with a high aspect ratio, thereby increasing the stack height and forming more repeating dielectric pillars in the stacking direction. One dielectric pillar can correspond to one memory cell including a capacitor and a transistor; thus, more memory cells can be formed in the stacking direction, increasing the memory capacity of the memory array.

[0007] Furthermore, the first electrode of the capacitor, as well as the channel layer, gate structure, and first electrode of the transistor, are all arranged around the dielectric pillar. Therefore, the first electrode of the capacitor, as well as the channel layer, gate structure, and first electrode of the transistor, can all be formed using mature semiconductor processes, such as atomic layer deposition. In other words, memory arrays can be fabricated using mature semiconductor processes, which is beneficial for improving yield and reducing costs.

[0008] In one possible implementation, a first end of the channel layer surrounds a first electrode, and a second end of the channel layer surrounds a first electrode of the capacitor. This increases the contact area between the channel layer and the first electrode, ensuring connection between the first electrode and the channel layer.

[0009] In one possible implementation, the transistor further includes a first intercalation layer and a second intercalation layer. The first intercalation layer is disposed between a first end of the channel layer and a first electrode, and contacts both the channel layer and the first electrode. The second intercalation layer is disposed between a second end of the channel layer and a first electrode of the capacitor, and contacts both the channel layer and the first electrode of the capacitor. The first intercalation layer can be used to establish an ohmic contact between the channel layer and the first electrode, and the second intercalation layer can be used to establish an ohmic contact between the channel layer and the first electrode. This reduces the resistance in the capacitor's charging and discharging path, improving the performance of the memory array.

[0010] In one possible implementation, the Fermi level of the material of the first intercalation layer is between the Fermi level of the material of the first electrode and the Fermi level of the material of the channel layer, and the Fermi level of the material of the second intercalation layer is between the Fermi level of the material of the first electrode and the Fermi level of the material of the channel layer. This facilitates ohmic contact between the channel layer and the first electrode through the first intercalation layer, and ohmic contact between the channel layer and the first electrode through the second intercalation layer.

[0011] In one possible implementation, the dielectric pillar has a rectangular or square shape along a cross-section perpendicular to the first direction. This allows the dielectric pillar to be formed by etching (anisotropic etching) the dielectric layers in the stacked structure.

[0012] In one possible implementation, multiple dielectric pillars are repeatedly arranged along a second direction and a third direction, both of which are perpendicular to the first direction and are also perpendicular to each other. The distance between adjacent dielectric pillars along the second direction is less than the distance between adjacent dielectric pillars along the third direction. Along the second direction, the gate structures of adjacent transistors are interconnected to form word lines. Thus, when forming the gate structure, the gate structures on adjacent dielectric pillars along the second direction are joined together, while the gate structures on adjacent dielectric pillars along the third direction remain separate. Therefore, by controlling the thickness of the formed gate structure, the connection of adjacent gate structures along the second direction can be achieved, while the non-connection of adjacent gate structures along the third direction is advantageous for directly forming word lines.

[0013] In one possible implementation, the memory array further includes a substrate, with a second direction parallel to the surface of the substrate. Thus, the word lines formed by the gate structure connections are parallel to the surface of the substrate, while the bit lines can be perpendicular to the substrate surface. Therefore, the bit lines can be formed by etching deep holes and then filling them with metal after forming the memory cells of the memory array.

[0014] In one possible implementation, the memory array further includes a substrate, with a second direction perpendicular to the surface of the substrate. Thus, the word lines formed by the gate structure connections are perpendicular to the surface of the substrate, while the bit lines can be parallel to the substrate surface. Therefore, the bit lines can be formed by removing part of the sacrificial layer fill metal after the stacked structure is formed.

[0015] In one possible implementation, the memory array further includes bit lines connecting the first electrodes of transistors on a plurality of dielectric pillars arranged along a third direction. This allows for the simple and easy implementation of forming bit lines by etching through-holes along the third direction and filling them with conductive material after forming the memory cells including transistors and capacitors.

[0016] In one possible implementation, the memory array further includes an isolation structure comprising a first portion; a gate structure comprising a first portion, a second portion, and a third portion arranged sequentially and connected along a first direction; the first portion of the isolation structure surrounding the second portion of the gate structure; and along a second direction, the first portions of the gate structures of adjacent transistors are connected, and the third portions of the gate structures of adjacent transistors are connected. Thus, the isolation structure can fill the gaps between adjacent gate structures along the second direction.

[0017] In one possible implementation, the memory array further includes a gate dielectric layer surrounding the channel layer, the gate dielectric layer being located between the channel layer and the gate structure and extending in a first direction; the isolation structure further includes a second portion and a third portion, the second portion and the third portion of the isolation structure being respectively disposed at both ends of the gate structure along the first direction, and respectively connecting to the gate dielectric layers of adjacent transistors along the second direction. Thus, the gate dielectric layers corresponding to different transistors can be separated from each other.

[0018] In one possible implementation, the second portion of the isolation structure is flush with the end face of the gate structure along the first direction, facing away from the gate structure, and with the end face of the gate dielectric layer near the second portion of the isolation structure, and the end face of the channel layer near the second portion of the isolation structure; the third portion of the isolation structure is flush with the end face of the gate structure along the first direction, facing away from the gate structure, and with the end face of the gate dielectric layer near the third portion of the isolation structure, and the end face of the channel layer near the third portion of the isolation structure. Thus, after depositing the materials for forming the channel layer, the gate dielectric layer, and the isolation structure, excess materials for these three layers can be simultaneously removed by etching, thereby simplifying the process steps for forming the channel layer, the gate dielectric layer, and the isolation structure.

[0019] In one possible implementation, the capacitor further includes a dielectric layer and a second electrode. The dielectric layer is disposed between the first and second electrodes and covers the end faces of the gate dielectric layer at opposite ends in the first direction, the end faces of the channel layer at opposite ends in the first direction, and the end faces of the second and third portions of the isolation structure that are respectively away from the gate structure along the first direction. This prevents the second electrode from contacting the channel layer.

[0020] In one possible implementation, the capacitor further includes a second electrode and a dielectric layer, the second electrode being disposed at least partially surrounding the first electrode, and the dielectric layer being disposed between the first and second electrodes. This results in a larger relative area between the first and second electrodes, increasing the capacitance of the capacitor.

[0021] In one possible implementation, there are multiple capacitors; the second electrodes of the multiple capacitors are interconnected. This facilitates the electrical connection of the second electrodes of the multiple capacitors.

[0022] In one possible implementation, a portion of the dielectric layer and a portion of the second electrode are disposed on the end face of the second end of the dielectric pillar. This allows the dielectric layer and the second electrode to be formed via an electrode process after one end of the dielectric pillar has been exposed, facilitating the interconnection of the second electrodes of multiple capacitors.

[0023] In one possible implementation, the material of the dielectric column includes any one or a combination of oxides or nitrides. This facilitates the selection of a suitable material.

[0024] In one possible implementation, the channel layer material comprises a metal oxide. This reduces the leakage current of the transistor.

[0025] Secondly, this application provides a method for fabricating a memory array, the method comprising: forming a plurality of dielectric pillars arranged in an array on a substrate, the dielectric pillars extending along a first direction, the first direction being perpendicular to or parallel to the substrate; forming a first electrode and a first pole, the first electrode being located at a first end of the dielectric pillars and surrounding the dielectric pillars, the first pole being located at a second end of the dielectric pillars and surrounding the dielectric pillars; forming a channel layer and a gate structure, the channel layer being at least partially located between the first electrode and the first pole, the channel layer being connected to the first electrode and the first pole and surrounding the dielectric pillars, and the gate structure surrounding the channel layer; wherein the first electrode is used to form a capacitor, and the channel layer, the first pole, and the gate structure are used to form a transistor.

[0026] In one possible implementation, forming a first electrode and a first pole includes: forming a first conductive layer on a dielectric pillar, the first conductive layer surrounding the dielectric pillar; removing a portion of the first conductive layer located between a first end and a second end of the dielectric pillar, the portion of the first conductive layer surrounding the first end of the dielectric pillar forming a first electrode, and the portion of the first conductive layer surrounding the second end of the dielectric pillar forming a first pole.

[0027] In one possible implementation, forming a channel layer and a gate structure includes: forming an initial channel layer and an initial gate layer, the initial channel layer surrounding a dielectric pillar and covering a first electrode and a first pole, and the initial gate layer surrounding the initial channel layer; removing at least a portion of the initial channel layer and the initial gate layer covering the first electrode and the first pole, and forming the channel layer and the gate structure by removing at least a portion of the initial channel layer and the initial gate layer located between the first electrode and the first pole.

[0028] Thirdly, this application provides a memory including a controller and a memory array of any one of the first aspects, the controller being connected to the memory array.

[0029] Fourthly, this application provides an electronic device including a circuit board and a memory as described in the third aspect, the memory being disposed on the circuit board.

[0030] The beneficial effects of the second to fourth aspects can be referred to the description of the first aspect or any of the embodiments in the first aspect, and will not be repeated here. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A frame diagram of an electronic device provided in an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application;

[0034] Figure 3 A schematic diagram of a storage unit structure provided for related technologies;

[0035] Figure 4 A partial structural diagram of a storage array provided for related technologies;

[0036] Figure 5 A partial structural diagram of another storage array provided for related technologies;

[0037] Figure 6 This is a three-dimensional structural diagram of a storage array provided in an embodiment of this application;

[0038] Figure 7a For along Figure 6 A schematic diagram of a possible cross-sectional structure of line A1-A2 in the middle;

[0039] Figure 7b For along Figure 6 Another possible cross-sectional structure of line A1-A2 in the middle;

[0040] Figure 7c Figure (a) is Figure 6 A possible schematic diagram of the front cross-sectional structure, (b) is shown in the figure. Figure 6 A possible schematic diagram of the left-side cross-sectional structure;

[0041] Figure 7d Figure (a) is Figure 6 Another possible schematic diagram of the front view cross-sectional structure, (b) is shown in the figure. Figure 6 Another possible schematic diagram of the left-side cross-sectional structure;

[0042] Figure 8 A flowchart illustrating a method for fabricating a storage array, as provided in this application embodiment;

[0043] Figures 9 to 25 This is a schematic diagram of the structure during the fabrication process of a storage array, as provided in an embodiment of this application.

[0044] Explanation of reference numerals in the attached figures:

[0045] 10 - Memory array; 100 - Memory cell; 101 - Dielectric pillar; 110 - Capacitor; 111 - First electrode; 112 - Second electrode; 113 - Dielectric layer; 120 - Transistor; 121 - Channel layer; 122 - Gate structure; 123 - First electrode; 124 - First intercalation layer; 125 - Second intercalation layer; 126 - Gate dielectric layer; 130 - Isolation structure; 131 - First isolation portion; 132 - Second isolation portion; 133 - Third isolation portion;

[0046] 20 - Electronic device; 21 - System-on-a-chip; 22 - Second storage device; 23 - Communication chip; 24 - Power management chip; 25 - Bus; 26 - Application processor; 27 - Image processing unit; 28 - First storage device;

[0047] 202-Sacrificial layer; 201-Dielectric layer; 203-Spacer; 204-Via; 210-Substrate; 221-Initial channel layer; 222-Initial gate layer; 223-First conductive layer; 224-Initial intercalation layer; 226-Initial gate dielectric layer; 230-Isolation layer; 240-Dielectric material; 241-Spin-coated carbon material;

[0048] 30 - Storage device; 320 - Decoder; 330 - Driver; 340 - Timing controller; 350 - Buffer; 360 - Input / output driver;

[0049] X - First direction; Y - Second direction; Z - Third direction; ACT - Channel structure; CAP - Capacitor; BL - Bit line; WL - Word line; T - Transistor; L - Semiconductor pillar; P1 - First gate portion; P2 - Second gate portion; P3 - Third gate portion. Detailed Implementation

[0050] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by those skilled in the art. The terms "first," "second," "third," and similar words used in this application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of embodiments in this application, unless otherwise stated, "a plurality of" means two or more.

[0051] The directional terms such as “left,” “right,” “up,” and “down” are defined relative to the orientation of the device shown in the accompanying drawings. It should be understood that these directional terms are relative concepts and are used for relative description and clarification. They can change accordingly depending on the orientation of the chip or semiconductor package structure.

[0052] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0053] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0054] Please see Figure 1 , Figure 1 This is a framework diagram of an electronic device 20 provided in an embodiment of this application. The electronic device 20 can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, and vehicle-mounted equipment, etc. The electronic device can also be a network device such as a base station. The embodiments of this application do not impose special limitations on the specific form of the electronic device.

[0055] Electronic device 20 may include a circuit board, a bus 25, and a system-on-chip (SoC) 21 connected to the bus 25. The bus 25 and the SoC 21 may be disposed on the circuit board. The SoC 21 may be used to process data, such as processing application data, image data, and caching temporary data. In one embodiment, the SoC 21 may include one or more processors, such as an application processor (AP) 26 for processing application data and a graphics processing unit (GPU) 27 for processing image data. The SoC 21 may also include a first storage device (random access memory, RAM) 28 for caching high-speed data. The first storage device 28 may be electrically connected to the processor of the SoC 21, and the first storage device 28 may be a static random access memory (SRAM) or NAND flash memory, etc.

[0056] The application processor 26, the image processing unit 27, and the first storage device 28 can be integrated into a single die or disposed in multiple dies.

[0057] The electronic device 20 may also include a second storage device 22 connected to the system-on-a-chip 21 via a bus 25. The second storage device 22 may also be mounted on a circuit board. The second storage device 22 may be a dynamic random access memory (DRAM), in which case it can be used to store volatile data, such as temporary data generated by the system-on-a-chip 21. The storage capacity of the second storage device 22 is typically larger than that of the first storage device 28, but its read speed is typically slower. The second storage device 22 may also be an external memory, which may be NAND flash memory. Furthermore, the electronic device 20 may also include a communication chip 23 and a power management chip 24 connected to the system-on-a-chip 21 via a bus 25. The communication chip 23 may be used for protocol stack processing, or for amplifying, filtering, or performing other processing on analog radio frequency signals, or simultaneously performing the above functions. The power management chip 24 may be used to supply power to other chips.

[0058] Figure 2 This is a schematic diagram of the structure of a storage device 30 provided in an embodiment of this application. In some embodiments, the storage device 30 may be as follows: Figure 1 The first storage device 28 shown can also be the second storage device 22.

[0059] The storage device 30 includes a storage array 10 and peripheral circuitry, with the storage array 10 connected to the peripheral circuitry.

[0060] The storage array 10 includes multiple storage cells 100, which can be arranged in three dimensions; that is, the storage array 10 can be a three-dimensional storage array. Each storage cell 100 may include a floating-gate transistor. For example, the number of electrons in the floating gate of the floating-gate transistor can be controlled to erase and write data. The storage array 10 may also include signal lines such as word lines (WL) and bit lines (BL). Each storage cell 100 is electrically connected to a corresponding signal line. One or more signal lines can be used to receive control levels or transmit data signals. After selecting the storage cell 100 to be read or written in the storage array 10 through the signal line, read and write operations can be performed on the storage cell 100.

[0061] The peripheral circuitry may include one or more of a decoder 320, a driver 330, a timing controller 340, a buffer 350, or an input / output driver 360. The decoder 320 is used to decode the address of memory cell 100. The decoder 320 decodes the received address to determine the memory cell 100 that needs to be accessed. The driver 330 controls the level of signal lines based on the decoding result generated by the decoder 320, thereby enabling access to the specified memory cell 100. The buffer 350 buffers the read data, for example, using a FIFO (first-in, first-out) buffer. The timing controller 340 controls the timing of the buffer 350 and controls the driver 330 to drive the signal lines in the memory array 10. The input / output driver 360 drives transmission signals, such as driving received data signals and data signals to be sent, enabling long-distance transmission of data signals. The aforementioned memory array 10, decoder 320, driver 330, timing controller 340, buffer 350 and input / output driver 360 can be integrated into one chip or integrated into different chips.

[0062] Please see Figure 3 and combined Figure 2 , Figure 3 This is a schematic diagram of a storage unit 100 provided by related technologies. For ease of description, a structure is established as follows: Figure 3The coordinate system shown is such that the first direction X, the second direction Y, and the third direction Z are mutually perpendicular. The memory cell 100 includes a channel structure ACT extending along the first direction X. One end of the channel structure ACT is connected to a capacitor CAP, and the other end is connected to a bit line BL. The channel structure ACT can be a thin structure formed using semiconductor materials such as silicon, silicon germanium, or metal oxides. Word lines WL are disposed on the upper and lower sides of the channel structure ACT, extending along the second direction Y. Thus, the conduction or disconnection of the channel structure ACT is controlled by the word lines WL, and the amount of charge stored in the capacitor CAP can be sensed or changed by the bit line BL, thereby enabling read and write operations on the memory cell 100.

[0063] The storage cell 100 can be repeatedly configured in the third direction Z to form a three-dimensional stacked storage array. However, in order to form the channel structure ACT, channel layers need to be stacked to form the channel structure ACT.

[0064] If the channel structure ACT is formed using silicon or silicon-germanium, an epitaxial process is required to form the channel layer. However, due to the accumulation of defects in the epitaxial process, each additional channel layer grown epitaxially will increase the defects in that additional channel layer. Therefore, the number of stacked channel layers is limited, which in turn limits the number of memory cells 100 stacked in the third direction Z, thus limiting the storage capacity of the memory array 10.

[0065] If the channel structure ACT is formed using metal oxide, then metal oxide layers and sacrificial layers need to be stacked in an overlapping manner. However, there is no mature mass production method for stacking metal oxide layers and sacrificial layers, and etching the stacked structure formed by metal oxide and sacrificial layers is difficult, which also limits the number of memory cells 100 stacked in the third direction Z. In addition, metal oxide has poor mechanical strength and is easily damaged during the process of removing the sacrificial layer, which is detrimental to the reliability of the memory array 10.

[0066] Please see Figure 4 , Figure 4 This is a partial structural schematic diagram of a memory array 10 provided by related technologies. The memory array 10 includes multiple memory cells 100, each memory cell 100 including a semiconductor pillar L extending along a first direction X. A gate dielectric layer and a gate electrode are disposed around the semiconductor pillar L to form a transistor T. A capacitor CAP is disposed at one end of the semiconductor pillar L, and the two electrode plates and the dielectric layer of the capacitor CAP are disposed around the semiconductor pillar L. Since the semiconductor pillar L is formed using semiconductor materials such as silicon or silicon-germanium, it is necessary to epitaxially form silicon or silicon-germanium stacks during the fabrication process. As described above, due to the accumulation of defects in the epitaxial process, the number of stacked silicon or silicon-germanium layers is limited, which is detrimental to improving the storage capacity of the memory array.

[0067] Please see Figure 5 , Figure 5 This is a partial structural schematic diagram of another memory array 10 provided by related technology. Each memory cell 100 of this memory array 10 includes a transistor T and a capacitor CAP, with the transistor T and capacitor CAP arranged vertically. Multiple memory cells 100 can also be stacked in the vertical direction. A vertically extending word line WL can serve as the gate of multiple vertically arranged transistors T, and a bit line BL perpendicular to the word line WL can serve as the source or drain of multiple horizontally arranged transistors T. The capacitor CAP includes both an electrode layer and a dielectric layer, and the transistor T includes a dielectric layer and a semiconductor layer. These electrode layers, dielectric layers, and semiconductor layers are stacked. During fabrication, etching of the stacked electrode layers, dielectric layers, and semiconductor layers is required, which is difficult and limits the stacking height.

[0068] Based on this, please see Figure 6 and Figure 7a , Figure 6 This is a three-dimensional structural diagram of a storage array 10 provided in an embodiment of this application. Figure 7a For along Figure 6 A schematic cross-sectional view of line A1-A2 shows that the memory array 10 can utilize existing mature fabrication processes to increase the stacking height and improve the storage capacity of the memory array 10. For ease of description, a structure is established as follows: Figure 6 The coordinate system shown has two intersecting directions: a first direction X and a second direction Y, and a third direction Z intersecting the plane formed by the first direction X and the second direction Y. For example, the first direction X and the second direction Y can be perpendicular to each other, and the third direction Z can be perpendicular to the plane formed by the first direction X and the second direction Y.

[0069] The storage array 10 may include dielectric pillars 101, capacitors 110, and transistors 120.

[0070] The dielectric pillar 101 may extend along a first direction X. Understandably, the dielectric pillar 101 may include a first end and a second end, which may be arranged in the first direction X. The dielectric pillar 101 may employ a dielectric material commonly used in semiconductor processes. Exemplarily, the dielectric pillar 101 may include any one or a combination of oxides or nitrides; for example, the oxide may be silicon oxide, and the nitride may be silicon nitride.

[0071] A capacitor 110 may be disposed at the first end of a dielectric pillar 101. The capacitor 110 may include a first electrode 111, which may be disposed around the first end of the dielectric pillar 101. The capacitor 110 may also include a second electrode 112 and a dielectric layer 113, which may be disposed between the first electrode 111 and the second electrode 112. The specific arrangement of the second electrode 112 will be described in detail later.

[0072] The first electrode 111 and the second electrode 112 may be made of conductive materials. Exemplarily, the first electrode 101 and the second electrode 112 may be made of metals or metal compounds, such as one or a combination of tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), indium tin oxide (ITO), etc. It is understood that the material used for the second electrode 112 may be the same as or different from that used for the first electrode 111.

[0073] Transistor 120 may be disposed adjacent to capacitor 110. Exemplarily, transistor 120 is disposed between the first and second ends of dielectric pillar 101.

[0074] Transistor 120 may include a channel layer 121, a gate structure 122, and a first electrode 123. The channel layer 121 may surround the dielectric pillar 101 and may extend a certain dimension in a first direction X. Therefore, the channel layer 121 also includes a first end and a second end arranged in the first direction X. The first end of the channel layer 121 may be connected to the first electrode 123, and the second end of the channel layer 121 may be connected to the first electrode 111 of capacitor 110.

[0075] Understandably, the channel layer 121 can be made of a metal oxide semiconductor material. For example, the material used for the channel layer 121 can be one or a combination of amorphous indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium tin oxide (ITO), indium tin oxide (IWO), etc., wherein the indium gallium zinc oxide can include c-axis crystalline indium gallium zinc oxide (CAAIGZO). Thus, the first electrode 123 is connected to the first electrode 111 of the capacitor 110 through the channel layer 121, and the charging and discharging operations of the charge stored in the capacitor 110 can be controlled by turning the channel layer 121 on and off, thereby realizing data reading and writing. In other words, the transistor 120 and the capacitor 110 constitute a memory cell 100.

[0076] A gate structure 122 may be disposed around a channel layer 121, thereby controlling the conduction and turn-off of the channel layer. Since the channel layer 121 may be disposed around a dielectric pillar 101, and the gate structure 122 may be disposed around the channel layer 121, the gate structure 122 may also be disposed around the dielectric pillar 101, and the channel layer 121 is located between the gate structure 122 and the dielectric pillar 101. Understandably, a gate dielectric layer 126 is disposed between the channel layer 121 and the gate structure 122. The material of the gate dielectric layer 126 may be a high-k value material, such as one or a combination of alumina (AlO), hafnium oxide (HfO), alumina-hafnium oxide (HfAlO), zirconium oxide (ZrO), and lanthanum oxide (LaO).

[0077] Therefore, in the preparation Figure 7aWhen the memory array 10 is shown, multiple dielectric pillars 101 arranged in an array can be formed in a plane perpendicular to the first direction X. The dielectric pillars 101 are made of dielectric material. During the fabrication process, dielectric layers and sacrificial layers can be stacked alternately, with the dielectric layers used to form the dielectric pillars 101. The sacrificial layer can be made of a dielectric material different from that of the dielectric pillars. It is easy to achieve alternating stacking of two different dielectric materials, that is, it is easy to form alternating stacked dielectric layers and sacrificial layers. After forming the stacked structure of dielectric layers and sacrificial layers, the stacked structure can be etched and the sacrificial layer removed by an etching process to form multiple dielectric pillars 101. Since the first electrode 111 of the capacitor 110 and the channel layer 121, gate structure 122, and first electrode 123 of the transistor 120 are all arranged around the dielectric pillars 101, these structures can be formed by mature semiconductor processes such as deposition, for example, by ALD, CVD, etc., which is beneficial to improve yield and reduce cost. Thus, a memory array 10 including a memory cell 100 composed of at least capacitors 110 and transistors 120 can be formed by mature semiconductor processes. Furthermore, by depositing two different dielectric materials, it is easy to form a stacked structure, which is also easy to etch with high aspect ratios. In this way, more memory cells 100 can be formed in the stacking direction, thereby increasing the storage capacity of the memory array 10.

[0078] In some embodiments, the dielectric pillar 101 has a rectangular or square shape along a cross-section perpendicular to the first direction X. Understandably, this cross-section refers to the interface where the dielectric pillar 101 intersects the plane perpendicular to the first direction X. Since the dielectric pillar 101 is formed by etching (anisotropic etching) the dielectric layers in the stacked structure, the shape of the cross-section of the dielectric pillar 101 can be rectangular or square.

[0079] In some embodiments, the first end of the channel layer 121 may surround the first electrode 123, and the second end of the channel layer 121 may surround the first electrode 121 of the capacitor 110. Since the first electrode 123 and the first electrode 111 are also disposed around the dielectric pillar 101, a portion of the first electrode 123 may be disposed between the channel layer 121 and the dielectric pillar 101, and a portion of the first electrode 111 may be disposed between the channel layer 121 and the dielectric pillar 101. In this way, the contact area between the channel layer 121 and the first electrode 123 and the first electrode 111 can be increased, ensuring that the first electrode 123 and the first electrode 111 are connected to the channel layer 121.

[0080] In some embodiments, transistor 120 may further include a first intercalation layer 124 and a second intercalation layer 125. The first intercalation layer 124 is disposed between a first end of channel layer 121 and a first electrode 123, and is in contact with channel layer 121 and the first electrode 123; the second intercalation layer 125 is disposed between a second end of channel layer 121 and a first electrode 111 of capacitor 110, and is in contact with channel layer 121 and the first electrode 111 of capacitor 110.

[0081] The first intercalation layer 124 can be used to achieve ohmic contact between the channel layer 121 and the first electrode 123, and the second intercalation layer 125 can be used to achieve ohmic contact between the channel layer 121 and the first electrode 111. In this way, the resistance in the charging and discharging path of the capacitor 110 can be reduced, thereby improving the performance of the memory array 10.

[0082] For example, the Fermi level of the material of the first intercalation layer 124 is between the Fermi level of the material of the first electrode 123 and the Fermi level of the material of the channel layer 121, and the Fermi level of the material of the second intercalation layer 125 is between the Fermi level of the material of the first electrode 111 and the Fermi level of the material of the channel layer 121. For example, if the materials of the first electrode 111 and the first electrode 123 are metallic materials and the material of the channel layer 121 is indium gallium zinc oxide, the materials of the first intercalation layer 124 and the second intercalation layer 125 can be indium tin oxide.

[0083] For example, when the first end of the channel layer 121 surrounds the first electrode 123 and the second end of the channel layer 121 surrounds the first electrode 121 of the capacitor 110, the first intercalation layer 124 may also be disposed around the first electrode 123, and the second intercalation layer 125 may also be disposed around the first electrode 111. In this way, the resistance between the channel layer 121 and the first electrode 123, and between the channel layer 121 and the first electrode 111, can be further reduced.

[0084] In some implementations, it is understood that since the storage array 10 includes a plurality of storage cells 100, each storage cell 100 may correspond to a medium pillar 101, so the number of medium pillars 101 may be plurality. The plurality of storage cells 100 may be stacked in a three-dimensional direction, therefore, the plurality of medium pillars 101 may also be arranged in a three-dimensional direction.

[0085] For example, a plurality of dielectric pillars 101 are repeatedly arranged along the second direction Y and the third direction Z; that is, the plurality of dielectric pillars 101 can be arrayed within a first plane YZ. The first plane YZ is a plane that is parallel to both the second direction Y and the third direction Z, and the first plane YZ can be perpendicular to the first direction X. Since the gate structure 122 is disposed around the dielectric pillars 101, the gate structure 122 is also arrayed. Therefore, the gate structures 122 of transistors 120 adjacent in one direction within the first plane YZ can be interconnected to form word lines.

[0086] For example, the gate structures 122 of adjacent transistors 120 along the second direction Y are connected to form word lines of the memory array 10. For this purpose, the distance D between adjacent dielectric pillars 101 along the second direction Y can be made smaller than the distance D between adjacent dielectric pillars 101 along the third direction Z.

[0087] In some embodiments, the memory array 10 may further include a substrate, that is, the aforementioned dielectric pillars 101, capacitors 110, and transistors 120 may be formed on the substrate. Understandably, when the memory array 10 further includes a substrate, the extending direction of the dielectric pillars 101 is parallel to the surface of the substrate, and the surface of the substrate is parallel to a third plane XY, which is the plane containing the first direction X and the second direction Y.

[0088] For example, please see Figure 7c The second direction, Y, can be parallel to the substrate. Figure 7c Figure (a) is Figure 6 A possible schematic diagram of the front cross-sectional structure. Figure 7c Figure (b) is Figure 6 A possible schematic diagram of the left-side cross-sectional structure shows that multiple gate structures 122 can be arranged along the second direction Y to form a word line WL, i.e., the word line WL extends in the second direction Y. Understandably, the memory array 10 may also include a bit line BL, which may extend in the third direction Z, i.e., the bit line BL is perpendicular to the surface of the substrate.

[0089] For example, please see Figure 7d The second direction, Y, can be perpendicular to the substrate. Figure 7d Figure (a) is Figure 6 Another possible schematic diagram of the front view cross-sectional structure. Figure 7d Figure (b) is Figure 6 Another possible schematic diagram of the left-side cross-sectional structure shows that multiple gate structures 122 can be arranged along the third direction Z to form a word line WL, i.e., the word line WL extends in the third direction Z. Understandably, the memory array 10 may also include a bit line BL, which can extend in the second direction Y, i.e., the bit line BL is parallel to the surface of the substrate.

[0090] As previously mentioned, the direction of the bit line BL can be perpendicular to the word line WL. For example, when the word line WL is along the second direction Y, the bit line BL can extend along the third direction Z. That is, the bit line BL can connect the first electrodes 123 of transistors 120 arranged on a plurality of dielectric pillars along the third direction X, wherein the plurality of first electrodes 123 are also arranged along the third direction Z. In other words, when the extension direction of the word line WL, the second direction Y, is parallel to the substrate, the extension direction of the bit line BL is perpendicular to the substrate; when the extension direction of the word line WL, the second direction Y, is perpendicular to the substrate, the extension direction of the bit line BL is parallel to the substrate.

[0091] Therefore, the process time and method for forming the bit line BL may differ, but those skilled in the art can easily conceive of them based on existing semiconductor fabrication processes. For example, when the extension direction of the bit line BL is perpendicular to the substrate, the bit line BL can be formed by etching a via along the third direction Y after forming the memory cell 100, followed by filling it with conductive material; this is simple and easy to implement. As another example, when the extension direction of the bit line BL is parallel to the substrate, the bit line BL can be formed by removing part of the sacrificial layer and filling it with metal after forming the stacked structure.

[0092] Understandably, the memory array 10 may also not include a substrate, for example, the substrate may be removed after the memory array 10 is formed.

[0093] Thus, the gate structure 122 surrounding the dielectric pillar 101 can be formed by a deposition process. Understandably, the material thickness of the gate structure 122 formed on the dielectric pillar 101 by the deposition process is substantially the same. Since the distance D between adjacent dielectric pillars 101 along the second direction Y can be smaller than the distance D between adjacent dielectric pillars 101 along the third direction Z, the materials of the gate structures 122 on adjacent dielectric pillars 101 along the second direction Y are bonded together, while the materials of the gate structures 122 on adjacent dielectric pillars 101 along the third direction Z remain separated. Therefore, by controlling the thickness of the material of the formed gate structure 122, it is possible to achieve connection of adjacent gate structures 122 along the second direction Y and non-connection of adjacent gate structures 122 along the third direction Z.

[0094] Please continue reading Figure 7aThe memory array 10 may further include an isolation structure 130, which may include a first isolation portion 131. The first isolation portion 131 of the isolation structure 130 may be disposed between two adjacent gate structures 122 along the second direction Y. For example, the gate structure 122 may include a first gate portion P1, a second gate portion P2, and a third gate portion P3 arranged sequentially along the first direction X. The first isolation portion 131 of the isolation structure 130 may be disposed between the first gate portion P1 and the third gate portion P3 of the gate structure 122 and surround the second portion P2 of the gate structure 122. Simultaneously, the first gate portions P1 of the gate structures 122 of adjacent transistors 120 along the second direction Y may be interconnected, and the third gate portions P1 of the gate structures 122 of adjacent transistors 120 along the second direction Y may be interconnected. A portion of the first isolation portion 131 of the isolation structure 130 may be a ring structure that surrounds the second portion P2 of the gate structure 122.

[0095] As previously described, the memory array 10 also includes a gate dielectric layer 126. The gate dielectric layer 126 is disposed between the channel layer 121 and the gate structure 122 and extends in the first direction X. Because the gate structure 122 is disposed around the channel layer 121 and the gate dielectric layer 126 is disposed between the channel layer 121 and the gate structure 122, the gate dielectric layer 126 is also disposed around the channel layer 121.

[0096] The isolation structure 130 may further include a second isolation portion 132 and a third isolation portion 133. The second isolation portion 132 and the third isolation portion 133 of the isolation structure 130 are respectively disposed at both ends of the gate structure 122 along the first direction X, and are respectively connected to the gate dielectric layer 126 of the adjacent transistors along the second direction Y. In this way, the gate dielectric layer 126 corresponding to different transistors 120 are also disposed separately from each other.

[0097] The second isolation portion 132 of the isolation structure 130 is opposite to the end face of the gate structure 122 along the first direction X, and is flush with one end face of the gate dielectric layer 126 near the second isolation portion 132 of the isolation structure 130, and one end face of the channel layer 121 near the second isolation portion 132 of the isolation structure 130. The third isolation portion 133 of the isolation structure 130 is opposite to the end face of the gate structure 122 along the first direction X, and is flush with one end face of the gate dielectric layer 126 near the third isolation portion 133 of the isolation structure 130, and one end face of the channel layer 121 near the third isolation portion 133 of the isolation structure 130. In this way, after depositing the materials for forming the channel layer 121, the gate dielectric layer 126, and the isolation structure 130, excess materials for the channel layer 121, the gate dielectric layer 126, and the isolation structure 130 can be removed simultaneously by etching, thereby simplifying the process steps for forming the channel layer 121, the gate dielectric layer 126, and the isolation structure 130.

[0098] The material of the isolation structure 130 may include a low-k value material. It is readily understood that in the storage array 10, the storage cells 100 are closely arranged, and during the read and write operations of the storage cells 100, parasitic capacitance can affect read and write performance. By setting an isolation structure, the impact of parasitic capacitance during read and write operations can be reduced, thereby improving the performance of the storage array 10.

[0099] Please see Figure 7b and combined Figure 7a The isolation structure 130 may not include the first isolation portion 131, meaning that the first gate portion P1, the second gate portion P2, and the third gate portion P3 of the gate structures 122 of adjacent transistors 120 along the second direction Y are all interconnected. Understandably, increasing the thickness of the gate structure 122 during its formation allows the second gate portions P2 to be interconnected.

[0100] As previously described, the capacitor 110 may further include a second electrode 112 and a dielectric layer 113, with the dielectric layer 113 disposed between the first electrode 111 and the second electrode 112. Furthermore, the dielectric layer 113 also covers the end faces of the gate dielectric layer 126 at opposite ends in the first direction X, the end faces of the channel layer 121 at opposite ends in the first direction X, and the end faces of the second isolation portion 132 and the third isolation portion 133 of the isolation structure 130 away from the gate structure 122. That is, the dielectric layer 113 can be formed by depositing material after the channel layer 121, the gate dielectric layer 126, and the isolation structure 130 are formed.

[0101] In some embodiments, at least a portion of the second electrode 112 of the capacitor 110 may be disposed around the first electrode 111. Understandably, since the first electrode 111 is disposed around the dielectric pillar 101, at least a portion of the second electrode 111 is also disposed around the dielectric 101. Simultaneously, since the dielectric layer 113 is disposed between the first electrode 111 and the second electrode 112, at least a portion of the dielectric layer 113 is also disposed around the dielectric 101. This allows the capacitor 110 to be formed around the dielectric pillar 101, increasing the amount of charge stored in the capacitor 110 and improving the performance of the storage array 10.

[0102] In some embodiments, the second electrodes 112 of the plurality of capacitors 110 may be interconnected. It is readily understood that the memory array 10 has a plurality of dielectric pillars 101, capacitors 110, and transistors 120, and that each dielectric pillar 101, capacitor 110, and transistor 120 corresponds one-to-one. The interconnection of the second electrodes 112 of the plurality of capacitors 110 simplifies the electrical connections of the memory array 10.

[0103] Please continue reading Figure 7a A portion of the dielectric layer 113 and a portion of the second electrode 112 are disposed on the end face of the second end of the dielectric pillar 101. That is, a portion of the dielectric layer 113 and a portion of the second electrode 112 are disposed on the end face of the dielectric pillar 101 where the capacitor 110 is located. Thus, with the second end of the dielectric pillar 101 exposed, the dielectric layer 113 and the second electrode 112 of multiple capacitors 110 can be deposited simultaneously, and the second electrodes 112 of the multiple capacitors 110 can be interconnected. Furthermore, the interconnection of the second electrodes 112 of multiple capacitors 110 can be achieved without limiting the thickness of the deposited second electrode 112.

[0104] Finally, this application embodiment also provides a method for fabricating a storage array 10. The materials of the components formed in this fabrication method can be referred to the materials of the corresponding components in the aforementioned storage array 10, and will not be repeated here. Please refer to... Figure 8 The preparation method includes the following steps:

[0105] S100, please refer to Figures 9-15 Multiple dielectric pillars 101 are formed in an array on the substrate 210. The dielectric pillars 101 extend along a first direction X, which is perpendicular to or parallel to the substrate 210.

[0106] An array of dielectric pillars 101 can be formed by forming a stacked structure of alternating sacrificial layers 202 and dielectric layers 201 on a substrate 210, etching the stacked structure to form trenches that at least partially penetrate the stacked structure, and then removing the sacrificial layers 202. Exemplarily, the following steps may be included:

[0107] S110, please refer to Figure 9 A stacked structure in which sacrificial layer 202 and dielectric layer 201 are alternately disposed is formed on substrate 210.

[0108] The sacrificial layer 202 and the dielectric layer 201 are stacked alternately in the third direction Z, meaning that the sacrificial layer 202 and the dielectric layer 201 extend in a plane parallel to the first direction X and the second direction Y. Both the sacrificial layer 202 and the dielectric layer 201 can be made of dielectric materials; for example, the sacrificial layer 202 may include a nitride dielectric material such as silicon nitride, and the dielectric layer 201 may include an oxide dielectric material such as silicon carbide. The sacrificial layer 202 and the dielectric layer 201 can be made of different materials and have a high etch selectivity. This facilitates the removal of the sacrificial layer 202 in subsequent processes.

[0109] S120, please refer to Figure 10 This forms a spacer 203, which penetrates the stacked structure and divides the stacked structure into multiple separated parts.

[0110] For example, trenches at least partially penetrating the stacked structure can be formed by etching the stacked structure, dividing the stacked structure into multiple separated sections. The etching of the stacked structure can employ anisotropic etching processes, such as dry etching. Since the stacked structure consists entirely of dielectric materials, it is easy to etch it with high aspect ratios, thus increasing the number of layers of sacrificial layer 202 and dielectric layer 201 in the stacked structure. Understandably, the more layers the stacked structure has, the larger the storage capacity of the final memory array formed by the stacked structure.

[0111] After the trenches are formed, a dielectric material can be deposited in the trenches to separate the multiple partitions. It is easy to understand that the dielectric material in the trenches can be different from the dielectric material used in the sacrificial layer 202 and the dielectric layer 201, and the dielectric material in the trenches can have a higher etching selectivity than the dielectric material of the sacrificial layer 202 and the dielectric layer 201.

[0112] S130, please refer to Figure 11 A channel 204 is formed, which penetrates the stacked structure and extends in the first direction X. The channel 204 divides the dielectric layer 201 in the multiple partitioned parts of the stacked structure into multiple dielectric pillars 101.

[0113] Understandably, multiple dielectric pillars 101 formed by the same dielectric layer 201 can be interconnected, and the dielectric pillars 101 include a cylindrical portion extending in a first direction X.

[0114] S140, please refer to Figure 12 Remove the sacrificial layer 202.

[0115] The sacrificial layer 202 can be removed using isotropic etching, such as wet etching. After the sacrificial layer 202 is removed, the multiple dielectric layers 201 stacked in the third direction Z are separated from each other. At least one end of each dielectric layer 201 can be connected to the spacer 203, so that the stacked dielectric layers 201 can be supported without collapsing.

[0116] In some embodiments, the distance between adjacent dielectric pillars 101 along the second direction Y may be less than the distance between adjacent dielectric pillars 101 along the third direction Z. Understandably, the distance between adjacent dielectric pillars 101 along the second direction Y can be controlled by controlling the size of the formed channel 204, the size of the channel 204 in the second direction Y being equal to the distance between adjacent dielectric pillars 101 along the second direction Y. The distance between adjacent dielectric pillars 101 along the third direction Z can be controlled by the thickness of the sacrificial layer 202, the thickness of the sacrificial layer 202 being equal to the distance between adjacent dielectric pillars 101 along the third direction Z.

[0117] Please see Figures 13-15 and combined Figure 7a , Figure 13 For along Figure 12 Schematic diagram of the cross-sectional structure of line A1-A2 in the middle. Figure 14 For along Figure 12 Schematic diagram of the cross-sectional structure of line B1-B2 (3D). Figure 15 For along Figure 14 A cross-sectional structural diagram (planar view) of line C1-C2. Multiple dielectric pillars 101 can be arranged in an array in a plane perpendicular to the first direction X, meaning that multiple dielectric pillars 101 are repeatedly arranged in the second direction Y and also repeatedly arranged in the third direction Z. Thus, storage cells 100 of the storage array 10 can be formed based on the dielectric pillars 101, with each storage cell 100 corresponding to one dielectric pillar 101.

[0118] S200, please refer to Figures 16-18 A first electrode 111 and a first electrode 123 are formed. The first electrode 111 is located at the first end of the dielectric pillar 101 and surrounds the dielectric pillar 101. The first electrode 123 is located at the second end of the dielectric pillar 101 and surrounds the dielectric pillar 101.

[0119] To clearly illustrate the subsequent preparation steps, Figure 13 The middle region G is illustrated by an example. Exemplarily, forming the first electrode 111 and the first electrode 123 may include the following steps:

[0120] S210, please refer to Figure 16 A first conductive layer 223 is formed, which surrounds the dielectric pillar 101.

[0121] The first conductive layer 223 can be formed using a deposition process. For example, the first conductive layer 223 can be formed using an atomic layer deposition (ALD) process. The first conductive layer 223 covers the surface of the dielectric layer 101, thereby achieving a surrounding dielectric pillar 101.

[0122] In some embodiments, after the first conductive layer 223 is formed, an initial intercalation layer 224 may be formed. The initial intercalation layer 224 may also be formed by a deposition process, such as atomic layer deposition. The initial intercalation layer 224 covers the surface of the first conductive layer 223 and also surrounds the dielectric pillar 101.

[0123] S220, please refer to Figures 17-18 Remove the portion of the first conductive layer 223 located between the first end and the second end of the dielectric pillar 101. The portion of the first conductive layer 223 surrounding the first end of the dielectric pillar 101 forms the first electrode 111, and the portion of the first conductive layer 223 surrounding the second end of the dielectric pillar forms the first electrode 123.

[0124] Multiple dielectric pillars 101 are stacked in the third direction Z, so the first conductive layer 223 to be removed is also repeatedly arranged in the third direction Z. Exemplarily, to remove a portion of the first conductive layer 223 repeatedly arranged in the third direction Z, a spin-on-carbon (SOC) material can be applied to the stacked dielectric pillars 101, and then the spin-on-carbon material 241 is patterned. A portion of the spin-on-carbon material 241 is then removed to expose the first conductive layer 223 to be removed, specifically the portion of the first conductive layer 223 located between the first and second ends of the dielectric pillar 101. The exposed first conductive layer 223 is then removed by an etching process. In this application, a similar method can be used when it is necessary to remove portions of the structure in the three-dimensional direction, and will not be elaborated further. The exposed first conductive layer 223 can be removed using an isotropic etching process, such as a wet etching process.

[0125] Understandably, when the surface of the first conductive layer 223 is covered with the initial intercalation layer 224, a portion of the initial intercalation layer 224 can be removed simultaneously with the removal of the first conductive layer 223, i.e., the spin-coated carbon material 241 exposes a portion of the initial intercalation layer 224. Alternatively, removing a portion of the initial intercalation layer 224 covering the surface of the first conductive layer 223, followed by removing a portion of the first conductive layer 223, can also be understood as simultaneously removing a portion of the initial intercalation layer 224 and a portion of the first conductive layer 223. Understandably, the same process can be used to remove both the first conductive layer 223 and the initial intercalation layer 224. This allows for uninterrupted processing, improving production efficiency.

[0126] S300, please refer to Figures 19-25 A channel layer 121 and a gate structure 122 are formed. The channel layer 121 is at least partially located between the first electrode 111 and the first electrode 123. The channel layer 121 is connected to the first electrode 111 and the first electrode 123 and surrounds the dielectric pillar 101. The gate structure 122 surrounds the channel layer 121. The first electrode 111 is used to form a capacitor 110, and the channel layer 121, the first electrode 123 and the gate structure 122 are used to form a transistor 120.

[0127] Understandably, the first electrode 111 is used to form a capacitor 110, and the first electrode 123 is used to form a transistor 120. The transistor 120 also includes a channel layer 121 and a gate structure 122. The channel layer 121 is connected to the first electrode 111 and the first electrode 123 and may surround the dielectric pillar 101. The gate structure 122 surrounds the channel layer 121. Thus, the transistor 120 is connected to the capacitor 110 and constitutes a memory cell.

[0128] Forming the channel layer 121 and the gate structure 122 may include the following steps:

[0129] S310, please refer to Figures 19-20 An initial channel layer 221 and an initial gate layer 222 are formed. The initial channel layer 221 surrounds the dielectric pillar 101 and covers the first electrode 111 and the first electrode 123. The initial gate layer 222 surrounds the initial channel layer 221.

[0130] Please see Figure 19An initial channel layer 221 can be formed by a deposition process. The initial channel layer 221 covers the surface of the structure formed in step S200. That is, the initial channel layer 221 surrounds the dielectric pillar 101. A portion of the initial channel layer 221 covers the portion between the first end and the second end of the dielectric pillar 101, and another portion of the initial channel layer 221 covers the first electrode 111 and the first electrode 123. In the case of including the initial intercalation layer 224, it is readily understood that another portion of the initial channel layer 221 covers the initial intercalation layer 224, and the initial intercalation layer 224 covers the first electrode 111 and the first electrode 123. In this case, it can also be considered that another portion of the initial channel layer 221 covers the first electrode 111 and the first electrode 123.

[0131] Understandably, a gate dielectric layer 126 is included between the channel layer 121 and the gate structure 122 of the transistor 120. Therefore, an initial gate dielectric layer 226 can be formed after the initial channel layer 221 is formed. The initial gate dielectric layer 226 covers the surface of the initial channel layer 221. Both the initial gate dielectric layer 226 and the initial channel layer 121 can be formed using semiconductor processes such as deposition processes, for example, atomic layer deposition processes.

[0132] Please see Figure 20 The initial gate layer 222 is then formed, covering the initial gate dielectric layer 226 on the surface of the initial channel layer 121. At this time, the initial gate layer 222 also surrounds the initial channel layer 221. The initial gate layer 222 can be formed using a suitable semiconductor process, such as atomic layer deposition.

[0133] In some embodiments, since the distance between adjacent dielectric pillars 101 along the second direction Y can be smaller than the distance between adjacent dielectric pillars 101 along the third direction Z, the initial gate layers 222 on the surfaces of adjacent dielectric pillars 101 will first bond in the second direction Y when forming the initial gate layer 222 surrounding the dielectric pillars 101. If the process of forming the initial gate layer 222 continues, the initial gate layers 222 on the surfaces of adjacent dielectric pillars 101 will only bond in the third direction Z. Thus, by controlling the timing of the process of forming the initial gate layer 222, the initial gate layers 222 on the surfaces of adjacent dielectric pillars 101 can bond in the second direction Y but not in the third direction Z. In this way, in subsequent process steps, when forming the gate structure 122 through the initial gate layer 222, a plurality of gate structures 122 connected sequentially can be formed in the second direction Y, thereby forming word lines of the memory array.

[0134] Furthermore, since the first electrode 111 and the first electrode 123 are respectively provided at both ends of the dielectric pillar 101, after the initial gate layer 222 covering the surface of the adjacent dielectric pillar 101 is bonded together at both ends of the dielectric pillar 101, the portion of the initial gate layer 222 between the two ends of the dielectric pillar 101 is not yet bonded. Figure 20 As shown.

[0135] Understandably, the distance between adjacent dielectric pillars 101 along the second direction Y can also be greater than the distance between adjacent dielectric pillars 101 along the third direction Z. In this case, the word lines of the formed memory array can be multiple gate structures 122 connected sequentially in the third direction Z.

[0136] In some embodiments, the distance between adjacent dielectric pillars 101 along the second direction Y can also be equal to the distance between adjacent dielectric pillars 101 along the third direction Z. In this case, during the formation of the initial gate layer 222, the initial gate layers 222 on the surfaces of adjacent dielectric pillars 101 can be bonded in both the second direction Y and the third direction Z, and then a portion of the initial gate layers 222 can be removed, so that the initial gate layers 222 surrounding the dielectric pillars 101 are spaced apart in the third direction Z. For example, an anisotropic etching process can be used to remove a portion of the initial gate layers 222 surrounding the dielectric pillars 101, so that the initial gate layers 222 surrounding the dielectric pillars 101 are spaced apart in the third direction Z. It can be understood that the formed initial gate layers 222 surrounding the dielectric pillars 101 can also be spaced apart in the second direction Y.

[0137] S320, at least a portion of the initial channel layer 221 and the initial gate layer 222 covering the first electrode 111 and the first electrode 123 is removed, and the portion of the initial channel layer 221 and the initial gate layer 222 located between the first electrode 111 and the first electrode 123 forms the channel layer 121 and the gate structure 122.

[0138] Understandably, the dielectric pillars 101 are repeatedly disposed in the third direction Z, so at least a portion of the initial channel layer 221 and the initial gate layer 222 that need to be removed are also distributed in the three-dimensional direction. Exemplarily, when removing at least a portion of the initial channel layer 221 and the initial gate layer 222, the stacked dielectric pillars 101 may also be coated with spin-coated carbon material, and then the spin-coated carbon material is patterned to expose the initial channel layer 221 and the initial gate layer 222 that need to be removed.

[0139] As mentioned above, the channel layer 121 connects the first electrode 123 and the first electrode 111. Therefore, after removing a portion of the initial channel layer 221 and the initial gate layer 222, the channel layer 121 formed by the initial channel layer 221 still needs to be in contact with the first electrode 123 and the first electrode 111.

[0140] For example, please see Figure 21a and combined Figure 7a A portion of the channel layer 121 and gate structure 122 formed after removing a portion of the initial channel layer 221 and the initial gate layer 222 surrounds the first electrode 123 and / or the first electrode 111.

[0141] In some implementations, please refer to Figure 21b As mentioned earlier, the distance between adjacent dielectric pillars 101 along the second direction Y can also be greater than the distance between adjacent dielectric pillars 101 along the third direction Z. In this case, the word lines of the memory array formed by the plurality of gate structures 122 connected sequentially along the third direction Z.

[0142] Understandably, the dielectric pillars 101 are repeatedly disposed in the third direction Z, so at least a portion of the initial channel layer 221 and the initial gate layer 222 that need to be removed are also distributed in the three-dimensional direction. Exemplarily, when removing at least a portion of the initial channel layer 221 and the initial gate layer 222, the stacked dielectric pillars 101 may also be coated with spin-coated carbon material, and then the spin-coated carbon material is patterned to expose the initial channel layer 221 and the initial gate layer 222 that need to be removed.

[0143] As mentioned above, the channel layer 121 connects the first electrode 123 and the first electrode 111. Therefore, after removing a portion of the initial channel layer 221 and the initial gate layer 222, the channel layer 121 formed by the initial channel layer 221 still needs to be in contact with the first electrode 123 and the first electrode 111.

[0144] For example, please see Figure 21a After removing a portion of the initial channel layer 221 and the initial gate layer 222, the formed channel layer 121 and a portion of the gate structure 122 may surround the first electrode 123 and / or the first electrode 111.

[0145] In some embodiments, a portion of the initial gate layer 222 and the initial channel layer 221 may be removed in stages. This optimizes the structural design of the gate structure 122 and the channel layer 121. For example, the size of the channel layer 121 may differ from the size of the gate structure 122 in the first direction X. Furthermore, additional process steps can be performed between removing a portion of the initial gate layer 222 and removing a portion of the initial channel layer 221 to improve the performance of the memory array.

[0146] For example, removing a portion of the initial gate layer 222 and the initial channel layer 221 in steps may include the following steps:

[0147] S321. A portion of the initial gate layer 222 is removed to form a gate structure 122, which surrounds the dielectric pillar 101.

[0148] Please see Figure 21a and combined Figure 20 and Figure 7a The portion of the initial gate layer 222 surrounding the dielectric pillar 101 at both ends along the first direction X is removed, that is, at least a portion of the initial gate layer 222 covering the first electrode 123 and the first electrode 111 is removed. In other words, the portion of the initial gate layer 222 between the two ends of the dielectric pillar 101 along the first direction X is retained, and this portion can be the gate structure 122.

[0149] For example, since the first electrode 123 and the first electrode 111 are spaced apart in the first direction X, and the channel layer 121 connects the first electrode 123 and the first electrode 111, the size of the gate structure 122 in the first direction X can be larger than the distance between the first electrode 123 and the first electrode 111 in the first direction X, and completely surround the spaced area between the first electrode 123 and the first electrode 111 in the first direction X. That is, the gate structure 122 and the first electrode 123, and the gate structure 122 and the first electrode 111, all have overlapping portions in the first direction X. This allows the gate structure 122 to completely cover the effective portion of the channel layer 121 used to conduct the first electrode 123 and the first electrode 111, improving the control capability of the gate structure 122 over the channel layer 121.

[0150] S322, Remove a portion of the initial channel layer 221 to form channel layer 121, which surrounds the medium column 101.

[0151] Please see Figure 22 and combined Figure 21a and Figure 7a The initial channel layer 221 is removed from both ends of the dielectric pillar 101 along the first direction X. Specifically, at least a portion of the initial channel layer 221 covering the first electrode 123 and the first electrode 111 is removed. In other words, the portion of the initial channel layer 221 between the two ends of the dielectric pillar 101 along the first direction X is retained, and this retained portion can be the channel layer 121. Understandably, the channel layer 121 formed in this way connects the first electrode 123 and the first electrode 111. If the surface of the initial channel layer 221 is covered by an initial gate dielectric layer 226, a portion of the initial gate dielectric layer 226 can be removed simultaneously with the removal of a portion of the initial channel layer 221, thereby forming the gate dielectric layer 126.

[0152] For example, the initial channel layer 221 and the first electrode 123, and the initial channel layer 221 and the first electrode 111, have overlapping portions in the first direction X. The end faces of the initial channel layer 221 along the first direction X are closer to the end faces of the dielectric pillar 101 along the first direction X than the end faces of the corresponding gate structure 122 along the first direction X.

[0153] Thus, transistor 120 is formed, which includes a channel layer 121, a gate structure 122, a first electrode 123, and a gate dielectric layer 126. Understandably, since the channel layer 121 connects the first electrode 111 and the first electrode 123, the first electrode 111 is equivalent to the second electrode of transistor 120.

[0154] In some implementations, please refer to [link / reference]. Figure 22 and combined Figure 21a and Figure 7a The surfaces of the first electrode 123 and the first electrode 111 may be covered with an initial intercalation layer 224. Therefore, a portion of the initial channel layer 221 and the initial intercalation layer 224 can be removed simultaneously. Thus, the initial intercalation layer 224 forms a first intercalation layer 124 and a second intercalation layer 125. The end faces of the initial channel layer 221 at both ends along the first direction X are aligned with the two opposite end faces of the first intercalation layer 124 and the second intercalation layer 125, respectively.

[0155] In some implementations, please refer to Figure 23 and combined Figure 21a , Figure 22 and Figure 7a Before removing a portion of the initial channel layer 221 to form the channel layer 121, an isolation layer 230 may be formed, covering the exposed surfaces of the gate structure 122 and the initial gate dielectric layer 226. The exposed surfaces of the gate structure 122 may include surfaces of the initial gate layer 222 on adjacent dielectric pillars 101 that are not bonded together. Thus, a portion of the isolation layer 230 can be removed simultaneously with the removal of a portion of the initial channel layer 221 to form the isolation structure 130.

[0156] Please continue reading Figure 24 and Figure 25 A capacitor 110 can be formed at one end of a dielectric pillar 101 by depositing a dielectric layer 113 and a second electrode 112. The capacitor 110 includes a first electrode 111, a second electrode 112 and a dielectric layer 113.

[0157] Please combine Figure 24 , Figure 12 and Figure 13 The dielectric layer 113 and the second electrode 112 may include portions formed on the end face of the dielectric pillar 101 along the first direction X. Since the end face of the dielectric pillar 101 along the first direction X is connected to the spacer 203, a gap needs to be formed between the end face of the dielectric pillar 101 along the first direction X and the spacer 203 before forming the dielectric layer 113 and the second electrode 112. For example, a portion of the spacer 203 may be etched away to separate the dielectric pillar 101 and the spacer 203 from each other.

[0158] Understandably, adjacent medium columns 101 in the third direction Z are supported by a spacer 203. If a gap is directly formed between the end face of the medium column 101 in the first direction X and the spacer 203, the medium column 101 will collapse in the third direction Z. Therefore, a structure supporting the medium column 101 in the third direction Z can be formed before forming a gap.

[0159] For example, dielectric material can be deposited first to fill the gaps as a support structure. Subsequently, a deep hole can be formed at the end of the dielectric pillar 101 opposite to the spacer 203, penetrating the stacked dielectric pillar 101 in the third direction Z. This deep hole can contact the first electrode 123 of the dielectric pillar 101, and then a conductive material can be formed in this through-hole. Thus, the conductive material can serve as both a support structure and a bit line.

[0160] Understandably, to facilitate the connection of peripheral circuits to word lines or bit lines of the memory array 10, the memory array 10 may also include step regions, which facilitate connection to the stacked memory cells in the memory array 10. When the word lines formed by the connection of adjacent gate structures 122 in the second direction Y are parallel to the surface of the substrate, each step of the peripheral circuit in the step region is connected to the word lines of the corresponding layer of each step. When the word lines formed by the connection of adjacent gate structures 122 in the second direction Y are perpendicular to the surface of the substrate, the bit lines are parallel to the surface of the substrate, and each step of the peripheral circuit in the step region is connected to the bit lines of the corresponding layer of each step. Therefore, the fabrication process of the memory array 10 may also include process steps for forming step regions and bit lines. Understandably, appropriate process steps can be used to form the step regions and bit lines, which can be done before or after the formation of memory cells, or during the formation of memory cells; this application will not elaborate further.

[0161] In some embodiments, the formed dielectric layer 113 and the second electrode 112 may only surround one end of the dielectric pillar 101, that is, the dielectric layer 113 and the second electrode 112 do not cover the end face of the dielectric pillar 101 along the first direction X. Thus, the dielectric pillar 101 is still supported by the spacer 203 in the third direction Z.

[0162] In some embodiments, the two ends of the dielectric column 101 along the first direction X can be connected to the spacer 203 respectively. Thus, after one end of the dielectric column 101 along the first direction X forms a gap with one spacer 203, the other end of the dielectric column 101 along the first direction X remains connected to the other spacer 203. This also allows for the formation of... Figure 25 The dielectric layer 113 and the second electrode 112 are shown.

[0163] Finally, other structures for the memory array can also be formed, such as forming dielectric material 240 to fill any gaps that may exist. These will not be elaborated further in this application.

[0164] The foregoing preferred embodiments have further illustrated the objectives, technical solutions, and advantages of the present invention. It should be understood that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A storage array, characterized in that, include: A medium column extending along a first direction; A capacitor is disposed at a first end of the dielectric pillar, the capacitor including a first electrode disposed around the first end of the dielectric pillar; A transistor is disposed adjacent to the capacitor. The transistor includes a channel layer, a first electrode, and a gate structure. The channel layer is disposed around the dielectric pillar. A first end of the channel layer is connected to the first electrode, a second end of the channel layer is connected to the first electrode of the capacitor, and the gate structure is disposed around the channel layer.

2. The storage array as described in claim 1, characterized in that, The first end of the channel layer surrounds the first electrode, and the second end of the channel layer surrounds the first electrode of the capacitor.

3. The storage array as described in claim 1 or 2, characterized in that, The transistor further includes a first intercalation layer and a second intercalation layer. The first intercalation layer is disposed between a first end of the channel layer and the first electrode, and is in contact with the channel layer and the first electrode. The second intercalation layer is disposed between a second end of the channel layer and the first electrode of the capacitor, and is in contact with the channel layer and the first electrode of the capacitor.

4. The storage array as described in claim 3, characterized in that, The Fermi level of the material of the first intercalation layer is between the Fermi level of the material of the first electrode and the Fermi level of the material of the channel layer, and the Fermi level of the material of the second intercalation layer is between the Fermi level of the material of the first electrode and the Fermi level of the material of the channel layer.

5. The storage array as described in any one of claims 1 to 4, characterized in that, The shape of the medium column along the cross section perpendicular to the first direction is rectangular or square.

6. The storage array as described in any one of claims 1 to 5, characterized in that, The plurality of the medium columns are repeatedly arranged along a second direction and a third direction, both of which are perpendicular to the first direction, and the second direction and the third direction are perpendicular to each other; The distance between adjacent dielectric columns along the second direction is less than the distance between adjacent dielectric columns along the third direction; Along the second direction, the gate structures of adjacent transistors are interconnected to form word lines.

7. The storage array as described in claim 6, characterized in that, It also includes a substrate, wherein the second direction is parallel to the surface of the substrate.

8. The storage array as described in claim 6, characterized in that, It also includes a substrate, wherein the second direction is perpendicular to the surface of the substrate.

9. The storage array as described in any one of claims 6 to 8, characterized in that, It also includes bit lines that connect the first terminals of transistors on a plurality of dielectric pillars arranged along the third direction.

10. The storage array as described in any one of claims 6 to 9, characterized in that, It also includes an isolation structure, the isolation structure including a first isolation portion; the gate structure includes a first gate portion, a second gate portion and a third gate portion arranged and connected sequentially along the first direction; The first isolation portion of the isolation structure is disposed around the second gate portion of the gate structure; Along the second direction, the first gate portions of the gate structures of adjacent transistors are connected, and the third gate portions of the gate structures of adjacent transistors are connected.

11. The storage array as claimed in claim 10, characterized in that, It also includes a gate dielectric layer surrounding the channel layer, the gate dielectric layer being located between the channel layer and the gate structure and extending in a first direction; The isolation structure further includes a second isolation portion and a third isolation portion, wherein the second isolation portion and the third isolation portion are respectively disposed at both ends of the gate structure along the first direction, and are respectively connected to the gate dielectric layer of the transistor adjacent along the second direction.

12. The storage array as claimed in claim 11, characterized in that, The second isolation portion of the isolation structure is opposite to the end face of the gate structure along the first direction, and is flush with one end face of the gate dielectric layer near the second isolation portion of the isolation structure, and one end face of the channel layer near the second isolation portion of the isolation structure. The third isolation portion of the isolation structure is opposite to the end face of the gate structure along the first direction, and is flush with the end face of the gate dielectric layer near the third isolation portion of the isolation structure and the end face of the channel layer near the third isolation portion of the isolation structure.

13. The storage array as described in claim 11 or 12, characterized in that, The capacitor further includes a dielectric layer and a second electrode. The dielectric layer is disposed between the first electrode and the second electrode and covers the end faces of the gate dielectric layer at opposite ends in the first direction, the end faces of the channel layer at opposite ends in the first direction, and the end faces of the second isolation portion and the third isolation portion of the isolation structure that are respectively away from the gate structure along the first direction.

14. The storage array as described in any one of claims 1 to 13, characterized in that, The capacitor further includes a second electrode and a dielectric layer, wherein the second electrode is disposed at least partially surrounding the first electrode, and the dielectric layer is disposed between the first electrode and the second electrode.

15. The storage array as claimed in claim 14, characterized in that, The number of capacitors is multiple, and the second electrodes of the multiple capacitors are interconnected.

16. The storage array as claimed in claim 12 or 13, characterized in that, A portion of the dielectric layer and a portion of the second electrode are disposed on the end face of the second end of the dielectric pillar.

17. The storage array as described in any one of claims 1 to 16, characterized in that, The material of the medium column includes any one or a combination of oxides or nitrides.

18. The storage array as claimed in any one of claims 1 to 17, characterized in that, The material of the channel layer includes metal oxides.

19. A method for fabricating a memory array, characterized in that, include: Multiple dielectric pillars are formed in an array on a substrate, the dielectric pillars extending along a first direction, the first direction being perpendicular or parallel to the substrate; A first electrode and a first pole are formed, wherein the first electrode is located at a first end of the dielectric pillar and surrounds the dielectric pillar, and the first pole is located at a second end of the dielectric pillar and surrounds the dielectric pillar; A channel layer and a gate structure are formed, wherein the channel layer is at least partially located between the first electrode and the first pole, the channel layer is connected to the first electrode and the first pole and surrounds the dielectric pillar, and the gate structure surrounds the channel layer; The first electrode is used to form a capacitor, and the channel layer, the first electrode, and the gate structure are used to form a transistor.

20. The method for fabricating a storage array as described in claim 19, characterized in that, The formation of the first electrode and the first pole includes: A first conductive layer is formed on the dielectric pillar, and the first conductive layer surrounds the dielectric pillar; The portion of the first conductive layer located between the first end and the second end of the dielectric pillar is removed. The portion of the first conductive layer surrounding the first end of the dielectric pillar forms the first electrode, and the portion of the first conductive layer surrounding the second end of the dielectric pillar forms the first pole.

21. The method for fabricating a storage array as described in claim 19 or 20, characterized in that, The formation of the channel layer and gate structure includes: An initial channel layer and an initial gate layer are formed, the initial channel layer surrounding the dielectric pillar and covering the first electrode and the first pole, and the initial gate layer surrounding the initial channel layer; At least a portion of the initial channel layer and the initial gate layer covering the first electrode and the first pole is removed, and the portion of the initial channel layer and the initial gate layer located at least between the first electrode and the first pole forms the channel layer and the gate structure.

22. A memory, characterized in that, It includes a controller and a storage array as described in any one of claims 1 to 18, wherein the controller is connected to the storage array.

23. An electronic device, characterized in that, It includes a circuit board and a memory as described in claim 22, the memory being disposed on the circuit board.

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