Semiconductor device

Abstract

A semiconductor device with excellent transistor characteristics is provided, comprising: first and second oxide semiconductor layers extending along a first direction and arranged in a second direction, comprising a first metal element and oxygen; a first conductive layer extending in the second direction and opposing a portion of the outer peripheral surface of the first and second oxide semiconductor layers; and first and second gate insulating layers disposed between the first and second oxide semiconductor layers and the first conductive layer. In a first cross-section extending along a third direction and including the first and second oxide semiconductor layers and the first conductive layer, the first conductive layer comprises: an annular first portion spaced apart from the outer peripheral surface of the first oxide semiconductor layer by a first width and surrounding the first oxide semiconductor layer; and an annular second portion spaced apart from the outer peripheral surface of the second oxide semiconductor layer by a first width and surrounding the second oxide semiconductor layer. A portion of a circle, ellipse, or oblong circle externally tangent to the first portion and the second portion overlaps with each other.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device. Background Technology

[0002] A semiconductor device is known to have an oxide semiconductor layer, a first wiring opposite to the oxide semiconductor layer, and a gate insulating film disposed between the oxide semiconductor layer and the first wiring. Summary of the Invention

[0003] The present invention provides a semiconductor device with excellent transistor characteristics.

[0004] A semiconductor device according to one embodiment includes: a substrate; a first oxide semiconductor layer and a second oxide semiconductor layer extending in a first direction intersecting a surface of the substrate and arranged in a second direction intersecting the first direction, comprising a first metal element and oxygen (O); a first conductive layer extending in the second direction and opposing a portion of the outer peripheral surface of the first oxide semiconductor layer and a portion of the outer peripheral surface of the second oxide semiconductor layer; a first gate insulating layer disposed between the first oxide semiconductor layer and the first conductive layer; and a second gate insulating layer disposed between the second oxide semiconductor layer and the first conductive layer. In a first cross-section extending along the second direction and a third direction intersecting the first and second directions and including the first oxide semiconductor layer, the second oxide semiconductor layer, and the first conductive layer, the first conductive layer includes: an annular first portion disposed at a first width spaced from the outer peripheral surface of the first oxide semiconductor layer and surrounding the first oxide semiconductor layer; and an annular second portion disposed at a first width spaced from the outer peripheral surface of the second oxide semiconductor layer and surrounding the second oxide semiconductor layer. A portion of a circle, ellipse, or oblong circumscribed by the first portion and a portion of a circle, ellipse, or oblong circumscribed by the second portion overlap. Attached Figure Description

[0005] Figure 1 This is a schematic circuit diagram showing the structure of a portion of the semiconductor device according to the first embodiment.

[0006] Figure 2 It is a schematic cross-sectional view showing a portion of the structure of the semiconductor device.

[0007] Figure 3 It is a schematic cross-sectional view showing a portion of the structure of the semiconductor device.

[0008] Figure 4 This is a schematic three-dimensional view showing a portion of the structure of the semiconductor device.

[0009] Figure 5 This is a schematic top view showing a portion of the structure of the semiconductor device.

[0010] Figure 6 This is a schematic top view showing a portion of the structure of the semiconductor device.

[0011] Figure 7 This is a schematic top view showing a portion of the structure of the semiconductor device.

[0012] Figure 8 This is a schematic top view showing a portion of the structure of the semiconductor device.

[0013] Figure 9 This is a schematic top view showing a portion of the structure of the semiconductor device.

[0014] Figure 10 This is a schematic three-dimensional view showing a portion of the structure of the semiconductor device.

[0015] Figure 11 It is a schematic cross-sectional view showing a portion of the structure of the semiconductor device.

[0016] Figure 12 It is a schematic cross-sectional view showing a portion of the structure of the semiconductor device.

[0017] Figure 13 This is a schematic top view showing a portion of the structure of the semiconductor device.

[0018] Figure 14 It is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device.

[0019] Figure 15 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0020] Figure 16 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0021] Figure 17 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0022] Figure 18 This is a schematic top view used to illustrate the manufacturing method.

[0023] Figure 19 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0024] Figure 20 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0025] Figure 21 This is a schematic top view used to illustrate the manufacturing method.

[0026] Figure 22 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0027] Figure 23 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0028] Figure 24 This is a schematic top view used to illustrate the manufacturing method.

[0029] Figure 25 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0030] Figure 26 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0031] Figure 27 This is a schematic top view used to illustrate the manufacturing method.

[0032] Figure 28 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0033] Figure 29 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0034] Figure 30 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0035] Figure 31 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0036] Figure 32 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0037] Figure 33 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0038] Figure 34 This is a schematic top view used to illustrate the manufacturing method.

[0039] Figure 35 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0040] Figure 36 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0041] Figure 37 This is a schematic top view used to illustrate the manufacturing method.

[0042] Figure 38 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0043] Figure 39It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0044] Figure 40 This is a schematic top view used to illustrate the manufacturing method.

[0045] Figure 41 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0046] Figure 42 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0047] Figure 43 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0048] Figure 44 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0049] Figure 45 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0050] Figure 46 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0051] Figure 47 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0052] Figure 48 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0053] Figure 49 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0054] Figure 50 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0055] Figure 51 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0056] Figure 52 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0057] Figure 53 This is a schematic cross-sectional view showing a portion of the structure of a modified example 1 of the semiconductor device according to the first embodiment.

[0058] Figure 54 This is a schematic top view showing a portion of the structure of this variant example.

[0059] Figure 55 This is a schematic cross-sectional view used to illustrate the manufacturing method of this modified example.

[0060] Figure 56 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0061] Figure 57 This is a schematic top view showing a portion of the structure of a modified example 2 of the semiconductor device according to the first embodiment.

[0062] Figure 58 This is a schematic three-dimensional diagram showing a portion of the structure of this modified example.

[0063] Figure 59 This is a schematic cross-sectional view showing a portion of the structure of this variant example.

[0064] Figure 60 This is a schematic top view showing a portion of the structure of a modified example 3 of the semiconductor device according to the first embodiment.

[0065] Figure 61 This is a schematic three-dimensional diagram showing a portion of the structure of this modified example.

[0066] Figure 62 This is a schematic cross-sectional view showing a portion of the structure of this variant example.

[0067] Figure 63 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor device according to the second embodiment.

[0068] Figure 64 It is a schematic cross-sectional view showing a portion of the structure of the semiconductor device.

[0069] Figure 65 It is a schematic cross-sectional view showing a portion of the structure of the semiconductor device.

[0070] Figure 66 It is a schematic cross-sectional view showing a portion of the structure of the semiconductor device.

[0071] Figure 67 This is a schematic cross-sectional view used to illustrate method 1 of manufacturing the semiconductor device.

[0072] Figure 68 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0073] Figure 69 This is a schematic top view used to illustrate the manufacturing method.

[0074] Figure 70 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0075] Figure 71 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0076] Figure 72 This is a schematic top view used to illustrate the manufacturing method.

[0077] Figure 73 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0078] Figure 74 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0079] Figure 75 This is a schematic top view used to illustrate the manufacturing method.

[0080] Figure 76 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0081] Figure 77 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0082] Figure 78 This is a schematic top view used to illustrate the manufacturing method.

[0083] Figure 79 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0084] Figure 80 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0085] Figure 81 This is a schematic top view used to illustrate the manufacturing method.

[0086] Figure 82 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0087] Figure 83 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0088] Figure 84 This is a schematic top view used to illustrate the manufacturing method.

[0089] Figure 85 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0090] Figure 86 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0091] Figure 87 This is a schematic top view used to illustrate the manufacturing method.

[0092] Figure 88 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0093] Figure 89It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0094] Figure 90 This is a schematic top view used to illustrate the manufacturing method.

[0095] Figure 91 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0096] Figure 92 This is a schematic cross-sectional view used to illustrate method 2 of manufacturing the semiconductor device.

[0097] Figure 93 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0098] Figure 94 This is a schematic top view used to illustrate the manufacturing method.

[0099] Figure 95 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0100] Figure 96 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0101] Figure 97 This is a schematic top view used to illustrate the manufacturing method.

[0102] Figure 98 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0103] Figure 99 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0104] Figure 100 This is a schematic top view used to illustrate the manufacturing method.

[0105] Figure 101 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0106] Figure 102 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0107] Figure 103 This is a schematic top view used to illustrate the manufacturing method.

[0108] Figure 104 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0109] Figure 105 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0110] Figure 106This is a schematic top view used to illustrate the manufacturing method.

[0111] Figure 107 This is a schematic cross-sectional view showing a portion of the structure of a modified example 1 of the semiconductor device according to the second embodiment.

[0112] Figure 108 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor device according to the third embodiment.

[0113] Figure 109 This is a schematic top view showing a portion of the structure of the semiconductor device.

[0114] Figure 110 This is a schematic three-dimensional view showing a portion of the structure of the semiconductor device.

[0115] Figure 111 It is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device.

[0116] Figure 112 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0117] Figure 113 This is a schematic top view used to illustrate the manufacturing method.

[0118] Figure 114 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0119] Figure 115 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0120] Figure 116 This is a schematic top view used to illustrate the manufacturing method.

[0121] Figure 117 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0122] Figure 118 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0123] Figure 119 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0124] Figure 120 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0125] Figure 121 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0126] Figure 122 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0127] Figure 123 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0128] Figure 124 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0129] Figure 125 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0130] Figure 126 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0131] Figure 127 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0132] Figure 128 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0133] Figure 129 This is a schematic top view used to illustrate the manufacturing method.

[0134] Figure 130 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0135] Figure 131 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0136] Figure 132 This is a schematic top view used to illustrate the manufacturing method.

[0137] Figure 133 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor device according to the third embodiment. Detailed Implementation

[0138] Next, the semiconductor device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic, and for ease of explanation, some structures may be omitted. Furthermore, the same reference numerals are used to denote common parts in multiple embodiments, and descriptions may sometimes be omitted.

[0139] Furthermore, in this specification, when the first structure and the second structure are referred to as "electrically connected," the first structure can be directly connected to the second structure, or the first structure can be connected to the second structure via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the off state, the first transistor is still "electrically connected" to the third transistor.

[0140] In addition, in this specification, the direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0141] In addition, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0142] Furthermore, in this specification, the terms "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when referring to a structure as a lower surface or lower end, it refers to the surface or end of the structure on the substrate side; when referring to an upper surface or upper end, it refers to the surface or end of the structure on the opposite side from the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, outer peripheral surfaces, etc.

[0143] (First Implementation)

[0144] [Circuit Structure]

[0145] Figure 1 This is a schematic circuit diagram showing a portion of the structure of the semiconductor device according to the first embodiment. The semiconductor device of the first embodiment, for example, includes... Figure 1 The storage cell array MCA and its peripheral circuit PC are shown.

[0146] The memory cell array (MCA) has multiple bit lines (BL), multiple word lines (WL), multiple board lines (PL), and multiple memory cells (MC) connected to these bit lines (BL), word lines (WL), and board lines (PL). Multiple memory cells (MC) connected to a single word line (WL) are each connected to a different bit line (BL). Furthermore, multiple memory cells (MC) connected to a single bit line (BL) are each connected to a different word line (WL).

[0147] Each memory cell MC has a selection transistor ST and a capacitor Cap connected in series between the bit line BL and the board line PL.

[0148] The selector transistor (ST) is a field-effect transistor (FET) that comprises a semiconductor layer that functions as a channel region, a gate insulating layer, and a gate electrode. The gate electrode of the selector transistor (ST) is connected to the word line (WL).

[0149] A capacitor (Cap) is a capacitor that has a pair of electrodes and an insulating film. A capacitor (Cap) includes a storage section.

[0150] Peripheral circuits (PCs) may include, for example, a voltage generation circuit that generates an operating voltage and outputs it to a voltage supply line, a decoding circuit that enables the desired voltage supply line to conduct to the wiring (bit line BL, word line WL, and board line PL) within the memory cell array (MCA), and a readout amplifier circuit that senses the current or voltage of the bit line BL.

[0151] Figure 2 It is a schematic cross-sectional view showing a portion of the structure of a semiconductor device. For example... Figure 2 As shown, the semiconductor device of the first embodiment includes: a substrate Sub; and a transistor layer L. Tr It is separated from the substrate Sub in the Z direction; wiring layer L ML Set in transistor layer L Tr Above; wiring layer L UL Set in wiring layer L ML Above; capacitor layer L CP Set in transistor layer L Tr Below; plate line layer L PT Set in capacitor layer L CP Below; and surrounding circuit layer L PC In the L-line layer of the board PT The substrate Sub is disposed below the substrate Sub. The substrate Sub may contain, for example, P-type silicon (Si) containing P-type impurities such as boron (B).

[0152] Furthermore, the semiconductor device of the first embodiment, such as Figure 2 As shown, it has a storage region R disposed on the substrate Sub. MC and surrounding areas R PC .

[0153] [Storage Area R] MC [Structure]

[0154] Next, refer to Figures 2-8 For storage area R MC The structure is explained. Figures 3-8 These are schematic cross-sectional views, top views, and perspective views showing a portion of the structure of the semiconductor device according to the first embodiment. Figure 3 Storage area R is shown MC A part of the structure. Figure 4 Transistor layer L is shown Tr Structure and its relationship with transistor layer L Tr The connection part. Furthermore, in Figure 4 For ease of explanation, the portion of the insulating layer 140 located above and below the conductive layer 150 is omitted from the illustration. Figure 5 It is Figure 3 The structure shown is a schematic top view cut along line AA′ and viewed in the direction of the arrow. Figure 6 It is Figure 3 The structure shown is a schematic top view cut along line BB′ and viewed in the direction of the arrow. Figure 7 It is Figure 3 The structure shown is a schematic top view cut along line CC′ and viewed in the direction of the arrow. Additionally, in Figure 7 In the middle, it is represented by a dashed line. Figure 6 Part of the structure shown. Figure 8 It is Figure 5 An enlarged schematic top view of a portion of the structure shown.

[0155] Storage area R MC transistor layer L Tr For example, Figure 3 As shown, it has a capacitor layer L CP The upper surface of the insulating layer 111, and the insulating layer 113 disposed above the insulating layer 111. Additionally, the storage area R... MC transistor layer L Tr For example, Figure 5 As shown, the device includes a plurality of insulating layers 112 and a plurality of conductive layers 150 disposed between insulating layers 111 and 113 and arranged alternately in the Y direction. Additionally, the storage region R... MC transistor layer L Tr For example, Figure 4 and Figure 5 As shown, the device includes a plurality of semiconductor layers 130 arranged in the X direction corresponding to the conductive layer 150 extending in the X direction, and an insulating layer 140 disposed between the semiconductor layers 130 and the conductive layer 150.

[0156] In addition, for example, Figure 5 As shown, the positions of the plurality of semiconductor layers 130 arranged corresponding to one of the two adjacent conductive layers 150 in the Y direction and the plurality of semiconductor layers 130 arranged corresponding to the other conductive layer 150 in the X direction can also be different.

[0157] In addition, for example, Figure 5 As shown, the direction in which the semiconductor layers 130 are arranged corresponding to different conductive layers 150 is sometimes referred to as the Y2 direction. Figure 5 The Y2 direction is a direction different from the X direction. The Y2 direction can be different from or the same as the Y direction. Additionally, the direction intersecting both the Y2 and Z directions is sometimes referred to as the X2 direction. Figure 5 ).

[0158] Insulating layers 111, 112, and 113 may contain, for example, silicon oxide (SiO2).

[0159] Semiconductor layer 130 extends, for example, along the Z direction and has a generally cylindrical shape. Semiconductor layer 130 is an oxide semiconductor, for example, used as a select transistor ST( Figure 1 The channel region of the semiconductor layer 130 functions as such. The semiconductor layer 130, for example, contains at least one element selected from the group GP1 of metal elements and oxygen (O).

[0160] The metal group GP1 includes indium (In), gallium (Ga), aluminum (Al), zinc (Zn), tin (Sn), titanium (Ti), tungsten (W), and molybdenum (Mo).

[0161] Semiconductor layer 130 may include, for example, indium (In), zinc (Zn) and oxygen (O), or indium (In), gallium (Ga) and oxygen (O), or gallium (Ga), zinc (Zn) and oxygen (O), or indium (In), gallium (Ga), zinc (Zn) and oxygen (O), or indium (In), gallium (Ga), tin (Sn) and oxygen (O), or indium (In), tungsten (W) and oxygen (O).

[0162] For example, Figure 5 As shown, in an XY cross-section comprising multiple semiconductor layers 130 and multiple conductive layers 150, the closest distance between the outer peripheral surfaces of one semiconductor layer 130 and the outer peripheral surface of the other semiconductor layer 130 arranged in the X direction is the width DX10. Furthermore, in two semiconductor layers 130 arranged in the Y2 direction, the closest distance between the outer peripheral surfaces of one semiconductor layer 130 and the outer peripheral surface of the other semiconductor layer 130 is the width DT10. Width DT10 is greater than width DX10.

[0163] The insulating layer 140 extends, for example, along the Z-direction and has a generally cylindrical shape. The insulating layer 140 is, for example, disposed on at least a portion of the outer peripheral surface of the semiconductor layer 130. The insulating layer 140 serves, for example, as a selection transistor ST. Figure 1 The gate insulating layer 140 functions as a gate insulating layer. The insulating layer 140 may include, for example, silicon oxide (SiO2), silicon nitride (SiN), or other insulating layers with high dielectric constants. The insulating layer 140 may also be a stacked structure comprising two or more layers of silicon oxide (SiO2), silicon nitride (SiN), and other insulating layers with high dielectric constants.

[0164] Conductive layer 150, for example Figure 3 and Figure 4 As shown, it is opposite to a portion of the outer peripheral surface of the semiconductor layer 130. The conductive layer 150 is, for example, as shown... Figure 4 As shown, a generally cylindrical portion surrounding a portion of the semiconductor layer 130 and a portion of the insulating layer 140 is disposed connected in the X direction. At least one surface S11 of the conductive layer 150 in the Y direction... Figure 4 , Figure 8It does not include the planar portion, but is set with curved surfaces connected.

[0165] For example, in such Figure 8 The diagram shows an XY cross-section of two adjacent semiconductor layers 130 in the X direction. The conductive layer 150 includes annular portions PT11 that are spaced apart from the outer peripheral surfaces of the semiconductor layers 130 by a width DW11 and surround the semiconductor layers 130. The width DW11 is, for example, equivalent to the film thickness of the insulating layer 140. Figure 8 In the XY section shown, a portion of the external tangent line OT that is externally tangent to one part of PT11 overlaps with a portion of the external tangent line OT that is externally tangent to the other part of PT11. The external tangent line OT is, for example, a circle, an ellipse, or an oblong.

[0166] In addition, Figure 8 In the XY cross-section shown, the PT11 sections arranged along the X direction partially overlap. Figure 5 and Figure 8 In the diagram, the overlapping portions of the PT11 arranged along the X direction are respectively illustrated as regions R10. Furthermore, the portion of the outer peripheral surface of the PT11 other than the portion included in region R10 is in contact with the insulating layer 112.

[0167] The conductive layer 150 serves, for example, as the gate electrode of a plurality of selection transistors ST arranged in the X direction and the word line WL of the memory cell array MCA. Figure 1 The conductive layer 150 can be, for example, tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), etc., or may contain a stacked structure of one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru) and cobalt (Co) with titanium nitride (TiN).

[0168] Storage area R MC wiring layer L ML For example, Figure 3 As shown, it has a transistor layer L Tr The plug layer L on the upper surface LP and set in the plug layer L LP Bit line layer L on the upper surface BL .

[0169] Plug layer L LP For example, Figure 3 and Figure 6 As shown, at the position corresponding to the semiconductor layer 130, transistor layers L are sequentially disposed. TrThe upper surface of the conductive layer 170, conductive layer 171, and conductive layer 172 are electrically connected to the semiconductor layer 130. Furthermore, the structure including conductive layer 170, conductive layer 171, and conductive layer 172 is sometimes referred to as a plug LP. Additionally, the configuration of the plug LP can be appropriately adjusted; for example, any one of conductive layer 170, conductive layer 171, and conductive layer 172 may be omitted.

[0170] For example, plug LP Figure 3 and Figure 6 As shown, multiple plugs LP extend in the Z direction and are arranged in the X and Y directions. The plugs LP function as, for example, the source electrodes of a selection transistor ST. An insulating layer 173, such as silicon oxide (SiO2), is provided between the multiple plugs LP.

[0171] The conductive layer 170 may contain, for example, at least one element selected from the metal group GP2 and oxygen (O). The metal group GP2 includes indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), niobium (Nb), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo). The conductive layer 170 may also be, for example, indium tin oxide (InSnO). In addition, the conductive layer 170 may also comprise a laminate containing at least one of these materials.

[0172] The conductive layer 171 may include, for example, titanium nitride (TiN) and titanium oxide (TiO). Alternatively, the conductive layer 171 may also comprise a laminate containing at least one of these materials.

[0173] The conductive layer 172 may contain, for example, tungsten (W), aluminum (Al), molybdenum (Mo), etc. Alternatively, the conductive layer 172 may also contain a laminated film containing at least one of these materials.

[0174] Bitline layer L BL For example, Figure 3 and Figure 7 As shown, at the position corresponding to the conductive layer 172, there is a plug layer L LP A portion of the upper surface is provided with conductive layers 182 and 184 sequentially. Conductive layers 182 and 184 are electrically connected to a plurality of conductive layers 172 arranged in the Y direction corresponding to conductive layers 182 and 184. Figure 7 Furthermore, the structure of conductive layer 182 and conductive layer 184 can be appropriately adjusted; for example, either conductive layer 182 or conductive layer 184 can be omitted.

[0175] The structure including conductive layer 182 and conductive layer 184 is as follows: Figure 3 and Figure 7As shown, multiple conductive layers 182 and 184 are arranged extending in the Y direction and arranged in the X direction. Conductive layers 182 and 184 serve, for example, as bit lines BL of the memory cell array MCA. Figure 1 To enable them to function. An insulating layer 183, such as silicon oxide (SiO2), is placed between these structures arranged along the X direction.

[0176] The conductive layer 182 may contain metallic elements such as tungsten (W), aluminum (Al), and molybdenum (Mo).

[0177] The conductive layer 184 may contain, for example, titanium nitride (TiN).

[0178] Storage area R MC capacitor layer L CP For example, Figure 2 and Figure 3 As shown, the device includes: a plurality of conductive layers 120 disposed corresponding to a plurality of semiconductor layers 130 and respectively connected to the lower ends of the plurality of semiconductor layers 130; a plurality of conductive layers 201 disposed corresponding to the plurality of conductive layers 120 and respectively connected to the lower ends of the plurality of conductive layers 120; and a plurality of conductive layers 121 disposed on the outer peripheral surfaces of the plurality of conductive layers 120 and on the outer peripheral surfaces and lower surfaces of the plurality of conductive layers 201. Additionally, a capacitor layer L... CP It includes an insulating layer 202 disposed on the outer peripheral surface and the lower surface of the conductive layer 121, and a conductive layer 203 disposed on the outer peripheral surface and the lower surface of the insulating layer 202. Figure 3 Furthermore, in the following description, implementations will sometimes be made in these storage areas R. MC capacitor layer L CP The set capacitor Cap( Figure 1 The structure of the capacitor is called "capacitor structure CP10". Capacitor structure CP10 includes, for example, conductive layer 120, conductive layer 121, conductive layer 201, insulating layer 202, and conductive layer 203. An insulating layer 100, such as silicon oxide (SiO2), is provided between multiple capacitor structures CP10.

[0179] Conductive layer 120, for example, serves as a selection transistor ST. Figure 1 The drain electrode and capacitor Cap () Figure 1 It functions as part of an electrode. The conductive layer 120 is generally circular in the XY cross-section, but may also have a plug shape. The conductive layer 120 may, for example, contain the same material as the conductive layer 170. The conductive layer 120 may also be, for example, indium tin oxide (InSnO) or the like.

[0180] Conductive layer 121 serves as, for example, a capacitor Cap ( Figure 1 It functions as part of an electrode. The conductive layer 121 can also be, for example, titanium nitride (TiN) or the like.

[0181] Conductive layer 201 serves as capacitor Cap( Figure 1 It functions as part of an electrode. The conductive layer 201 may contain, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0182] Insulating layer 202 serves as capacitor Cap( Figure 1 The insulating layer between the electrodes functions as a conductor. The insulating layer 202 may contain, for example, aluminum oxide (AlO). The insulating layer 202 may also be, for example, silicon oxide (SiO2) or other insulating metal oxides.

[0183] Conductive layer 203, for example, serves as capacitor Cap( Figure 1 The other electrode functions. The conductive layer 203 may contain, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0184] For example, such as Figure 2 As shown, storage area R MC L-layer of the board PT Including the capacitor layer L CP A conductive layer 204 is located on the lower surface of the substrate. The conductive layer 204 is electrically connected to multiple conductive layers 203. The conductive layer 204 serves, for example, as a plate line PL (…). Figure 1 To perform its function. The conductive layer 204 may also include, for example, a stacked structure of tungsten (W), or titanium nitride (TiN) and tungsten (W).

[0185] [Surrounding Area R] PC [Structure]

[0186] Next, refer to Figure 2 as well as Figures 9-13 For the surrounding area R PC ( Figure 2 The structure of ) will be explained. Figures 9-13 These are schematic cross-sectional views, top views, and perspective views showing a portion of the semiconductor device according to the first embodiment. Figure 9 It is Figure 2 The structure shown is a schematic top view cut along line DD′ and viewed in the direction of the arrow. Furthermore, in Figure 9 In order to indicate the positional relationship, the conductive layer 150, which is not shown in this cross-section, and a portion of the electrodes C1_WL and C1_WLP, which will be described later, are represented by dashed lines. Figure 10 Storage area R is shown MC and surrounding areas R PC The structure. Figure 11 The region R is shown PC1 A part of the structure. Figure 12 The region R is shown PC2 A part of the structure. Figure 13The structure of the end of the conductive layer 150 is shown.

[0187] Surrounding area R PC L-layer of the board PT For example, Figure 2 As shown, it includes multiple conductive layers 205. The conductive layers 205 may, for example, contain the same material as the conductive layer 204.

[0188] Surrounding area R PC peripheral circuit layer L PC For example, Figure 2 As shown, the substrate includes multiple transistors TrP1 disposed on a substrate Sub and multiple electrodes 210 connected to the multiple transistors TrP1. The multiple electrodes 210 are connected to a conductive layer 205 at their upper ends, for example. The multiple electrodes 210 are connected to the source region, drain region, gate electrode, etc., of the multiple transistors TrP1 at their lower ends, for example. The multiple transistors TrP1 constitute a peripheral circuit PC (PC). Figure 1 ).

[0189] Surrounding area R PC wiring layer L ML It has a conductive layer BP disposed in the same layer as the bit line BL and an electrode 192 connected to the upper surface of the conductive layer BP.

[0190] Conductive layer BP ( Figure 12 For example, conductive layers 182a and 184a contain the same material as conductive layers 182 and 184.

[0191] Electrode 192, for example Figure 2 As shown, it extends along the Z direction and has a generally cylindrical shape. Electrode 192 may, for example, comprise a stacked structure of tungsten (W), or titanium nitride (TiN) and tungsten (W).

[0192] Wiring layer L UL For example, Figure 2 As shown, it includes the wiring layer L ML Wiring 301 on the upper surface, wiring 302 connected to wiring 301 on the upper surface of wiring 301, and wiring 303 connected to wiring 302 on the upper surface of wiring 302. An insulating layer 304, such as silicon oxide (SiO2), is provided between wiring 301, wiring 302 and wiring 303.

[0193] Wiring 301, wiring 302, and wiring 303 function, for example, as wiring to supply voltage and current to peripheral circuits PC and bit lines BL. Wiring 301, wiring 302, and wiring 303 may contain materials such as copper (Cu), tungsten (W), and aluminum (Al).

[0194] Surrounding area R PCcapacitor layer L CP For example, Figure 2 and Figure 9 As shown, it has multiple through electrodes CC_WL and multiple through electrodes CC_WLP extending along the Z direction. Furthermore, below, the surrounding region R is sometimes referred to as... PC The region containing the through electrode CC_WL is called region R. PC1 The region containing the through electrode CC_WLP is called region R. PC2 Region R PC1 Set in region R PC2 With storage area R MC between( Figure 10 ).

[0195] Through electrode CC_WL, for example Figure 2 As shown, it is connected to the transistor layer L at the upper end. Tr The electrode C1_WL, described later, is electrically connected at its lower end to the plate wire layer L. PT A portion of the multiple conductive layers 205 in Figure 2 For example, the through electrode CC_WL. Figure 10 and Figure 11 As shown, it includes a conductive layer 220 such as tungsten (W) and a conductive layer 221 such as titanium nitride (TiN).

[0196] Through electrode CC_WLP, for example Figure 2 As shown, at the upper end and the transistor layer L Tr The electrode C1_WLP, described later, is connected to the lower end of the plate line layer L. PT A portion of the multiple conductive layers 205 are electrically connected ( Figure 2 For example, the through electrode CC_WLP. Figure 10 and Figure 12 As shown, it includes conductive layer 220 and conductive layer 221.

[0197] [Region R] PC1 [Structure]

[0198] Region R PC1 transistor layer L Tr ( Figure 11 It has storage area R MC transistor layer L Tr ( Figure 3 The same insulating layers 111, 112, 113 and a portion of conductive layer 150. Furthermore, in region R... PC1 transistor layer L Tr One end of the conductive layer 150 is provided in the X direction. Additionally, region R... PC1 transistor layer L TrIt includes semiconductor layers 130D1 and 130D2 arranged in the X direction corresponding to the conductive layer 150, an insulating layer 140 disposed between the semiconductor layers 130D1 and 130D2 and the conductive layer 150, and an electrode C1_WL disposed between the conductive layer 150 and the through electrode CC_WL.

[0199] Semiconductor layers 130D1 and 130D2 are essentially the same as semiconductor layer 130, containing the same material, and arranged in the X direction as semiconductor layer 130. However, semiconductor layers 130D1 and 130D2 are configured as a dummy structure and do not serve as the selection transistor ST. Figure 1 The channel area plays a functional role.

[0200] Electrode C1_WL surrounds a portion of the side surface of semiconductor layer 130D2 and the lower surface of semiconductor layer 130D2. Electrode C1_WL is, for example, as shown in... Figure 10 and Figure 11 As shown, the conductive layer 150a contains the same material as the conductive layer 150, and a conductive layer 152 such as titanium nitride (TiN). The conductive layer 150a may also be formed continuously with the conductive layer 150. The conductive layer 150 is electrically connected to the through electrode CC_WL via the electrode C1_WL.

[0201] Figure 13 The diagram shows the region R. PC1 The semiconductor layer 130D1 and the conductive layer 150 opposite the semiconductor layer 130D1 are disposed at their ends in the X direction. The conductive layer 150 is, for example, located at... Figure 13 In the XY cross-section shown, a portion PT12, separated from the outer peripheral surface of the semiconductor layer 130D1 by a width DW11, is provided and includes an annular portion surrounding the semiconductor layer 130D1. The portion PT12 is at least a portion of the end of the conductive layer 150 in the X direction. A portion of the outer peripheral surface of the portion PT12 is in contact with the insulating layer 112.

[0202] [Region R] PC2 [Structure]

[0203] Region R PC2 transistor layer L Tr ( Figure 12 It has electrodes WLP and C1_WLP.

[0204] The electrode WLP is connected to the conductive layer BP at its upper end and to the electrode C1_WLP at its lower end. The electrode WLP includes a conductive layer 153 such as tungsten (W) and a conductive layer 154 such as titanium nitride (TiN).

[0205] Electrode C1_WLP is disposed between electrode WLP and through electrode CC_WLP. Electrode WLP and through electrode CC_WLP are electrically connected via electrode C1_WLP. Electrode C1_WLP includes conductive layer 150a and conductive layer 152.

[0206] [Manufacturing method of the first embodiment]

[0207] Next, refer to Figures 14 to 52 The manufacturing method of the semiconductor device according to this embodiment will be described. Figures 14 to 52 These are schematic cross-sectional and top views used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0208] also, Figure 14 , Figure 16 , Figure 19 , Figure 22 , Figure 25 , Figure 28 , Figure 30 , Figure 32 , Figure 35 , Figure 38 , Figure 41 , Figure 43 , Figure 45 , Figure 49 as well as Figure 51 Is with Figure 11 A schematic sectional view of the corresponding part. Figure 15 , Figure 17 , Figure 20 , Figure 23 , Figure 26 , Figure 29 , Figure 31 , Figure 33 , Figure 36 , Figure 39 , Figure 42 , Figure 44 , Figure 46 , Figure 50 as well as Figure 52 It is Figure 5 The structure shown is a schematic cross-sectional view cut along line EE′ and corresponding to the portion viewed in the direction of the arrow. Figure 18 , Figure 24 , Figure 27 , Figure 34 , Figure 37 as well as Figure 40 It means and Figure 5 Top view of the same section. Figure 21 It is used to explain the formation Figure 19 as well as Figure 20 A schematic top view of the structure shown. Figure 47 and Figure 48 Is with Figure 12A schematic cross-sectional view of the corresponding part. Additionally, the following drawings illustrating the manufacturing method are schematic; for ease of explanation, some structural elements may be omitted.

[0209] In this manufacturing method, on the substrate Sub( Figure 1 A peripheral circuit layer L is formed above it. PC ( Figure 2 ), Plate line layer L PT ( Figure 2 ) and including through electrodes CC_WL, CC_WLP and conductive layer 120 ( Figure 14 capacitor layer L CP ( Figure 2 Additionally, for example, Figure 14 and Figure 15 As shown, in capacitor layer L CP An insulating layer 111 is formed on the upper surface. Furthermore, an opening TH_150 is formed in the portion of the insulating layer 111 corresponding to electrodes C1_WL and C1_WLP, and a conductive layer 152 is formed inside the opening TH_150. This process is performed, for example, by CVD (Chemical Vapor Deposition) and RIE (Reactive Ion Etching).

[0210] Next, for example, Figures 16-18 As shown, in Figure 14 and Figure 15 On the upper surface of the structure shown and inside the opening TH_150, conductive layers 150B' and 150a, containing the same material as conductive layer 150, are formed. Additionally, an insulating layer 230, such as silicon oxide (SiO2), is formed on the upper surface of conductive layer 150B'. This process is performed, for example, by CVD and RIE.

[0211] Next, for example, Figure 19 and Figure 20 As shown, in Figure 16 and Figure 17 The upper surface of the structure shown is covered with a mask material HM10 formed by photolithography or other methods. The mask material HM10 may also contain insulating layers such as silicon nitride (SiN) or silicon oxide (SiO2), or materials such as photoresist.

[0212] In addition, Figure 21An example of the shape of a photoresist RM10 used to form a mask material HM10 by photolithography or the like is shown. The photoresist RM10 includes a first portion extending in the X direction and having a width DRY1 in the Y direction, and a second portion extending in a direction differing from the extending direction of the first portion by an angle AG1 and having a width DRX2 in a direction orthogonal to the extending direction. By appropriately adjusting the widths DRY1, DRX2, and the angle AG1, the shape can be adjusted as described later. Figures 22 to 24 The shape, size, and arrangement interval of TH_130 and TH_130a formed in the process shown are set to the desired values.

[0213] Next, for example, Figures 22-24 As shown, openings TH_130 and TH_130a are formed. Opening TH_130 extends in the Z direction, penetrating the insulating layer 230, conductive layer 150B', and insulating layer 111, exposing the conductive layer 120. Opening TH_130a extends in the Z direction, penetrating the insulating layer 230, conductive layer 150B', and insulating layer 111, exposing electrodes such as C1_WL. Through this process, a conductive layer 150B containing the same material as the conductive layer 150 is formed. This process is performed, for example, by a re-emulation process (RIE).

[0214] Next, for example, Figures 25-27 As shown, a sacrificial layer SC_130, such as amorphous silicon (αSi), is formed inside the openings TH_130 and TH_130a. This process is performed, for example, by CVD.

[0215] Next, for example, Figure 28 and Figure 29 As shown, the insulating layer 230 is removed, exposing the upper surface of the conductive layer 150B and the upper end of the sacrificial layer SC_130. This process is performed, for example, by wet etching.

[0216] Next, for example, Figure 30 and Figure 31 As shown, in Figure 28 and Figure 29 An insulating layer MS_113, such as silicon oxide (SiO2), is formed on the upper surface of the structure shown. Through this process, the sacrificial layers SC_130 arranged in the X direction are sealed by the insulating layer MS_113. Figure 30 On the other hand, the sacrificial layers SC_130 arranged in the Y2 direction are not sealed by the insulating layer MS_113, and an opening TH_112B is formed between the sacrificial layers SC_130 arranged in the Y2 direction. Figure 31 This process is performed, for example, by CVD, ALD (Atomic Layer Deposition), etc.

[0217] Next, for example, Figures 32-34 As shown, the insulating layer MS_113 is etched back to form the insulating layer 113′. In this process, the portion of the insulating layer MS_113 below the portion where the opening TH_112B is formed is removed, and then a portion of the conductive layer 150B below the opening TH_112B is removed, forming the opening TH_112′ in the portion between the sacrificial layers SC_130 arranged along the Y2 direction. Figure 33 The opening TH_112 extends in both the X and Z directions, penetrating the insulating layer 113' and the conductive layer 150B, exposing the insulating layer 111. Through this process, a conductive layer 150 is formed that is interrupted in the Y direction. Figure 34 This process is carried out, for example, by RIE (Research Instruction).

[0218] Next, for example, Figure 36 and Figure 37 As shown, an insulating layer 112 is formed at the opening TH_112. This process is performed, for example, by CVD. Additionally, for example, as... Figures 35-37 As shown, a portion of the upper surface of the insulating layer 113′ and the sacrificial layer SC_130 are removed to form openings TH_130_1 and TH_130_1a. This process can be performed, for example, by CMP (Chemical Mechanical Planning) or wet etching.

[0219] Next, for example, Figures 38-40 As shown, after forming an insulating layer 140 inside openings TH_130_1 and TH_130_1a, a semiconductor layer 130 is formed inside opening TH_130_1, and semiconductor layers 130D1 and 130D2 are formed inside opening TH_130_1a. In this process, the insulating layer 140 is formed by removing the portion of the insulating layer formed on the inner and bottom surfaces of openings TH_130_1 and TH_130_1a after forming an insulating layer containing the same material as the insulating layer 140 on the inner and bottom surfaces of openings TH_130_1 and TH_130_1a. Semiconductor layers 130, 130D1, and 130D2 are connected to the inner surfaces of the insulating layer 140 and are formed in a manner that embeds them into openings TH_130_1 and TH_130_1a. This process is performed, for example, by ALD, CVD, RIE, CMP, etc.

[0220] Next, for example, Figure 41 and Figure 42 As shown, in Figure 38 and Figure 39The upper surface of the structure shown is sequentially formed with conductive layers 170″, 171″, and 172″. Conductive layers 170″, 171″, and 172″ may contain, for example, the same material as conductive layers 170, 171, and 172. This process is performed, for example, by CVD.

[0221] Next, for example, Figure 43 and Figure 44 As shown, a mask material is formed at the positions corresponding to conductive layers 170, 171, and 172 using a photolithography method or the like, and the portions not covered by the mask material are removed, thereby forming conductive layers 170′, 171′, and 172′. This process is performed, for example, by a re-emulation process (RIE).

[0222] Next, for example, Figure 45 and Figure 46 As shown, in Figure 43 and Figure 44 An insulating layer 173′, such as silicon oxide (SiO2), is formed on the upper surface of the structure shown. This process is performed, for example, by CVD.

[0223] Next, for example, Figure 47 As shown, an opening TH_WLP is formed at a position corresponding to the electrode WLP. The opening TH_WLP extends along the Z direction, penetrating the insulating layer 173′ and the insulating layer 112, exposing the electrode C1_WLP. This process is performed, for example, by a RIE (Reinforcing Equipment).

[0224] Next, for example, Figure 48 As shown, the same material as conductive layer 154 and conductive layer 153 is sequentially formed inside the opening TH_WLP. Additionally, Figure 48 The upper surface of the structure shown is planarized until the conductive layer 172' is exposed, forming a conductive layer 154, a conductive layer 153, and an insulating layer 173. This process is performed, for example, by CVD or CMP.

[0225] Next, for example, Figure 49 and Figure 50 As shown, conductive layers 182' and 184' are formed on the upper surfaces of insulating layer 173 and conductive layer 172'. This process is performed, for example, by CVD.

[0226] Next, for example, Figure 51 and Figure 52As shown, conductive layers 182, 184, and insulating layer 183 are formed. This process is performed, for example, by forming a mask material at the positions corresponding to conductive layers 182 and 184 using a photolithography method, and then removing the portions not covered by the mask material. Through this process, a portion of conductive layers 170', 171', and 172' is simultaneously removed, forming conductive layers 170, 171, and 172. This process is performed, for example, using a resonant optical echo chamber (RIE).

[0227] Next, in Figure 51 and Figure 52 The upper surface of the structure shown forms a wiring layer L. UL ( Figure 2 (e.g., etc.) thereby manufacturing the semiconductor device of the first embodiment.

[0228] [Effect]

[0229] In the semiconductor device of this embodiment, such as Figure 5 As shown, the closest distance between the outer peripheral surfaces of the two semiconductor layers 130 arranged in the Y2 direction, i.e., the width DT10, is greater than the closest distance between the outer peripheral surfaces of the two semiconductor layers 130 arranged in the X direction, i.e., the width DX10.

[0230] In such a structure, in reference Figures 30-34 In the described process, the sacrificial layers SC_130 arranged in the Y2 direction corresponding to the location where the semiconductor layer 130 is formed are not closed by the insulating layer MS_113. Figure 31 Thus, the conductive layer 150 is formed by etching back the insulating layer MS_113. Figures 32-34 They are connected in the X direction and disconnected in the Y direction. In such a process, the conductive layer 150 can be formed in a self-matching manner along the sacrificial layer SC_130 arranged in the X direction.

[0231] In the semiconductor device of this embodiment, even when ST (as a selection transistor) is used... Figure 1 When the semiconductor layer 130, which functions as the channel, is configured with a finer shape and higher density, the conductive layer 150, which functions as the word line WL, can be precisely aligned with the formation position of the semiconductor layer 130, enabling high-precision processing. This allows for the manufacture of select transistors (ST) with high integration density and excellent transistor characteristics. Figure 1 And fine word lines WL. In addition, since the fine photolithography process for processing the conductive layer 150 is not required, the manufacturing cost can be reduced.

[0232] (Modification 1 of the first embodiment)

[0233] Next, refer to Figure 53 and Figure 54 A modified example 1 of the semiconductor device according to the first embodiment will be described. Figure 53 and Figure 54 These are schematic cross-sectional and top views showing a portion of the structure of the semiconductor device in this modified example. Additionally, Figure 53 It shows the relationship with Figure 11 The corresponding part. Figure 54 The structure of the end of the conductive layer 150 is shown.

[0234] In this modified example, the semiconductor device ( Figure 53 In this process, insulating layers 132D1 and 132D2 are used to replace semiconductor layers 130D1 and 130D2. Figure 11 ).

[0235] Insulating layers 132D1 and 132D2 extend, for example, along the Z direction and have a generally cylindrical shape. A portion of insulating layers 132D1 and 132D2 faces conductive layer 150. Insulating layers 132D1 and 132D2 contain the same material as insulating layer 173, such as silicon oxide (SiO2). Insulating layers 132D1 and 132D2 may also be disposed continuously with insulating layer 173.

[0236] In addition, in this modified example, the electrode C1_WL is arranged to surround a portion of the side surface of the insulating layer 132D2 and the lower surface of the insulating layer 132D2.

[0237] Figure 54 The diagram shows the X-direction ends of the insulating layer 132D1 and the conductive layer 150, which are disposed at their outermost ends in the X-direction. The conductive layer 150, for example, is located at... Figure 54 In the XY cross-section shown, a portion PT13, separated from the outer peripheral surface of the insulating layer 132D1 by a width DW11, is provided and includes an annular portion surrounding the insulating layer 132D1. The portion PT13 is at least a portion of the end of the conductive layer 150 in the X direction. Furthermore, a portion of the outer peripheral surface of the portion PT13 is in contact with the insulating layer 112.

[0238] [Manufacturing method of Modification 1 of the First Embodiment]

[0239] Next, refer to Figure 55 as well as Figure 56 The manufacturing method of the semiconductor device of this modified example will be described. Figure 55 and Figure 56 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device of Modification 1 of the first embodiment. Furthermore, Figure 55 and Figure 56 Is with Figure 53 A schematic sectional view of the corresponding part.

[0240] In the manufacture of the semiconductor device in this modified example, until reference is made... Figures 14 to 44 Up to the steps described, the same steps as the manufacturing method of the first embodiment are performed.

[0241] Next, for example, such as Figure 55 As shown, semiconductor layers 130D1 and 130D2 are removed to form an opening TH_130_1a. This process is performed, for example, by wet etching.

[0242] Next, for example, Figure 56 As shown, in Figure 55 An insulating layer such as silicon oxide (SiO2) is formed on the upper surface of the structure shown, thereby forming insulating layers 132D1, 132D2 and insulating layer 173′ inside the opening TH_130_1a. This process is performed, for example, by CVD.

[0243] Next, reference will be made, for example, to the manufacturing method of the first embodiment. Figure 47 The procedures will be explained later.

[0244] (Modification 2 of the first embodiment)

[0245] Next, refer to Figures 57-59 A modified example 2 of the semiconductor device of the first embodiment will be described. Figures 57-59 These are schematic top views, perspective views, and sectional views showing a portion of the structure of the semiconductor device in this modified example. Figure 57 , Figure 58 and Figure 59 They respectively showed the same as Figure 9 , Figure 10 and Figure 12 The corresponding part.

[0246] Region R in this variation PC2 transistor layer L Tr ( Figure 59 In ), no electrode was set in WLP ( Figure 12 Instead, it is equipped with electrode WLP2 and conductive layer 150_1a. Figure 59 ).

[0247] Electrode WLP2, for example Figure 59 As shown, the upper end is connected to the conductive layer BP, and the lower end is electrically connected to the electrode C1_WLP. A portion of the side surface and the lower surface of electrode WLP2 can also be surrounded by electrode C1_WLP. Electrode WLP2 includes electrodes WLP ( Figure 12 The same conductive layer 153 and conductive layer 154.

[0248] Conductive layer 150_1a, for example, Figure 58 and Figure 59As shown, it is disposed in the same layer as conductive layer 150. Conductive layer 150_1a may also contain the same material as conductive layer 150 and be formed by the same process as conductive layer 150. Conductive layer 150_1a is, for example, as shown in... Figure 58 and Figure 59 As shown, it can also be arranged in a way that surrounds a portion of electrode WLP2.

[0249] The conductive layer 150_1a can also be formed, for example, as follows. For example, in conjunction with... Figures 22-24 In the corresponding process, an opening identical to the opening TH_130a is also formed on the electrode C1_WLP. Additionally, in relation to... Figures 25-29 In the corresponding process, a sacrificial layer identical to the sacrificial layer SC_130 is also formed on the electrode C1_WLP. Therefore, in conjunction with... Figures 30-34 In the corresponding process, a conductive layer 150_1a containing the same material as the conductive layer 150 is also formed on the electrode C1_WLP.

[0250] [Modification 3 of the First Embodiment]

[0251] Next, refer to Figures 60-62 A variation 3 of the semiconductor device of the first embodiment will be described. Figures 60-62 These are schematic top views, perspective views, and sectional views showing a portion of the structure of the semiconductor device in this modified example. Figure 60 , Figure 61 and Figure 62 They respectively showed the same as Figure 9 , Figure 10 and Figure 12 The corresponding part.

[0252] Region R in this variation PC2 transistor layer L Tr ( Figure 62 ), without setting electrodes WLP ( Figure 12 Instead, the settings and variations of Example 2 () are used. Figure 59 The same electrode WLP2 is then provided with an insulating layer 132D3 and a conductive layer 150_1b. Figure 62 Additionally, in this variation, such as Figure 60 As shown, it can also be done in region R. PC1 With region R PC2 An insulating layer 101, such as silicon oxide (SiO2), is provided between them.

[0253] Conductive layer 150_1b, for example Figure 61 and Figure 62As shown, it is disposed in the same layer as conductive layer 150. Conductive layer 150_1b contains the same material as conductive layer 150 and is formed by the same process as conductive layer 150. Conductive layer 150_1b can also be, for example, as shown in the diagram. Figure 61 and Figure 62 As shown, it is arranged in a manner that surrounds a portion of the electrode WLP2 and the insulating layer 132D3.

[0254] Insulating layer 101 can also be, for example, Figure 60 As shown, to divide region R PC1 The conductive layer 150 and region R PC2 The conductive layer 150_1b is set in a segmented manner.

[0255] Insulation layer 132D3 ( Figure 62 For example, it extends along the Z direction and has a generally cylindrical shape. A portion of the insulating layer 132D3 is opposite to the conductive layer 150_1b. The insulating layer 132D3 contains the same material as the insulating layer 173, such as silicon oxide (SiO2). The insulating layer 132D3 may also be disposed continuously with the insulating layer 173.

[0256] The conductive layer 150_1b can also be formed, for example, as follows. For example, in conjunction with... Figures 22-24 In the corresponding process, in region R PC2 This also creates multiple openings identical to those in opening TH_130a. Additionally, in relation to... Figures 25-29 In the corresponding process, in region R PC2 This also creates multiple sacrificial layers identical to the sacrificial layer SC_130. Therefore, in conjunction with... Figures 30-34 In the corresponding process, in region R PC2 A conductive layer 150_1b containing the same material as the conductive layer 150 is also formed.

[0257] In addition, Figure 60 In the example of the XY cross-section shown, region R PC2 The conductive layer 150_1b and region R PC1 Similarly, the conductive layer 150 has a shape with connected annular portions. However, the shape of the conductive layer 150_1b can be appropriately adjusted. For example, the conductive layer 150_1b may also have a shape with connected annular portions, such as an ellipse or an oblong shape, where the minor axis and major axis are longer than those of the conductive layer 150. Furthermore, even if the conductive layer 150_1b has the same shape as the conductive layer 150 at its central portion in the X direction, it may have different shapes, such as an ellipse or an oblong shape, with a longer major axis at its ends in the X direction.

[0258] (Second Implementation)

[0259] Next, use Figures 63-66The semiconductor device of the second embodiment will be described. Figures 63-66 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor device according to the second embodiment. Additionally, Figure 63 and Figure 66 Indicates and Figure 11 and Figure 12 The corresponding part. Figure 64 It is Figure 63 An enlarged schematic cross-sectional view of a portion of the structure shown. Figure 65 It is Figure 5 The structure shown is a schematic cross-sectional view cut along line FF′ and viewed in the direction of the arrow.

[0260] The semiconductor device of this embodiment is basically the same as the semiconductor device of the first embodiment. Figure 11 , Figure 12 The semiconductor device of this embodiment is constructed similarly. Figure 63 ) has the ability to replace the insulation layer 140 ( Figure 11 Insulation layer 140_2 ( Figure 63 ), replacing conductive layer 150 ( Figure 11 Conductive layer 150_2 ( Figure 63 ), replacing electrode C1_WL and semiconductor layer 130D2 ( Figure 11 Electrode C1_WL2 ( Figure 63 ), replacing electrode C1_WLP and electrode WLP ( Figure 12 Electrode C1_WLP2 ( Figure 66 ).

[0261] Insulation layer 140_2 ( Figure 63 Basically with insulation layer 140 ( Figure 11 The same applies. However, the insulating layer 140_2 ( Figure 63 ) and insulation layer 140 ( Figure 11 Unlike other materials, it is not disposed between the insulating layer 111 and the semiconductor layer 130. Additionally, as... Figure 64 and Figure 65 As shown, the insulating layer 140_2 is also continuously disposed on the lower surface of the conductive layer 150_2. Figure 64 ) and a portion of the lower surface of the insulating layer 112 ( Figure 65 ).

[0262] Insulating layer 140_2, for example, in Figure 64 The XZ cross-section shown includes a portion of PT_140_1 disposed between the insulating layer 113 and the conductive layer 150_2 and the semiconductor layer 130, and a portion of PT_140_2 disposed on the lower surface (substrate side) of the conductive layer 150_2. The portions of PT_140_1 and PT_140_2 are disposed continuously.

[0263] Insulating layer 140_2, for example, in Figure 65 The YZ cross-section shown includes a portion of PT_140_1, a portion of PT_140_2, and a portion of PT_140_3 disposed between portions of PT_140_1 and PT_140_2. The portion of PT_140_3 is disposed on a portion of the lower surface (substrate-side surface) of the insulating layer 112. The portions of PT_140_1, PT_140_2, and PT_140_3 are disposed continuously.

[0264] Conductive layer 150_2 ( Figure 63 Basically with conductive layer 150 ( Figure 11 The same arrangement applies. However, the lower surface of the conductive layer 150_2 is in contact with the insulating layer 140_2.

[0265] Electrode C1_WL2 ( Figure 63 The lower surface is connected to the through electrode CC_WL. Electrode C1_WL2 includes a conductive layer 150a_2 such as tungsten (W) and a conductive layer 152_2 such as titanium nitride (TiN). The conductive layer 150_2 is electrically connected to the through electrode CC_WL via electrode C1_WL2.

[0266] Electrode C1_WLP2( Figure 66 For example, it is connected to the conductive layer BP at the upper end and electrically connected to the through electrode CC_WLP at the lower end. The electrode WLP includes conductive layer 150a_2 and conductive layer 152_2.

[0267] [Manufacturing Method 1 of the Second Embodiment]

[0268] Next, refer to Figures 67 to 91 The manufacturing method 1 of the semiconductor device of this embodiment will be described. Figures 67 to 91 These are schematic cross-sectional and top views used to illustrate the manufacturing method 1 of the semiconductor device according to the second embodiment.

[0269] also, Figure 67 , Figure 70 , Figure 73 , Figure 76 , Figure 79 , Figure 82 , Figure 85 , Figure 88 and Figure 91 Is with Figure 63 A schematic sectional view of the corresponding part. Figure 68 , Figure 71 , Figure 74 , Figure 77 , Figure 80 , Figure 83 , Figure 86 as well as Figure 89 It is Figure 5 The structure shown is a schematic cross-sectional view cut along line EE′ and corresponding to the portion viewed in the direction of the arrow. Figure 69 , Figure 72 , Figure 75 , Figure 78 , Figure 81 , Figure 84 , Figure 87 as well as Figure 90 It means and Figure 5 Top view of the same parts. Additionally, the following drawings illustrating the manufacturing method are schematic; for ease of explanation, some structural elements may be omitted.

[0270] In this manufacturing method, similarly to the first embodiment, on the substrate Sub( Figure 1 A peripheral circuit layer L is formed above it. PC ( Figure 2 ), Plate line layer L PT ( Figure 2 ) and including through electrodes CC_WL, CC_WLP and conductive layer 120 ( Figure 14 capacitor layer L CP ( Figure 2 Additionally, for example, Figures 67-69 As shown, in capacitor layer L CP An insulating layer 111 and a sacrificial layer SC_230 of amorphous silicon (αSi) are formed on the upper surface. This process is performed, for example, by CVD.

[0271] Next, for example, Figures 70-72 As shown, openings TH_130_2 and TH_130_2a are formed. Opening TH_130_2 extends in the Z direction, penetrating the sacrificial layer SC_230 and the insulating layer 111, exposing the conductive layer 120. Opening TH_130_2a extends in the Z direction, penetrating the insulating layer 111 and exposing the through electrode CC_WL, etc. This process is performed, for example, by a RIE (Reinforcing Electrode Interface).

[0272] Next, for example, Figures 73-75 As shown, a semiconductor layer 130B containing the same material as semiconductor layer 130 is formed inside the openings TH_130_2 and TH_130_2a. This process is performed, for example, by CVD, CMP, etc.

[0273] Next, for example, Figures 76-78 As shown, the sacrificial layer SC_230 is removed, exposing the upper surface of the insulating layer 111 and a portion of the upper surface and outer peripheral surface of the semiconductor layer 130B. This process is performed, for example, by wet etching.

[0274] Next, for example, Figures 79-81As shown, an insulating layer 140_2B containing the same material as the insulating layer 140_2 is formed on the upper surface and a portion of the outer peripheral surface of the semiconductor layer 130B, as well as on the upper surface of the insulating layer 111. This process is performed, for example, by CVD, ALD, etc.

[0275] Next, for example, Figures 82-84 As shown, in Figure 79 and Figure 80 On the upper surface of the structure shown, a conductive layer 150_2B containing the same material as the conductive layer 150_2 is formed. Through this process, the semiconductor layers 130B arranged in the X direction are closed by the conductive layer 150_2B. Figure 82 On the other hand, the semiconductor layers 130B arranged in the Y2 direction are not blocked by the conductive layer 150_2B, and an opening TH_150_2B is formed between the semiconductor layers 130B arranged in the Y2 direction. Figure 83 This process is performed, for example, by CVD.

[0276] Next, for example, Figures 85-87 As shown, conductive layer 150_2B is etched back to form conductive layer 150_2. In this process, the portion below the portion of conductive layer 150_2B where the opening TH_150_2B is formed is removed, and opening TH_150_3B is formed in the portion between the semiconductor layers 130B arranged along the Y2 direction. Figure 86 The opening TH_150_3B extends in both the X and Z directions, penetrating the conductive layer 150_2B, exposing a portion of the insulating layer 140_2B formed on the upper surface of the insulating layer 111. Through this process, a conductive layer 150_2 (segmented in the Y direction) is formed. Figure 87 This process is carried out, for example, by RIE (Research Instruction).

[0277] Next, for example, Figures 88-90 As shown, in Figure 85 as well as Figure 86 The upper surface of the structure shown is formed with the same material as the insulating layer 113, and a portion of the insulating layer and insulating layer 140_2B on the upper surface is removed, thereby forming the insulating layer 113, the semiconductor layer 130, and the insulating layer 140_2. This process is performed, for example, by CVD, CMP, etc.

[0278] Next, for example, Figure 91 As shown, conductive layers 170', 171', and 172' and an insulating layer 173' are formed. This process is, for example, similar to the reference... Figures 41-46 The procedures described are performed in the same manner.

[0279] Next, for example, Figure 91As shown, an opening TH_C1_WL2 is formed at a position corresponding to electrode C1_WL2. The opening TH_C1_WL2 extends along the Z direction, penetrating insulating layers 173′, 113, conductive layer 150_2, and insulating layer 112, exposing electrode C1_WLP. This process is performed, for example, by means of a RIE (Reinforcing Electrode Interface).

[0280] Next, conductive layer 152_2 and conductive layer 150a_2 are formed in the opening TH_C1_WL2. Figure 63 ), and reference Figures 49-52 The described process similarly forms the plug LP, bit line BL, and wiring layer L. UL ( Figure 2 (e.g., etc.) thereby manufacturing the semiconductor device of the second embodiment.

[0281] [Manufacturing method 2 of the second embodiment]

[0282] Next, refer to Figures 92-106 The manufacturing method 2 of the semiconductor device of this embodiment will be described. Figures 92-106 These are schematic cross-sectional and top views used to illustrate the manufacturing method 2 of the semiconductor device according to the second embodiment.

[0283] in addition, Figure 92 , Figure 95 , Figure 98 , Figure 101 and Figure 104 Is with Figure 63 A schematic sectional view of the corresponding part. Figure 93 , Figure 96 , Figure 99 , Figure 102 as well as Figure 105 Is with General Figure 5 The diagram shows a schematic cross-sectional view of the part of the structure cut along line EE′ and viewed in the direction of the arrow. Figure 94 , Figure 97 , Figure 100 , Figure 103 and Figure 106 It means and Figure 5 Top view of the same parts. Additionally, the following drawings illustrating the manufacturing method are schematic; for ease of explanation, some structural elements may be omitted.

[0284] In this manufacturing method, the process is carried out in accordance with the reference. Figures 67-72 The process described is the same as the process described.

[0285] Next, for example, Figures 92-94 As shown, a sacrificial layer SC_130_2, such as amorphous silicon (αSi), is formed inside the openings TH_130_2 and TH_130_2a. This process is performed, for example, by CVD or CMP.

[0286] Next, refer to, for example Figures 76-78 Similarly, the sacrificial layer SC_230 is removed in the described process. This process exposes a portion of the upper surface of the insulating layer 111 and the upper surface and outer peripheral surface of the sacrificial layer SC_130_2.

[0287] Next, for example, Figures 95-97 As shown, an insulating layer 140_2B containing the same material as the insulating layer 140_2 is formed on the upper surface and a portion of the outer peripheral surface of the sacrificial layer SC_130_2, as well as on the upper surface of the insulating layer 111. This process is performed, for example, by CVD, ALD, etc.

[0288] Next, for example, Figures 95-97 As shown, a conductive layer 150_2B is formed. Through this process, the conductive layer 150_2B seals the spaces between the sacrificial layers SC_130_2 arranged in the X direction. Figure 95 On the other hand, the sacrificial layers SC_130_2 arranged in the Y2 direction are not closed by the conductive layer 150_2B, and an opening TH_150_2B is formed between the sacrificial layers SC_130_2 arranged in the Y2 direction. Figure 96 This process is performed, for example, by CVD.

[0289] Next, for example, Figures 98-100 As shown, conductive layer 150_2B is etched back to form conductive layer 150_2. In this process, the portion below the part of conductive layer 150_2B where the opening TH_150_2B is formed is removed, and the portion between the sacrificial layers SC_130_2 arranged in the Y2 direction forms opening TH_150_3B. Figure 99 This process forms a conductive layer 150_2 that is broken in the Y direction. This process is performed, for example, by a RIE (Radio Interchange Electrode).

[0290] Next, for example, Figures 101-103 As shown, in Figure 98 and Figure 99 The upper surface of the structure shown is formed with the same material as the insulating layer 113. A portion of the insulating layer and insulating layer 140_2B on the upper surface is removed, thereby forming insulating layer 113 and insulating layer 140_2, exposing the upper surface of the sacrificial layer SC_130_2. This process is performed, for example, by CVD, CMP, etc.

[0291] Next, for example, Figures 104-106As shown, the sacrificial layer SC_130_2 is removed to form openings TH_130_3 and TH_130_3a. Openings TH_130_3 and TH_130_3a extend in the Z direction, exposing a portion of the insulating layer 140_2 and the insulating layer 111 on the side surface, and exposing the conductive layer 120 and the through electrode CC_WL on the bottom surface. This process is performed, for example, by wet etching.

[0292] Next, a semiconductor layer 130 is formed inside the openings TH_130_3 and TH_130_3a, and a semiconductor layer 130D1 is formed inside the opening TH_130_3a. This process is performed, for example, by CVD or CMP.

[0293] Next, refer to Figure 91 After the described process, the same process as manufacturing method 1 of the second embodiment is performed to manufacture the semiconductor device of the second embodiment.

[0294] [Effect]

[0295] In the semiconductor device of this embodiment, it is also similar to that of the first embodiment ( Figure 5 Similarly, the width DT10 is greater than the width DX10.

[0296] In this structure, for example in manufacturing method 1, in reference Figures 82-84 In the described process, the semiconductor layer 130B is arranged in the Y2 direction corresponding to the position where the semiconductor layer 130 is formed. Figures 82-84 The spaces between them are not sealed by conductive layer 150_2B. Figure 83 Thus, conductive layer 150_2 is formed by etching back conductive layer 150_2B. Figures 85-87 They are connected in the X direction and separated in the Y direction. In such a process, a conductive layer 150_2 can be formed in a self-matching manner along the semiconductor layer 130B arranged in the X direction.

[0297] Additionally, for example in manufacturing method 2, in reference Figures 95-97 In the described process, the sacrificial layer SC_130_2, which is arranged in the Y2 direction corresponding to the position where the semiconductor layer 130 is formed, Figures 95-97 The spaces between them are not sealed by conductive layer 150_2B. Figure 96 Thus, conductive layer 150_2 is formed by etching back conductive layer 150_2B. Figures 98-100 They are connected in the X direction and separated in the Y direction. In such a process, a conductive layer 1502 can be formed in a self-matching manner along the sacrificial layer SC_130_2 arranged in the X direction.

[0298] This enables the manufacture of select transistors (ST) with high integration density and excellent transistor characteristics. Figure 1 And fine word lines WL. In addition, by eliminating the need for a fine photolithography process for processing the conductive layer 150_2, manufacturing costs can be reduced.

[0299] (A variation of the second embodiment)

[0300] Next, refer to Figure 107 A variation of the semiconductor device according to the second embodiment will be described. Figure 107 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor device in this modified example.

[0301] In this modified example, the semiconductor device ( Figure 107 In this process, insulating layer 140_3 is used to replace insulating layer 140_2. Figure 65 ).

[0302] Insulation layer 140_3 ( Figure 107 Basically with insulating layer 140_2 ( Figure 65 The same arrangement applies. However, a portion corresponding to the portion PT_140_3 of insulating layer 140_2 is not provided in insulating layer 140_3. Insulating layer 140_3 is interrupted in the Y direction.

[0303] (Third Implementation)

[0304] Next, use Figures 108-110 The semiconductor device of the third embodiment will be described. Figures 108-110 These are schematic cross-sectional views, top views, and perspective views showing a portion of the structure of the semiconductor device according to the third embodiment.

[0305] Figure 108 It shows the relationship with Figure 11 The corresponding part. Figure 109 It is Figure 108 The structure shown is cut along line GG′, and is a schematic top view corresponding to the portion viewed in the direction of the arrow. Figure 110 Storage area R is shown MC and region R PC1 The structure.

[0306] The semiconductor device of this embodiment is basically the same as the semiconductor device of the first embodiment. Figure 11 The same configuration applies. However, in this embodiment, the semiconductor device is provided with a conductive layer 150_3. Figure 108 ) to replace conductive layer 150 ( Figure 11 Additionally, in region R PC1 Semiconductor layers 130D1 and 130D2 are not provided.

[0307] Conductive layer 150_3 ( Figure 108Basically with conductive layer 150 ( Figure 11 Similarly, the conductive layer 150_3 is configured as follows. Figure 110 As shown, in storage area R MC In the middle, a generally cylindrical portion surrounding a portion of the semiconductor layer 130 and the insulating layer 140 is connected in the X direction, but in region R PC1 In the middle, the roughly cylindrical parts are connected and arranged in the X direction.

[0308] [Manufacturing method of the third embodiment]

[0309] Next, refer to Figures 111-132 The manufacturing method of the semiconductor device according to this embodiment will be described. Figures 111-132 These are schematic cross-sectional and top views used to illustrate the manufacturing method of the semiconductor device according to the third embodiment.

[0310] Figure 111 , Figure 114 , Figure 117 , Figure 119 , Figure 121 , Figure 123 , Figure 125 , Figure 127 and Figure 130 Is with Figure 108 A schematic sectional view of the corresponding part. Figure 112 , Figure 115 , Figure 118 , Figure 120 , Figure 122 , Figure 124 , Figure 126 , Figure 128 as well as Figure 131 Is with General Figure 5 The diagram shows a schematic cross-sectional view of the part of the structure cut along line EE′ and viewed in the direction of the arrow. Figure 113 , Figure 116 , Figure 129 as well as Figure 132 Is with Figure 109 A schematic cross-sectional view of the corresponding part. Additionally, the following drawings illustrating the manufacturing method are schematic; for ease of explanation, some structural elements may be omitted.

[0311] In this manufacturing method, until reference Figure 14 and Figure 15 Up to the steps described, the same steps as the manufacturing method of the first embodiment are performed.

[0312] Next, for example, Figure 111 and Figure 112 As shown, in Figure 14 and Figure 15The upper surface and opening TH_150 of the structure shown are shown. Figure 14 Inside the conductive layer 150, a conductive layer and a conductive layer 150a containing the same material as the conductive layer 150_3 are formed, and an insulating layer 113 is formed on the upper surface of the conductive layer. This process is performed, for example, by CVD.

[0313] Next, for example, Figures 111-113 As shown, an opening TH_130_4 is formed. The opening TH_130_4 extends in the Z direction, penetrating the insulating layer 113, the conductive layer containing the same material as the conductive layer 150_3, and the insulating layer 111, exposing the conductive layer 120. Through this process, the conductive layer 150B is formed. This process can also be performed, for example, with reference to... Figures 19-21 The process described above is also performed using mask material HM10.

[0314] Next, for example, Figures 114-116 As shown, an insulating layer 140 and a semiconductor layer 130 are formed inside the opening TH_130_4. In this process, the insulating layer 140 is formed by removing the portion of the insulating layer formed on the bottom surface of the opening TH_130_4 after forming an insulating layer containing the same material as the insulating layer on the inner surface and bottom surface of the opening TH_130_4. The semiconductor layer 130 is formed in a manner that is in contact with the inner surface of the insulating layer 140 and fills the opening TH_130_4. This process is performed, for example, by ALD, CVD, RIE, CMP, etc.

[0315] Next, for example, Figure 117 and Figure 118 As shown, in Figure 114 and Figure 115 The upper surface of the structure shown is sequentially formed with conductive layers 170″, 171″, and 172″. Additionally, in the storage region R... MC The positions corresponding to conductive layers 170, 171, and 172, and in region R PC1 In, for example, storage area R MC Silicon oxide (SiO2) and silicon nitride (SiN) mask materials MS_PL are formed using photolithography and other methods with the same shape and arrangement. This process is performed, for example, by CVD or RIE.

[0316] Next, for example, Figure 119 and Figure 120 As shown, portions of conductive layers 170″, 171″, and 172″ not covered by the masking material MS_PL are removed, thereby forming conductive layers 170′, 171′, and 172′. This process is performed, for example, by a RIE (Reinforcing Electrode).

[0317] Next, for example, Figure 121 as well as Figure 122 As shown, in Figure 119 as well as Figure 120 An insulating layer 330″, such as silicon oxide (SiO2), is formed on the upper surface of the structure shown. Through this process, the structure containing conductive layers 170', 171', and 172' arranged in the X direction is sealed by the insulating layer 330″. Figure 121 On the other hand, the structure containing conductive layers 170', 171', and 172' arranged in the Y2 direction is not sealed by the insulating layer 330", thus forming an opening TH_170B. Figure 122 This process is performed, for example, by CVD, ALD, etc.

[0318] Next, for example, Figure 123 and Figure 124 As shown, insulating layer 330″ is etched back to form insulating layer 330′. In this process, the portion of insulating layer 330″ that is in contact with the bottom surface of opening TH_170B is removed to form opening TH_170. Figure 124 The opening TH_170 extends in both the X and Z directions, exposing a portion of the insulating layer 113 on the bottom surface. This process is performed, for example, by a RIE (Reinforcing Interchange).

[0319] Next, for example, Figure 125 and Figure 126 As shown, the exposed portion of the upper surface of the insulating layer 113 is removed to form an opening TH_113. The opening TH_113 extends in both the X and Z directions, exposing a portion of the upper surface of the conductive layer 150B at its bottom surface. Through this process, the insulating layer 330 is formed. For example, the outer peripheral surface of the insulating layer 330 in the Y2 direction is located outside the distance DW30 from the outer peripheral surface of the conductive layer 172' in the Y2 direction. Additionally, in this process, a portion of the upper surface of the mask material MS_PL is also removed. This process is performed, for example, by using a RIE (Reinforcing Image Processor).

[0320] Next, for example, Figures 127-129 As shown, the exposed portion of the upper surface of the conductive layer 150B is removed to form an opening TH_112B2. The opening TH_112B2 extends in both the X and Z directions, penetrating the conductive layer 150B and exposing a portion of the upper surface of the insulating layer 111 on the bottom surface. Through this process, the conductive layer 150_3 is formed. Furthermore, when the outer peripheral surface of the opening TH_112B2 is machined to be perpendicular to the substrate, the outer peripheral surface of the conductive layer 150_3 in the Y2 direction is, for example, located outside the outer peripheral surface of the conductive layer 172' in the Y2 direction at a distance of DW30. This process is performed, for example, by a RIE (Reinforcing Equipment).

[0321] Furthermore, if, depending on the processing conditions, the outer peripheral surface of the opening TH_112B2 is not perpendicular to the substrate but is inclined, when viewed from the Z direction, the outer peripheral surface of the conductive layer 150_3 in the Y2 direction can, for example, be located outside the outer peripheral surface of the conductive layer 172' in the Y2 direction at a width smaller than the distance from DW30, or it can be located outside the outer peripheral surface at a width larger than the distance from DW30. Alternatively, the outer peripheral surface of the conductive layer 150_3 in the Y2 direction can also coincide with the outer peripheral surface of the conductive layer 172' in the Y2 direction, or the outer peripheral surface of the conductive layer 150_3 in the Y2 direction can be located at a predetermined distance inward from the outer peripheral surface of the conductive layer 172' in the Y2 direction.

[0322] Next, for example, Figures 130-132 As shown, insulating layer 330 and mask material MS_PL are removed, and insulating layer 112 is formed in opening TH_112B2. Additionally, in region R... PC1 In this process, after removing the conductive layers 170', 171', and 172' that are not connected to the semiconductor layer 130, an insulating layer 173 is formed between the structures containing the conductive layers 170', 171', and 172'. This process is performed, for example, by CVD.

[0323] Next, reference will be made, for example, to the manufacturing method of the first embodiment. Figure 47 The following steps describe the manufacturing process of the semiconductor device according to the third embodiment.

[0324] [Positional relationship between conductive layer 172 and conductive layer 150_3]

[0325] Figure 133 This is a schematic top view showing the configuration of a portion of the semiconductor device according to the third embodiment. Additionally, Figure 133 Indicates and Figure 6 The corresponding part. Additionally, in Figure 133 In order to indicate the positional relationship, the conductive layer 150_3 that does not appear in this cross-section is represented by a dashed line.

[0326] For example, Figure 133 As shown, in an XY cross-section containing multiple conductive layers 172, the closest distance between the outer peripheral surfaces of one conductive layer 172 and the outer peripheral surface of the other conductive layer 172 arranged in the X direction is distance DX30. Furthermore, the closest distance between the outer peripheral surfaces of one conductive layer 172 and the outer peripheral surface of the other conductive layer 172 arranged in the Y2 direction is distance DT30. Distance DT30 is greater than distance DX30.

[0327] Additionally, for example in Figure 133In the example shown, when viewed from the Z direction, a portion of the surface of the conductive layer 150_3 on one side in the Y direction is located on the outer side of the surface of the conductive layer 172 on the Y direction.

[0328] Additionally, distance DW31 can be compared with distance DW30 ( Figure 128 () can be of the same degree, or larger or smaller than the distance DW30.

[0329] In addition, Figure 133 In addition to the example shown, when viewed from the Z direction, a portion of the surface of the conductive layer 150-3 on one side in the Y direction can also be located at a position a certain width inward from a portion of the surface of the conductive layer 172 on one side in the Y direction, or it can be consistent with a portion of the surface of the conductive layer 172 on one side in the Y direction.

[0330] [Effect]

[0331] In the semiconductor device of this embodiment, such as Figure 133 As shown, the closest distance between the outer peripheral surfaces of the two conductive layers 172 arranged in the Y2 direction, i.e., the distance DT30, is greater than the closest distance between the outer peripheral surfaces of the two conductive layers 172 arranged in the X direction, i.e., the distance DX30.

[0332] In this structure, in reference Figure 121 and Figure 122 In the described process, the conductive layers 172' arranged in the Y2 direction are not sealed by the insulating layer 330". Figure 122 Thus, the conductive layer 150_3 is formed by etching back the insulating layer 330″. Figures 127-129 They are connected in the X direction and separated in the Y direction. In this process, the conductive layer 150_3 can be formed in a self-matching manner along the conductive layer 172' arranged in the X direction.

[0333] This enables the manufacture of select transistors (ST) with high integration density and excellent transistor characteristics. Figure 1 And fine word lines WL. In addition, by eliminating the need for a fine photolithography process for processing the conductive layer 150_3, manufacturing costs can be reduced.

[0334] [Other Implementation Methods]

[0335] The semiconductor devices of the first to third embodiments have been described above. However, these semiconductor devices are merely examples, and the specific structure, operation, etc., can be appropriately adjusted.

[0336] Regarding the semiconductor devices of the first to third embodiments, for example, Figure 5The image shows an example where the semiconductor layer 130 has an elliptical shape in the XY cross-section. Additionally, in... Figure 5 The diagram shows an example where the major axis of the ellipse is not aligned with either the X or Y directions. However, the shapes of these semiconductor layers 130 are merely illustrative, and the specific shapes can be adjusted accordingly.

[0337] The shape of the semiconductor layer 130 can be, for example, a circle or an oblong shape, in addition to an ellipse. Furthermore, in the case of an ellipse or an oblong shape, the direction of its major axis can be consistent with or different from the X, Y, X2, and Y2 directions.

[0338] For example, in the above description, regarding the selection of transistor ST ( Figure 1 ) Connect capacitor Cap( Figure 1 An example is provided to illustrate this. In such examples, the shape and structure of the capacitor Cap can be adjusted appropriately.

[0339] Additionally, in the above explanation, regarding the use of capacitor Cap( Figure 1 ) as connected to the select transistor ST ( Figure 1 The example of a storage unit has been illustrated. However, the storage unit does not have to be a capacitor (Cap). For example, the storage unit may also contain ferroelectric, ferromagnetic, chalcogenide materials such as GeSbTe, or other materials, utilizing the properties of these materials to record data. For example, in any of the structures described above, the insulating layer between the electrodes forming the capacitor (Cap) may also contain any of these materials.

[0340] Additionally, in the above explanation, regarding the ST (selector transistor) Figure 1 The semiconductor layer 130, which functions in the channel region of the semiconductor layer, is shown in an example of extending in the Z direction and having a generally cylindrical shape. However, the semiconductor layer 130 may also be a generally cylindrical shape extending in the Z direction. Alternatively, an insulating layer, such as silicon oxide (SiO2), which has a generally cylindrical shape extending in the Z direction, may be provided inside the semiconductor layer 130.

[0341] [other]

[0342] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention as set forth in the claims and its equivalents.

[0343] [Explanation of reference numerals in the attached figures]

[0344] Substrate, 130 semiconductor layer, 140 insulating layer, 150 conductive layer, PT11 portion, OT tangent.

Claims

1. A semiconductor device comprising: substrate; The first oxide semiconductor layer and the second oxide semiconductor layer extend in a first direction intersecting the surface of the substrate and are arranged in a second direction intersecting the first direction, and contain a first metal element and oxygen (O). A first conductive layer extends in the second direction and is opposite to a portion of the outer peripheral surface of the first oxide semiconductor layer and a portion of the outer peripheral surface of the second oxide semiconductor layer. A first gate insulating layer is disposed between the first oxide semiconductor layer and the first conductive layer; as well as A second gate insulating layer is disposed between the second oxide semiconductor layer and the first conductive layer. In a first cross-section extending upward in the second direction and a third direction intersecting the first and second directions, and including the first oxide semiconductor layer, the second oxide semiconductor layer, and the first conductive layer, the first conductive layer comprises: The annular first portion is provided with a first width spaced apart from the outer peripheral surface of the first oxide semiconductor layer and surrounds the first oxide semiconductor layer; as well as The annular second portion, spaced apart from the outer peripheral surface of the second oxide semiconductor layer by the first width, surrounds the second oxide semiconductor layer. A portion of a circle, ellipse, or oblong circumscribed by the first portion overlaps with a portion of a circle, ellipse, or oblong circumscribed by the second portion.

2. The semiconductor device according to claim 1, wherein, have: A third oxide semiconductor layer extends in the first direction, is arranged relative to the first oxide semiconductor layer in a direction that intersects the first direction and is different from the second direction, and contains the first metal element and oxygen (O); The second conductive layer is arranged adjacent to the first conductive layer in the third direction, extends in the second direction, and is opposite to a portion of the outer peripheral surface of the third oxide semiconductor layer; as well as A third gate insulating layer is disposed between the third oxide semiconductor layer and the second conductive layer. The first cross-section also includes the third oxide semiconductor layer and the second conductive layer. In the first cross-section, when the closest distance between the outer peripheral surface of the first oxide semiconductor layer and the outer peripheral surface of the second oxide semiconductor layer is set as the second width, and the closest distance between the outer peripheral surface of the first oxide semiconductor layer and the outer peripheral surface of the third oxide semiconductor layer is set as the third width, the third width is greater than the second width.

3. The semiconductor device according to claim 1, wherein, have: A fourth oxide semiconductor layer extends in the first direction and is aligned with the first oxide semiconductor layer in the second direction, with a portion of its outer peripheral surface facing the first conductive layer, and contains the first metal element and oxygen (O). A through electrode is disposed on one side of the fourth oxide semiconductor layer in the first direction and extends in the first direction; as well as A third conductive layer, disposed between the first conductive layer and the through electrode, surrounds another portion of the outer peripheral surface of the fourth oxide semiconductor layer. The first conductive layer is electrically connected to the through electrode via the third conductive layer.

4. The semiconductor device according to claim 1, wherein, have: A first insulating layer extends in the first direction, is aligned with the first oxide semiconductor layer in the second direction, and a portion of its outer peripheral surface is opposite to the first conductive layer. A through electrode is disposed on one side of the first insulating layer in the first direction and extends in the first direction; as well as A third conductive layer is disposed between the first conductive layer and the through electrode, surrounding another portion of the outer peripheral surface of the first insulating layer. The first conductive layer is electrically connected to the through electrode via the third conductive layer.

5. The semiconductor device according to claim 1, wherein, It has a fifth oxide semiconductor layer extending in the first direction and aligned with the first oxide semiconductor layer in the second direction. A portion of its outer peripheral surface faces the first conductive layer and contains the first metal element and oxygen (O). In a second cross-section extending along the second direction and the third direction, and including the fifth oxide semiconductor layer and the first conductive layer, the first conductive layer includes an annular third portion, which is disposed spaced apart from the outer peripheral surface of the fifth oxide semiconductor layer by the first width, and surrounds the fifth oxide semiconductor layer. A portion of the third part is the end of the first conductive layer in the second direction.

6. The semiconductor device according to claim 1, wherein, It includes a second insulating layer extending in the first direction and aligned with the first oxide semiconductor layer in the second direction, with a portion of its outer peripheral surface facing the first conductive layer. In a third cross-section extending along the second direction and the third direction, and including the second insulating layer and the first conductive layer, the first conductive layer includes an annular fourth portion surrounding the outer peripheral surface of the second insulating layer. A portion of the fourth part is the end of the first conductive layer in the second direction.

7. The semiconductor device according to claim 1, wherein, A third insulating layer is provided on one side of the first conductive layer in the first direction. The third insulating layer comprises the same material as the first gate insulating layer and the second gate insulating layer, and is continuous with the first gate insulating layer and the second gate insulating layer.

8. The semiconductor device according to claim 2, wherein, have: A third insulating layer is disposed on one side of the first conductive layer in the first direction; and A fourth insulating layer is disposed on one side of the second conductive layer in the first direction. The third insulating layer comprises the same material as the first gate insulating layer and is continuous with the first gate insulating layer. The fourth insulating layer comprises the same material as the third gate insulating layer and is continuous with the third gate insulating layer. A fifth insulating layer is disposed between the third insulating layer and the fourth insulating layer. The fifth insulating layer contains the same material as the third insulating layer and the fourth insulating layer, and is continuous with the third insulating layer and the fourth insulating layer.

9. The semiconductor device according to claim 1, wherein, The first metallic element is selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), zinc (Zn), tin (Sn), titanium (Ti), tungsten (W), and molybdenum (Mo).

10. The semiconductor device according to claim 1, wherein, It includes a capacitor layer disposed on one side of the first oxide semiconductor layer and the second oxide semiconductor layer in the first direction. The capacitor layer has a capacitor structure that is electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer respectively.

11. A semiconductor device comprising: substrate; The first oxide semiconductor layer and the second oxide semiconductor layer extend in a first direction intersecting the surface of the substrate and are arranged in a second direction intersecting the first direction, and contain a first metal element and oxygen (O). A first conductive layer extends in the second direction and is opposite to a portion of the outer peripheral surface of the first oxide semiconductor layer and a portion of the outer peripheral surface of the second oxide semiconductor layer. A gate insulating layer is disposed between the first oxide semiconductor layer and the first conductive layer and between the second oxide semiconductor layer and the first conductive layer, respectively. as well as The first electrode and the second electrode are respectively connected to one end of the first oxide semiconductor layer and the second oxide semiconductor layer in the first direction. Viewed from the first direction, a portion of the surface of the first conductive layer on the third direction side intersecting the first and second directions is disposed consistent with the surface of the first electrode and the second electrode on the third direction side, or disposed on the outer or inner side at a first distance from the surface of the first electrode and the second electrode on the third direction side.

12. The semiconductor device according to claim 11, wherein, The first electrode includes a fourth conductive layer that is connected to one end of the first oxide semiconductor layer in the first direction and includes a second metal element and oxygen (O). The second metallic element is selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo).

13. The semiconductor device according to claim 11, wherein, have: A third oxide semiconductor layer extends in the first direction, is arranged relative to the first oxide semiconductor layer in a direction that intersects the first direction and is different from the second direction, and contains the first metal element and oxygen (O); The third electrode is connected to one end of the third oxide semiconductor layer in the first direction; as well as The second conductive layer is arranged adjacent to the first conductive layer in the third direction, extends in the second direction, and is opposite to a portion of the outer peripheral surface of the third oxide semiconductor layer. In a cross-section extending along the second direction and the third direction, and including the first electrode, the second electrode and the third electrode, when the closest distance between the outer peripheral surfaces of the first electrode and the second electrode is set as the second distance, and the closest distance between the outer peripheral surfaces of the first electrode and the third electrode is set as the third distance, the third distance is greater than the second distance.

14. The semiconductor device according to claim 11, wherein, The first metallic element is selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), zinc (Zn), tin (Sn), titanium (Ti), tungsten (W), and molybdenum (Mo).

15. The semiconductor device according to claim 11, wherein, It includes a capacitor layer disposed on one side of the first oxide semiconductor layer and the second oxide semiconductor layer in the first direction. The capacitor layer has a capacitor structure that is electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer respectively.

Images