Semiconductor memory device and semiconductor package including the same

Abstract

The present disclosure provides a semiconductor memory device and a semiconductor package including the same. The semiconductor memory device according to some embodiments of the present disclosure includes a memory cell structure including a cell substrate, a peripheral circuit structure overlapping the memory cell structure in a first direction perpendicular to an upper surface of the cell substrate, a plurality of semiconductor structures stacked in the first direction, and a plurality of through electrodes extending in the first direction in each of the plurality of semiconductor structures. The memory cell structure includes a semiconductor pattern having a channel region and a capacitor structure located at one side of the semiconductor pattern, a plurality of memory cells stacked along the first direction and spaced apart on the cell substrate, a plurality of word lines extending in a second direction parallel to the upper surface of the cell substrate and surrounding the channel region, and a bit line located at the other side of the semiconductor pattern.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices and semiconductor packages including the thereof. Background Technology

[0002] Semiconductor memory devices are primarily used for storing and retrieving data. They are used in electronic devices across a wide range of fields, including computers, communication equipment, and consumer electronics. As the electronics industry has advanced rapidly and user demands have diversified, electronic devices have become smaller, more versatile, and have greater capacity.

[0003] To improve the performance of semiconductor memory devices, the integration density of these devices has been continuously increasing. In this development process, several transistor structures, such as vertical channel transistors and vertically stacked transistors, have been proposed. Summary of the Invention

[0004] Some embodiments of this disclosure are intended to provide semiconductor memory devices and semiconductor packages with improved integration density, electrical performance, and reliability.

[0005] According to some embodiments of this disclosure, a semiconductor memory device may include: a plurality of semiconductor structures stacked in a first direction perpendicular to the upper surface of a cell substrate, each of the plurality of semiconductor structures including a memory cell structure having the cell substrate and a peripheral circuit structure overlapping the memory cell structure in the first direction; and a plurality of through electrodes extending in the first direction in each of the plurality of semiconductor structures. The memory cell structure may include: a plurality of memory cells stacked on the cell substrate and spaced apart in the first direction, each of the plurality of memory cells including a semiconductor pattern having a channel region and a capacitor structure located on a first side of the semiconductor pattern; a plurality of word lines extending in a second direction parallel to the upper surface of the cell substrate and surrounding the channel region; and bit lines located on a second side of the semiconductor pattern, the second side of the semiconductor pattern being opposite to the first side of the semiconductor pattern.

[0006] According to some embodiments of this disclosure, a semiconductor memory device may include: a first semiconductor structure, the first semiconductor structure including a first memory cell structure and a first peripheral circuit structure, the first peripheral circuit structure overlapping the first memory cell structure in a first direction; a second semiconductor structure, the second semiconductor structure stacked on the first semiconductor structure in the first direction, the second semiconductor structure including a second memory cell structure and a second peripheral circuit structure, the second peripheral circuit structure overlapping the second memory cell structure in the first direction; a first through electrode, the first through electrode extending in the first direction into the first memory cell structure and the first peripheral circuit structure; and a second through electrode, the second through electrode extending in the first direction into the second memory cell structure and the second peripheral circuit structure and aligned with the first through electrode in the first direction. Each of the first memory cell structure and the second memory cell structure may include: a plurality of memory cells stacked and spaced apart from each other in the first direction, each of the plurality of memory cells including a semiconductor pattern comprising: a channel region; a first source / drain region and a second source / drain region, the first source / drain region and the second source / drain region being located on opposite sides of the channel region; and a capacitor structure connected to the first source / drain region; a plurality of word lines extending in a second direction intersecting the first direction, wherein the plurality of word lines stacked and spaced apart from each other in the first direction, wherein the plurality of word lines surround the channel region of each of the plurality of memory cells; and a bit line extending in the first direction and connected to the second source / drain region.

[0007] According to some embodiments of this disclosure, a semiconductor package may include: a package substrate; a semiconductor memory device including a plurality of semiconductor structures stacked on the package substrate in a first direction perpendicular to the upper surface of the package substrate; and a plurality of through electrodes electrically connected to the plurality of semiconductor structures. Each of the plurality of semiconductor structures may include: a memory cell structure including a cell substrate; a peripheral circuit structure overlapping the memory cell structure in the first direction; and a wiring structure electrically connected to both the memory cell structure and the peripheral circuit structure. Furthermore, the memory cell structure may include: a plurality of memory cells spaced apart from each other in the first direction, each of the plurality of memory cells having a semiconductor pattern, the semiconductor pattern including: a channel region; a first source / drain region and a second source / drain region disposed on opposite sides of the channel region; and a capacitor structure connected to the first source / drain region; a plurality of word lines extending in a second direction intersecting the first direction and spaced apart from each other in the first direction, wherein the plurality of word lines surround the channel region; and bit lines extending in the first direction and connected to the second source / drain region.

[0008] According to some embodiments of this disclosure, a method of manufacturing a semiconductor memory device may include: manufacturing a plurality of semiconductor structures by stacking peripheral circuit structures on a memory cell structure having a cell substrate, such that the peripheral circuit structures overlap the cell substrate in a first direction perpendicular to the upper surface of the cell substrate; forming a through electrode that penetrates at least a portion of each of the plurality of semiconductor structures in the first direction; and stacking the plurality of semiconductor structures. The memory cell structure may include: a plurality of memory cells stacked on the cell substrate in the first direction and spaced apart, each memory cell including a semiconductor pattern having a channel region and a capacitor structure disposed on one side of the semiconductor pattern; a plurality of word lines extending in a second direction parallel to the upper surface of the cell substrate and surrounding the channel region; and bit lines disposed on the other side of the semiconductor pattern.

[0009] In some embodiments, the through electrode may include a first surface and a second surface opposite to the first surface, and the width of the through electrode may decrease from the first surface toward the second surface along the first direction.

[0010] In some embodiments, the method may further include: forming a first connection pad and a second connection pad electrically connected to the through electrode at a location where the first surface of the through electrode overlaps with the first surface of the through electrode along the first direction.

[0011] In some embodiments, the second connection pad may be disposed on the second surface of the through electrode.

[0012] In some embodiments, each semiconductor structure may further include a first bonding insulating layer and a second bonding insulating layer, wherein the first bonding insulating layer overlaps with the first connection pad in the second direction, and the second bonding insulating layer overlaps with the second connection pad in the second direction.

[0013] In some embodiments, the plurality of semiconductor structures may include a first semiconductor structure and a second semiconductor structure stacked on the first semiconductor structure, and stacking the plurality of semiconductor structures may include: bonding the first connection pad of the first semiconductor structure to the first connection pad of the second semiconductor structure and bonding the first bonding insulating layer of the first semiconductor structure to the second bonding insulating layer of the second semiconductor structure.

[0014] In some embodiments, the plurality of semiconductor structures may include a first semiconductor structure and a second semiconductor structure stacked on the first semiconductor structure, and stacking the plurality of semiconductor structures may include: bonding the second connection pad of the first semiconductor structure to the first connection pad of the second semiconductor structure and bonding the second bonding insulating layer of the first semiconductor structure to the first bonding insulating layer of the second semiconductor structure.

[0015] In some embodiments, the memory cell structure may further include a cell bonding insulating layer and cell bonding pads overlapping the cell bonding insulating layer in the second direction, and the peripheral circuit structure may further include a peripheral bonding insulating layer and peripheral bonding pads overlapping the peripheral bonding insulating layer in the second direction. Manufacturing the plurality of semiconductor structures may include bonding the cell bonding insulating layer to the peripheral bonding insulating layer and bonding the cell bonding pads to the peripheral bonding pads.

[0016] In some embodiments, fabricating the plurality of semiconductor structures may include stacking the peripheral circuit structures on the memory cell structure.

[0017] In some embodiments, fabricating the plurality of semiconductor structures may include stacking the memory cell structures on the peripheral circuit structure.

[0018] According to some embodiments of this disclosure, the semiconductor memory device and the semiconductor package can improve integration density, electrical performance, and reliability. Attached Figure Description

[0019] Figure 1 Semiconductor packages according to some embodiments of the present disclosure are shown.

[0020] Figure 2 This is a perspective view showing components of a memory cell structure according to some embodiments of the present disclosure.

[0021] Figure 3 This is a cross-sectional view showing a semiconductor structure according to some embodiments of the present disclosure.

[0022] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 This is a cross-sectional view illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0023] Figure 9 , Figure 10 , Figure 11 and Figure 12 It shows that it is stacked in it Figure 3 A diagram of an example semiconductor memory device with a semiconductor structure.

[0024] Figure 13 This is a cross-sectional view showing a semiconductor structure according to some embodiments of the present disclosure.

[0025] Figure 14 , Figure 15 , Figure 16 and Figure 17 This is a cross-sectional view illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0026] Figure 18 , Figure 19 , Figure 20 and Figure 21 It shows that it is stacked in it Figure 13 A diagram of an example stacked memory device with a semiconductor structure.

[0027] Figure 22 , Figure 23 and Figure 24 This is a diagram illustrating example semiconductor structures and semiconductor memory devices according to some embodiments of the present disclosure.

[0028] Figure 25 , Figure 26 and Figure 27This is a diagram illustrating example semiconductor structures and semiconductor memory devices according to some embodiments of the present disclosure. Detailed Implementation

[0029] In the following, stacked memory devices and semiconductor packages according to some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] Figure 1 Semiconductor packages according to some embodiments of the present disclosure are shown.

[0031] refer to Figure 1 The semiconductor package 1 may include a package substrate SUB, a semiconductor memory device 1000, a main die 2000, and a plurality of through electrodes 300.

[0032] The main die 2000 and the semiconductor memory device 1000 can be stacked on the package substrate SUB. The main die 2000 and the semiconductor memory device 1000 can be sequentially stacked on the upper surface of the package substrate SUB along a first direction D1. The first direction D1 can be perpendicular to the upper surface of the package substrate SUB.

[0033] Semiconductor memory device 1000 may include multiple semiconductor structures 10, 20, and 30. Although three semiconductor structures are shown, a greater number can be provided. Each of the multiple semiconductor structures 10, 20, and 30 may be stacked on a first direction D1. Semiconductor memory device 1000 may include a high-bandwidth memory (HBM) chip. That is, semiconductor memory device 1000 may be implemented based on the HBM standard.

[0034] Semiconductor memory device 1000 may include a buffer die 10 and core dies 20 and 30. Each core die 20, 30 may include an array of memory cells. In some embodiments, the semiconductor memory device 1000 may omit the buffer die, and the main die 2000 may be used as a buffer die.

[0035] The buffer die 10 may include a physical layer and a direct access region. The physical layer is electrically connected to the physical layer of the main die via an interposer. The semiconductor memory device 1000 can receive signals from or send signals to the main die 2000 via the physical layer.

[0036] The buffer die 10 and the core dies 20 and 30 can be electrically connected to each other through multiple through electrodes 300, a first connection pad 310 and a second connection pad 320.

[0037] The main die 2000 can be mounted on the package substrate SUB via solder bumps. The main die 2000 can use the semiconductor memory device 1000 to perform applications supported by the semiconductor package 1. For example, the main die 2000 may include at least one processor selected from a central processing unit (CPU), application processor (AP), graphics processing unit (GPU), neural processing unit (NPU), tensor processing unit (TPU), vision processing unit (VPU), image signal processor (ISP), and digital signal processor (DSP) to perform dedicated operations.

[0038] The master die 2000 may include a physical layer and a memory controller. The physical layer of the master die 2000 may include input / output circuitry for sending and receiving signals with the physical layer of the semiconductor memory device 1000. The master die 2000 can provide various signals to the physical layer of the semiconductor memory device 1000 via the physical layer. Signals provided to the physical layer of the semiconductor memory device 1000 can be delivered to the core die via interface circuitry of the physical layer of the semiconductor memory device 1000 and multiple through electrodes 300.

[0039] The semiconductor package described above is merely an example, and other forms of semiconductor packages may be included. For example, the main die 2000 may be implemented as a system-on-a-chip (SoC) including at least one processor such as a CPU, AP, GPU, or NPU. Alternatively, the main die 2000 and the semiconductor memory device 1000 may be mounted on an interposer layer connecting the semiconductor memory device and the main die, and the interposer layer may be mounted on a printed circuit board (PCB).

[0040] A semiconductor memory device according to this disclosure will now be described.

[0041] Figure 2 This is a perspective view illustrating some components of a memory cell structure according to some embodiments of the present disclosure, and Figure 3 This is a cross-sectional view showing a semiconductor structure according to some embodiments of the present disclosure.

[0042] refer to Figure 2 and Figure 3 A semiconductor memory device according to some embodiments of the present disclosure may include a plurality of semiconductor structures 10. The semiconductor memory device may be formed by stacking a plurality of semiconductor structures 10.

[0043] Each semiconductor structure 10 may include a memory cell structure CS, a peripheral circuit structure PS, a wiring structure WS, a through electrode 300, a through path 360, etc.

[0044] The memory cell structure CS can include at least one of various types of memory semiconductors. For example, the memory cell structure CS can include vertically stacked dynamic random access memory (VSDRAM), three-dimensional ferroelectric field-effect transistor memory (3D FeFET), or three-dimensional monolithic memory. In some embodiments, the memory cell structure CS can include a two-dimensional memory such as buried channel array transistor (BCAT) or vertical channel transistor (VCT) dynamic random access memory.

[0045] The peripheral circuit structure PS can be stacked on the memory cell structure CS. That is, the memory cell structure CS and the peripheral circuit structure PS can overlap each other in a first direction D1 perpendicular to the upper surface of the cell substrate 100. The peripheral circuit structure PS can overlap with the memory cell array in the memory cell structure CS in the first direction D1 perpendicular to the upper surface of the cell substrate 100.

[0046] The memory cell structure CS may include a cell substrate 100, an interlayer dielectric layer ILD, a semiconductor pattern SP, word lines WL, bit lines BL, and a data storage pattern DSP. The memory cell structure CS may include a plurality of memory cells stacked on the cell substrate 100 along a first direction D1 and spaced apart from each other, and each memory cell may include a semiconductor pattern SP having a channel region CH and a capacitor structure CAP disposed on one side of the semiconductor pattern SP.

[0047] The unit substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the unit substrate 100 may include silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, etc., but is not limited thereto.

[0048] The first surface 100_1 of the unit substrate 100 may be the upper surface, and the second surface 100_2 may be the lower surface. A direction perpendicular to the first surface 100_1 of the unit substrate 100 is defined as a first direction D1, and a direction parallel to the first surface 100_1 and perpendicular to the first direction D1 is defined as a second direction D2. A third direction D3 is a direction perpendicular to both the first direction D1 and the second direction D2.

[0049] Multiple semiconductor patterns SP can be stacked on a first direction D1. The semiconductor patterns SP can be spaced apart from each other on a second direction D2 and a third direction D3. That is, the semiconductor patterns SP can be arranged three-dimensionally on the unit substrate 100. Each semiconductor pattern SP may include at least one of silicon and germanium. For example, each semiconductor pattern SP may include monocrystalline silicon.

[0050] Each semiconductor pattern SP can be a strip shape with a long axis in the third direction D3. Each semiconductor pattern SP may include a first source / drain region SD1, a second source / drain region SD2 spaced apart from the first source / drain region SD1, and a channel region CH located between the first source / drain region SD1 and the second source / drain region SD2. The first source / drain region SD1 may be adjacent to the bit line BL, and the second source / drain region SD2 may be adjacent to the capacitor structure CAP. Impurities may be doped into the first source / drain region SD1 and the second source / drain region SD2.

[0051] Each semiconductor pattern SP can penetrate a word line WL on the third-direction D3. A portion of each semiconductor pattern SP can be surrounded by the word line WL. Each word line WL can have a fully encircling gate structure that completely surrounds the channel region CH of the corresponding semiconductor pattern SP. A gate insulating layer Gox can be located between the channel region CH of each semiconductor pattern SP and the word line WL.

[0052] Each of the multiple word lines WL can extend along a second direction D2. Memory cells arranged along the second direction D2 can be connected to a single word line WL. The multiple word lines WL can be arranged along a first direction D1 or a third direction D3. The multiple word lines WL can be stacked on the upper surface of the cell substrate 100 and spaced apart along the first direction D1.

[0053] Multiple word lines (WL) may include conductive materials. For example, conductive materials may be semiconductor materials, conductive metal nitrides, metals, or metal-semiconductor compounds.

[0054] An interlayer dielectric layer (ILD) can be situated between adjacent word lines (WLs) of a plurality of word lines (WLs). The word lines (WLs) and the interlayer dielectric layers (ILDs) can be stacked alternately. The interlayer dielectric layers (ILDs) can comprise insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Although the interlayer dielectric layer (ILD) is shown as a single layer, it can be a multilayer structure. The word lines (WLs) and the interlayer dielectric layers (ILDs) can be stacked alternately to form a stacked structure (MS). The stacked structure (MS) can have a stepped structure; that is, one end of the word lines (WLs) and the interlayer dielectric layers (ILDs) can have a step.

[0055] A cell insulating layer 110 may be disposed on the cell substrate 100 and the stacked structure MS. The cell insulating layer 110 may cover the upper surface and the side surface of the stacked structure MS. That is, the cell insulating layer 110 may cover the upper surface of the word line WL located at the top horizontal height of the stacked structure MS, as well as the side surface of the word line WL forming the side surface of the stacked structure MS and the side surface of the interlayer dielectric layer ILD.

[0056] A gate insulating layer Gox may be located between each word line WL and each semiconductor pattern SP. The gate insulating layer Gox may surround each channel region CH. Each channel region CH may be separated from its corresponding word line WL by the gate insulating layer Gox. The gate insulating layer Gox may not contact the first source / drain region SD1 and the second source / drain region SD2 of each semiconductor pattern SP.

[0057] The gate insulating layer Gox may include at least one of a high dielectric constant layer, silicon oxide, silicon nitride, and silicon oxynitride. The high dielectric constant layer may include at least one of, for example, hafnium oxide, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate oxide, barium titanate oxide, strontium titanate oxide, lithium oxide, aluminum oxide, lead scandium tantalate oxide, and lead zinc niobate.

[0058] Each of the multiple bit lines BL can extend in a first direction D1. The bit lines BL can have substantially equal lengths in the first direction D1. The bit lines BL can be arranged to be spaced apart from each other in a second direction D2 and a third direction D3. Each bit line BL can be connected to the first source / drain region SD1 of each semiconductor pattern SP stacked in the first direction D1.

[0059] Each bit line BL may include a conductive material. The conductive material may be at least one of the following: a doped semiconductor material such as doped silicon or doped germanium; a conductive metal nitride such as titanium nitride or tantalum nitride; a metal such as tungsten, titanium or tantalum; and a metal semiconductor compound such as tungsten silicide, cobalt silicide or titanium silicide.

[0060] The data storage pattern DSP may include multiple capacitor structures (CAPs) and plate electrodes (PEs). Each capacitor structure (CAP) can transmit or receive signals (e.g., data) from the outside via the plate electrodes (PEs). The data storage pattern DSP may be positioned between a first semiconductor pattern SP1 and a second semiconductor pattern SP2.

[0061] Each of the multiple capacitor structures CAP may include a lower electrode BE, a dielectric layer CIL, and an upper electrode UE. Each capacitor structure CAP may be connected to the second source / drain region SD2 of the corresponding semiconductor pattern SP. The multiple lower electrodes BE of the capacitor structure CAP may be connected to the second source / drain region SD2 of the semiconductor pattern SP, respectively.

[0062] Each lower electrode BE can be disposed on a side surface of the semiconductor pattern SP. For example, the lower electrode BE may include at least one of the following: a metallic material such as titanium, tantalum, tungsten, copper or aluminum; a conductive metal nitride such as titanium nitride, tantalum nitride or tungsten nitride; and a doped semiconductor material such as doped silicon or doped germanium.

[0063] The lower electrode BE can be positioned at substantially the same vertical horizontal height as the semiconductor pattern SP. The thickness of each lower electrode BE can be greater than or equal to the thickness of each semiconductor pattern SP. That is, the lower electrodes BE can be stacked in the first direction D1 and can have a major axis in the third direction D3. In some embodiments, an interface layer can be interposed between each lower electrode BE and the corresponding semiconductor pattern SP. The interface layer may include, for example, a silicide layer.

[0064] The dielectric layer CIL can conformally cover the surface of each lower electrode BE. The dielectric layer CIL can be located between each lower electrode BE and the corresponding upper electrode UE. The dielectric layer CIL can include a high dielectric constant material. For example, the dielectric layer CIL can include titanium oxide (TiO2). In some embodiments, the dielectric layer CIL can include hafnium oxide, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate oxide, barium titanate oxide, strontium titanate oxide, lithium oxide, aluminum oxide, lead scandium tantalate oxide, lead zinc niobate, or combinations thereof.

[0065] The upper electrode UE can conformally cover the surface of the dielectric layer CIL. The upper electrode UE can be disposed on the dielectric layer CIL. For example, the upper electrode UE can include at least one of titanium, cobalt, nickel, copper, tungsten, niobium, tantalum, manganese, indium, molybdenum, vanadium, hafnium, zirconium, and combinations thereof.

[0066] The plate electrode PE can be disposed on the upper electrode UE. The plate electrode PE can fill the space within the capacitor structure CAP. For example, the plate electrode PE can include doped silicon or doped silicon germanium.

[0067] The memory cell structure CS may also include cell wiring structure 140 and word line contact WLC.

[0068] The cell wiring structure 140 may include cell paths 141 and cell wiring layers 142. The number, location, and / or connection structure of the cell paths 141 and cell wiring layers 142 may be modified differently. The cell wiring structure 140 may include conductive materials. For example, each cell path 141 and each cell wiring layer 142 may include at least one of a metal, a conductive metal nitride, a conductive metal oxide, and a doped semiconductor material.

[0069] A word line contact WLC can be disposed on a word line WL. The word line contact WLC can extend in the first direction D1. The word line contact WLC can connect the word line WL to the cell wiring structure 140. For example, cell path 141 and cell wiring layer 142 can be sequentially disposed on the word line contact WLC. The word line contact WLC can penetrate the cell insulation layer 110 and connect to the word line WL. The word line contact WLC can be surrounded by the cell insulation layer 110.

[0070] The peripheral circuit structure PS may include a peripheral circuit board 200, a peripheral circuit device PTR, and a peripheral wiring structure 240.

[0071] The peripheral circuit board 200 may include a first surface 200_1 and a second surface 200_2 opposite to the first surface 200_1. The peripheral circuit structure PS may be configured such that the second surface 200_2 of the peripheral circuit board 200 faces the first surface 100_1 of the cell board 100 on the memory cell structure CS.

[0072] A peripheral circuit structure PS can be disposed on a memory cell structure CS. In some embodiments, the peripheral circuit structure PS and the memory cell structure CS can be joined by a wafer-to-wafer bonding method. For example, the peripheral circuit structure PS can be joined to the memory cell structure CS by fusion bonding. A bonding surface BS can be formed at the interface between the peripheral circuit structure PS and the memory cell structure CS. Specifically, a cell bonding insulating layer 150 can be disposed on the upper surface of the memory cell structure CS, and a peripheral bonding insulating layer 250 can be disposed on the lower surface of the peripheral circuit structure PS. The contact surface between the cell bonding insulating layer 150 and the peripheral bonding insulating layer 250 can be the bonding surface BS.

[0073] The peripheral circuit device (PTR) can be disposed on the first surface 200_1 of the peripheral circuit substrate 200. The PTR can include circuit devices such as transistors. The PTR can configure circuitry to control memory cells located in the memory cell structure CS. For example, the circuitry may include, but is not limited to, a row decoder for selecting rows of the memory cell array based on address signals, a column decoder for selecting columns of the memory cell array based on address signals, a sense amplifier for detecting and amplifying data in the memory cells, and a word line driver for activating the word line of the selected row.

[0074] The peripheral wiring structure 240 may include peripheral paths 241 and peripheral wiring layers 242. The number, location, and / or connection structure of the peripheral paths 241 and peripheral wiring layers 242 may be modified differently. The peripheral wiring structure 240 may include conductive materials. For example, each peripheral path 241 and each peripheral wiring layer 242 may include at least one of a metal, a conductive metal nitride, a conductive metal oxide, and a doped semiconductor material.

[0075] The peripheral circuit structure PS can be electrically connected to the memory cell structure CS, enabling the peripheral circuit device PTR to control the memory cells of the memory cell structure CS. A through path 360 can be provided to electrically connect the peripheral circuit structure PS and the memory cell structure CS. For example, the through path 360 can electrically connect the peripheral wiring structure 240 to the cell wiring structure 140. The through path 360 can extend in a first direction D1 and can penetrate the peripheral circuit substrate 200, the peripheral bonding insulating layer 250, and the cell bonding insulating layer 150 in the first direction D1. That is, a portion of the through path 360 can be located in the peripheral circuit structure PS, and the remainder can be located in the memory cell structure CS.

[0076] The through-path 360 may include a conductive material. For example, the through-path 360 may include a metallic material such as copper, aluminum, or tungsten. Spacers 360a may be provided on the side surface of the through-path 360. The spacers 360a may insulate the through-path 360 from the peripheral circuit board 200 or prevent the diffusion of metal atoms. For example, the spacers 360a may include an insulating material such as silicon oxide or silicon nitride.

[0077] The wiring structure WS can be disposed on the peripheral circuit structure PS. That is, the memory cell structure CS, the peripheral circuit structure PS, and the wiring structure WS can be stacked sequentially in the first direction D1. The wiring structure WS can be electrically connected to the memory cell structure CS and the peripheral circuit structure PS. The wiring structure WS can include multiple wiring paths and multiple wiring layers. The number, location, and / or connection structure of the wiring paths and wiring layers can be modified differently. In some embodiments, the wiring structure WS can be part of the peripheral wiring structure 240. That is, the peripheral wiring structure 240 can include the wiring structure WS.

[0078] Each of the plurality of through electrodes 300 may be disposed in the semiconductor structure 10. Each through electrode 300 may connect a wiring structure WS to a second connection pad 320. Each through electrode 300 may extend in the semiconductor structure 10 in a first direction D1. Each through electrode 300 may penetrate at least a portion of the semiconductor structure 10 in the first direction D1. For example, each through electrode 300 may penetrate a memory cell structure CS and a peripheral circuit structure PS in the first direction D1. Each through electrode 300 may overlap with the memory cell structure CS and the peripheral circuit structure PS in a second direction D2 or a third direction D3. The through electrode 300 may be a through silicon via (TSV).

[0079] The through electrode 300 may include a conductive film 300a and a barrier film surrounding the conductive film 300a. The conductive film 300a may include a conductive material such as copper, aluminum, or tungsten. The barrier film may include a conductive material with barrier properties, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, or tungsten nitride. The barrier film can prevent the diffusion of metal atoms from the conductive film 300a. In some embodiments, an insulating film 300b may surround the sidewalls of the through electrode 300.

[0080] The through electrode 300 may include a first surface 300_1 and a second surface 300_2. The first surface 300_1 is defined as the surface in contact with the wiring structure WS, and the second surface 300_2 is defined as the surface opposite to the first surface 300_1. The width of the through electrode 300 may decrease from the first surface 300_1 along a first direction D1 toward the second surface 300_2.

[0081] The first surface 300_1 of the through electrode 300 can be coplanar with the upper surface of the peripheral circuit structure PS. That is, the first surface 300_1 of the through electrode 300 can be coplanar with the interface between the peripheral circuit structure PS and the wiring structure WS.

[0082] On the wiring structure WS, a first interlayer dielectric layer 311, a first bonding insulating layer 351, and a first connection pad 310 can be disposed. The first connection pad 310 can be formed after removing portions of the first interlayer dielectric layer 311 and the first bonding insulating layer 351. The first connection pad 310 can overlap with the first interlayer dielectric layer 311 and the first bonding insulating layer 351 in a second direction D2 or a third direction D3. The upper surface of the first connection pad 310 can be coplanar with the upper surface of the first bonding insulating layer 351. That is, the upper surfaces of the first connection pad 310 and the first bonding insulating layer 351 can form the upper surface of the semiconductor structure 10. Although the first interlayer dielectric layer 311 and the first bonding insulating layer 351 are shown as separate layers, they can be single layers or multiple layers. Each of the first interlayer dielectric layer 311 and the first bonding insulating layer 351 can include an insulating material such as silicon oxide or silicon nitride.

[0083] In some embodiments, the first connection pad 310 may have a width that decreases as the distance along the first direction D1 to the wiring structure WS decreases. However, the shape of the first connection pad 310 is not limited to this, and it may have a width that increases as the distance along the first direction D1 to the wiring structure WS decreases.

[0084] The second interlayer dielectric layer 312 and the second bonding insulating layer 352 can be sequentially disposed on the second surface 100_2 of the unit substrate 100. A second connection pad 320 can be formed after removing portions of the second interlayer dielectric layer 312 and the second bonding insulating layer 352. The second connection pad 320 can overlap the second interlayer dielectric layer 312 and the second bonding insulating layer 352 in a second direction D2 or a third direction D3. The lower surface of the second connection pad 320 can be coplanar with the lower surface of the second bonding insulating layer 352. That is, the lower surface of the second connection pad 320 and the lower surface of the second bonding insulating layer 352 can form the lower surface of the semiconductor structure 10. Although the second interlayer dielectric layer 312 and the second bonding insulating layer 352 are shown as separate layers, they can be single layers or multiple layers. Each of the second interlayer dielectric layer 312 and the second bonding insulating layer 352 can include an insulating material such as silicon oxide or silicon nitride.

[0085] In some embodiments, the second connection pad 320 may have a width that decreases as the distance along the first direction D1 to the through electrode 300 decreases. However, the shape of the second connection pad 320 is not limited to this, and it may have a width that increases as the distance along the first direction D1 to the through electrode 300 decreases.

[0086] Each of the first bonding pad 310 and the second bonding pad 320 may include a conductive material such as copper. Therefore, the upper surface of the semiconductor structure 10 may consist of a first bonding insulating layer 351 comprising an insulating material and a first bonding pad 310 comprising copper. The lower surface of the semiconductor structure 10 may consist of a second bonding insulating layer 352 comprising an insulating material and a second bonding pad 320 comprising copper.

[0087] Figures 4 to 8 This is a cross-sectional view illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0088] refer to Figure 4 A peripheral circuit structure PS can be stacked on the memory cell structure CS. For example, a cell bonding insulating layer 150 can be formed on the upper surface of the memory cell structure CS, and a peripheral bonding insulating layer 250 can be formed on the lower surface of the peripheral circuit structure PS. Next, the cell bonding insulating layer 150 and the peripheral bonding insulating layer 250 can be stacked so that they face each other. With the cell bonding insulating layer 150 in contact with the peripheral bonding insulating layer 250, the cell bonding insulating layer 150 can be bonded to the peripheral bonding insulating layer 250 by plasma activation and / or annealing to form a bonding surface BS.

[0089] refer to Figure 5A portion of the memory cell structure CS and a portion of the peripheral circuit structure PS can be removed to form a via VH. The portion of the memory cell structure CS and the portion of the peripheral circuit structure PS can penetrate to a predetermined depth in the first direction D1. For example, the portion can penetrate the peripheral circuit structure PS, and a portion can penetrate from the upper surface of the memory cell structure CS to the cell substrate 100. Specifically, the portion can penetrate the upper surface of the cell substrate 100, but may not penetrate the lower surface of the cell substrate 100.

[0090] refer to Figure 6 An insulating film 300b can be formed in the via VH. The insulating film 300b may include an insulating material having at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the insulating film 300b can be formed by chemical vapor deposition (CVD), but is not limited thereto.

[0091] Next, a barrier film can be formed on the insulating film 300b. The barrier film can be formed in the via VH. The barrier film can include a conductive material with barrier properties, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, or tungsten nitride. For example, the barrier film can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0092] refer to Figure 7 Conductive material can fill the vias VH to form a conductive film 300a. The conductive film 300a can be formed by an electroplating process, in which a seed layer is formed on a barrier film (or insulating film 300b), and the conductive material grows from the seed layer. For example, the conductive film 300a may include copper. In some embodiments, the insulating film 300b, the barrier film, and / or the conductive film 300a may also be formed on the upper surface of the peripheral circuit structure PS. In this case, a planarization process can be performed.

[0093] In this way, a through electrode 300 can be formed. The first surface 300_1 of the through electrode 300 can be coplanar with the upper surface of the peripheral circuit structure PS. A wiring structure WS can be formed on the upper surface of the peripheral circuit structure PS and the first surface 300_1 of the through electrode 300. The wiring structure WS can be electrically connected to the peripheral wiring structure 240 and the through electrode 300.

[0094] Next, a first interlayer dielectric layer 311 and a first bonding insulating layer 351 can be sequentially formed on the wiring structure WS. After a portion of the first interlayer dielectric layer 311 and a portion of the first bonding insulating layer 351 are removed, a first connection pad 310 can be formed. For example, an etching process can remove a portion of the first interlayer dielectric layer 311 and a portion of the first bonding insulating layer 351, and a conductive material such as copper can fill the removed areas to form the first connection pad 310. The first connection pad 310 can be positioned to overlap with the through electrode 300 in a first direction D1. In some embodiments, the wiring structure WS can be omitted, and the first connection pad 310 can be disposed on the through electrode 300.

[0095] Through an etching process, the width of the first interlayer dielectric layer 311 and the first bonding insulating layer 351 can gradually decrease as the distance to the wiring structure WS decreases. Therefore, the first connection pad 310 can have a width that decreases as the distance to the wiring structure WS decreases. In some embodiments, through a planarization process, the upper surface of the first connection pad 310 can be coplanar with the upper surface of the first bonding insulating layer 351. In some embodiments, surface dishing may occur at the upper surface of the first connection pad 310.

[0096] refer to Figure 8 A portion of the unit substrate 100 can be removed. In some embodiments, a portion of the through electrode 300 can be removed together. For example, the insulating film 300b located on the lower surface of the conductive film 300a can be removed. A planarization process can be performed on the unit substrate 100 and / or the through electrode 300. A second interlayer dielectric layer 312 and a second bonding insulating layer 352 can be sequentially formed in the region where the unit substrate 100 and / or the through electrode 300 have been removed.

[0097] Next, after a portion of the second dielectric layer 312 and a portion of the second bonding insulating layer 352 are removed, a second connection pad 320 can be formed. For example, an etching process can remove a portion of the second dielectric layer 312 and a portion of the second bonding insulating layer 352, and a conductive material such as copper can fill the removed area to form the second connection pad 320. In some embodiments, through a planarization process, the lower surface of the second connection pad 320 can be coplanar with the lower surface of the second bonding insulating layer 352.

[0098] Figures 9 to 12 It shows that it is stacked in it Figure 3 A diagram of a semiconductor memory device with a semiconductor structure.

[0099] refer to Figure 9 and Figure 10Multiple semiconductor structures 10, 20, and 30 can be stacked sequentially along the first direction D1. For example, a second semiconductor structure 20 can be disposed on the first semiconductor structure 10, and a third semiconductor structure 30 can be disposed on the second semiconductor structure 20.

[0100] Multiple semiconductor structures 10, 20, and 30 may have the same structure. Each of the multiple semiconductor structures 10, 20, and 30 may include a through electrode 300. The through electrode located in the first semiconductor structure 10 is referred to as the first through electrode, the through electrode located in the second semiconductor structure 20 is referred to as the second through electrode, and the through electrode located in the third semiconductor structure 30 is referred to as the third through electrode. In addition, the memory cell structure and the peripheral circuit structure may be referred to as the first memory cell structure to the third memory cell structure and the first peripheral circuit structure to the third peripheral circuit structure, respectively.

[0101] Each of the plurality of through electrodes 300 can be aligned in a first direction D1. For example, the first through electrode, the second through electrode, and the third through electrode can be aligned with each other in the first direction D1. The plurality of semiconductor structures 10, 20, and 30 can have a periphery-on-cell (PoC) structure, wherein the peripheral circuit structure is disposed on top of the memory cell structure. The first semiconductor structure 10 can be placed in a normal state N, the second semiconductor structure 20 can be stacked on the first semiconductor structure 10 in a flipped state F, and the third semiconductor structure 30 can be stacked on the second semiconductor structure 20 in a normal state N. That is, the front surface of the first semiconductor structure 10 can be bonded to the front surface of the second semiconductor structure 20, and the rear surface of the second semiconductor structure 20 can be bonded to the rear surface of the third semiconductor structure 30. For example, the plurality of semiconductor structures 10, 20, and 30 can be bonded to each other using a hybrid copper bonding (HCB) method.

[0102] In the first bonding region BA1 located between the first semiconductor structure 10 and the second semiconductor structure 20, the corresponding first connection pads 310 and corresponding first bonding insulating layers 351 of the first semiconductor structure 10 and the second semiconductor structure 20 can be bonded to each other. The first connection pads 310 of the first semiconductor structure 10 (also referred to as "first front-side connection pads") can contact the first connection pads 310 of the second semiconductor structure 20 (also referred to as "second front-side connection pads"), and the first bonding insulating layer 351 of the first semiconductor structure 10 can contact the first bonding insulating layer 351 of the second semiconductor structure 20 (also referred to as "front-side bonding insulating layer"). In some embodiments, the first connection pads 310 of the first semiconductor structure 10 can partially contact the first bonding insulating layer 351 of the second semiconductor structure 20.

[0103] In the second bonding region BA2 located between the second semiconductor structure 20 and the third semiconductor structure 30, the corresponding second connection pads 320 and corresponding second bonding insulating layers 352 of the second semiconductor structure 20 and the third semiconductor structure 30 can be bonded to each other. The second connection pads 320 of the second semiconductor structure 20 can contact the second connection pads 320 of the third semiconductor structure 30, and the second bonding insulating layer 352 of the second semiconductor structure 20 can contact the second bonding insulating layer 352 of the third semiconductor structure 30. In some embodiments, the second connection pads 320 of the second semiconductor structure 20 can partially contact the second bonding insulating layer 352 of the third semiconductor structure 30.

[0104] refer to Figure 11 and Figure 12 Multiple semiconductor structures 10, 20, and 30 can be stacked sequentially along the first direction D1. For example, a second semiconductor structure 20 can be disposed on the first semiconductor structure 10, and a third semiconductor structure 30 can be disposed on the second semiconductor structure 20.

[0105] Multiple semiconductor structures 10, 20, and 30 may have the same structure. Multiple semiconductor structures 10, 20, and 30 may have a Proof-of-Concept (PoC) structure, wherein the peripheral circuit structure is disposed on top of the memory cell structure. Each of the first semiconductor structure 10, the second semiconductor structure 20, and the third semiconductor structure 30 may be stacked sequentially in a flipped state F. That is, the rear surface of the first semiconductor structure 10 may be bonded to the front surface of the second semiconductor structure 20, and the rear surface of the second semiconductor structure 20 may be bonded to the front surface of the third semiconductor structure 30.

[0106] For example, multiple semiconductor structures 10, 20, and 30 can be bonded to each other using the HCB method. In the third bonding region BA3 located between the first semiconductor structure 10 and the second semiconductor structure 20, the second connection pad 320 of the first semiconductor structure 10 (also referred to as the "first back-side connection pad 320") can be bonded to the first connection pad 310 of the second semiconductor structure 20 (also referred to as the "second front-side connection pad 310"), and the second bonding insulating layer 352 of the first semiconductor structure 10 can be bonded to the first bonding insulating layer 351 of the second semiconductor structure 20. The second connection pad 320 of the first semiconductor structure 10 can contact the first connection pad 310 of the second semiconductor structure 20, and the second bonding insulating layer 352 of the first semiconductor structure 10 can contact the first bonding insulating layer 351 of the second semiconductor structure 20. In some embodiments, the first connection pad 310 of the second semiconductor structure 20 can partially contact the second bonding insulating layer 352 of the first semiconductor structure 10.

[0107] In the fourth bonding region BA4 located between the second semiconductor structure 20 and the third semiconductor structure 30, the second connection pad 320 of the second semiconductor structure 20 can be bonded to the first connection pad 310 of the third semiconductor structure 30, and the second bonding insulating layer 352 of the second semiconductor structure 20 can be bonded to the first bonding insulating layer 351 of the third semiconductor structure 30. The second connection pad 320 of the second semiconductor structure 20 can contact the third connection pad 310 of the third semiconductor structure 30, and the second bonding insulating layer 352 of the second semiconductor structure 20 can contact the first bonding insulating layer 351 of the third semiconductor structure 30. In some embodiments, the first connection pad 310 of the third semiconductor structure 30 can partially contact the second bonding insulating layer 352 of the second semiconductor structure 20.

[0108] In the following sections, embodiments different from those described above will be described. The same reference numerals are assigned to the same elements, and their detailed descriptions are omitted.

[0109] Figure 13 This is a cross-sectional view showing a semiconductor structure according to some embodiments of the present disclosure.

[0110] refer to Figure 13 According to some embodiments of this disclosure, the semiconductor structure 10A can be aligned with the arrangement of the memory cell structure CS and the peripheral circuit structure PS. Figure 3 The implementation methods are different.

[0111] The memory cell structure CS and the wiring structure WS can be sequentially stacked on the peripheral circuit structure PS. That is, the memory cell structure CS can be disposed on the peripheral circuit structure PS, and the wiring structure WS can be disposed on the memory cell structure CS. In some embodiments, the peripheral circuit structure PS and the memory cell structure CS can be joined by a wafer-to-wafer bonding method. For example, the peripheral circuit structure PS can be joined to the memory cell structure CS by fusion bonding. A bonding surface BS can be formed at the interface between the peripheral circuit structure PS and the memory cell structure CS. Specifically, a cell bonding insulating layer 150 can be disposed on the upper surface of the peripheral circuit structure PS, and a peripheral bonding insulating layer 250 can be disposed on the lower surface of the memory cell structure CS. The contact surface between the cell bonding insulating layer 150 and the peripheral bonding insulating layer 250 can be the bonding surface BS.

[0112] The memory cell structure CS may also include a first through path 361 and a second through path 362.

[0113] The first through-path 361 can electrically connect the peripheral circuit structure PS to the memory cell structure CS. The first through-path 361 can extend in the first direction D1 and can penetrate portions of the memory cell structure CS and the peripheral circuit structure PS in the first direction D1. For example, the first through-path 361 can penetrate the cell insulating layer 110, the cell substrate 100, the cell bonding insulating layer 150, and the peripheral bonding insulating layer 250 in the first direction D1. The first through-path 361 can connect the cell wiring structure 140 to the peripheral wiring structure 240.

[0114] The second through-path 362 can electrically connect the peripheral circuit structure PS to the wiring structure WS. The second through-path 362 can extend in the first direction D1 and can penetrate portions of the memory cell structure CS and the peripheral circuit structure PS in the first direction D1. For example, the second through-path 362 can penetrate the cell insulating layer 110, the cell substrate 100, the cell bonding insulating layer 150, and the peripheral bonding insulating layer 250 in the first direction D1. The second through-path 362 can connect the wiring structure WS to the peripheral wiring layer 240.

[0115] The first surface 300_1 of the through electrode 300 can be coplanar with the upper surface of the memory cell structure CS. That is, the first surface 300_1 of the through electrode 300 can be coplanar with the interface between the memory cell structure CS and the wiring structure WS.

[0116] The distance between the interface of the memory cell structure CS and the wiring structure WS and the second surface 300_2 of the through electrode 300 can be greater than the distance from the same interface to the second surface 200_2 (i.e., the lower surface) of the peripheral circuit board 200. That is, the second surface 300_2 of the through electrode 300 can be located at a lower horizontal height than the peripheral circuit board 200.

[0117] Figures 14 to 17 This is a cross-sectional view illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0118] refer to Figure 14 The memory cell structure CS can be stacked on the peripheral circuit structure PS. For example, a cell bonding insulating layer 150 can be formed on the lower surface of the memory cell structure CS, and a peripheral bonding insulating layer 250 can be formed on the upper surface of the peripheral circuit structure PS. Next, the cell bonding insulating layer 150 and the peripheral bonding insulating layer 250 can be stacked so that they face each other. With the cell bonding insulating layer 150 in contact with the peripheral bonding insulating layer 250, the cell bonding insulating layer 150 can be bonded to the peripheral bonding insulating layer 250 by plasma activation and / or annealing to form a bonding surface BS.

[0119] refer to Figure 15 A portion of the memory cell structure CS and a portion of the peripheral circuit structure PS can be removed to form a via VH. The via VH can penetrate a portion of the memory cell structure CS and a portion of the peripheral circuit structure PS to a predetermined depth in the first direction D1. For example, it can penetrate the memory cell structure CS and a portion of the portion from the upper surface of the peripheral circuit structure PS to the peripheral circuit substrate 200. Specifically, it can penetrate the upper surface of the peripheral circuit substrate 200, but may not penetrate its lower surface.

[0120] An insulating film 300b can be formed in the via VH. The insulating film 300b may include an insulating material having at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the insulating film 300b can be formed by a CVD method, but is not limited thereto.

[0121] Next, a barrier film can be formed on the insulating film 300b in the via VH. The barrier film can include conductive materials with barrier properties, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, or tungsten nitride, and can be formed by PVD, CVD, or ALD.

[0122] refer to Figure 16 The vias can be filled with a conductive material to form a conductive film 300a. The conductive film 300a can be formed by an electroplating process, in which a seed layer is formed on a barrier film, and the conductive material grows from the seed layer. For example, the conductive film 300a may include copper. In some embodiments, an insulating film 300b, a barrier film, and / or a conductive film 300a may also be formed on the upper surface of the peripheral circuit structure PS, after which a planarization process can be performed.

[0123] Therefore, a through electrode 300 can be formed. The first surface 300_1 of the through electrode 300 can be coplanar with the upper surface of the peripheral circuit structure PS. A wiring structure WS can be formed on the upper surface of the peripheral circuit structure PS and the first surface 300_1 of the through electrode 300. The wiring structure WS can be electrically connected to the peripheral wiring structure 240 and the through electrode 300.

[0124] Next, a first interlayer dielectric layer 311 and a first bonding insulating layer 351 can be sequentially formed on the wiring structure WS. After portions of the first interlayer dielectric layer 311 and the first bonding insulating layer 351 are removed, a first connection pad 310 can be formed by filling with a conductive material such as copper. Through an etching process, the width of the first interlayer dielectric layer 311 and the first bonding insulating layer 351 can gradually decrease as the distance from the wiring structure WS decreases, and therefore the first connection pad 310 can have a width that decreases as the distance from the wiring structure WS decreases. In some embodiments, a planarization process can cause the upper surface of the first connection pad 310 to be coplanar with the upper surface of the first bonding insulating layer 351. In some embodiments, surface depressions may occur on the upper surface of the first connection pad 310.

[0125] refer to Figure 17 A portion of the peripheral circuit board 200 can be removed, and a planarization process can be performed on the peripheral circuit board 200 and / or the through electrode 300. In the region where the peripheral circuit board 200 and / or the through electrode 300 have been removed, a second interlayer dielectric layer 312 and a second bonding insulating layer 352 can be sequentially formed.

[0126] Next, after a portion of the second dielectric layer 312 and a portion of the second bonding insulating layer 352 are removed, the second connection pad 320 can be formed by filling with a conductive material such as copper. In some embodiments, the planarization process may cause the lower surface of the second connection pad 320 to be coplanar with the lower surface of the second bonding insulating layer 352.

[0127] Figures 18 to 21 It shows that it is stacked in it Figure 13 A diagram of a semiconductor memory device with a semiconductor structure.

[0128] refer to Figure 18 and Figure 19 Semiconductor structures 11, 21, and 31 can be stacked sequentially along the first direction D1. For example, a second semiconductor structure 21 can be disposed on the first semiconductor structure 11, and a third semiconductor structure 31 can be disposed on the second semiconductor structure 21.

[0129] Multiple semiconductor structures 11, 21, and 31 may have the same structure. The multiple semiconductor structures 11, 21, and 31 may have a peripheral cell-on-a-pillar (CoP) structure, wherein the memory cell structure is disposed on top of the peripheral circuit structure. The first semiconductor structure 11, the second semiconductor structure 21, and the third semiconductor structure 31 may each be stacked in a normal state N. That is, the front surface of the first semiconductor structure 11 may be bonded to the rear surface of the second semiconductor structure 21, and the front surface of the second semiconductor structure 21 may be bonded to the rear surface of the third semiconductor structure 31. For example, the multiple semiconductor structures 11, 21, and 31 may be bonded to each other using the HCB method.

[0130] In the fifth bonding region BA5 located between the first semiconductor structure 11 and the second semiconductor structure 21, the first connection pad 310 of the first semiconductor structure 11 can be bonded to the second connection pad 320 of the second semiconductor structure 21, and the first bonding insulating layer 351 of the first semiconductor structure 11 can be bonded to the second bonding insulating layer 352 of the second semiconductor structure 21. The first connection pad 310 of the first semiconductor structure 11 can contact the second connection pad 320 of the second semiconductor structure 21. The first bonding insulating layer 351 of the first semiconductor structure 11 can contact the second bonding insulating layer 352 of the second semiconductor structure 21. In some embodiments, the first connection pad 310 of the first semiconductor structure 11 can partially contact the second bonding insulating layer 352 of the second semiconductor structure 21.

[0131] In the sixth bonding region BA6 located between the second semiconductor structure 21 and the third semiconductor structure 31, the first connection pad 310 of the second semiconductor structure 21 can be bonded to the second connection pad 320 of the third semiconductor structure 31, and the first bonding insulating layer 351 of the second semiconductor structure 21 can be bonded to the second bonding insulating layer 352 of the third semiconductor structure 31.

[0132] The first connection pad 310 of the second semiconductor structure 21 can contact the second connection pad 320 of the third semiconductor structure 31. The first bonding insulating layer 351 of the second semiconductor structure 21 can contact the second bonding insulating layer 352 of the third semiconductor structure 31. In some embodiments, the first connection pad 310 of the second semiconductor structure 21 can partially contact the second bonding insulating layer 352 of the third semiconductor structure 31.

[0133] refer to Figure 20 and Figure 21The first semiconductor structure 11 can be placed in a normal state N, the second semiconductor structure 21 can be stacked on the first semiconductor structure 11 in a flipped state F, and the third semiconductor structure 31 can be stacked on the second semiconductor structure 21 in a normal state N. That is, the first semiconductor structure 11 and the second semiconductor structure 21 can be bonded face to face, and the second semiconductor structure 21 and the third semiconductor structure 31 can be bonded back to back.

[0134] For example, multiple semiconductor structures 11, 21, and 31 can be bonded to each other using the HCB method. In the seventh bonding region BA7 located between the first semiconductor structure 11 and the second semiconductor structure 21, the corresponding first connection pads 310 of the first semiconductor structure 11 and the corresponding first bonding insulating layers 351 of the second semiconductor structure 21 can be bonded to each other. The first connection pads 310 of the first semiconductor structure 11 can contact the first connection pads 310 of the second semiconductor structure 21. The first bonding insulating layer 351 of the first semiconductor structure 11 can contact the first bonding insulating layer 351 of the second semiconductor structure 21. In some embodiments, the first connection pads 310 of the first semiconductor structure 11 can partially contact the first bonding insulating layer 351 of the second semiconductor structure 21.

[0135] In the eighth bonding region BA8 located between the second semiconductor structure 21 and the third semiconductor structure 31, the corresponding second connection pads 320 and corresponding second bonding insulating layers 352 of the second semiconductor structure 21 and the third semiconductor structure 31 can be bonded to each other. The second connection pads 320 of the second semiconductor structure 21 can contact the second connection pads 320 of the third semiconductor structure 31. The second bonding insulating layer 352 of the second semiconductor structure 21 can contact the second bonding insulating layer 352 of the third semiconductor structure 31. In some embodiments, the second connection pads 320 of the second semiconductor structure 21 can partially contact the second bonding insulating layer 352 of the third semiconductor structure 31.

[0136] Figures 22 to 24 This is a diagram illustrating a semiconductor structure and a semiconductor memory device according to some embodiments of the present disclosure.

[0137] refer to Figures 22 to 24 The connection scheme between the memory cell structure CS and the peripheral circuit structure PS can be different. Figure 3 The bonding scheme of the implementation method. The semiconductor structure 12 may have a CoP structure, wherein the memory cell structure CS is disposed on top of the peripheral circuit structure PS.

[0138] The memory cell structure CS can be disposed on the peripheral circuit structure PS, such that the first surface 100_1 of the cell substrate 100 faces the first surface 200_1 of the peripheral circuit substrate 200. In some embodiments, the peripheral circuit structure PS and the memory cell structure CS can be bonded using a wafer-to-wafer bonding method. For example, the memory cell structure CS can be bonded to the peripheral circuit structure PS using the HCB method. A bonding surface BS can be formed at the interface between the peripheral circuit structure PS and the memory cell structure CS. In some embodiments, a wiring structure can be provided between the memory cell structure CS and the peripheral circuit structure PS.

[0139] A cell bonding insulating layer 150 can be provided on the lower surface of the memory cell structure CS. A peripheral bonding insulating layer 250 can be provided on the upper surface of the peripheral circuit structure PS. The cell bonding pad 151 can be configured to overlap with the cell bonding insulating layer 150 in the second direction D2. The lower surface of the cell bonding pad 151 can be coplanar with the lower surface of the cell bonding insulating layer 150. The peripheral bonding pad 251 can be configured to overlap with the peripheral bonding insulating layer 250 in the second direction D2. The upper surface of the peripheral bonding pad 251 can be coplanar with the upper surface of the peripheral bonding insulating layer 250. The cell bonding pad 151 and the peripheral bonding pad 251 can correspond to each other. The cell bonding pad 151 and the peripheral bonding pad 251 can contact each other. The contact surface between the lower surface of the cell bonding insulating layer 150 and the cell bonding pad 151 and the upper surface of the peripheral bonding insulating layer 250 and the peripheral bonding pad 251 can be a bonding surface BS.

[0140] The through-electrode 300 can connect the first connection pad 310 to the second connection pad 320 and can extend in the semiconductor structure 10 in a first direction D1. The through-electrode 300 can penetrate at least a portion of the semiconductor structure 10 in the first direction D1. For example, the through-electrode 300 can penetrate the memory cell structure CS and the peripheral circuit structure PS in the first direction D1. The through-electrode 300 can overlap with the memory cell structure CS and the peripheral circuit structure PS in a second direction D2 or a third direction D3. The through-electrode 300 can be a TSV.

[0141] The first surface 300_1 of the through electrode 300 may be coplanar with the second surface 100_2 (e.g., the upper surface) of the memory cell structure CS. The second surface 300_2 of the through electrode 300 may be located at a lower horizontal height than the second surface 200_2 (e.g., the lower surface) of the peripheral circuit board 200.

[0142] refer to Figure 23Semiconductor structures 12, 22, and 32 can each be stacked in a normal state N. That is, the front surface of the first semiconductor structure 12 can be bonded to the rear surface of the second semiconductor structure 22, and the front surface of the second semiconductor structure 22 can be bonded to the rear surface of the third semiconductor structure 32. Multiple semiconductor structures 12, 22, and 32 can be bonded to each other using the HCB method.

[0143] The first connection pad 310 of the first semiconductor structure 12 can be bonded to the second connection pad 320 of the second semiconductor structure 22, and the first bonding insulating layer 351 of the first semiconductor structure 12 can be bonded to the second bonding insulating layer 352 of the second semiconductor structure 22. The first bonding insulating layer 351 of the first semiconductor structure 12 can contact the second bonding insulating layer 352 of the second semiconductor structure 22.

[0144] The first connection pad 310 of the second semiconductor structure 22 can be bonded to the second connection pad 320 of the third semiconductor structure 32, and the first bonding insulating layer 351 of the second semiconductor structure 22 can be bonded to the second bonding insulating layer 352 of the third semiconductor structure 32. The first bonding insulating layer 351 of the second semiconductor structure 22 can contact the second bonding insulating layer 352 of the third semiconductor structure 32.

[0145] refer to Figure 24 The first semiconductor structure 12 can be placed in a normal state N, the second semiconductor structure 22 can be stacked on the first semiconductor structure 12 in a flipped state F, and the third semiconductor structure 32 can be stacked on the second semiconductor structure 22 in a normal state N. That is, the first semiconductor structure 12 and the second semiconductor structure 22 can be bonded face-to-face, and the second semiconductor structure 22 and the third semiconductor structure 32 can be bonded back-to-back. Multiple semiconductor structures 12, 22, and 32 can be bonded to each other using the HCB method.

[0146] The corresponding first connection pads 310 and corresponding first bonding insulating layers 351 of the first semiconductor structure 12 and the second semiconductor structure 22 can be bonded to each other. The corresponding second connection pads 320 and corresponding second bonding insulating layers 352 of the second semiconductor structure 22 and the third semiconductor structure 32 can be bonded to each other.

[0147] Figures 25 to 27 This is a diagram illustrating a semiconductor structure and a semiconductor memory device according to some embodiments of the present disclosure.

[0148] refer to Figure 25 The semiconductor structure 13 according to some embodiments of this disclosure may differ in shape from that of the through electrode 300A. Figure 22Implementation methods. For example, the through electrode 300A may be a contact structure instead of a TSV. In some implementations, the through electrode 300A may include a first connection pad 310 provided as both a TSV and a contact structure. In this case, an insulating film may be provided on the side surface of the first connection pad 310.

[0149] Semiconductor structure 13 may have a CoP structure, wherein the memory cell structure CS is disposed on the upper side of the peripheral circuit structure PS. The memory cell structure CS may be configured such that the first surface 100_1 of the cell substrate 100 faces the first surface 200_1 of the peripheral circuit substrate 200. For example, the memory cell structure CS may be bonded to the peripheral circuit structure PS by means of the HCB method.

[0150] Each of the plurality of through electrodes 300A can be disposed in a corresponding one of the plurality of semiconductor structures 13. The through electrode 300A can penetrate the memory cell structure CS in a first direction D1. Each through electrode 300A can electrically connect a peripheral circuit structure PS to the memory cell structure CS. The through electrode 300A can include a conductive material. For example, the conductive material can include at least one of aluminum, tungsten, and titanium.

[0151] The first connection pad 310 can be disposed on the memory cell structure CS. The first connection pad 310 can be electrically connected to the through electrode 300A via a contact through electrode 300A. The second connection pad 320 can be disposed on the lower surface of the peripheral circuit structure PS. The second connection pad 320 can be disposed on the lower surface of the peripheral circuit substrate 200. The first connection pad 310 and the second connection pad 320 can be aligned in the first direction D1.

[0152] The through electrode 300A can be connected to the unit bonding pad 151. The unit bonding pad 151 can be connected to the peripheral bonding pad 251 via the HCB process. Therefore, the through electrode 300A can electrically connect the first connection pad 310 to the second connection pad 320 connected to the peripheral wiring structure.

[0153] refer to Figure 26 Semiconductor structures 13, 23, and 33 can each be stacked in a normal state N. That is, the front surface of the first semiconductor structure 13 can be bonded to the rear surface of the second semiconductor structure 23, and the front surface of the second semiconductor structure 23 can be bonded to the rear surface of the third semiconductor structure 33. Multiple semiconductor structures 13, 23, and 33 can be bonded to each other using the HCB method.

[0154] The first connection pad 310 of the first semiconductor structure 13 can be bonded to the second connection pad 320 of the second semiconductor structure 23, and the first bonding insulating layer 351 of the first semiconductor structure 13 can be bonded to the second bonding insulating layer 352 of the second semiconductor structure 23. The first bonding insulating layer 351 of the first semiconductor structure 13 can contact the second bonding insulating layer 352 of the second semiconductor structure 23.

[0155] The first connection pad 310 of the second semiconductor structure 23 can be bonded to the second connection pad 320 of the third semiconductor structure 33, and the first bonding insulating layer 351 of the second semiconductor structure 23 can be bonded to the second bonding insulating layer 352 of the third semiconductor structure 33. The first bonding insulating layer 351 of the second semiconductor structure 23 can contact the second bonding insulating layer 352 of the third semiconductor structure 33.

[0156] refer to Figure 27 The first semiconductor structure 13 can be placed in a normal state N, the second semiconductor structure 23 can be stacked on the first semiconductor structure 13 in a flipped state F, and the third semiconductor structure 33 can be stacked on the second semiconductor structure 23 in a normal state N. That is, the first semiconductor structure 13 and the second semiconductor structure 23 can be bonded from front to front, and the second semiconductor structure 23 and the third semiconductor structure 33 can be bonded from back to back.

[0157] For example, multiple semiconductor structures 13, 23, and 33 can be bonded to each other using the HCB method. The corresponding first connection pads 310 and corresponding first bonding insulating layers 351 of the first semiconductor structure 13 and the second semiconductor structure 23 can be bonded to each other. The corresponding second connection pads 320 and corresponding second bonding insulating layers 352 of the second semiconductor structure 23 and the third semiconductor structure 33 can be bonded to each other.

[0158] While this disclosure contains details of numerous specific embodiments, these should not be construed as limiting the scope of the claims, their equivalents, and the claims themselves. Certain features described in individual embodiments of this disclosure may also be implemented in combination within a single embodiment. Conversely, various features described in individual embodiments of this disclosure may also be implemented individually or in any suitable sub-combination across multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from that combination in some cases, and the combination may be for sub-combinations or variations thereof.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A plurality of semiconductor structures are stacked in a first direction perpendicular to the upper surface of a unit substrate, each of the plurality of semiconductor structures comprising (i) a memory cell structure having the unit substrate and (ii) a peripheral circuit structure overlapping the memory cell structure in the first direction; as well as A plurality of through electrodes, wherein the plurality of through electrodes extend in the first direction in each of the plurality of semiconductor structures. The memory cell structure includes: A plurality of memory cells are stacked on the cell substrate along the first direction and spaced apart, each of the plurality of memory cells including a semiconductor pattern having a channel region and a capacitor structure located on a first side of the semiconductor pattern; Multiple word lines extending in a second direction parallel to the upper surface of the cell substrate and surrounding the channel region; and Bit lines are located on a second side of the semiconductor pattern, which is opposite to the first side of the semiconductor pattern.

2. The semiconductor memory device according to claim 1, wherein, Each of the plurality of through electrodes extends in the first direction into the memory cell structure and the peripheral circuit structure.

3. The semiconductor memory device according to claim 1, wherein, Each of the plurality of through electrodes includes a first surface and a second surface opposite to the first surface, wherein the width of each of the plurality of through electrodes decreases from the first surface toward the second surface along the first direction.

4. The semiconductor memory device according to claim 3, wherein, The peripheral circuit structure includes a peripheral circuit substrate, at least one peripheral circuit device located on the peripheral circuit substrate, and a peripheral wiring structure electrically connected to the at least one peripheral circuit device. Each of the plurality of semiconductor structures further includes wiring structures stacked on the peripheral circuit structure, and The first surface of each of the plurality of through electrodes is coplanar with the interface between the peripheral wiring structure and the wiring structure.

5. The semiconductor memory device according to claim 3, wherein, Each of the plurality of semiconductor structures further includes wiring structures stacked on the peripheral circuit structure, and The interface between the peripheral circuit structure and the wiring structure is coplanar with the first surface of each through electrode.

6. The semiconductor memory device according to claim 5, wherein, The distance from the interface to the second surface of each of the plurality of through electrodes is greater than the distance from the interface to the lower surface of the peripheral circuit substrate.

7. The semiconductor memory device according to claim 3, wherein, Each of the plurality of semiconductor structures further includes: A first connection pad, the first connection pad overlapping with one of the plurality of through electrodes in the first direction; and The second connection pad is located on the second surface of the through electrode, and The width of the first connecting pad decreases as the distance from the first direction to the through electrode decreases.

8. The semiconductor memory device according to claim 7, wherein, Each of the plurality of semiconductor structures further includes a bonding insulating layer that overlaps with the second connection pad in the second direction.

9. The semiconductor memory device according to claim 7, wherein, The plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure stacked on the first semiconductor structure, and The first connection pad of the first semiconductor structure is in contact with the first connection pad of the second semiconductor structure.

10. The semiconductor memory device according to claim 7, wherein, The plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure stacked on the first semiconductor structure, and The first connection pad of the first semiconductor structure is in contact with the second connection pad of the second semiconductor structure.

11. The semiconductor memory device according to claim 1, wherein, The memory cell structure also includes a cell bonding insulating layer, and The peripheral circuit structure includes a peripheral bonding insulating layer bonded to the unit bonding insulating layer.

12. The semiconductor memory device according to claim 11, wherein, The memory cell structure further includes cell bonding pads that overlap with the cell bonding insulating layer in the second direction. The peripheral circuit structure further includes peripheral bonding pads that overlap with the peripheral bonding insulating layer in the second direction, and The unit bonding pad is in contact with the peripheral bonding pad.

13. A semiconductor memory device, the semiconductor memory device comprising: A first semiconductor structure, the first semiconductor structure including a first memory cell structure and a first peripheral circuit structure, the first peripheral circuit structure overlapping the first memory cell structure in a first direction; A second semiconductor structure is stacked on the first semiconductor structure in the first direction. The second semiconductor structure includes a second memory cell structure and a second peripheral circuit structure. The second peripheral circuit structure overlaps with the second memory cell structure in the first direction. A first through electrode extends in the first direction into the first memory cell structure and the first peripheral circuit structure; as well as The second through electrode extends into the second memory cell structure and the second peripheral circuit structure in the first direction and is aligned with the first through electrode in the first direction. Each memory cell structure in the first memory cell structure and the second memory cell structure includes: A plurality of memory cells are stacked in the first direction and spaced apart from each other. Each memory cell includes a semiconductor pattern, the semiconductor pattern including a channel region, a first source / drain region and a second source / drain region located on opposite sides of the channel region, and a capacitor structure connected to the first source / drain region. Multiple word lines extending in a second direction intersecting the first direction, wherein the multiple word lines are stacked and spaced apart from each other in the first direction, and wherein the multiple word lines surround the channel region of each of the plurality of memory cells; and Bit lines that extend in the first direction and connect to the second source / drain region.

14. The semiconductor memory device according to claim 13, wherein, The first semiconductor structure further includes: a first wiring structure located on a first surface of the first through electrode, a first front-side connection pad located on the first wiring structure, and a first back-side connection pad located on a second surface of the first through electrode. The second semiconductor structure further includes: a second wiring structure located on the first surface of the second through electrode, a second front-side connection pad located on the second wiring structure, and a second back-side connection pad located on the second surface of the second through electrode. Wherein, the width of the first front-side connecting pad decreases as the distance along the first direction to the first wiring structure decreases, and The width of the second front connecting pad decreases as the distance from the first direction to the second wiring structure decreases.

15. The semiconductor memory device according to claim 14, wherein, The first semiconductor structure further includes a bonding insulating layer that overlaps with the first front-side connection pad in the second direction. The second semiconductor structure further includes a front-side bonding insulating layer that overlaps with the second front-side connection pad in the second direction. Wherein, the front bonding insulating layer is located on the bonding insulating layer, and The second front-side connection pad is located on the first front-side connection pad.

16. The semiconductor memory device of claim 14, wherein, The first semiconductor structure further includes a bonding insulating layer that overlaps with the first back-side connection pad in the second direction. The second semiconductor structure further includes a front-side bonding insulating layer that overlaps with the second front-side connection pad in the second direction. Wherein, the front bonding insulating layer is located on the bonding insulating layer, and The second front-side connection pad is located on the first back-side connection pad.

17. The semiconductor memory device of claim 14, wherein, The width of each of the first and second through electrodes decreases in the direction from the first surface toward the second surface.

18. The semiconductor memory device according to claim 17, wherein, The first through electrode overlaps with both the first memory cell structure and the first peripheral circuit structure in the second direction. The second through electrode overlaps with both the second memory cell structure and the second peripheral circuit structure in the second direction.

19. The semiconductor memory device according to claim 13, wherein, Each of the first through electrode and the second through electrode includes a conductive film and an insulating film disposed on the side surface of the conductive film.

20. A semiconductor package, the semiconductor package comprising: Packaging substrate; A semiconductor memory device, the semiconductor memory device comprising a plurality of semiconductor structures stacked on the packaging substrate in a first direction perpendicular to the upper surface of the packaging substrate; as well as Multiple through electrodes, the multiple through electrodes being electrically connected to the multiple semiconductor structures. Each of the plurality of semiconductor structures includes: A memory cell structure, the memory cell structure including a cell substrate; Peripheral circuit structure, wherein the peripheral circuit structure overlaps with the memory cell structure in the first direction; and A wiring structure electrically connected to both the memory cell structure and the peripheral circuit structure. The memory cell structure includes: A plurality of memory cells are spaced apart from each other in the first direction. Each memory cell includes a semiconductor pattern, the semiconductor pattern including a channel region, a first source / drain region and a second source / drain region disposed on opposite sides of the channel region, and a capacitor structure connected to the first source / drain region. Multiple character lines extending in a second direction intersecting the first direction and spaced apart from each other in the first direction, wherein the multiple character lines surround the channel region; and Bit lines that extend in the first direction and connect to the second source / drain region.

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