Semiconductor device

Abstract

A semiconductor device includes: bit lines disposed on a substrate and extending along a first horizontal direction; an active pattern extending along a vertical direction on each bit line and including a first end facing the bit line and a second end opposite to the first end; a unit capacitor disposed on the second end of the active pattern; and an anti-oxidation film pattern disposed between the first end of the active pattern and each bit line and extending along the first horizontal direction on the top surface of each bit line, wherein the anti-oxidation film pattern comprises an oxide semiconductor containing indium and a first dopant, and the first dopant comprises at least one of magnesium (Mg), tantalum (Ta), fluorine (F), or nitrogen (N).

Description

Cross-reference to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0036216, filed with the Korean Intellectual Property Office on March 20, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device comprising a vertical channel transistor. Background Technology

[0003] As semiconductor device dimensions shrink, so too do dynamic random access memory (DRAM) devices. In DRAM devices with a single transistor and single capacitor (1T-1C) structure (i.e., one capacitor connected to one transistor), a problem arises: leakage current through the channel region gradually increases as the device shrinks. To reduce leakage current, a vertical channel transistor using oxide semiconductor material as the channel layer has been proposed. Summary of the Invention

[0004] The present invention provides a semiconductor device with excellent electrical performance.

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising: bit lines disposed on a substrate and extending along a first horizontal direction; an active pattern extending along a vertical direction on each bit line and including a first end facing the bit line and a second end opposite to the first end; a unit capacitor disposed on the second end of the active pattern; and an anti-oxidation film pattern disposed between the first end of the active pattern and each bit line, and extending along the first horizontal direction on the top surface of each bit line, wherein the anti-oxidation film pattern comprises an oxide semiconductor containing indium and a first dopant, and the first dopant comprises at least one selected from magnesium (Mg), tantalum (Ta), fluorine (F), or nitrogen (N).

[0006] According to one aspect of the present invention, a semiconductor device is provided, comprising: a plurality of bit lines disposed on a substrate, extending parallel to each other and along a first horizontal direction; a plurality of anti-oxidation film patterns disposed on the plurality of bit lines, extending parallel to each other and along the first horizontal direction; a plurality of molded structures disposed on the plurality of anti-oxidation film patterns and extending along a second horizontal direction; a plurality of active patterns including a first end and a second end opposite to the first end, the first end being disposed on a sidewall of each of the plurality of molded structures and facing each of the anti-oxidation film patterns; and a plurality of unit capacitors, respectively disposed on the second ends of the plurality of active patterns, wherein the constituent material of the anti-oxidation film patterns is of chemical formula [Inx Ga y Zn z O 1.5 ] 1-u X u This indicates that, where 0.9 ≤ x ≤ 1, 0 ≤ y ≤ 0.1, 0 ≤ z ≤ 0.1, x + y + z = 1, and X can be at least one of Mg, Ta, F, or N, and 0 <u≤0.1。

[0007] According to one aspect of the present invention, a semiconductor device is provided, comprising: a substrate; peripheral circuitry disposed on the substrate; bit lines disposed on the substrate at a vertical height higher than the peripheral circuitry and extending along a first horizontal direction; an active pattern extending along a vertical direction on each bit line, and including a first end facing the bit line and a second end opposite to the first end; a unit capacitor disposed on the second end of the active pattern; and an anti-oxidation film pattern disposed between the first end of the active pattern and each bit line, and extending along the first horizontal direction on the top surface of each bit line, wherein the constituent material of the anti-oxidation film pattern is of the chemical formula [In x Ga y Zn z O 1.5 ] 1-u X u This indicates that, where 0.9≤x≤1, 0≤y≤0.1, 0≤z≤0.1, x+y+z=1, and X can be at least one of Mg, Ta, F, or N, and 0 <u≤0.1。

[0008] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a bit line extending along a first horizontal direction on a substrate; forming an anti-oxidation film pattern extending along the first horizontal direction on the bit line; forming a molding structure extending along a second horizontal direction on the anti-oxidation film pattern; forming an active pattern on the sidewall of each molding structure in the molding structure; and forming a unit capacitor on the top surface of the active pattern, wherein the anti-oxidation film pattern comprises an oxide semiconductor containing indium and a first dopant, and the first dopant comprises at least one selected from magnesium (Mg), tantalum (Ta), fluorine (F), or nitrogen (N).

[0009] In the embodiments, the constituent material of the antioxidant film pattern is composed of chemical formula [In x Ga y Zn z O 1.5 ] 1-u X u This indicates that, where 0.9≤x≤1, 0≤y≤0.1, 0≤z≤0.1, x+y+z=1, and X can be at least one of Mg, Ta, F, or N, and 0 <u≤0.1。

[0010] In an embodiment, the antioxidant film pattern also includes oxygen vacancies, and the oxygen vacancy content can be 1 to 19 atomic percentages relative to the total atomic content of the components constituting the antioxidant film pattern.

[0011] In an embodiment, the active pattern may include: a vertical extension extending vertically on the sidewall of the molded structure; and a horizontal extension connected to the bottom of the vertical extension and extending in a first horizontal direction.

[0012] In an embodiment, when forming an active pattern, the active pattern can be formed on the portion of the anti-oxidation film pattern that is not covered by the molding structure, and the top surface of each bit line in the bit line may not be exposed to the process atmosphere used to form the active pattern.

[0013] In an embodiment, the method may further include: forming a gate insulating layer on the sidewall of the active pattern; and forming word lines on the gate insulating layer facing the sidewall of the active pattern.

[0014] In this embodiment, the formation of the antioxidant film pattern can be performed using a physical vapor deposition (PVD) process.

[0015] In an embodiment, the formation of the anti-oxidation film pattern can be performed by a sputtering process using a sputtering target comprising indium oxide or indium gallium zinc oxide.

[0016] In one embodiment, a first dopant may be included in the sputtering target when forming the antioxidant film pattern.

[0017] In an embodiment, a carrier gas including a first dopant may be used when forming an antioxidant film pattern. Attached Figure Description

[0018] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is a schematic perspective view of a semiconductor device according to an embodiment;

[0020] Figure 2 yes Figure 1 An enlarged layout diagram of a portion of the cell array region;

[0021] Figure 3 It is along Figure 2 A cross-sectional view taken by line A1-A1' in the diagram;

[0022] Figure 4 It is along Figure 2 A cross-sectional view taken by line A2-A2' in the diagram;

[0023] Figure 5 yes Figure 3 A magnified view of part of EN1;

[0024] Figure 6 yes Figure 3 A magnified view of part of EN2;

[0025] Figure 7 This is a ternary diagram showing the composition of the antioxidant film pattern according to an embodiment;

[0026] Figure 8 and Figure 9 This shows a cross-sectional view of a semiconductor device according to an embodiment;

[0027] Figure 10 yes Figure 9 A magnified view of part of EN2;

[0028] Figure 11 This shows a cross-sectional view of a semiconductor device according to an embodiment;

[0029] Figure 12 yes Figure 11 A magnified view of part of EN2;

[0030] Figure 13 This shows a cross-sectional view of a semiconductor device according to an embodiment;

[0031] Figure 14 This shows a cross-sectional view of a semiconductor device according to an embodiment;

[0032] Figure 15 A cross-sectional view of a semiconductor device according to an embodiment is shown; and

[0033] Figure 16 , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B and Figure 24C This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0034] Figure 1 This is a schematic perspective view of a semiconductor device 100 according to an embodiment. Figure 2 yes Figure 1 An enlarged layout diagram of a portion of the cell array region MCA in the diagram. Figure 3 It is along Figure 2 The cross-sectional view taken by line A1-A1' in the diagram. Figure 4 It is along Figure 2 The cross-sectional view taken from line A2-A2' in the diagram. Figure 5 yes Figure 3 An enlarged view of part of EN1. Figure 6 yes Figure 3 A magnified view of part of EN2.

[0035] Reference Figures 1 to 6 The semiconductor device 100 may include a peripheral circuit region PCA and a cell array region MCA arranged at a vertical height higher than the peripheral circuit region PCA.

[0036] In some embodiments, the cell array region (MCA) can be a memory cell region of a dynamic random access memory (DRAM) device, while the peripheral circuit region (PCA) can be the core region or peripheral circuit region of the DRAM device. For example, the PCA may include a peripheral circuit transistor (PTR) for sending signals and / or power to the memory cell array included in the MCA. In embodiments, the PTR may be configured with various circuits, such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, data input / output circuits, etc.

[0037] In the cell array region MCA, multiple word lines WL extending along the first horizontal direction X and multiple bit lines BL extending along the second horizontal direction Y can be arranged. Multiple cell transistors CTR can be arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. Multiple cell capacitors CAP can be arranged on the multiple cell transistors CTR respectively.

[0038] Multiple word lines WL may include first word lines WL1 and second word lines WL2 alternately arranged in the second horizontal direction Y, and multiple unit transistors CTR may include first unit transistors CTR1 and second unit transistors CTR2 alternately arranged in the second horizontal direction Y. First unit transistors CTR1 may be arranged adjacent to first word lines WL1, and second unit transistors CTR2 may be arranged adjacent to second word lines WL2. First unit transistors CTR1 and second unit transistors CTR2 may have a structure that is mirror-symmetrical to each other. For example, first unit transistors CTR1 and second unit transistors CTR2 may have a structure that is mirror-symmetrical with respect to a center line extending along the first horizontal direction X between first unit transistors CTR1 and second unit transistors CTR2.

[0039] Although not shown, an edge region may be arranged around the cell array region MCA. The edge region may be a region with components electrically connected to each word line in the word line WL and / or to each bit line in the bit line BL, and may also be a region with electrically connected components for realizing the electrical connection between the cell array region MCA and the peripheral circuit region PCA.

[0040] In the following text, such as Figure 3 and Figure 4 As shown, the case where the cell array region MCA is arranged at a higher vertical height than the peripheral circuit region PCA will be described (e.g., when the cell array region MCA is arranged on top of the peripheral circuit region PCA). However, the semiconductor device 100 can be inverted such that the cell array region MCA is located at a lower vertical height than the peripheral circuit region PCA. In this case, the term "top surface" or "bottom surface" of the component described below should be understood to refer to the "bottom surface" or "top surface" of the component, respectively. Components described as "above" or "below" should be understood to be "below" or "above" in any component, respectively. Components described as "located at a higher vertical height" should be understood to be "located at a lower vertical height".

[0041] In some embodiments, substrate 110 may include silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, substrate 110 may include conductive regions, such as doped wells or doped structures.

[0042] In the peripheral circuit region PCA, an active region AC can be defined in the substrate 110, and a peripheral circuit transistor PTR can be disposed on the active region AC of the substrate 110. The peripheral circuit transistor PTR may include a gate electrode PTG and a gate insulating layer PTI. Source / drain regions may be disposed on both sides of the gate electrode PTG and on the top of the substrate 110.

[0043] The peripheral circuit wiring structure 120 can be disposed on the substrate 110. The peripheral circuit wiring structure 120 may include peripheral circuit wiring 122, peripheral circuit contacts 124, and peripheral circuit insulating layer 126. The peripheral circuit wiring 122 and peripheral circuit contacts 124 may be electrically connected to the peripheral circuit transistor PTR and / or the substrate 110, and the peripheral circuit insulating layer 126 may cover the peripheral circuit transistor PTR, peripheral circuit wiring 122, and peripheral circuit contacts 124 on the substrate 110. The peripheral circuit insulating layer 126 may include an oxide film, a nitride film, a low-k dielectric film, or a combination thereof, and may be formed in a stacked structure of multiple insulating layers.

[0044] The cell array region MCA can be arranged on the peripheral circuit wiring structure 120. Within the cell array region MCA, multiple bit lines BL, multiple cell transistors CTR, and multiple cell capacitors CAP can be arranged sequentially along the vertical direction Z. For example, multiple bit lines BL can be arranged on the peripheral circuit wiring structure 120, multiple cell transistors CTR can be arranged on multiple bit lines BL, and multiple cell capacitors CAP can be arranged on multiple cell transistors CTR. In an embodiment, the bit lines BL can be arranged closer to the top surface of the substrate 110 than the cell transistors CTR or cell capacitors CAP. Accordingly, the vertical distance between the bit lines BL and the peripheral circuit transistors PTR can be smaller than the vertical distance between the cell capacitors CAP and the peripheral circuit transistors PTR.

[0045] In an embodiment, multiple bit lines BL may extend along a second horizontal direction Y. The bit lines BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, or combinations thereof. A first insulating layer 132 may be disposed between the multiple bit lines BL. The first insulating layer 132 may fill the space between the multiple bit lines BL and may have multiple line pattern shapes extending along the second horizontal direction Y between the multiple bit lines BL.

[0046] In this embodiment, the bit line contact BLC can be disposed between the bottom surface of the bit line BL and the peripheral circuit line 122. The bit line BL can be electrically connected to the peripheral circuit transistor PTR through the bit line contact BLC.

[0047] In one embodiment, multiple antioxidant film patterns AL can be disposed on the top surfaces of multiple bit lines BL. The multiple antioxidant film patterns AL respectively cover the top surfaces of the multiple bit lines BL and can extend along a second horizontal direction Y. In another embodiment, each antioxidant film pattern AL can cover the entire top surface BL_u of the corresponding bit line BL. A first portion of the antioxidant film pattern AL can be disposed between the top surface BL_u of the bit line BL and the unit transistor CTR, and a second portion of the antioxidant film pattern AL can be disposed between the top surface BL_u of the bit line BL and the molding structure 140.

[0048] In an embodiment, the anti-oxidation film pattern AL may include an indium-rich oxide semiconductor. Here, an indium-rich oxide semiconductor may refer to an oxide with a relatively high indium content. In an embodiment, the anti-oxidation film pattern AL may include a semiconductor composed of the chemical formula In... x Ga y Zn z O 1.5 The oxide semiconductor is represented by (0.9≤x≤1, 0≤y≤0.1, 0≤z≤0.1, and x+y+z=1).

[0049] Figure 7 This is a ternary diagram showing the composition of the antioxidant film pattern AL according to an embodiment. (e.g.) Figure 7 As shown, the anti-oxidation film pattern AL can include an indium-rich oxide semiconductor falling within the content range C_EX, such as an oxide semiconductor including indium, gallium, and zinc as cations. For example, the content range C_EX can refer to a triangle defined by points A, B, and C, and each of points A, B, and C can represent the relative content of the three cations (indium, gallium, and zinc) included in the oxide. Point A can indicate a composition where indium content is 100% among the three cations, i.e., indium oxide (InO). 1.5 Point B indicates the component among the three cations that corresponds to 90% indium and 10% gallium, namely, indium gallium oxide (In). 0.9 Ga 0.1 O 1.5 Point C indicates the component among the three cations that corresponds to 90% indium and 10% zinc, namely, indium zinc oxide (In). 0.9 Zn 0.1 O 1.5 ).

[0050] In an embodiment, the anti-oxidation film pattern AL may include an indium-rich oxide semiconductor having a composition at any point within the content range C_EX, and based on the total number of atoms of indium, gallium and zinc, indium may be included in a ratio of 90 to 100 atomic percent, gallium may be included in a ratio of 0 to 10 atomic percent, and zinc may be included in a ratio of 0 to 10 atomic percent.

[0051] In an embodiment, the anti-oxidation film pattern AL may further include a first dopant added to the indium-rich oxide semiconductor. In an embodiment, the first dopant may include at least one of magnesium (Mg), tantalum (Ta), fluorine (F) or nitrogen (N). The first dopant may be included in the indium-rich oxide semiconductor at a predetermined concentration, and the indium-rich oxide semiconductor has a composition at any point within the content range C_EX.

[0052] In an embodiment, the anti-oxidation film pattern AL may have a composition including the first dopant with a content greater than 0 and less than or equal to 10 atomic percent (at%), with an oxide represented by the chemical formula In x Ga y Zn z O 1.5 (0.9≤x≤1, 0≤y≤0.1, 0≤z≤0.1, and x+y+z=1) as the starting composition. In an embodiment, the anti-oxidation film pattern AL is represented by the chemical formula [In x Ga y Zn z O 1.5 1-u X u , wherein 0.9≤x≤1, 0≤y≤0.1, 0≤z≤0.1, x+y+z=1, X may be at least one of Mg, Ta, F or N, and 0<u≤0.1.

[0053] In some embodiments, the anti-oxidation film pattern AL may substantially not include gallium atoms and zinc atoms, and the anti-oxidation film pattern AL may include indium oxide added with the first dopant. The anti-oxidation film pattern AL may include an indium-based oxide represented by the chemical formula [In x O y 1-u X u (0.38≤x≤0.42, 0.58≤y≤0.62, X is at least one of Mg, Ta, F or N, and 0<u≤0.1). In some embodiments, the anti-oxidation film pattern AL may include indium oxynitride (In x O y N z ).

[0054] ​​In an embodiment, the anti-oxidation film pattern AL may include oxygen vacancies. In other words, the anti-oxidation film pattern AL comprises an indium-rich oxide semiconductor having a composition at any point within the content range C_EX, and some oxygen atoms included in the indium-rich oxide semiconductor may be replaced by oxygen vacancies. In some examples, relative to [In... x Ga y Zn z O 1.5 ] 1-u X u The oxygen vacancy content can be from 1 to 19 atomic percentages.

[0055] In an embodiment, the sidewalls of the anti-oxidation film pattern AL can be aligned with the sidewalls of the bit line BL, and the sidewalls of the anti-oxidation film pattern AL can contact the first insulating layer 132. The bit line BL can have a first width w1 in the first horizontal direction X, and the portion of the anti-oxidation film pattern AL disposed on each bit line BL can have a second width w2 in the first horizontal direction X. In an embodiment, the second width w2 can be substantially the same as the first width w1. In an embodiment, the anti-oxidation film pattern AL can have a thickness of 1 angstrom to 50 angstroms in the vertical direction Z.

[0056] In an embodiment, a bit line material layer (BLM) can be formed first (see...). Figure 17A An antioxidant film layer ALM is formed on the bit line material layer BLM (see [link]). Figure 17A Then, a mask pattern is used to pattern the anti-oxidation film material layer ALM and the bit line material layer BLM to form the anti-oxidation film pattern AL and the bit line BL. Here, the characteristic that the second width w2 of the anti-oxidation film pattern AL is substantially the same as the first width w1 of the bit line BL can mean that, taking into account the errors or tolerances that may occur when the bit line BL and the anti-oxidation film pattern AL are manufactured in the same process, one value falls within the range of 90% to 110% of the other value.

[0057] Multiple molded structures 140 and multiple unit transistors CTRs can be arranged on an anti-oxidation film pattern AL and a first insulating layer 132. For example, each of the multiple molded structures 140 can extend along a first horizontal direction X, and the multiple unit transistors CTRs can be arranged on two sidewalls of each molded structure 140.

[0058] Each of the plurality of molding structures 140 may include a first molding layer 142, a second molding layer 144, and a third molding layer 146 arranged along the vertical direction Z. For example, the first molding layer 142 may be disposed on the anti-oxidation film pattern AL and the first insulating layer 132, the second molding layer 144 may be disposed on the first molding layer 142, and the third molding layer 146 may be disposed on the second molding layer 144.

[0059] In embodiments, each of the first to third molding layers 142, 144, and 146 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material. In some embodiments, the first molding layer 142 and the third molding layer 146 may include silicon nitride or silicon oxynitride, and the second molding layer 144 may include silicon oxide or a low-k dielectric material.

[0060] In an embodiment, the unit transistor CTR may include an active pattern AP, a gate insulating layer 150, and a word line WL arranged sequentially on the sidewall of the molded structure 140.

[0061] In an embodiment, the active pattern AP may include a vertical extension AP_V extending in the vertical direction Z on the sidewall of the molding structure 140 and a horizontal extension AP_P extending in the second horizontal direction Y on the bottom of the vertical extension AP_V. The horizontal extension AP_P may be directly disposed on the top surface of the antioxidant film pattern AL.

[0062] In an embodiment, the active pattern AP disposed between two adjacent molding structures 140 may have a U-shaped vertical cross-section. For example, the vertical extension AP_V disposed on the sidewall of the first molding structure of the two adjacent molding structures 140 may be the channel region of the first unit transistor CTR1, and the vertical extension AP_V disposed on the sidewall of the second molding structure of the two adjacent molding structures 140 may be the channel region of the second unit transistor CTR2.

[0063] In embodiments, the active pattern AP may include at least one of the following: zinc tin oxide (ZnO) x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) xIn y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O) or zirconium zinc tin oxide (Zr) x Zn y Sn z O).

[0064] In an embodiment, a gate insulating layer 150 may be disposed on an active pattern AP. The gate insulating layer 150 may be disposed on the sidewalls of the vertical extension AP_V and the top surface of the horizontal extension AP_P, and the gate insulating layer 150 disposed between two adjacent molding structures 140 may have a U-shaped vertical cross-section. The gate insulating layer 150 may include a first portion 150_V and a second portion 150_P, the first portion 150_V being disposed on the sidewalls of the vertical extension AP_V and the second portion 150_P being disposed on the top surface of the horizontal extension AP_P.

[0065] In some embodiments, the gate insulating layer 150 may include at least one selected from high-k dielectric materials or ferroelectric materials with a dielectric constant higher than that of silicon oxide. In some embodiments, the gate insulating layer 150 may be formed from at least one selected from: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanium oxide (PbZrTiO), strontium tantalum bismuth oxide (StTaBiO), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).

[0066] Word lines WL can be disposed on the sidewalls of the gate insulating layer 150. In some embodiments, word lines WL may comprise Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or combinations thereof. For example, two word lines WL may be spaced apart from each other between two adjacent molding structures 140 and extend along a first horizontal direction X. For example, a first word line WL1 and a second word line WL2 may be spaced apart from each other between two adjacent molding structures 140. The bottom surface of the word lines WL may be disposed on a second portion 150_P of the gate insulating layer 150.

[0067] The insulating pad 162 and the buried insulating layer 164 can be disposed between the first word line WL1 and the second word line WL2. The insulating pad 162 can be conformally disposed on the upper sidewall of the first portion 150_V of the gate insulating layer 150, the upper surface of its second portion 150_P, and the sidewalls and top surface of the first word line WL1 and the second word line WL2. The buried insulating layer 164 can be disposed on the insulating pad 162.

[0068] Multiple bonding pads 170 can be disposed on multiple unit transistors (CTRs). An upper insulating layer 172 can be disposed on the sidewalls of the multiple bonding pads 170 and the top surface of the molded structure 140. Unit capacitors (CAPs) can be disposed on the bonding pads 170. The multiple bonding pads 170 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or combinations thereof. The unit capacitors (CAPs) may have a metal-insulator-metal type capacitor structure. For example, each unit capacitor in the unit capacitor (CAP) may include a first electrode, a second electrode, and a capacitor dielectric layer disposed between the first electrode and the second electrode.

[0069] In reference Figures 1 to 7 In the semiconductor device 100 described according to an embodiment, since the anti-oxidation film pattern AL covers the entire top surface BL_u of the bit line BL and extends along the second horizontal direction Y, oxidation of the bit line BL that would have occurred during the formation of the active pattern AP if the anti-oxidation film pattern AL were not present can be prevented and / or reduced. Furthermore, the presence of oxygen vacancies in the anti-oxidation film pattern AL can reduce the contact resistance between the bit line BL and the active pattern AP.

[0070] Electrical performance tests have been performed on the semiconductor device according to an embodiment of the present invention. The structure of the semiconductor device according to the embodiment further includes indium oxide (In₂O₃). 0.42 O 0.58 The embodiment features an anti-oxidation film pattern, while the structure of the semiconductor device according to the comparative example does not include an anti-oxidation film pattern. In both the embodiment and the comparative example, indium gallium zinc oxide containing indium, gallium, and zinc in a ratio of 1:1:1 is used as the semiconductor pattern or channel region.

[0071] The semiconductor device according to the embodiment has a cell operating current that is 2.6 times higher than that of the comparative example, indicating that the carrier mobility in the channel of the embodiment is increased by two times or more. Furthermore, the contact resistance of the semiconductor device according to the embodiment is reduced by 26% compared to the comparative example, and / or the channel resistance is reduced by 71% compared to the comparative example. This indicates that inserting an antioxidant film pattern in the embodiment can reduce the total resistance between the bit lines and the active pattern, and increase the overall operating current of the semiconductor device. Therefore, the semiconductor device 100 can have excellent electrical performance.

[0072] Figure 8 and Figure 9 This is a cross-sectional view of the semiconductor device 100A according to an embodiment. Figure 10 yes Figure 9 A magnified view of part of EN2.

[0073] Reference Figures 8 to 10 Multiple bit lines BL can have a first width w1, and the anti-oxidation film pattern AL can have a second width w2, wherein the second width w2 can be greater than the first width w1. A first insulating layer 132 can be disposed between the multiple bit lines BL, and the anti-oxidation film pattern AL can be disposed on the top surface BL_u of each bit line BL and the top surface of the first insulating layer 132. A second insulating layer 134 can be formed on the top surface of the first insulating layer 132 and can be disposed on the sidewall of the anti-oxidation film pattern AL. In an embodiment, multiple bit lines BL can be formed, a first insulating layer 132 can be formed to fill the space between the multiple bit lines BL, and an anti-oxidation film pattern AL can be formed on the bit lines BL and the first insulating layer 132.

[0074] In the embodiment, since the width of the anti-oxidation film pattern AL is greater than the width of the bit line BL, and is formed to cover the entire top surface BL_u of the bit line BL, oxidation of the bit line BL during the formation of the active pattern AP can be prevented and / or reduced.

[0075] Figure 11 This is a cross-sectional view of the semiconductor device 100B according to an embodiment. Figure 12 yes Figure 11 A magnified view of part of EN2.

[0076] Reference Figure 11 and Figure 12 The anti-oxidation film pattern AL can cover multiple bit lines BL and the top surface of the first insulating layer 132, and can extend along the first horizontal direction X and the second horizontal direction Y. In an embodiment, since the anti-oxidation film pattern AL is formed to cover the entire top surface BL_u of the bit lines BL, oxidation of the bit lines BL can be prevented and / or reduced during the formation of the active pattern AP.

[0077] Figure 13 This is a cross-sectional view of the semiconductor device 100C according to an embodiment.

[0078] Reference Figure 13 The active pattern AP may include a first portion AP1 and a second portion AP2. The first portion AP1 may include a vertical extension AP1_V and a horizontal extension AP1_P, and may have a U-shaped vertical cross-section. The second portion AP2 may be disposed between the bottom surface of the horizontal extension AP1_P and the anti-oxidation film pattern AL. The second portion AP2 may have a strip-shaped vertical cross-section.

[0079] In an embodiment, the first portion AP1 may include an oxide semiconductor with a composition different from that of the second portion AP2. In an embodiment, the first portion AP1 and the second portion AP2 may include at least one of the following: zinc tin oxide (ZnO). x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) xO), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O) or zirconium zinc tin oxide (Zr) x Zn y Sn z O).

[0080] Figure 14 This is a cross-sectional view of a semiconductor device 100D according to an embodiment.

[0081] Reference Figure 14 The active pattern AP may include a first portion AP1 and a second portion AP2. The first portion AP1 may include a vertical extension AP1_V and a horizontal extension AP1_P, and may have a U-shaped vertical cross-section. The second portion AP2 may be disposed between the bottom surface of the horizontal extension AP1_P and the anti-oxidation film pattern AL, and between the sidewall of the vertical extension AP1_V and the sidewall of the molding structure 140. The second portion AP2 may also have a U-shaped vertical cross-section. In an embodiment, the first portion AP1 may include an oxide semiconductor with a composition different from that of the second portion AP2.

[0082] Figure 15 This is a cross-sectional view of the semiconductor device 100E according to an embodiment.

[0083] Reference Figure 15The top surface of the active patterned AP can be disposed at a height lower than the top surface of the gate insulating layer 150. In an embodiment, the bonding pad opening 170H can be formed by removing a portion of the molding structure 140, and the bonding pad 170 can be disposed within the bonding pad opening 170H.

[0084] In one embodiment, a portion of the bonding pad 170 may extend to a height lower than the top surface of the active pattern AP, and the bonding pad 170 may contact the top surface of the active pattern AP and the upper side of the sidewall of the active pattern AP. Because a portion of the bonding pad 170 extends to a height lower than the top surface of the active pattern AP, a relatively large contact area between the bonding pad 170 and the active pattern AP can be ensured.

[0085] Figure 16 , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B and Figure 24C This is a schematic diagram illustrating a method for manufacturing a semiconductor device 100 according to an embodiment. Specifically, Figure 16 , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A and Figure 24A It is along Figure 2 The cross-sectional view taken by line A1-A1' in the diagram. Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B and Figure 24B It is along Figure 2 The cross-sectional view taken by line A2-A2' in the diagram, and Figure 17C , Figure 18C , Figure 19C , Figure 23C and Figure 24CIs it separate from Figure 17A , Figure 18A , Figure 19A , Figure 23A and Figure 24A The plan view corresponding to the cross-sectional view.

[0086] Reference Figure 16 An active region AC can be formed on the substrate 110, and a peripheral circuit transistor PTR can be formed on the active region AC. For example, the peripheral circuit transistor PTR may include a gate electrode PTG and a gate insulating layer PTI.

[0087] Subsequently, peripheral circuit wiring 122 and peripheral circuit contacts 124 electrically connected to the substrate 110 and the peripheral circuit transistor PTR can be formed, and a peripheral circuit insulating layer 126 covering the peripheral circuit wiring 122 and peripheral circuit contacts 124 can be formed over the substrate 110. The peripheral circuit insulating layer 126 can be formed using an oxide film, a nitride film, a low-k dielectric film, or a combination thereof.

[0088] The peripheral circuit contact 124 formed at the uppermost part of the peripheral circuit contact 124 can be referred to as the bit line contact BLC. The top surface of the bit line contact BLC can be arranged on the same plane as the uppermost surface of the peripheral circuit insulating layer 126.

[0089] Reference Figures 17A to 17C Bit line material layer BLM and anti-oxidation film material layer ALM can be sequentially formed on the peripheral circuit insulating layer 126.

[0090] In this embodiment, the bit line material layer (BLM) can be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The bit line material layer (BLM) may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polycrystalline silicon, or combinations thereof.

[0091] In embodiments, the anti-oxidation film material layer ALM may include an indium-rich oxide semiconductor. For example, an indium-rich oxide semiconductor may refer to an oxide with a relatively high indium content, and may include an oxide semiconductor containing indium, gallium, and / or zinc as cations. For example, an indium-rich oxide semiconductor may contain indium as the main constituent cation, and may selectively contain gallium and zinc. In embodiments, the anti-oxidation film material layer ALM may include materials with the chemical formula In… x Ga y Zn z O 1.5 The oxide is represented by (0.9≤x≤1, 0≤y≤0.1, 0≤z≤0.1, and x+y+z=1).

[0092] In embodiments, in the process of forming the anti-oxidation film material layer ALM, the indium-rich oxide semiconductor may include a first dopant. In embodiments, the first dopant may include at least one of magnesium (Mg), tantalum (Ta), fluorine (F) or nitrogen (N). In some embodiments, in addition to the first dopant, the indium-rich oxide semiconductor may further include a second dopant in the process of forming the anti-oxidation film material layer ALM. The second dopant may be a material that is the same as or different from the first dopant, and may include at least one of magnesium (Mg), tantalum (Ta), fluorine (F) or nitrogen (N).

[0093] In embodiments, the anti-oxidation film material layer ALM may be formed using a physical vapor deposition (PVD) process. In embodiments, the anti-oxidation film material layer ALM may be formed by a PVD process, such as a sputtering process using a sputtering target, where the sputtering target includes an oxide having components required to be included in the anti-oxidation film material layer ALM.

[0094] In embodiments, the anti-oxidation film material layer ALM may be formed by a PVD process, such as a sputtering process using a sputtering target, where the sputtering target includes an oxide represented by the chemical formula [In x Ga y Zn z O 1.5 1-u X u (0.9≤x≤1, 0≤y≤0.1, 0≤z≤0.1, x+y+z=1, X is at least one of Mg, Ta, F or N, and 0<u≤0.1).

[0095] In an exemplary embodiment, the anti-oxidation film material layer ALM may be formed by co-sputtering using two or more sputtering targets. For example, the anti-oxidation film material layer ALM may be formed using a first sputtering target including an oxide having an InGaO composition, a second sputtering target including an oxide having an InZnO composition, and a third sputtering target including a source material of the first dopant.

[0096] In embodiments, some elements of the first dopant (e.g., nitrogen or fluorine) may be included in the sputtering target and provided in the process of forming the anti-oxidation film material layer ALM. In some other embodiments, in the process of forming the anti-oxidation film material layer ALM, some elements of the first dopant (e.g., nitrogen or fluorine) may be provided as part of a carrier gas or part of a reaction gas.

[0097] ​In an embodiment, the antioxidant film material layer ALM can be formed using a sputtering target comprising the oxide InGaZnO, in which case a carrier gas comprising at least one of nitrogen or ammonia can be supplied to the process chamber. Accordingly, the antioxidant film material layer ALM may include a nitrogen-containing first dopant.

[0098] In an embodiment, the antioxidant film material layer ALM can be formed by a plasma-enhanced atomic layer deposition (PE-ALD) process using a plasma source including at least one of nitrogen or ammonia.

[0099] Reference Figures 18A to 18C A mask pattern can be formed on the antioxidant film material layer ALM, and multiple antioxidant film patterns AL and multiple bit lines BL can be formed by patterning the antioxidant film material layer ALM and the bit line material layer BLM using this mask pattern. The multiple antioxidant film patterns AL and multiple bit lines BL can have the shape of line patterns extending along a second horizontal direction Y. The two sidewalls of the multiple antioxidant film patterns AL can be aligned with the two sidewalls of the multiple bit lines BL.

[0100] Subsequently, a first insulating layer 132 can be formed to fill the spaces between multiple antioxidant film patterns AL and multiple bit lines BL. The first insulating layer 132 can contact two sidewalls of the multiple antioxidant film patterns AL and two sidewalls of the multiple bit lines BL, and the top surface of the first insulating layer 132 can be coplanar with the top surface of the multiple antioxidant film patterns AL.

[0101] Reference Figures 19A to 19C Multiple molded structures 140 extending along a first horizontal direction X can be formed on the top surface of multiple antioxidant film patterns AL and the first insulating layer 132. Each of the multiple molded structures 140 may include a first molded layer 142, a second molded layer 144, and a third molded layer 146 sequentially stacked on the top surface of the multiple antioxidant film patterns AL and the first insulating layer 132.

[0102] In embodiments, each of the first to third molding layers 142, 144, and 146 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material. In some embodiments, the first molding layer 142 and the third molding layer 146 may include silicon nitride or silicon oxynitride, and the second molding layer 144 may include silicon oxide or a low-k dielectric material.

[0103] Reference Figure 20A and Figure 20BAn active material layer APL can be formed on the sidewalls and top surface of the molded structure 140. The active material layer APL can be conformally arranged on the sidewalls and top surface of the molded structure 140, as well as on the top surface of the plurality of anti-oxidation film patterns AL and the first insulating layer 132.

[0104] In the embodiments, the active material layer APL may include at least one of the following: zinc tin oxide (ZnO) x Sn y O), Indium zinc oxide (In) x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O) or zirconium zinc tin oxide (Zr) x Zn y Sn z O).

[0105] In the embodiments, the active material layer APL can be formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or plasma-enhanced atomic layer deposition (PEALD).

[0106] In an embodiment, the active material layer APL can be formed by sequentially performing a deposition cycle that supplies a precursor comprising cations of an oxide semiconductor constituting the active material layer APL. For example, to form a substrate containing indium gallium zinc oxide (In... x Ga y Zn z The active material layer APL (O) can sequentially execute indium precursor supply sub-cycles, gallium precursor supply sub-cycles, and zinc precursor supply sub-cycles, and each sub-cycle can be executed multiple times. In the embodiments, O2, O3, H2O, H2O2, oxygen plasma, etc., can be used as reactants or oxygen sources in the process of forming the active material layer APL.

[0107] In this embodiment, during the process of forming the active material layer APL, the entire top surface of the bit line BL can be covered by an anti-oxidation film pattern AL, and therefore is not exposed to oxidizing atmospheres caused by O2, O3, H2O, H2O2, oxygen plasma, etc. Thus, undesirable oxidation or damage to the bit line BL that would occur without the anti-oxidation film pattern AL can be prevented.

[0108] Subsequently, a protective layer 210 can be formed on the active material layer APL, with a thickness sufficient to fill the space between the molded structures 140. In an embodiment, the protective layer 210 may include a spin-coated hard mask or a spin-coated dielectric.

[0109] Reference Figure 21A and Figure 21B A mask pattern 220 extending along the second horizontal direction Y can be formed on the protective layer 210. Subsequently, a portion of the protective layer 210 and a portion of the active material layer APL can be removed by using the mask pattern 220 as an etching mask. Accordingly, the active material layer APL can extend along the second horizontal direction Y along the top surface and sidewalls of the molded structure 140.

[0110] Reference Figure 22A and Figure 22B The mask pattern 220 and the protective layer 210 can be removed. Afterward, an anisotropic etching process or a back-etching process can be performed on the portion of the active material layer APL arranged on the top surface of the molded structure 140.

[0111] In an embodiment, a portion of the active material layer APL disposed on the top surface of the molded structure 140 can be removed by an anisotropic etching process or an etch-back process, while the portions of the active material layer APL disposed on the sidewalls of the molded structure 140 and the portions of the active material layer APL disposed between two adjacent molded structures 140 are retained. The remaining active material layer APL after the anisotropic etching process or etch-back process is referred to as the active pattern AP. The top surface of the molded structure 140 (e.g., the top surface of the third molding layer 146) can be exposed again by anisotropic etching process or etch-back process. The top surface of the molded structure 140 (e.g., the top surface of the third molding layer 146) can be disposed at the same height as the top surface of the active pattern AP.

[0112] In one embodiment, an active pattern AP can be defined between two adjacent molded structures 140, and the active pattern AP can have a U-shaped vertical cross-section. In another embodiment, the bottom of the active pattern AP (e.g., the horizontal extension AP_P) (see...) Figure 5 It can be in contact with the antioxidant film pattern AL arranged at the bottom of the active pattern AP and between each bit line in the bit line BL, rather than directly with the bit line BL.

[0113] Subsequently, a gate insulating layer 150 and a word line material layer WLM can be sequentially formed on the molded structure 140 and the active pattern AP.

[0114] In one embodiment, the gate insulating layer 150 may be conformally formed on the top surface of the molded structure 140, the sidewalls of the active pattern AP, and the top surface of the first insulating layer 132. Subsequently, the word line material layer WLM may be conformally formed on the gate insulating layer 150.

[0115] Reference Figures 23A to 23C An anisotropic etching or recessing process can be performed on the word line material layer WLM so that the word line WL remains only between two adjacent molded structures 140 (e.g., only on the sidewall of the gate insulating layer 150).

[0116] In an embodiment, an anisotropic etching process or a recessed process can be performed on the upper side of the word line WL so that the top surface of the word line WL can be arranged at a lower height than the top surface of the active pattern AP and the gate insulating layer 150 and / or the top surface of the molding structure 140.

[0117] like Figure 23CAs shown, as a result of an anisotropic etching or recessing process, a first word line WL1 can be arranged on the sidewall of one of two adjacent molding structures 140, and a second word line WL2 can be arranged on the sidewall of the other molding structure 140. The top surface of the gate insulating layer 150 can be exposed between the first word line WL1 and the second word line WL2.

[0118] In an embodiment, the portion of the gate insulating layer 150 disposed between the first word line WL1 and the second word line WL2 may not be removed by anisotropic etching or recessing processes, and the gate insulating layer 150 may have a U-shaped vertical cross-section.

[0119] In some embodiments, an anisotropic etching process or a recessing process may be performed until the portion of the gate insulating layer 150 disposed between the first word line WL1 and the second word line WL2 is further removed, and in this case, the portion of the gate insulating layer 150 disposed below the first word line WL1 has an L-shape and may be physically spaced apart from the portion of the gate insulating layer 150 disposed below the second word line WL2.

[0120] Subsequently, an insulating liner 162 and a buried insulating layer 164 may be sequentially formed on the top surface of the molded structure 140. In an example embodiment, the insulating liner 162 may be formed to have a relatively small thickness, and the buried insulating layer 164 may be formed to have a sufficiently large thickness to fill the space between two adjacent molded structures 140.

[0121] Subsequently, portions of the insulating pad 162 disposed on the top surface of the molded structure 140, portions of the buried insulating layer 164 disposed on the top surface of the molded structure 140, and portions of the gate insulating layer 150 disposed on the top surface of the molded structure 140 can be removed to re-expose the top surface of the molded structure 140 and the top surface of the active pattern AP.

[0122] The process of removing a portion of the insulating pad 162 and a portion of the gate insulating layer 150 can be a grinding or chemical mechanical polishing (CMP) process, and after the grinding or CMP process, the upper surface of the buried insulating layer 164, the top surface of the gate insulating layer 150, the top surface of the active pattern AP, and the top surface of the molded structure 140 can be arranged on the same plane.

[0123] Reference Figures 24A to 24C A bonding pad 170 and an upper insulating layer 172 covering the sidewalls of the bonding pad 170 can be formed on the molding structure 140. The bottom of each bonding pad in the bonding pad 170 can be formed to have a bottom surface in contact with the top surface of the active pattern AP.

[0124] In some embodiments, a portion of each molding structure in the molding structure 140 may be removed to form a bonding pad recess 170H that exposes a portion of the top surface and sidewalls of the active pattern AP (see [link]). Figure 15 Furthermore, a bonding pad 170 can be formed in the bonding pad recess 170H, contacting a portion of the top surface and sidewall of the active pattern AP. In this case, a reference can be formed. Figure 15 The semiconductor device described is 100E.

[0125] Then, a unit capacitor CAP can be formed on each of the bonding pads 170.

[0126] By performing the above process, the semiconductor device 100 can be completely formed.

[0127] According to an embodiment, the anti-oxidation film pattern AL can cover the top surface of the bit line BL and can prevent the metal material included in the bit line BL from being oxidized during the process of forming the active pattern AP including the oxide semiconductor. The semiconductor device 100 can have relatively low contact resistance and relatively high operating current. Therefore, the semiconductor device 100 can have excellent electrical performance.

[0128] In the above embodiments, reference is made to Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B and Figure 18C The text describes patterning bit lines BL and antioxidant film patterns AL in the same process. However, in other embodiments, a bit line material layer BLM can be formed first, a mask pattern can be formed on the bit line material layer BLM, the bit line material layer BLM can be patterned to form bit lines BL, and a first insulating layer 132 can be formed to fill the spaces between the multiple bit lines BL. Subsequently, an antioxidant layer ALM can be formed to cover the bit lines BL, a mask pattern can be formed on the antioxidant layer ALM, and the antioxidant layer ALM can be patterned to form the antioxidant film pattern AL. In these embodiments, the second width w2 of the antioxidant film pattern AL can be different from the first width w1 of each bit line in the bit lines BL. For example, the second width w2 of the antioxidant film pattern AL can be greater than the first width w1 of each bit line BL, and the top surface of the bit lines BL can be completely covered during the formation of the active pattern AP. In this case, a reference can be manufactured. Figures 8 to 10 The semiconductor device described is 100A.

[0129] In some other embodiments, a first insulating layer 132 is first formed to fill the space between the multiple bit lines BL, and an antioxidant layer ALM is formed to cover the bit lines BL and the first insulating layer 132. The patterning process for the antioxidant layer ALM can then be omitted. The antioxidant layer ALM can be retained as a continuous layer extending horizontally at locations where it vertically overlaps with the multiple bit lines BL. In this case, a reference can be fabricated. Figure 11 and Figure 12 The semiconductor device 100B is described.

[0130] In the above embodiments, reference is made to Figure 20A and Figure 20B The description states that the active material layer APL is formed as a single layer. However, in other embodiments, a first active material layer and a second active material layer with different compositions can be formed sequentially, and in this case, a reference layer can be fabricated. Figure 13 The semiconductor device described 100C or referenced Figure 14 The semiconductor device 100D is described.

[0131] According to the present invention, an anti-oxidation film pattern can cover the top surface of the bit line and prevent the metal material included in the bit line from being oxidized during the process of forming the active pattern including the oxide semiconductor. Due to the structure of the anti-oxidation film pattern arranged between the active pattern and each bit line in the bit line, the semiconductor device can have relatively low contact resistance and relatively high operating current. Therefore, the semiconductor device can have excellent electrical performance.

[0132] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Bit lines are arranged on the substrate and extend along a first horizontal direction; An active pattern extends vertically along each of the bit lines and includes a first end facing the bit line and a second end opposite to the first end; A unit capacitor is disposed on the second end of the active pattern; as well as An antioxidant film pattern is disposed between the first end of the active pattern and each bit line in the bit lines, and extends along the first horizontal direction on the top surface of each bit line in the bit lines, wherein: The antioxidant film pattern comprises an oxide semiconductor containing indium and a first dopant, and The first dopant includes at least one of magnesium (Mg), tantalum (Ta), fluorine (F), or nitrogen (N).

2. The semiconductor device according to claim 1, wherein: The oxide semiconductor included in the antioxidant film pattern includes indium gallium zinc oxide. The oxide semiconductor contains a higher indium content than the oxide semiconductor contains gallium content, and The oxide semiconductor contains a higher content of indium than the oxide semiconductor contains of zinc.

3. The semiconductor device according to claim 1, wherein, The antioxidant film pattern is composed of materials with the chemical formula [In x Ga y Zn z O 1.5 ] 1-u X u This indicates that, where 0.9 ≤ x ≤ 1, 0 ≤ y ≤ 0.1, 0 ≤ z ≤ 0.1, x + y + z = 1, X is at least one of Mg, Ta, F or N, and 0 <u≤0.1。 4. The semiconductor device according to claim 1, wherein, The oxide semiconductor included in the antioxidant film pattern includes indium oxide.

5. The semiconductor device according to claim 1, wherein, The oxide semiconductor included in the antioxidant film pattern includes In. x O y , where 0.38≤x≤0.42 and 0.58≤y≤0.

62.

6. The semiconductor device according to claim 1, wherein: The antioxidant film pattern also includes oxygen vacancies, and The oxygen vacancy content is 1 to 19 atomic percentages relative to the total atomic content of the components constituting the antioxidant film pattern.

7. The semiconductor device according to claim 1, wherein: The antioxidant film pattern covers the entire top surface of the bit line, and The width of the antioxidant film pattern in the second horizontal direction intersecting the first horizontal direction is greater than or equal to the width of each bit line in the bit line in the second horizontal direction.

8. The semiconductor device according to claim 1, further comprising: A molded structure is disposed on the first sidewall of the active pattern and extends along a second horizontal direction intersecting the first horizontal direction; The character lines are arranged on the second sidewall of the active pattern opposite to the first sidewall and extend along the second horizontal direction; as well as A gate insulating layer is disposed between the second sidewall of the active pattern and the word line.

9. The semiconductor device according to claim 8, wherein: The first portion of the antioxidant film pattern is disposed between the bottom surface of the first end of the active pattern and the top surface of each bit line in the bit lines, and The second portion of the antioxidant film pattern is arranged between the bottom surface of each molded structure and the top surface of each bit line in the bit line.

10. The semiconductor device according to claim 9, wherein, The active pattern includes: A vertical extension extends along the vertical direction on the sidewall of each of the molded structures in the molded structure; and A horizontal extension connects to the bottom of the vertical extension and extends along the first horizontal direction. The first portion of the antioxidant film pattern is covered by the bottom surface of the vertical extension and the bottom surface of the horizontal extension.

11. The semiconductor device according to claim 1, further comprising: Peripheral circuitry is arranged on the substrate, wherein, The bit line is positioned at a vertical height higher than the peripheral circuitry relative to the top surface of the substrate. Each bit line in the bit lines is electrically connected to the peripheral circuit through a bit line contact portion.

12. A semiconductor device, comprising: Multiple bit lines are arranged on the substrate, extending parallel to each other and along a first horizontal direction; Multiple antioxidant film patterns are arranged on the multiple bit lines, extending parallel to each other and extending along the first horizontal direction; Multiple molded structures are arranged on the multiple antioxidant film patterns and extend along a second horizontal direction intersecting the first horizontal direction; Multiple active patterns, including a first end and a second end opposite to the first end, the first end being disposed on the sidewall of each of the multiple molded structures and facing each of the antioxidant film patterns; as well as Multiple unit capacitors are respectively arranged on the second terminals of the multiple active patterns, wherein, The antioxidant film pattern is composed of materials with the chemical formula [In x Ga y Zn z O 1.5 ] 1-u X u This indicates that, where 0.9 ≤ x ≤ 1, 0 ≤ y ≤ 0.1, 0 ≤ z ≤ 0.1, x + y + z = 1, X is at least one of Mg, Ta, F or N, and 0 <u≤0.1。 13. The semiconductor device according to claim 12, wherein, Each of the plurality of active patterns includes: A vertical extension extends vertically along the sidewall of each molded structure in the molded structure, and A horizontal extension is connected to the bottom of the vertical extension and extends along the first horizontal direction.

14. The semiconductor device according to claim 13, further comprising: Character lines are arranged on the sidewall of the vertical extension and the top surface of the horizontal extension of each of the plurality of active patterns; as well as A gate insulating layer is located between the sidewall of the vertical extension of each of the plurality of active patterns and the word line, and between the top surface of the horizontal extension and each of the word lines.

15. The semiconductor device according to claim 13, wherein: The first portion of the antioxidant film pattern is disposed between the bottom surface of the horizontal extension of each of the plurality of active patterns and the top surface of each of the plurality of bit lines, and The second portion of the antioxidant film pattern is disposed between the bottom surface of each molded structure and the top surface of each of the plurality of bit lines in the molded structure.

16. The semiconductor device according to claim 12, wherein: The antioxidant film pattern covers the entire top surface of each of the plurality of bit lines, and The width of the antioxidant film pattern in the second horizontal direction is greater than or equal to the width of each of the plurality of bit lines in the second horizontal direction.

17. The semiconductor device of claim 12, further comprising: Peripheral circuitry is arranged on the substrate, wherein, Relative to the top surface of the substrate, the plurality of bit lines are arranged at a vertical height higher than the peripheral circuitry, and Each of the multiple bit lines is electrically connected to the peripheral circuit through a bit line contact portion.

18. A semiconductor device, comprising: Substrate; Peripheral circuitry is arranged on the substrate; Bit lines are arranged on the substrate at a vertical height higher than the peripheral circuit and extend along a first horizontal direction; An active pattern extends vertically along each of the bit lines and includes a first end facing the bit line and a second end opposite to the first end; A unit capacitor is disposed on the second end of the active pattern; as well as An antioxidant film pattern is disposed between the first end of the active pattern and each bit line in the bit lines, and extends along the first horizontal direction on the top surface of each bit line in the bit lines, wherein, The antioxidant film pattern is composed of materials with the chemical formula [In x Ga y Zn z O 1.5 ] 1-u X u This indicates that, where 0.9 ≤ x ≤ 1, 0 ≤ y ≤ 0.1, 0 ≤ z ≤ 0.1, x + y + z = 1, X is at least one of Mg, Ta, F or N, and 0 <u≤0.1。 19. The semiconductor device of claim 18, further comprising: A molded structure is disposed on the first sidewall of the active pattern and extends along a second horizontal direction intersecting the first horizontal direction; The character lines are arranged on the second sidewall of the active pattern opposite to the first sidewall and extend along the second horizontal direction; as well as A gate insulating layer is disposed between the second sidewall of the active pattern and the word line, wherein, The first portion of the antioxidant film pattern is disposed between the bottom surface of the first end of the active pattern and the top surface of each bit line in the bit lines, and The second portion of the antioxidant film pattern is arranged between the bottom surface of each molded structure and the top surface of each bit line in the bit line.

20. The semiconductor device according to claim 19, wherein, The active pattern includes: A vertical extension extends along the vertical direction on the sidewall of each molded structure in the molded structure. A horizontal extension connects to the bottom of the vertical extension and extends along the first horizontal direction. The first portion of the antioxidant film pattern is covered by the bottom surface of the vertical extension and the bottom surface of the horizontal extension.

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