Semiconductor memory device and method of manufacturing semiconductor memory device

Abstract

A semiconductor memory device includes a cell region and a peripheral circuit region provided over the cell region. The cell region includes a stack structure including gate electrodes stacked in a first direction, and a channel structure provided in the stack structure and extending in the first direction. The peripheral circuit region includes a well structure including a first surface and a second surface facing each other, the well structure including a first well region and a second well region provided on the first surface, a first transistor provided in the first well region, and a second transistor provided in the second well region, an isolation structure isolating the first well region and the second well region from each other, a stop structure provided on the isolation structure, and a through structure partially extending into the stop structure in the first direction.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0035405, filed on March 19, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor memory devices and methods for manufacturing semiconductor memory devices. Background Technology

[0003] To meet consumer demand for high-performance and low-cost semiconductor memory devices, it is necessary to increase the integration density of these devices. The integration density is a crucial factor determining the price of semiconductor memory devices. Therefore, semiconductor memory devices with increased integration density are in particular in demand.

[0004] The integration density of two-dimensional (2D) or planar semiconductor memory devices is largely determined by the area occupied by a single memory cell, and is therefore greatly affected by the level of fine patterning technology. However, the formation of fine patterns requires extremely expensive equipment. Therefore, although the integration density of 2D semiconductor memory devices is improving, this improvement is limited. Consequently, 3D semiconductor memory devices incorporating memory cells arranged in three dimensions have been proposed. Summary of the Invention

[0005] One aspect is to provide a semiconductor memory device with improved electrical performance and reliability.

[0006] On the other hand, it provides a method for manufacturing semiconductor memory devices with improved electrical performance and reliability.

[0007] According to one or more embodiments, a semiconductor memory device is provided, comprising: a cell region; and a peripheral circuit region disposed on the cell region. The cell region includes: a stacked structure including a plurality of gate electrodes stacked in a first direction; and a channel structure disposed in the stacked structure and extending in the first direction. The peripheral circuit region includes: a well structure including a first surface and a second surface facing each other, wherein the well structure includes a first well region and a second well region disposed on the first surface, wherein a first transistor is disposed in the first well region and a second transistor is disposed in the second well region; an isolation structure isolating the first well region and the second well region from each other; a stop structure disposed on the isolation structure; and a through structure extending at least partially into the stop structure in the first direction.

[0008] According to another aspect of one or more embodiments, a semiconductor memory device is provided, comprising: a cell region; and a peripheral circuit region disposed on the cell region. The cell region includes: a stacked structure including a plurality of gate electrodes stacked in a first direction; and a channel structure disposed in the stacked structure and extending in the first direction. The peripheral circuit region includes: a well structure including a first well region of a first conductivity type and a second well region of a second conductivity type different from the first conductivity type; an isolation structure disposed between the first well region and the second well region and including an insulating material; a first transistor disposed on the first well region; a second transistor disposed on the second well region; a first interlayer insulating film disposed on the well structure, wherein a first wiring structure is disposed in the first interlayer insulating film; a second interlayer insulating film disposed between the well structure and the cell region, wherein a second wiring structure is disposed in the second interlayer insulating film; a conductive structure disposed on the isolation structure; a first via disposed in the first interlayer insulating film and extending in the first direction and contacting the conductive structure; and a second via disposed in the second interlayer insulating film and extending in the first direction and contacting the conductive structure.

[0009] According to another aspect of one or more embodiments, a semiconductor memory device is provided, comprising: a cell region; and a peripheral circuit region disposed on the cell region. The cell region includes: a stacked structure including a plurality of gate electrodes stacked in a first direction; a channel structure disposed in the stacked structure and extending in the first direction; a bit line extending in a second direction different from the first direction and connected to the channel structure; and a first bonding pad disposed on the bit line. The peripheral circuit region includes: a well structure comprising a first well region of a first conductivity type and a second well region of a second conductivity type different from the first conductivity type; an isolation structure isolating the first well region from the second well region; a PMOS transistor disposed on the first well region; an NMOS transistor disposed on the second well region; a first interlayer insulating film disposed on the well structure; a second interlayer insulating film disposed between the well structure and the cell region; a second bonding pad disposed on the second interlayer insulating film and bonded to the first bonding pad; a bias structure comprising a first bias region connected to the first well region and a second bias region connected to the second well region; a conductive structure disposed on the isolation structure; a first via disposed in the first interlayer insulating film and extending in a first direction and contacting the conductive structure; and a second via disposed in the second interlayer insulating film and extending in a first direction and contacting the conductive structure.

[0010] According to another aspect of one or more embodiments, a method of manufacturing a semiconductor memory device is provided, comprising: providing a substrate including a first surface and a second surface facing each other; forming a first well region and a second well region and an isolation structure on the first surface of the substrate, such that the isolation structure is disposed between the first well region and the second well region, the first well region and the second well region comprising different conductive materials; forming a conductive material layer on the first well region, the second well region and the isolation structure; performing an etching process on the conductive material layer to form a first gate structure on the first well region, a second gate structure on the second well region, and a conductive structure on the isolation structure; forming a first via, the first via extending at least partially into the conductive structure; and forming a second via extending through the isolation structure and at least partially into the conductive structure. Attached Figure Description

[0011] The above and other contents will become clearer by referring to the detailed description of the embodiments in the accompanying drawings, wherein:

[0012] Figure 1 This is a schematic block diagram illustrating a semiconductor memory device according to some embodiments;

[0013] Figure 2 It is a schematic circuit diagram used to illustrate a semiconductor memory device according to some embodiments;

[0014] Figure 3 This is an example plan view used to illustrate a semiconductor memory device according to some embodiments;

[0015] Figure 4 It is along Figure 3 A cross-sectional view taken from line AA;

[0016] Figure 5 yes Figure 4 A magnified view of region P1;

[0017] Figure 6 yes Figure 4 A magnified view of region P2;

[0018] Figure 7 yes Figure 4 A magnified view of region P3;

[0019] Figures 8 to 12 Is with Figure 5 The enlarged view shown corresponds to a diagram used to illustrate a semiconductor memory device according to some embodiments;

[0020] Figure 13 yes Figure 5 A magnified view of region Q1;

[0021] Figure 14and Figure 15 Is with Figure 13 The enlarged view shown corresponds to a diagram used to illustrate a semiconductor memory device according to some embodiments;

[0022] Figures 16 to 18 This is an example layout diagram used to illustrate a semiconductor memory device according to some embodiments;

[0023] Figure 19 and Figure 20 This shows a cross-sectional view of a semiconductor memory device according to some embodiments;

[0024] Figure 21 and Figure 22 This shows a cross-sectional view of a semiconductor memory device according to some embodiments;

[0025] Figures 23 to 25 This illustrates an example layout diagram of a semiconductor memory device according to some embodiments;

[0026] Figures 26 to 35 This is a diagram of an intermediate structure corresponding to an intermediate step in a method of manufacturing a semiconductor memory device according to some embodiments;

[0027] Figure 36 This is an example block diagram used to illustrate an electronic system according to some embodiments;

[0028] Figure 37 This is an example perspective view showing an electronic system according to some embodiments. Detailed Implementation

[0029] Figure 1 This is a schematic block diagram illustrating a semiconductor memory device according to some embodiments. As used in this specification, expressions in the form of "at least one of A, B, or C" include "A only", "B only", "C only", "A and B", "A and C", "B and C", and "A, B, and C" within its scope.

[0030] Reference Figure 1 According to some embodiments, the semiconductor device 10 may include a memory cell array 20 and peripheral circuitry 30. In some embodiments, the peripheral circuitry 30 may include a row decoder 33, a page buffer 35, and control logic 37.

[0031] The memory cell array 20 may include multiple memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include multiple memory cells. The memory cell array 20 may be connected to peripheral circuitry 30 via bit line BL, word line WL, at least one serial select line SSL, and at least one ground select line GSL. Specifically, memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 via word line WL, serial select line SSL, and ground select line GSL. In addition, memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 via bit line BL.

[0032] Peripheral circuitry 30 can receive address ADDR, command CMD, and control signal CTRL from external devices outside semiconductor device 10, and can send data DATA to and receive data DATA from external devices outside semiconductor device 10. Although not shown, peripheral circuitry 30 may also include various sub-circuits, such as input / output circuitry, voltage generation circuitry for generating various voltages for the operation of semiconductor device 10, and error correction circuitry for correcting errors in data DATA read from memory cell array 20.

[0033] Control logic 37 can be connected to line decoder 33, page buffer 35, input / output circuitry, and voltage generation circuitry, etc. Control logic 37 can control the overall operation of semiconductor device 10. Control logic 37 can generate various internal control signals used in semiconductor device 10 in response to the control signal CTRL. For example, when performing memory operations such as programming or erasing operations, control logic 37 can adjust the voltage levels supplied to word line WL and bit line BL.

[0034] The row decoder 33 can select at least one memory block from a plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and can select at least one word line WL, at least one serial select line SSL, or at least one ground select line GSL of the selected at least one memory cell block BLK1 to BLKn. Furthermore, the row decoder 33 can send a voltage for performing memory operations to the word line WL of the selected at least one memory cell block BLK1 to BLKn.

[0035] Page buffer 35 can be connected to memory cell array 20 via bit line BL. Page buffer 35 can operate as a write driver or a sense amplifier. Specifically, when performing a programming operation, page buffer 35 operates as a write driver to apply a voltage to bit line BL based on the data DATA to be stored in memory cell array 20. When performing a read operation, page buffer 35 can operate as a sense amplifier to detect the data DATA stored in memory cell array 20.

[0036] Figure 2 This is a schematic circuit diagram used to illustrate a semiconductor memory device according to some embodiments.

[0037] Reference Figure 2 A memory cell array of a semiconductor memory device according to some embodiments (e.g., Figure 1 The memory cell array 20 in the memory cell array may include a common source line CSL, multiple bit lines BL and multiple cell strings CSTR.

[0038] A common source line (CSL) may extend in the second direction Y. In some embodiments, multiple common source lines (CSLs) may be arranged in a two-dimensional manner. For example, multiple common source lines (CSLs) may be spaced apart from each other, and each of the multiple common source lines (CSLs) may extend in the second direction Y. The same voltage may be applied to the common source line (CSL). In some embodiments, different voltages may be applied to the common source line (CSL) individually.

[0039] Multiple bit lines (BLs) can be arranged in a two-dimensional manner. For example, multiple bit lines (BLs) can be spaced apart from each other in a first direction (X) perpendicular to the second direction (Y), and each bit line in the multiple bit lines (BLs) can extend in the second direction (Y). Multiple cell strings (CSTRs) can be connected in parallel to each bit line (BL). The cell strings (CSTRs) can be connected to a common source line (CSL). That is, multiple cell strings (CSTRs) can be arranged between the bit line (BL) and the common source line (CSL).

[0040] Each cell string (CSTR) may include a ground select transistor (GST) connected to the common source line (CSL), a string select transistor (SST) connected to the bit line (BL), and a plurality of memory cell transistors (MCTs) disposed between the ground select transistor (GST) and the string select transistor (SST). Each memory cell transistor in the MCTs may include a data storage element. The ground select transistor (GST), the string select transistor (SST), and the memory cell transistors (MCTs) may be connected in series with each other.

[0041] The common source line CSL can be connected to the source of the ground select transistor GST. Furthermore, the ground select line GSL, multiple word lines WL1 to WLn, and the serial select line SSL can be positioned between the common source line CSL and the bit line BL. The ground select line GSL can be used as the gate electrode of the ground select transistor GST. The word lines WL1 to WLn can each be used as the gate electrodes of the memory cell transistor MCT. The serial select line SSL can be used as the gate electrode of the serial select transistor SST.

[0042] In some embodiments, the erase control transistor ECT can be disposed between the common source line CSL and the ground select transistor GST. The common source line CSL can be connected to the source of the erase control transistor ECT. Furthermore, the erase control line ECL can be disposed between the common source line CSL and the ground select line GSL. The erase control line ECL can serve as the gate electrode of the erase control transistor ECT. The erase control transistor ECT can generate gate-induced drain leakage (GIDL) to perform the erase operation of the memory cell array.

[0043] Figure 3 This is an example plan view used to illustrate a semiconductor memory device according to some embodiments. Figure 4 It is along Figure 3 The cross-sectional view taken from line AA. Figure 5 yes Figure 4 A magnified view of region P1. Figure 6 yes Figure 4 A magnified view of region P2. Figure 7 yes Figure 4 A magnified view of region P3.

[0044] Reference Figure 3 and Figure 4 According to some embodiments, a semiconductor memory device may include a memory cell region (CELL) and a peripheral circuit region (PERI).

[0045] The memory cell region CELL may include a cell substrate 102, a stacked structure SS, a channel structure CH, a word line cut structure WLC, a gate contact GC, a support pattern SP, an interlayer insulating film 142, a bit line 182, and a first bonding pad 190.

[0046] The cell substrate 102 may include a cell array region CA and an extended region EA.

[0047] A storage cell array that includes multiple storage cells (e.g., Figure 1 The memory cell array 20 can be disposed on the cell array region CA. For example, the stacked structure SS, the channel structure CH, the word line cut structure WLC, the gate contact GC, the support pattern SP, the cell interlayer insulating film 142, the bit line 182, and the first bonding pad 190 (described later) can be disposed on the cell array region CA. In the following description, the surface of the cell substrate 102 on which the memory cell array is disposed can be referred to as the front surface or front side of the cell substrate 102. Conversely, the surface of the cell substrate 102 opposite to the front surface of the cell substrate 102 can be referred to as the back surface, rear surface, back side, or rear side of the cell substrate 102.

[0048] The extended region EA can be positioned around the cell array region CA. The extended region EA can be adjacent to the cell array region CA in the first direction X. Although Figure 3 The diagram shows a single cell array region CA and an extended region EA, but multiple cell array regions CA and multiple extended regions EA can exist. Although Figure 3 The extended region EA is shown as being adjacent to the cell array region CA on one side of the cell array region CA, but in some embodiments, the extended region EA may be configured to surround the cell array region CA. For example, in some embodiments, such as Figure 3 As shown, the extended region EA can surround the cell array region CA on all sides of the cell array region CA.

[0049] The cell array region CA may be in which multiple channel structures, described later, are formed (e.g., Figure 4 The channel structure (CH) is located in the region. The extended region EA can be a region in which multiple gate contacts (GC), described later, are formed (see [link to relevant documentation]). Figure 4 The area is defined as follows: Multiple channel structures CH and multiple gate contacts GC can be disposed on the cell substrate 102.

[0050] The unit substrate 102 may include, for example, a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In some embodiments, the unit substrate 102 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some embodiments, the unit substrate 102 may contain impurities. For example, the unit substrate 102 may contain n-type impurities (e.g., phosphorus (P) and / or arsenic (As)).

[0051] In some embodiments, the cell substrate 102 may include a source layer. For example, the source layer of the cell substrate 102 may be disposed in the cell array region CA. In some embodiments, the source layer of the cell substrate 102 may be formed on the cell array region CA, and may not be formed on the extended region EA.

[0052] The source layer of the cell substrate 102 may include a conductive material, such as doped polysilicon or a metal. However, embodiments of this disclosure are not limited thereto. The source layer of the cell substrate 102 may be configured as a common source line of a semiconductor memory device (e.g., Figure 2 (Common source line CSL in the middle).

[0053] A stacked structure SS may be disposed on the front surface of the unit substrate 102. The stacked structure SS may include a plurality of gate electrodes 112 and a plurality of molded insulating films 110 stacked on the unit substrate 102. In some embodiments, the plurality of gate electrodes 112 may be interwoven with the plurality of molded insulating films 110, such as... Figure 4As shown. Each gate electrode 112 and each molded insulating film 110 may have a layered structure extending parallel to the front surface of the unit substrate 102. The gate electrodes 112 may be sequentially stacked on the unit substrate 102 to be spaced apart from each other via the molded insulating film 110.

[0054] In the following text, thickness and height can be based on a third direction Z. The third direction Z can be vertically intersecting the plane defined by the first direction X and the second direction Y. The third direction Z can be a direction perpendicular to the front surface of the unit substrate 102. The first direction X and the second direction Y can be parallel to the front surface of the unit substrate 102. As used herein, the third direction Z can be referred to as the vertical direction.

[0055] In some embodiments, the gate electrode 112 may include ground selection lines sequentially stacked on the cell substrate 102 (e.g., Figure 2 In the selection line GSL), word line (e.g., Figure 2 The word lines WL1 to WLn), erase control lines (e.g., Figure 2 The erase control line (ECL) and the serial select line (e.g., Figure 2 The string select line (SSL) in the middle. The ground select line (e.g., Figure 2 In the selection line GSL), word line (e.g., Figure 2 The word lines WL1 to WLn), erase control lines (e.g., Figure 2 The erase control line (ECL) and the serial select line (e.g., Figure 2 The number and arrangement of the String Select Lines (SSL) are merely examples and are not limited to those shown. In some embodiments, the Erase Control Line (ECL) may be omitted (see [link to ECR documentation]). Figure 2 In some embodiments, the gate electrode 112 may also include a dummy word line.

[0056] Each gate electrode 112 may include a conductive material, such as a metal (e.g., tungsten (W), cobalt (Co), nickel (Ni)) or a semiconductor material (e.g., silicon). However, embodiments of this disclosure are not limited thereto.

[0057] The molded insulating film 110 and the gate electrode 112 may be stacked alternately on top of each other. The molded insulating film 110 may include an insulating material, such as at least one of silicon oxide, silicon nitride, or silicon oxynitride. However, the embodiments disclosed herein are not limited thereto.

[0058] A channel structure CH can be disposed on the cell array region CA. Each of the plurality of channel structures CH can extend in the third direction Z to extend through the stacked structure SS. For example, the channel structure CH can be a cylindrical (e.g., cylindrical) structure having a third direction Z extension. Thus, the channel structure CH can intersect each gate electrode 112. In some embodiments, the width of the channel structure CH can decrease as the channel structure CH extends toward the cell substrate 102.

[0059] like Figure 6 As shown, the channel structure CH may include a channel pattern 130 and a channel pattern insulating film 132.

[0060] The channel pattern 130 may extend in a third direction Z to extend through the stacked structure SS. In embodiments, the channel pattern 130 may have, for example, a cup shape. In some embodiments, the channel pattern 130 may have various shapes, such as cylindrical, square, solid column, etc.

[0061] The channel pattern 130 may include, for example, semiconductor materials such as monocrystalline silicon, polycrystalline silicon, organic semiconductors and / or carbon nanostructures.

[0062] A channel pattern insulating film 132 may be inserted between the channel pattern 130 and each gate electrode 112. For example, the channel pattern insulating film 132 may extend along at least a portion of the outer surface of the first channel pattern 130.

[0063] In some embodiments, the channel patterned insulating film 132 may include multiple films. For example, such as Figure 6 As shown, the channel pattern insulating film 132 may include a first insulating film 132a, a second insulating film 132b and a third insulating film 132c sequentially stacked on the outer surface of the channel pattern 130.

[0064] In one embodiment, the first insulating film 132a may include an oxide, the second insulating film 132b may include a nitride, and the third insulating film 132c may include an oxide. In another embodiment, the first insulating film 132a may be a tunnel insulating film, the second insulating film 132b may be a charge storage film, and the third insulating film 132c may be a barrier insulating film.

[0065] The first insulating film 132a may include, for example, silicon oxide or a high-k material with a dielectric constant higher than that of silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)). The second insulating film 132b may include, for example, silicon nitride. The third insulating film 132c may include, for example, silicon oxide or a high-k material with a dielectric constant higher than that of silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)).

[0066] In some embodiments, the channel structure CH may further include a fill pattern 134. The fill pattern 134 may fill the interior of the cup-shaped channel pattern 130. The channel pattern 130 may surround the outer sidewall of the fill pattern 134. The fill pattern 134 may include an insulating material. For example, in an embodiment, the fill pattern 134 may include silicon oxide.

[0067] The source layer of the unit substrate 102 can be electrically connected to the channel pattern 130 of each channel structure CH. In some embodiments, a portion of the channel pattern 130 can be disposed in the source layer of the unit substrate 102. The lower surface 130ls of the channel pattern 130 can be disposed in the source layer of the unit substrate 102.

[0068] The channel pattern insulating film 132 may extend along a portion of the side surface of the channel pattern 130. In an embodiment, the channel pattern insulating film 132 may not cover the lower portion of the channel pattern 130. Figure 6 As shown, the channel pattern insulating film 132 may not cover the lower surface 130ls of the channel pattern 130 or a portion of the side surface of the channel pattern 130. The lower surface 130ls of the channel pattern 130 may be located at a vertical height lower than the vertical height of the lower surface 132ls of the channel pattern insulating film 132. The lower surface 130ls of the channel pattern 130 may contact the source layer of the cell substrate 102. A portion of the side surface of the channel pattern 130 may contact the source layer of the cell substrate 102.

[0069] For example, the lower surface 132ls of the channel pattern insulating film 132 may be flat. In some embodiments, for example, the lower surface 132ls of the channel pattern insulating film 132 may have steps. For example, the lower surface of the first insulating film 132a may be located at a vertical height lower than the vertical height of the lower surface of the second insulating film 132b, and the lower surface of the second insulating film 132b may be located at a vertical height lower than the vertical height of the lower surface of the third insulating film 132c.

[0070] In some embodiments, the channel structure CH may also include channel pads 136 (see...). Figure 4 The channel pad 136 may be electrically connected to the channel pattern 130. The channel pad 136 may include, for example, doped polysilicon.

[0071] In some embodiments, multiple channel structures CH can be arranged in a zigzag pattern or a honeycomb pattern. For example, as Figure 3As shown, multiple channel structures CH can be arranged alternately in a first direction X and a second direction Y, which are parallel to the upper surface of the cell substrate 102. The staggered arrangement of channel structures CH can further improve the integration density of semiconductor memory devices. The number and arrangement of channel structures CH are merely examples and are not limited to the examples shown.

[0072] Reference Figure 7 In some embodiments, the channel structure CH may include a first channel CHa and a second channel CHb connected to each other. For example, the channel structure CH can be formed by performing a process to form the first channel CHa and a process to form the second channel CHb. The first channel CHa may be the lower portion of the channel structure CH, and the second channel CHb may be the upper portion of the channel structure CH. At the boundary between the first channel CHa and the second channel CHb, the width of the first channel CHa may be greater than the width of the second channel CHb. The channel structure CH may have a curved portion at the boundary between the first channel CHa and the second channel CHb.

[0073] Word lines located near the boundary between the first channel CHa and the second channel CHb can be dummy word lines. For example, the boundary between the first channel CHa and the second channel CHb can lie between word line WLk (where k is a natural number less than n) and word line WL(k+1). In this respect, each of word line WLk (where k is a natural number less than n) and word line WL(k+1) can be a dummy word line. In this case, data may not be stored in the memory cells connected to the dummy word lines. In some embodiments, the number of pages corresponding to memory cells connected to dummy word lines may be less than the number of pages corresponding to memory cells connected to ordinary word lines. The voltage level applied to the dummy word lines may be different from the voltage level applied to the ordinary word lines.

[0074] Return to reference Figure 3 and Figure 4 The word line cut structure (WLC) can extend in a first direction X to cut the stacked structure SS on the cell array region CA and the extended region EA. Although not specifically shown, multiple word line cut structures (WLCs) can be spaced apart from each other in a second direction Y and can extend parallel to each other in the first direction X. The stacked structure SS can be divided by the word line cut structures (WLCs) into multiple memory cell blocks (e.g., ...). Figure 1 The memory cell blocks (BLK1 to BLKn) are portions thereof. For example, two adjacent word line cut structures (WLCs) may define a memory cell block between them. Multiple channel structures (CHs) may be provided in each memory cell block defined by the word line cut structures (WLCs). Although not specifically shown, the width of the word line cut structures (WLCs) may decrease as the word line cut structures (WLCs) extend toward the cell substrate 102 (e.g., in the third direction Z).

[0075] The word line cut structure (WLC) can extend in a first direction X to cut the source layer of the cell substrate 102. In an embodiment, the vertical height of the lower surface of the word line cut structure WLC can be lower than, for example, the vertical height of the upper surface of the source layer of the cell substrate 102. In some embodiments, the lower surface of the word line cut structure WLC can be substantially coplanar with the lower surface of the source layer of the cell substrate 102.

[0076] In some embodiments, the word line cut structure (WLC) may include an insulating material. For example, the word line cut structure (WLC) may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0077] Each of the plurality of gate contacts GC can be formed in a contact hole GCH corresponding to a gate contact GC. For example, the plurality of gate contacts GC can be formed in a plurality of contact holes GCH. Each gate contact GC may include an insulating pattern 161 and a conductive pattern 162. The conductive pattern 162 may fill at least a portion of the contact hole GCH. The conductive pattern 162 may contact the portion of the gate electrode 112 exposed through the contact hole GCH. The conductive pattern 162 may include a conductive material. The conductive pattern 162 may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), or alloys thereof.

[0078] The insulating pattern 161 may surround the side surface of the conductive pattern 162. The insulating pattern 161 may extend conformally along the sidewall of the conductive pattern 162. The insulating pattern 161 does not cover the portion of the gate electrode 112 exposed through the contact hole GCH. The insulating pattern 161 may include an insulating material. The insulating pattern 161 may include, for example, silicon oxide. However, embodiments of this disclosure are not limited thereto.

[0079] The support pattern SP can be formed in the extended region EA. The support pattern SP can be formed around the gate contact GC. The support pattern SP can be a cylindrical (e.g., cylindrical) structure extending in the third direction Z. The number and arrangement of the support patterns SP are merely examples and are not limited to, for example... Figure 3 The structure shown.

[0080] In some embodiments, the support pattern SP may include an insulating material, such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0081] In some embodiments, the support pattern SP may be formed at the same height as the channel structure CH. In this case, the support pattern SP may have the same structure as the channel structure CH and may include the same material as the channel structure CH.

[0082] Interlayer insulating film 142 may be disposed on the stacked structure SS. Interlayer insulating film 142 may be formed on the cell substrate 102 to cover the gate electrode 112 and the molded insulating film 110. Interlayer insulating film 142 may include at least one of, for example, silicon oxide, silicon oxynitride, or a low-k material with a dielectric constant lower than that of silicon oxide. However, embodiments of this disclosure are not limited thereto. Although not specifically shown, interlayer insulating film 142 may include multiple insulating layers, and the number of layers of interlayer insulating film 142 is not limited to, for example... Figure 4 The number of layers shown.

[0083] The interlayer insulating film 142 of the cell array region CA may include a first contact pattern 181, a first wire 182, and a second contact pattern 185.

[0084] A first contact pattern 181 may be formed on the channel structure CH. The first contact pattern 181 may connect the channel pad 136 to the first conductor 182. The first conductor 182 may be electrically connected to the channel structure CH via the first contact pattern 181.

[0085] The first conductor 182 can be disposed in the cell array region CA. The first conductor 182 can extend in the second direction Y. Although not shown, the first conductors 182 can be spaced apart from each other in the first direction X and can extend parallel to each other in the second direction Y. The first conductors 182 can be electrically connected to the channel structure CH arranged in the second direction Y. The first conductor 182 can be configured as a bit line BL (see...). Figure 2 ).

[0086] The second contact pattern 185 can be formed on the stacked structure SS of the cell array region CA. The second contact pattern 185 can be disposed between the first conductor 182 and the first bonding pad 190. The second contact pattern 185 can connect the first conductor 182 and the first bonding pad 190 to each other.

[0087] Each of the first contact pattern 181, the first wire 182, and the second contact pattern 185 may include a conductive material, such as at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), or alloys thereof. However, embodiments of this disclosure are not limited thereto.

[0088] The interlayer insulating film 142 of the extended region EA may also include a third contact pattern 183, a second conductor 184, and a fourth contact pattern 186.

[0089] The third contact pattern 183 can be formed on the gate contact GC. The third contact pattern 183 can connect the gate contact GC and the second wire 184 to each other.

[0090] The second conductor 184 may extend in the second direction Y and within the extended region EA. Although not shown, the second conductors 184 may be spaced apart from each other in the first direction X and may extend parallel to each other in the second direction Y. The second conductors 184 may be electrically connected to the gate contact GC arranged in the second direction Y.

[0091] A fourth contact pattern 186 may be formed on the stacked structure SS of the extended region EA. The fourth contact pattern 186 may be disposed between the second conductor 184 and the first bonding pad 190. The fourth contact pattern 186 may connect the second conductor 184 and the first bonding pad 190 to each other.

[0092] Each of the third contact pattern 183, the second wire 184, and the fourth contact pattern 186 may include a conductive material, such as at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), or alloys thereof. However, embodiments of this disclosure are not limited thereto.

[0093] A first bonding insulating layer 146 may be disposed on the interlayer insulating film 142. A first bonding pad 190 may be disposed in the first bonding insulating layer 146. The first bonding pad 190 may be electrically connected to the first contact pattern 181, the first wire 182, and the second contact pattern 185. The first bonding pad 190 may include a conductive material. In an embodiment, the first bonding pad 190 may include, for example, copper (Cu).

[0094] The peripheral circuit region PERI may include a first interlayer insulating film 242, a third interlayer insulating film 240, a first via 284, a first well region 1aW, a second well region 1bW, a first transistor PT1, a second transistor PT2, an isolation structure IST, a stop structure CS, a protection region GB, a second interlayer insulating film 244, a second via 282A, a first contact portion 282B, a first wiring structure 280, and a second bonding pad 290.

[0095] The second bonding insulating layer 246 may be disposed on the storage cell region CELL. The second bonding pad 290 may be disposed in the second bonding insulating layer 246.

[0096] The second bonding insulating layer 246 may be disposed beneath the second interlayer insulating film 244. The second bonding pad 290 may be disposed within the second bonding insulating layer 246. The second bonding pad 290 may be electrically connected to the first wiring structure 280. The second bonding pad 290 may include a conductive material. The second bonding pad 290 may include, for example, copper (Cu).

[0097] The second bonding pad 290 may contact the first bonding pad 190. The second bonding insulating layer 246 may contact the first bonding insulating layer 146. The first bonding insulating layer 146 may be formed between the first bonding pads 190, and the second bonding insulating layer 246 may be formed between the second bonding pads 290. Each of the first bonding insulating layer 146 and the second bonding insulating layer 246 may include silicon carbonitride. The second bonding insulating layer 246 may contact the first bonding insulating layer 146.

[0098] Because the first bonding pad 190 and the second bonding pad 290 are in contact with each other, the memory cell region CELL and the peripheral circuit region PERI can be bonded to each other. Because the first bonding pad 190 and the second bonding pad 290 are bonded to each other, the memory cell region CELL can be electrically connected to the peripheral circuit region PERI.

[0099] The first interlayer insulating film 242 may be disposed on the memory cell region CELL. The first interlayer insulating film 242 may be disposed on the first well region 1aW and the second well region 1bW. The first interlayer insulating film 242 may be disposed in a third direction Z between the second interlayer insulating film 244 and the third interlayer insulating film 240. The first interlayer insulating film 242 may include at least one of, for example, silicon oxide, silicon oxynitride, or a low-k material with a dielectric constant lower than that of silicon oxide. However, embodiments of this disclosure are not limited thereto. Although not specifically shown, the first interlayer insulating film 242 may include multiple insulating layers. The number of layers of the first interlayer insulating film 242 is not limited to the example shown.

[0100] The first interlayer insulating film 242 may include at least a portion of the first through-hole 284 and a first wiring 285 connected to the first through-hole 284. The first wiring 285 may be connected to the input / output contact 288, which will be described later. The first wiring 285 may be electrically connected to the input / output pad 287 via the input / output contact 288.

[0101] Each of the first through-hole 284 and the first wiring 285 may include a conductive material, such as at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), or alloys thereof. However, embodiments of this disclosure are not limited thereto.

[0102] The third interlayer insulating film 240 may be disposed on the first interlayer insulating film 242 in a third direction Z. The third interlayer insulating film 240 may include input / output pads 287 electrically connected to external devices outside the semiconductor device 10. The third interlayer insulating film 240 may include at least one of, for example, silicon oxide, silicon oxynitride, or a low-k material with a dielectric constant lower than that of silicon oxide. However, embodiments of this disclosure are not limited thereto.

[0103] Each of the input / output pads 287 and the input / output contacts 288 may include a conductive material, such as at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), or alloys thereof. However, embodiments of this disclosure are not limited thereto.

[0104] A first well region 1aW and a second well region 1bW may be disposed on a first interlayer insulating film 242. The first well region 1aW and the second well region 1bW may be arranged alternately in the horizontal direction. As used herein, the first well region 1aW and the second well region 1bW are understood to be included in a well structure. The well structure may include a first surface 200_1 and a second surface 200_2 facing each other. That is, each of the first well region 1aW and the second well region 1bW may include a first surface 200_1 and a second surface 200_2 facing each other. The second surface 200_2 may be a region in contact with the first interlayer insulating film 242, and the first surface 200_1 may be a region in contact with the second interlayer insulating film 244. As used herein, the first surface 200_1 and the second surface 200_2 may also be referred to as the first region and the second region of the well structure, respectively.

[0105] A first transistor PT1 can be disposed in the first surface 200_1 of the first well region 1aW. For example, the first transistor PT1 can be disposed at the first surface of the first well region 1aW. A second transistor PT2 can be disposed in the first surface 200_1 of the second well region 1bW. For example, the second transistor PT2 can be disposed at the first surface of the second well region 1bW. The first transistor PT1 and the second transistor PT2 can be disposed on the first surface 200_1 of the well structure and in the second interlayer insulating film 244. For example, the first transistor PT1 and the second transistor PT2 can be disposed in the second interlayer insulating film 244 to contact the first surface of the first well region 1aW and the first surface of the second well region 1bW, respectively.

[0106] The first well region 1aW and the second well region 1bW may include different conductive materials. For example, the first well region 1aW may include an n-type conductive material, and the second well region 1bW may include a p-type conductive material. In this case, the first transistor PT1 may be a PMOS, and the second transistor PT2 may be an NMOS. However, the embodiments are not limited to this.

[0107] Each of the first transistor PT1 and the second transistor PT2 can be an element that controls the operation of a semiconductor memory device. For example, the first transistor PT1 can be electrically connected to the line decoder 33 (see [link to documentation]). Figure 1 ), and the second transistor PT2 can be electrically connected to the page buffer 35 (see Figure 1However, the embodiments are not limited thereto. The first transistor PT1 and the second transistor PT2 can be electrically connected to an external circuit (e.g., Figure 1 Various circuits in the peripheral circuit 30).

[0108] In the first direction X and / or the second direction Y, the isolation structure IST can be disposed between the first well region 1aW and the second well region 1bW (e.g. Figure 5 (As shown). For example, the isolation structure IST can be disposed in the first direction X between the first well region 1aW and the second well region 1bW. The isolation structure IST can be disposed in the first direction X between the first well region 1aW and the second well region 1bW while extending in the third direction Z. The isolation structure IST can extend through the well structure in the third direction Z.

[0109] In the third direction Z, the isolation structure IST can be disposed between the first interlayer insulating film 242 and the second interlayer insulating film 244. The width of the isolation structure IST in the first direction X and / or the second direction Y can decrease as the isolation structure IST extends from the second interlayer insulating film 244 toward the first interlayer insulating film 242. However, the embodiments of this disclosure are not limited thereto.

[0110] The isolation structure IST can electrically isolate the first well region 1aW from the second well region 1bW. The isolation structure IST can include an insulating material. The isolation structure IST can include at least one of, for example, silicon oxide, silicon oxynitride, or a low-k material with a dielectric constant lower than that of silicon oxide. However, embodiments of this disclosure are not limited thereto.

[0111] Reference Figure 4 and Figure 5 The stop structure CS can be disposed on the isolation structure IST. The stop structure CS can be disposed in the second interlayer insulating film 244 and on the first surface 200_1 of the well structure, and can vertically overlap with the isolation structure IST in the third direction Z. For example, the stop structure CS can be disposed in the second interlayer insulating film 244 and can contact the first surface of the well structure, and can vertically overlap with the isolation structure IST in the third direction Z.

[0112] In the stop structure CS, the first through hole 284 and the second through hole 282A may at least partially overlap each other in the third direction Z. The lengths of the first through hole 284 and the second through hole 282A in the third direction Z may be different from each other. In an embodiment, the length of the first through hole 284 in the third direction Z may be greater than the length of the second through hole 282A in the third direction Z. The widths of the first through hole 284 and the second through hole 282A in the horizontal direction may decrease as the first through hole 284 and the second through hole 282A extend toward the stop structure CS. For example, the width of the first through hole 284 in the horizontal direction may decrease as the first through hole 284 extends from the first wiring 285 toward the stop structure CS, and the width of the second through hole 282A in the horizontal direction may decrease as the second through hole 282A extends from the second wiring 281 toward the stop structure CS, such as... Figure 5 As shown.

[0113] The first through hole 284 and the second through hole 282A can be spaced apart from each other when installed in the stop structure CS. The vertical height of the end of the first through hole 284 in the third direction Z in the stop structure CS can be different from the vertical height of the end of the second through hole 282A in the third direction Z in the stop structure CS.

[0114] The stop structure CS may include a conductive material. As used herein, the stop structure CS may be referred to as a conductive structure. The stop structure CS may include a conductive material, such as a metallic material and / or a doped semiconductor material. For example, the stop structure CS may include at least one of an n-type conductive material, a p-type conductive material, polysilicon (poly Si), silicon germanium (SiGe), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), aluminum (Al), or molybdenum (Mo). However, embodiments of this disclosure are not limited thereto.

[0115] In this embodiment, the stop structure CS can be formed in the same process as that used to form the first transistor PT1 and the second transistor PT2. In this case, the stop structure CS may comprise the same material as each of the first transistor PT1 and the second transistor PT2. The detailed structure and material of the stop structure CS will be described later.

[0116] Unlike the first transistor PT1 and the second transistor PT2, the stop structure CS may not be used as a component to control the operation of the semiconductor memory device.

[0117] The protection region GB can be disposed in each of the first well region 1aW and the second well region 1bW, and in the first surface 200_1 of the first well region 1aW and the second well region 1bW. For example, the protection region GB can be disposed in each of the first well region 1aW and the second well region 1bW, and can be in contact with the first surface of the first well region 1aW and the second well region 1bW. In, for example... Figure 4 In the cross-sectional view shown, the protection region GB can be set on each of the opposite sides of the first transistor PT1 and in the first well region 1aW, and can be set on each of the opposite sides of the second transistor PT2 and in the second well region 1bW.

[0118] The protection region GB may be electrically connected to at least one of the first well region 1aW or the second well region 1bW. For example, when the first well region 1aW comprises an n-type conductive material, the protection region GB in the first well region 1aW may comprise an n-type conductive material. When the second well region 1bW comprises a p-type conductive material, the protection region GB in the second well region 1bW may comprise a p-type conductive material.

[0119] As used herein, the guard region GB may be referred to as the bias region. The guard region GB may be connected to wiring (not shown) that provides a ground voltage to each of transistors PT1 and PT2 to provide a bias voltage to at least one of the first well region 1aW or the second well region 1bW. Although not specifically shown, in this case, the wiring (not shown) may be disposed in the second interlayer insulating film 244 and on the first surface 200_1 of the well structure.

[0120] The first through-hole 284 may extend through the isolation structure IST and extend in the third direction Z. The first through-hole 284 may extend in the third direction Z and in the first interlayer insulating film 242 to contact the stop structure CS. At least a portion of the first through-hole 284 may be provided in the stop structure CS.

[0121] The second interlayer insulating film 244 may be disposed on the memory cell region CELL. The second interlayer insulating film 244 may be disposed in the third direction Z between the first interlayer insulating film 242 and the memory cell region CELL. The second interlayer insulating film 244 may be disposed in the third direction Z between the well structure and the memory cell region CELL. The second interlayer insulating film 244 may include at least one of, for example, silicon oxide, silicon oxynitride, or a low-k material with a dielectric constant lower than that of silicon oxide. However, embodiments of this disclosure are not limited thereto. Although not specifically shown, the second interlayer insulating film 244 may include multiple insulating layers, and the number of layers of the second interlayer insulating film 244 is not limited to the example shown.

[0122] The second interlayer insulating film 244 can accommodate at least a portion of the second through hole 282A, the second wiring 281 connected to the second through hole 282A, and the first contact portion 282B connected to the second wiring 281.

[0123] A second through-hole 282A may be disposed on the first through-hole 284. The second through-hole 282A may extend in the third direction Z and in the second interlayer insulating film 244 to contact the stop structure CS. At least a portion of the second through-hole 282A may be disposed in the stop structure CS.

[0124] The second wiring 281 can connect the second through-hole 282A and the first contact portion 282B to each other in the horizontal direction. The first contact portion 282B can extend in the third direction Z in the second interlayer insulating film 244 to connect to the protection area GB.

[0125] The stop structure CS can be electrically connected to the protected area GB via the second through hole 282A, the second wiring 281, and the first contact 282B. Each of the first through hole 284 and the second through hole 282A can be electrically connected to the protected area GB.

[0126] Each of the first through-hole 284, the second through-hole 282A, the second wiring 281, and the first contact portion 282B may include a conductive material, such as at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), or alloys thereof. However, embodiments of this disclosure are not limited thereto.

[0127] The second interlayer insulating film 244 may further include a first wiring structure 280. The first wiring structure 280 may be disposed between the second wiring 281 and the second bonding pad 290. The first wiring structure 280 may include multiple wirings and multiple vias for electrically connecting the second wiring 281 and the second bonding pad 290 to each other. The first wiring structure 280 may include a conductive material, such as at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), or alloys thereof. However, embodiments of this disclosure are not limited thereto. The number, number of layers, and positional relationship of the multiple wirings and multiple vias included in the first wiring structure 280 are not limited to, for example... Figure 4 The situation is shown below.

[0128] Figures 8 to 12 Is with Figure 5 The enlarged view corresponds to the schematic diagram used to illustrate a semiconductor memory device according to some embodiments. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 7 The description contains repetitive content, or the description is omitted for brevity.

[0129] Reference Figure 8In some embodiments, in the stop structure CS, the first through hole 284 and the second through hole 282A may not overlap each other in the third direction Z. Figure 8 In the stop structure CS, the vertical height L2 of the end of the first through hole 284 in the third direction Z can be higher than or equal to the vertical height L1 of the end of the second through hole 282A in the third direction Z.

[0130] Reference Figure 9 In some embodiments, in the stop structure CS, the vertical height L2 of the first through hole 284 at one end in the third direction Z can be lower than or equal to the vertical height L1 of the second through hole 282A at one end in the third direction Z.

[0131] Reference Figure 10 In some embodiments, in the stop structure CS, the first through hole 284 and the second through hole 282A can contact each other. Figure 10 In the stop structure CS, the vertical height of one end of the first through hole 284 in the third direction Z can be equal to the vertical height of one end of the second through hole 282A in the third direction Z.

[0132] Reference Figure 11 In some embodiments, in the stop structure CS, the first through hole 284 can be bent to one side. Figure 11 In the stop structure CS, the first through hole 284 can have a curved surface. Figure 11 In the stop structure CS, the vertical height L2 of the end of the first through hole 284 in the third direction Z can be equal to or higher than the vertical height L1 of the end of the second through hole 282A in the third direction Z.

[0133] Reference Figure 12 In some embodiments, in the stop structure CS, the first through hole 284 can be bent to one side. Figure 12 In the stop structure CS, the first through hole 284 can have a curved surface. Figure 12 In the stop structure CS, the vertical height L2 of the first through hole 284 at one end in the third direction Z can be equal to or lower than the vertical height L1 of the second through hole 282A at one end in the third direction Z.

[0134] Figure 13 yes Figure 5 A magnified view of region Q1. Figures 14 to 15 Is with Figure 13 The enlarged view corresponds to the schematic diagram used to illustrate a semiconductor memory device according to some embodiments. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 12 The description contains repetitive content, or the description is omitted for brevity.

[0135] Reference Figure 13The stop structure CS may include the same structure as an NMOS transistor. The stop structure CS may include a gate insulating film 201, a first gate conductive layer 202, a second gate conductive layer 203, a third gate conductive layer 204, a fourth gate conductive layer 205, and a capping layer 206, which are sequentially stacked on the isolation structure IST.

[0136] For example, in one embodiment, one end of the first via 284 and one end of the second via 282A may be disposed in the fourth gate conductive layer 205 of the stop structure CS. However, the embodiments of this disclosure are not limited thereto.

[0137] For example, the gate insulating film 201 may include a high-k material. A high-k material can refer to a dielectric material with a dielectric constant higher than that of silicon oxide (SiO2). High-k materials can be, for example, alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2) and hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x Oy), lanthanum hafnium oxide (LaHf) x O y Hafnium aluminum oxide (HfAl) x O y It may be one of praseodymium oxide (Pr2O3) or praseodymium oxide. However, the embodiments disclosed herein are not limited thereto.

[0138] For example, the first gate conductive layer 202 may include a metallic material. For example, the first gate conductive layer 202 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).

[0139] For example, the second gate conductive layer 203 may include a metallic material. For example, the second gate conductive layer 203 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The thickness of the second gate conductive layer 203 may be greater than the thickness of the first gate conductive layer 202. However, embodiments of this disclosure are not limited thereto.

[0140] For example, the third gate conductive layer 204 may include a conductive semiconductor material, such as polysilicon. The thickness of the third gate conductive layer 204 may be greater than the thickness of each of the first gate conductive layer 202 and the second gate conductive layer 203. However, embodiments of this disclosure are not limited thereto.

[0141] For example, the fourth gate conductive layer 205 may include at least one of the following: tungsten (W), tungsten nitride (WN), ruthenium (Ru), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), or vanadium (V). The thickness of the fourth gate conductive layer 205 may be greater than the thickness of the third gate conductive layer 204. However, the embodiments of this disclosure are not limited thereto.

[0142] For example, the capping layer 206 may include silicon nitride (SiN), and the thickness of the capping layer 206 may be greater than the thickness of the fourth gate conductive layer 205. However, the embodiments of this disclosure are not limited thereto.

[0143] The capping film 252 may cover at least a portion of the surface of the stop structure CS. The capping film 252 may be disposed on at least a portion of the sidewall and upper surface of each of the first transistor PT1, the second transistor PT2, and the stop structure CS. The capping film 252 may include, for example, silicon nitride. However, embodiments of this disclosure are not limited thereto.

[0144] Reference Figure 14 The stop structure CS can be formed in the process used to form an NMOS transistor or a PMOS transistor, and can have a structure different from that of each of the NMOS transistors or PMOS transistors. The stop structure CS may include a gate insulating film 201, a fifth gate conductive layer 207, a first gate conductive layer 202, a second gate conductive layer 203, a third gate conductive layer 204, a fourth gate conductive layer 205, and a capping layer 206, which are sequentially stacked on the isolation structure IST.

[0145] For example, the fifth gate conductive layer 207 may include a metallic material. For example, the fifth gate conductive layer 207 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).

[0146] Reference Figure 15 The stop structure CS can include the same structure as a PMOS transistor. The stop structure CS can include a semiconductor material layer 208, a gate insulating film 201, a fifth gate conductive layer 207, a first gate conductive layer 202, a second gate conductive layer 203, a third gate conductive layer 204, a fourth gate conductive layer 205, and a capping layer 206, sequentially stacked on the isolation structure IST. For example, the semiconductor material layer 208 can include SiGe.

[0147] Figures 16 to 18 This is an example layout diagram of a semiconductor memory device according to some embodiments. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 15 The description contains repetitive content, or omits descriptions for the sake of brevity. For reference, Figures 16 to 18 It is used to show a reference. Figure 4 A schematic layout diagram of the semiconductor memory device.

[0148] Reference Figure 16 The first transistor PT1 may include a first gate structure GS1 and a first active region ACT1. The second transistor PT2 may include a second gate structure GS2 and a second active region ACT2. Each of the first gate structure GS1 and the second gate structure GS2 may extend in a second direction Y, and each of the first active region ACT1 and the second active region ACT2 may extend in a first direction X.

[0149] In a plan view, the protection region GB may extend in a ring shape when disposed in each of the first well region 1aW or the second well region 1bW. In a plan view, a plurality of stop structures CS may be disposed between the first well region 1aW and the second well region 1bW. As used herein, a plan view may represent a top view of a semiconductor memory device according to some embodiments.

[0150] The stop structure CS can be electrically connected to the protection area GB via the second through hole 282A and the second wiring 281 connected to the second through hole 282A.

[0151] Reference Figure 17 In the plan view, multiple stop structures CS can be disposed around the first well region 1aW and the second well region 1bW. In the plan view, the multiple stop structures CS can be spaced apart from each other and can be arranged around the first well region 1aW and the second well region 1bW. The stop structures CS can be electrically connected to the protection area GB via a second wiring 281 extending in the second direction Y.

[0152] Reference Figure 18 In the plan view, multiple stop structures CS can be spaced apart from each other and can be arranged between the first well region 1aW and the second well region 1bW and around the first well region 1aW and the second well region 1bW.

[0153] Figure 19 and Figure 20 This is a cross-sectional view of a semiconductor memory device according to some embodiments. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 18 The description contains repetitive content, or the description is omitted for brevity.

[0154] Reference Figure 19 The protection region GB can be disposed in the first well region 1aW and the second well region 1bW, and in the second surface 200_2 of each of the first well region 1aW and the second well region 1bW. For example, the protection region GB can be disposed in the first well region 1aW and the second well region 1bW to contact the second surface of each of the first well region 1aW and the second well region 1bW. (See below.) Figure 23 As described above, in the plan view, multiple protection zones GB can be arranged in a matrix form when set in each of the first well region 1aW and the second well region 1bW.

[0155] The protection region GB may be electrically connected to at least one of the first well region 1aW or the second well region 1bW. For example, when the first well region 1aW comprises an n-type conductive material, the protection region GB in the first well region 1aW may comprise an n-type conductive material. When the second well region 1bW comprises a p-type conductive material, the protection region GB in the second well region 1bW may comprise a p-type conductive material.

[0156] The protection region GB can be referred to as the bias region. The protection region GB can be connected to wiring (not shown) that provides ground voltage to transistors PT1 and PT2 to provide a bias voltage to at least one of the first well region 1aW and the second well region 1bW. Although not specifically shown, in this case, the wiring (not shown) can be provided in the first interlayer insulating film 242 and on the second surface 200_2 of the well structure.

[0157] The first interlayer insulating film 242 may further include a second contact portion 286 connected to the first wiring 285. The second contact portion 286 may include a conductive material, such as at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), or alloys thereof. However, embodiments of this disclosure are not limited thereto.

[0158] Although not specifically shown, a plurality of second contacts 286 may be spaced apart from the first wiring 285 and may be disposed on the second surface 200_2.

[0159] The stop structure CS can be electrically connected to the protection area GB via a first through hole 284, a first wiring 285 connected to the first through hole 284, and a second contact portion 286 connected to the first wiring 285 and extending in the third direction Z.

[0160] See Figure 20Multiple second contacts 286 connected to the first wiring 285 can be disposed on the second surface 200_2. In the plan view, multiple protection regions GB can be arranged in a matrix in each of the first well regions 1aW and the second well region 1bW. The multiple protection regions GB can be connected to the first wiring 285 respectively through multiple second contacts 286.

[0161] Figure 21 and Figure 22 This is a cross-sectional view of a semiconductor memory device according to some embodiments. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 20 The description contains repetitive content, or the description is omitted for brevity.

[0162] Reference Figure 21 According to some embodiments, a semiconductor memory device may include a first memory cell region CELL1, a second memory cell region CELL2, and a peripheral circuit region PERI. Figure 21 An example is shown that includes only two memory cell regions, CELL1 and CELL2, in a semiconductor memory device. However, embodiments of this disclosure are not limited thereto. Figure 21 Unlike the example shown, semiconductor memory devices may include memory cell regions stacked in two or more layers.

[0163] The first memory cell region CELL1 may include a first stacked structure SS1, a first channel structure CH1, a first gate contact GC1, a first cell interlayer insulating film 142, a first cell wiring structure WS1, a first bonding insulating layer 146, and a first bonding pad 190.

[0164] The first stacked structure SS1 may include multiple gate electrodes and multiple molded insulating films that can be stacked on the first unit substrate 102. (Refer to above) Figure 4 and Figure 19 The description of the unit substrate 102 can be equally applied to Figure 21 The first unit substrate 102. See above for reference. Figure 4 and Figure 19 The description of the plurality of gate electrodes 112 and the plurality of molded insulating films 110 can be equally applied to Figure 21 It contains multiple gate electrodes and multiple molded insulating films.

[0165] The first channel structure CH1 can be set in the cell array region (e.g., Figure 3 On the cell array region CA). Each of the multiple first channel structures CH1 can extend in the third direction Z to extend through the first stack structure SS1. See above. Figure 4 and Figure 19The description of the channel structure CH can be equally applied to Figure 21 The first channel structure CH1 in the middle.

[0166] The first gate contact GC1 can be disposed on the extended region EA (see...). Figure 3 Each of the plurality of first gate contacts GC1 may extend in a third direction Z to at least partially extend through the first stack structure SS1. (See above for reference.) Figure 4 and Figure 19 The description of the gate contact GC can be equally applied to Figure 21 The first gate contact GC1 in the middle.

[0167] The first unit interlayer insulating film 142 can be disposed on the first stacked structure SS1. The first unit interlayer insulating film 142 can be formed on the first unit substrate 102 to cover the first stacked structure SS1. (Refer to above) Figure 4 and Figure 19 The description of the interlayer insulating film 142 can be equally applied to Figure 21 The first unit interlayer insulating film 142.

[0168] The first unit wiring structure WS1 can be disposed in the first unit interlayer insulating film 142. The first unit wiring structure WS1 may include multiple wirings and multiple vias electrically connected to the first channel structure CH1, and multiple wirings and multiple vias electrically connected to the first gate contact GC1.

[0169] The first bonding insulating layer 146 may be disposed on the first unit interlayer insulating film 142. The first bonding pad 190 may be disposed in the first bonding insulating layer 146 and the first unit interlayer insulating film 142. (Refer to the above) Figure 4 and Figure 19 The description of the first bonding insulating layer 146 and the first bonding pad 190 can be equally applied. Figure 21 The first bonding insulating layer 146 and the first bonding pad 190 are in the middle.

[0170] The first bonding insulating layer 146 and the first bonding pad 190 can be directly bonded to the second bonding insulating layer 246 and the second bonding pad 290 of the peripheral circuit region PERI, respectively.

[0171] The first memory cell region CELL1 may further include a third interlayer insulating film 344, a fourth bonding insulating layer 446, and a fourth bonding pad 490. The third interlayer insulating film 344 may be disposed between the first cell substrate 102 and the fourth bonding insulating layer 446. Although not shown, multiple wirings and vias electrically connected to the first cell substrate 102 of the first memory cell region CELL1 may be provided in the third interlayer insulating film 344. (Refer to above) Figure 4 and Figure 19 The description of the interlayer insulating film 142 can be equally applied to Figure 21 The third unit interlayer insulating film 344.

[0172] The fourth bonding insulating layer 446 and the fourth bonding pad 490 may be disposed below the first unit substrate 102. (See above reference...) Figure 4 and Figure 19 The description of the first bonding insulating layer 146 and the first bonding pad 190 can be equally applied. Figure 21 The fourth bonding insulating layer 446 and the fourth bonding pad 490 are in the middle.

[0173] The second memory cell region CELL2 may include a second stacked structure SS2, a second channel structure CH2, a second gate contact GC2, a second cell interlayer insulating film 342, a second cell wiring structure WS2, a third bonding insulating layer 346, and a third bonding pad 390.

[0174] The second stacked structure SS2 may include multiple gate electrodes and multiple molded insulating films that can be stacked on the second unit substrate 202. (Refer to above) Figure 4 and Figure 19 The description of the unit substrate 102 can be equally applied to Figure 21 The second unit substrate 202. See above for reference. Figure 4 and Figure 19 The description of the plurality of gate electrodes 112 and the plurality of molded insulating films 110 can be equally applied to Figure 21 It contains multiple gate electrodes and multiple molded insulating films.

[0175] The second channel structure CH2 can be set in the unit array region ( Figure 3 On the CA). Each of the multiple second channel structures CH2 can extend in the third direction Z to extend through the second stack structure SS2. See above. Figure 4 and Figure 19 The description of the channel structure CH can be equally applied to Figure 21 The second channel structure CH2 in the middle.

[0176] The second gate contact GC2 can be disposed on the extended region EA (see...). Figure 3 Each of the plurality of second gate contacts GC2 may extend in a third direction Z to at least partially extend through the second stack structure SS2. (See above for reference.) Figure 4 and Figure 19 The description of the gate contact GC can be equally applied to Figure 21 The second gate contact GC2 in the middle.

[0177] The second unit interlayer insulating film 342 can be disposed on the second stacked structure SS2. The second unit interlayer insulating film 342 can be formed on the second unit substrate 202 to cover the second stacked structure SS2. (Refer to above) Figure 4 and Figure 19 The description of the interlayer insulating film 142 can be equally applied to Figure 21 The second unit interlayer insulating film 342.

[0178] The second unit wiring structure WS2 can be disposed in the second unit interlayer insulating film 342. The second unit wiring structure WS2 may include multiple wirings and multiple vias electrically connected to the second channel structure CH2, and multiple wirings and multiple vias electrically connected to the second gate contact GC2.

[0179] The third bonding insulating layer 346 can be disposed on the second unit interlayer insulating film 342. The third bonding pad 390 can be disposed in the third bonding insulating layer 346 and the second unit interlayer insulating film 342. (Refer to the above.) Figure 4 and Figure 19 The description of the first bonding insulating layer 146 and the first bonding pad 190 can be equally applied. Figure 21 The third bonding insulating layer 346 and the third bonding pad 390 are in the middle.

[0180] The third bonding insulating layer 346 and the third bonding pad 390 can be directly bonded to the fourth bonding insulating layer 446 and the fourth bonding pad 490 of the first memory cell region CELL1, respectively.

[0181] The width of the isolation structure IST can decrease as the isolation structure IST extends toward the stop structure CS. The width of the first well region 1aW can increase as the first well region 1aW extends toward the stop structure CS, and the width of the second well region 1bW can increase as the second well region 1bW extends toward the stop structure CS.

[0182] Reference Figure 22A plurality of second contacts 286 connected to the first wiring 285 may be disposed on the second surface 200_2. In the plan view, a plurality of protection regions GB may be arranged in a matrix in each of the first well regions 1aW and the second well region 1bW. The plurality of protection regions GB may be connected to the first wiring 285 via the plurality of second contacts 286 respectively.

[0183] Figures 23 to 25 This is an example layout diagram of a semiconductor memory device according to some embodiments. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 20 The description contains repetitive content, or the description is omitted for brevity.

[0184] Reference Figure 23 In the plan view, multiple stop structures CS can be disposed between the first well region 1aW and the second well region 1bW. The stop structures CS can be electrically connected via a first wiring 285 connected to the first through-hole 284 to protection regions GB arranged in a matrix and spaced apart from each other. The same bias voltage can be provided to the protection regions GB and the stop structures CS connected to each other via the first wiring 285. The number and location of the protection regions GB connected to the stop structures CS via the first wiring 285 are not limited to, for example... Figure 23 The example shown. The number and location of the protective regions GB arranged spaced apart from each other in each of the first well region 1aW and the second well region 1bW are not limited to, for example Figure 23 Example shown.

[0185] Reference Figure 24 In the plan view, multiple stop structures CS can be arranged around the first well region 1aW and the second well region 1bW.

[0186] Reference Figure 25 In the plan view, multiple stop structures CS can be spaced apart from each other when arranged between the first well region 1aW and the second well region 1bW and around the first well region 1aW and the second well region 1bW.

[0187] Figures 26 to 35 This is a schematic diagram of an intermediate structure corresponding to an intermediate step in a method of manufacturing a semiconductor memory device according to some embodiments. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 25 The description contains repetitive content, or the description is omitted for brevity.

[0188] Reference Figure 26A substrate 200 is provided. The substrate 200 may include a semiconductor material, such as silicon (Si). In some embodiments, the substrate 200 may include a semiconductor element material (such as germanium (Ge)) or a compound semiconductor material (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP)). The substrate 200 may include conductive regions, such as impurity-doped wells or impurity-doped structures. In some embodiments, the substrate 200 may include a p-type conductive material.

[0189] The substrate 200 may include a first surface 200_1 and a second surface 200_2 facing each other. As described above, alternatively, the first surface 200_1 and the second surface 200_2 may be referred to as the first surface and the second surface, respectively. A first well region 1aW and a second well region 1bW may be formed from the second surface 200_2 to the first surface 200_1 of the substrate 200. The first well region 1aW and the second well region 1bW may be arranged alternately in the substrate 200. The first well region 1aW may include an n-type conductive material, and the second well region 1bW may include a p-type conductive material. The second well region 1bW may be a region doped with p-type material, the concentration of which is relatively higher than the concentration of p-type material in the substrate 200.

[0190] An isolation structure IST can be formed between the first well region 1aW and the second well region 1bW. For example, the width of the isolation structure IST in the first direction X can decrease as the isolation structure IST extends toward the substrate 200 (i.e., from the first surface 200_1 toward the second surface 200_2). The isolation structure IST can include, for example, an insulating material (such as silicon oxide). The isolation structure IST can be formed by filling a trench extending from the first surface 200_1 to the second surface 200_2 with an insulating material.

[0191] Although not specifically shown, element isolation films (not shown) can be formed on each of the opposite sides of the isolation structure IST. For example, the element isolation film can have a shallow trench isolation (STI) structure.

[0192] Although not specifically shown, a first protection region for providing a first bias voltage to at least one of the first well region 1aW or the second well region 1bW can be formed on the first surface 200_1 of the substrate 200 (e.g., Figure 4 The protected area (GB) in the document. Figure 4 The stop structure CS can be electrically connected to the first contact portion 282B on the first surface 200_1 via the first contact portion 282B. Figure 4 The first protected area GB.

[0193] Figure 28 yes Figure 27 A magnified view of region R1.

[0194] Reference Figure 27 and Figure 28 A gate material layer GM can be formed on the first well region 1aW, the second well region 1bW, and the isolation structure IST. The gate material layer GM can be formed such that the structures of the portions disposed on the first well region 1aW, the isolation structure IST, and the second well region 1bW are different from each other.

[0195] When the second well region 1bW includes a p-type conductive material, an NMOS transistor can be formed on the second well region 1bW.

[0196] The portion of the gate material layer GM on the second well region 1bW may include a gate insulating film 201, a first gate conductive layer 202, a second gate conductive layer 203, a third gate conductive layer 204, a fourth gate conductive layer 205, and a capping layer 206. (Refer to the above...) Figure 13 The descriptions of the gate insulating film 201, the first gate conductive layer 202, the second gate conductive layer 203, the third gate conductive layer 204, the fourth gate conductive layer 205, and the capping layer 206 are equally applicable. Figure 27 and Figure 28 The second well region 1bW contains a gate insulating film 201, a first gate conductive layer 202, a second gate conductive layer 203, a third gate conductive layer 204, a fourth gate conductive layer 205, and a capping layer 206.

[0197] When the first well region 1aW includes an n-type conductive material, a PMOS transistor can be formed on the first well region 1aW.

[0198] The portion of the gate material layer GM on the first well region 1aW may include a semiconductor material layer 208, a gate insulating film 201, a fifth gate conductive layer 207, a first gate conductive layer 202, a second gate conductive layer 203, a third gate conductive layer 204, a fourth gate conductive layer 205, and a capping layer 206. For example, the semiconductor material layer 208 may include SiGe. (Refer to the above...) Figure 15 The descriptions of semiconductor material layer 208, gate insulating film 201, fifth gate conductive layer 207, first gate conductive layer 202, second gate conductive layer 203, third gate conductive layer 204, fourth gate conductive layer 205, and capping layer 206 can be equivalently applied to each other. Figures 27 to 28 The semiconductor material layer 208, gate insulating film 201, fifth gate conductive layer 207, first gate conductive layer 202, second gate conductive layer 203, third gate conductive layer 204, fourth gate conductive layer 205 and capping layer 206 are on the first well region 1aW.

[0199] The portion of the gate material layer GM on the isolation structure IST can be formed in the same process as a portion of the gate material layer of an NMOS or PMOS transistor, and can have a structure different from that portion of the gate material layer of the NMOS or PMOS transistor. The portion of the gate material layer GM on the isolation structure IST may include a gate insulating film 201, a fifth gate conductive layer 207, a first gate conductive layer 202, a second gate conductive layer 203, a third gate conductive layer 204, a fourth gate conductive layer 205, and a capping layer 206. (Refer to the above...) Figure 14 The descriptions of the gate insulating film 201, the fifth gate conductive layer 207, the first gate conductive layer 202, the second gate conductive layer 203, the third gate conductive layer 204, the fourth gate conductive layer 205, and the capping layer 206 can be equivalently applied to each other. Figures 27 to 28 The isolation structure IST contains a gate insulating film 201, a fifth gate conductive layer 207, a first gate conductive layer 202, a second gate conductive layer 203, a third gate conductive layer 204, a fourth gate conductive layer 205, and a capping layer 206.

[0200] A semiconductor material layer 208 may be selectively formed on the first well region 1aW. Then, a gate insulating film 201 may be formed on the first well region 1aW, the second well region 1bW, and the isolation structure IST. The gate insulating film 201 may cover the semiconductor material layer 208. Next, a fifth gate conductive layer 207 may be formed on the isolation structure IST and the first well region 1aW. The fifth gate conductive layer 207 may be formed on a portion of the gate insulating film 201 on the isolation structure IST and on a portion of the gate insulating film 201 on the first well region 1aW. Then, a first gate conductive layer 202 may be formed on the first well region 1aW, the second well region 1bW, and the isolation structure IST. The first gate conductive layer 202 may be formed on a portion of the fifth gate conductive layer 207 on the isolation structure IST and on a portion of the fifth gate conductive layer 207 on the first well region 1aW. Subsequently, the second gate conductive layer 203, the third gate conductive layer 204, the fourth gate conductive layer 205 and the capping layer 206 can be sequentially formed on the first well region 1aW, the second well region 1bW and the isolation structure IST.

[0201] Subsequently, a hard mask film 209 and an insulating film 210 covering the capping layer 206 can be formed on the first well region 1aW, the second well region 1bW, and the isolation structure IST. The hard mask film 209 can be, for example, a spin-coated hard mask (SOH). The insulating film 210 can include, for example, an insulating material such as silicon oxide. However, the embodiments disclosed herein are not limited thereto.

[0202] Figure 30 yes Figure 29A magnified view of region R2.

[0203] Reference Figure 29 and Figure 30 , can be Figure 27 The gate material layer GM is patterned to form a first structure G1, a second structure G2, and a third structure G3.

[0204] Although not specifically shown, it can be found in insulating films (see...) Figure 28 A mask pattern (not shown) is formed on the gate material layer GM, spaced apart from each other by a predetermined distance. The mask pattern (not shown) can be used to mask the gate material layer GM (see [reference]). Figure 27 Patterning is performed on the gate material layer (see [link]). Figure 27 Patterning of the hard mask 209 can be performed using known etching processes. Afterwards, the hard mask 209 can be removed (see...). Figure 28 ) and insulating film 210 (see Figure 28 ), to form the first structure G1, the second structure G2 and the third structure G3.

[0205] A capping film 252 can be formed along the upper surfaces of the first well region 1aW, the second well region 1bW, and the isolation structure IST, as well as the sidewalls and upper surfaces of the first structure G1, the second structure G2, and the third structure G3. The capping film 252 may include, for example, silicon nitride. Subsequently, portions of the capping film 252 formed on the upper surfaces of the first well region 1aW, the second well region 1bW, and the isolation structure IST can be removed. In some embodiments, a portion of the capping film 252 may remain on the upper surfaces of the first well region 1aW, the second well region 1bW, and the isolation structure IST.

[0206] Figure 32 yes Figure 31 A magnified view of region R3.

[0207] Reference Figure 31 and Figure 32 A second interlayer insulating film 244 can be formed on the first well region 1aW, the second well region 1bW, and the isolation structure IST. A second via 282, a second wiring 281, and a first wiring structure 280 can be formed in the second interlayer insulating film 244. A second bonding insulating layer 246 can be formed on the second interlayer insulating film 244, and a second bonding pad 290 can be formed in the second bonding insulating layer 246.

[0208] The second interlayer insulating film 244 may include an insulating material (such as silicon oxide), and the second bonding insulating layer 246 may include silicon carbonitride. However, embodiments of this disclosure are not limited thereto.

[0209] Each of the second via 282, the second wiring 281, the first wiring structure 280, and the second bonding pad 290 may include a conductive material, such as at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and alloys thereof. However, embodiments of this disclosure are not limited thereto.

[0210] The second via 282 can be disposed on the gate structure GS and extend partially into the gate structure GS. Specifically, the second via 282 can extend in the third direction Z to contact the fourth gate conductive layer 205 of each of the first structure G1, the second structure G2, and the third structure G3. However, embodiments of this disclosure are not limited thereto. Therefore, a pre-peripheral circuit region P_PERI can be formed.

[0211] like Figure 33 As shown, a pre-memory cell region P_CELL can be stacked on the pre-peripheral circuit region P_PERI. The second bonding pad 290 of the pre-peripheral circuit region P_PERI and the first bonding pad 190 of the pre-memory cell region P_CELL can be configured to face each other and bond to each other.

[0212] A cell substrate 102 can be formed on the stacked structure SS of the pre-storage cell region P_CELL. At least a portion of the channel structure CH can be formed in the cell substrate 102.

[0213] Subsequently, a carrier substrate CW can be formed on the rear surface of the cell substrate 102. The carrier substrate CW can be formed on the pre-storage cell region P_CELL. The carrier substrate CW can include, for example, silicon and / or silicon oxide. Although not specifically shown, an adhesive layer including silicon carbonitride can be inserted between the cell substrate 102 and the carrier substrate CW.

[0214] Figure 35 yes Figure 34 A magnified view of region R4.

[0215] Reference Figure 34 and Figure 35 The pre-peripheral circuit area P_PERI can be set on the pre-storage cell area P_CELL.

[0216] It can be used on the substrate (see Figure 33 The grinding process is performed. Therefore, the substrate can be removed (see...). Figure 33 At least a portion thereof. Although not specifically shown, a second protective region may be formed on the second surface 200_2 of the substrate 200 (see [reference]). Figure 19 This is used to provide a second bias voltage to at least one of the first well region 1aW and the second well region 1bW. In this case, Figure 19The stop structure CS can be located via the second surface 200_2 Figure 19 The second contact 286 is electrically connected to the second protection zone GB (see Figure 19 ).

[0217] Afterwards, the substrate 200 can be removed (see...) Figure 33 A first interlayer insulating film 242 is formed on the isolation structure IST and the first well region 1aW and the second well region 1bW. The first interlayer insulating film 242 may include an insulating material (such as silicon oxide). However, embodiments of the present disclosure are not limited thereto.

[0218] A first through-hole 284, a first wiring 285, and a second contact portion 286 can be formed in the first interlayer insulating film 242.

[0219] Each of the first through-hole 284, the first wiring 285, and the second contact portion 286 may include a conductive material, such as at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), or alloys thereof. However, embodiments of this disclosure are not limited thereto.

[0220] The first via 284 may extend through the isolation structure IST. The first via 284 may extend, for example, in the third direction Z, to contact the fourth gate conductive layer 205 of each of the first structure G1, the second structure G2, and the third structure G3. However, embodiments of this disclosure are not limited thereto.

[0221] Then, input / output contacts can be formed in the first interlayer insulating film 242 (see...) Figure 4 or Figure 19 A third interlayer insulating film 240 can be formed on the first interlayer insulating film 242 (see [link]). Figure 4 or Figure 19 ) and input / output pads 287 (see Figure 4 or Figure 19 ). Figure 4 or Figure 19 The input / output pads 287 can be accessed via Figure 4 or Figure 19 The input / output contact 288 is connected to the first wiring 285.

[0222] Afterwards, the carrier substrate CW can be removed.

[0223] Therefore, a reference can be created. Figures 1 to 25 The semiconductor memory device described.

[0224] In semiconductor devices, including transistors formed in well regions and isolation structures that isolate the well regions from each other, electrical paths can be formed using vias extending through the isolation structures.

[0225] In some embodiments, a portion of the conductive material layer formed during the process of forming the gate of the transistor can be left behind, thus serving as a stop pad on which a via lands. That is, the via lands on the stop pad, which minimizes via bending due to the difficulty of etching the via holes. Therefore, a semiconductor memory device with improved electrical characteristics and reliability can be formed.

[0226] Figure 36 This is an example block diagram used to illustrate an electronic system according to some embodiments. Figure 37 This is an example perspective view illustrating an electronic system according to some embodiments. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 35 The description contains repetitive content, or the description is omitted for brevity.

[0227] Reference Figure 36 According to some embodiments, the electronic system 1000 may include a non-volatile memory device 1100 and a controller 1200 electrically connected to the non-volatile memory device 1100. The electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100, or an electronic device including a storage device. For example, the electronic system 1000 may be embodied as a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor memory devices 1100.

[0228] The non-volatile memory device 1100 may be embodied, for example, as a NAND flash memory device, and may include, for example, the above-mentioned reference. Figures 1 to 35 The semiconductor memory device described. The non-volatile memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0229] The first structure 1100F may include a decoder circuit 1110 (e.g., Figure 1 The line decoder 33 and page buffer 1120 (e.g., in the row decoder 33) are used to decode the page buffer 1120. Figure 1 Page buffer 35) and logic circuit 1130 (e.g., Figure 1 The peripheral circuit structure of the control logic 37 in the middle.

[0230] The second structure 1100S may include, as referred above. Figure 2 The description includes a common source line CSL, multiple bit lines BL, and multiple cell strings CSTR. The cell strings CSTR can be connected to the decoder circuit 1110 via a word line WL, at least one string select line SSL, and at least one ground select line GSL. Furthermore, the cell strings CSTR can be connected to the page buffer 1120 via the bit line BL.

[0231] In some embodiments, the common source line CSL and the cell string CSTR can be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from the first structure 1100F to the second structure 1100S.

[0232] In some embodiments, bit line BL may be electrically connected to page buffer 1120 via a second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0233] Non-volatile memory device 1100 can be connected via logic circuit 1130 (e.g., Figure 1 The control logic 37) communicates with the controller 1200 via the electrically connected input / output pads 1101. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via the input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0234] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In some embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100. In this case, the controller 1200 may control the plurality of semiconductor memory devices 1100.

[0235] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate based on predefined firmware and can control NAND controller 1220 to access non-volatile memory device 1100. NAND controller 1220 may include NAND interface (I / F) 1221 for processing communication with non-volatile memory device 1100. Through NAND interface 1221, control commands for controlling non-volatile memory device 1100, data to be written to memory cell transistors (MCTs) of non-volatile memory device 1100, and data to be read from memory cell transistors (MCTs) of non-volatile memory device 1100 can be transmitted. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When a control command is received from an external host via host interface 1230, processor 1210 can control non-volatile memory device 1100 in response to the control command.

[0236] Reference Figures 36 to 37According to some embodiments, the electronic system may include a main substrate 2001, a main controller 2002 mounted on the main substrate 2001, at least one semiconductor package 2003, and at least one DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 via wiring patterns 2005 formed on the main substrate 2001.

[0237] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary based on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host using one of the following interfaces: USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect High Speed ​​Interface), SATA (Serial Advanced Technology Attachment), M-Phy for UFS (Universal Flash Memory). In some embodiments, the electronic system 2000 may operate using power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

[0238] The main controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0239] DRAM 2004 can be used as a buffer memory to reduce the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 can operate as a high-speed cache memory and can provide space for temporary data storage during the control operations of the semiconductor package 2003. When DRAM 2004 is included in the electronic system 2000, the main controller 2002 may include a DRAM controller for controlling DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003.

[0240] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be embodied as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 disposed on the package substrate 2100 and covering the semiconductor chips 2200 and the connection structure 2400.

[0241] The package substrate 2100 may be embodied as a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 36 Input / output pad 1101.

[0242] In some embodiments, the connection structure 2400 may be embodied as bonding wiring that electrically connects the input / output pads 2210 to the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wiring scheme and may be electrically connected to the on-package pads 2130 of the package substrate 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs), instead of using the bonding wiring scheme of the connection structure 2400.

[0243] In some embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in a single package. In some embodiments, the main controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the main controller 2002 and the semiconductor chip 2200 may be interconnected with each other via wiring formed in the interposer substrate.

[0244] In an electronic system according to some embodiments, each semiconductor chip 2200 may include the above-mentioned reference. Figures 1 to 35 The semiconductor memory device described. For example, each semiconductor chip 2200 may include a peripheral circuit region (PERI) and a memory cell region (CELL). For example, the peripheral circuit region (PERI) may include the above-described reference... Figures 1 to 35The description includes a first well region 1aW, a second well region 1bW, an isolation structure IST, a first transistor PT1, a second transistor PT2, a stop structure CS, and through structures 284 and 282A. Furthermore, for example, the memory cell region CELL may include the above-described... Figures 1 to 35 The described unit substrate 102, stacked structure SS, channel structure CH, bit line 182, etc.

[0245] The first well region 1aW may include impurities of a first conductivity type, and the second well region 1bW may include impurities of a second conductivity type different from the first conductivity type. An isolation structure IST electrically isolates the first well region 1aW and the second well region 1bW from each other. A first transistor PT1 may be disposed on the first well region 1aW, and a second transistor PT2 may be disposed on the second well region 1bW. A stop structure CS may be disposed on the isolation structure IST. Through structures 284 and 282A may extend at least partially into the stop structure CS in the vertical direction.

[0246] The through structures 284 and 282A may include a first through hole 284 extending through the isolation structure IST and extending in the vertical direction, and a second through hole 282A extending in the vertical direction when disposed on the first through hole 284.

[0247] The peripheral circuit region PERI may include a first protection (bias) region GB that provides a first bias voltage to the first well region 1aW, and a second protection (bias) region GB that provides a second bias voltage to the second well region 1bW.

[0248] For example, the first transistor PT1 can be electrically connected to the decoder circuit (e.g., Figure 36 The decoder circuit 1110), and the second transistor PT2 can be electrically connected to the page buffer (e.g., Figure 36 (page buffer 1120). However, embodiments of this disclosure are not limited thereto.

[0249] The stacked structure SS may include a plurality of gate electrodes 112 disposed on the cell substrate 102 and extending in a first horizontal direction. The channel structure CH may extend in the stacked structure SS in a vertical direction different from the first horizontal direction. The bit line 182 may extend in a second horizontal direction and may be electrically connected to the channel structure CH.

[0250] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, but can be implemented in various different forms. Those skilled in the art will understand that the present disclosure can be practiced in other specific forms without altering the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects rather than restrictive, and all such forms, variations, and modifications are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor memory device, comprising: Unit region; as well as The peripheral circuit area is located on the unit area. The unit region includes: A stacked structure, comprising a plurality of gate electrodes stacked in a first direction; and A channel structure is disposed in the stacked structure and extends in the first direction, and The peripheral circuit region includes: A well structure includes a first surface and a second surface facing each other, wherein the well structure includes a first well region and a second well region disposed on the first surface, wherein a first transistor is disposed in the first well region and a second transistor is disposed in the second well region; An isolation structure isolates the first well region from the second well region; A stop structure is provided on the isolation structure; and The through-structure extends at least partially into the stop structure in the first direction.

2. The semiconductor memory device according to claim 1, wherein, The peripheral circuit region further includes: a first protection region disposed on the first surface and connected to at least one of the first well region or the second well region. The stop structure is connected to the first protected area via the through structure, a first wiring connected to the through structure, and a first contact portion connected to the first wiring. The first contact portion extends in the first direction.

3. The semiconductor memory device according to claim 1, wherein, The peripheral circuit region further includes: a second protection region disposed on the second surface and connected to at least one of the first well region or the second well region. The stop structure is connected to the second protected area via the through structure, a second wiring connected to the through structure, and a second contact portion connected to the second wiring. The second contact portion extends in the first direction.

4. The semiconductor memory device according to claim 1, wherein, In the plan view, the stop structure is disposed between the first well region and the second well region.

5. The semiconductor memory device according to claim 1, wherein, In the plan view, the stop structure is disposed around the first well region and the second well region.

6. The semiconductor memory device according to claim 1, wherein, The through-structure includes: A first through-hole extends through the isolation structure and extends in the first direction; and A second through hole is disposed on the first through hole and extends in the first direction.

7. The semiconductor memory device according to claim 6, wherein, In the stop structure, the first through hole and the second through hole are spaced apart.

8. The semiconductor memory device according to claim 6, wherein, The width of the first through hole decreases as the first through hole extends toward the stop structure in the first direction, and the width of the second through hole decreases as the second through hole extends toward the stop structure in the first direction.

9. The semiconductor memory device according to claim 6, wherein, The vertical height of the first through hole in the first direction in the stop structure is different from the vertical height of the second through hole in the first direction in the stop structure.

10. The semiconductor memory device according to claim 6, wherein, In the stop structure, the first through hole is in contact with the second through hole.

11. The semiconductor memory device according to claim 1, wherein, The stop structure includes a conductive material.

12. The semiconductor memory device according to claim 1, wherein, The first well region comprises an n-type conductive material. The second well region includes a p-type conductive material. Wherein, the first transistor is a PMOS transistor, and The second transistor is an NMOS transistor.

13. A semiconductor memory device, comprising: Unit region; as well as The peripheral circuit area is located on the unit area. The unit region includes: A stacked structure, comprising a plurality of gate electrodes stacked in a first direction; and A channel structure is disposed in the stacked structure and extends in the first direction, and The peripheral circuit region includes: The well structure includes a first well region of a first conductivity type and a second well region of a second conductivity type different from the first conductivity type; An isolation structure is disposed between the first well region and the second well region, and includes insulating material; A first transistor is disposed on the first well region; The second transistor is disposed on the second well region; A first interlayer insulating film is disposed on the well structure, wherein a first wiring structure is disposed in the first interlayer insulating film; A second interlayer insulating film is disposed between the well structure and the unit region, wherein the second wiring structure is disposed in the second interlayer insulating film; A conductive structure is disposed on the isolation structure; A first through-hole is disposed in the first interlayer insulating film and extends in the first direction and contacts the conductive structure; and A second through-hole is disposed in the second interlayer insulating film and extends in the first direction and contacts the conductive structure.

14. The semiconductor memory device according to claim 13, wherein, The peripheral circuit region further includes a protection region disposed in the well structure and connected to at least one of the first well region or the second well region.

15. The semiconductor memory device according to claim 14, wherein, In the plan view, the protection area extends in a ring shape when disposed in each of the first and second well regions.

16. The semiconductor memory device according to claim 14, wherein, In the plan view, the protected area includes multiple protected areas arranged in a matrix.

17. The semiconductor memory device according to claim 13, wherein, In the conductive structure, the first through hole overlaps with the second through hole in the first direction.

18. The semiconductor memory device according to claim 13, wherein, The length of the first through hole in the first direction is different from the length of the second through hole in the first direction.

19. A semiconductor memory device, comprising: Unit region; as well as The peripheral circuit area is located on the unit area. The unit region includes: A stacked structure, comprising a plurality of gate electrodes stacked in the first direction; A channel structure is disposed in the stacked structure and extends in the first direction; Bit lines extend in a second direction different from the first direction and are connected to the channel structure; and The first bonding pad is disposed on the bit line, and The peripheral circuit region includes: The well structure includes a first well region of a first conductivity type and a second well region of a second conductivity type different from the first conductivity type; An isolation structure isolates the first well region from the second well region; A PMOS transistor is disposed on the first well region; An NMOS transistor is disposed on the second well region; A first interlayer insulating film is disposed on the well structure; A second interlayer insulating film is disposed between the well structure and the unit region; The second bonding pad is disposed on the second interlayer insulating film and bonded to the first bonding pad; The bias structure includes a first bias region connected to the first well region and a second bias region connected to the second well region; A conductive structure is disposed on the isolation structure; A first through-hole is disposed in the first interlayer insulating film and extends in the first direction and contacts the conductive structure; and A second through-hole is disposed in the second interlayer insulating film and extends in the first direction and contacts the conductive structure.

20. The semiconductor memory device according to claim 19, wherein, The first bias region comprises an n-type conductive material, and The second bias region includes a p-type conductive material.

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