Semiconductor device with fence structure

Abstract

A semiconductor device includes: a substrate including an active region; a cell gate structure disposed within the substrate and extending across the active region in a first direction; a bit line structure intersecting the cell gate structure and extending in a second direction; a spacer structure covering two sidewalls of the bit line structure; a buried contact structure disposed in the lower portion of a space between the spacer structures and connected to the active region; a bonding pad structure disposed on the buried contact structure in the upper portion of the space between the spacer structures; and a fence structure penetrating the buried contact structure and the bonding pad structure and extending in the first direction, and overlapping the cell gate structure in a vertical direction.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2025-0036372, filed with the Korean Intellectual Property Office on March 21, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices including fence structures. Background Technology

[0004] As the demand for high performance, high speed, and / or multifunctionality in semiconductor devices increases, the integration level of semiconductor devices is rising. When manufacturing semiconductor devices with fine patterns corresponding to this trend of high integration, it is necessary to achieve patterns with fine widths or fine pitches. Summary of the Invention

[0005] The example embodiment provides a semiconductor device with improved electrical characteristics and reliability.

[0006] An example embodiment provides a method for manufacturing a semiconductor device with improved manufacturing process efficiency.

[0007] In an example embodiment, a semiconductor device includes: a substrate including an active region; a cell gate structure disposed within the substrate and extending across the active region in a first direction; a bit line structure intersecting the cell gate structure and extending in a second direction intersecting the first direction; a spacer structure covering two sidewalls of the bit line structure; a buried contact structure disposed on the substrate in the lower portion of a space between the spacer structures and connected to the active region; a metal semiconductor compound layer disposed on the buried contact structure; a bonding pad structure disposed on the metal semiconductor compound layer and the bit line structure in the upper portion of the space between the spacer structures; and a fence structure extending in the first direction by penetrating the buried contact structure, the metal semiconductor compound layer, and the bonding pad structure, and overlapping the cell gate structure in a vertical direction intersecting the first and second directions. The bonding pad structure includes: a conductive barrier layer disposed on a side surface of the spacer structure protruding from the metal semiconductor compound layer; and a conductive pad pattern disposed on the conductive barrier layer and contacting the fence structure.

[0008] In an example embodiment, a semiconductor device includes: a substrate including an active region; a cell gate structure disposed within the substrate and extending across the active region in a first direction; a bit line structure intersecting the cell gate structure and extending in a second direction intersecting the first direction; a spacer structure covering two sidewalls of the bit line structure; a buried contact structure disposed on the substrate in the lower portion of a space between the spacer structures and connected to the active region; a bonding pad structure disposed on the buried contact structure and the bit line structure in the upper portion of the space between the spacer structures; and a fence structure penetrating the buried contact structure and the bonding pad structure and extending in the first direction, and overlapping the cell gate structure in a vertical direction intersecting the first and second directions. The width of the fence structure in the second direction narrows as the fence structure extends downward, and the width of the bonding pad structure in the second direction widens as the bonding pad structure extends downward.

[0009] In an example embodiment, a semiconductor device includes: a substrate including a cell region and a peripheral circuit region; a cell active region disposed on the substrate within the cell region; a peripheral active region disposed on the substrate within the peripheral circuit region; a cell gate structure disposed within the substrate within the cell region and extending across the cell active region in a first direction; a bit line structure intersecting the cell gate structure and extending in a second direction intersecting the first direction; a spacer structure covering two sidewalls of the bit line structure; and a buried contact structure disposed on the substrate in the lower portion of the space between the spacer structures and on the cell gate structure, and connected to... The system comprises: a source region; a metal-semiconductor compound layer on a buried contact structure; a bonding pad structure disposed in the upper part of the space between the spacer structure and the bit line structure on the metal-semiconductor compound layer and the bit line structure; a fence structure extending in a first direction, penetrating the buried contact structure, the metal-semiconductor compound layer and the bonding pad structure, and overlapping the cell gate structure in a vertical direction intersecting the first and second directions; a peripheral gate structure disposed on a substrate in a peripheral circuit region; a peripheral contact plug disposed adjacent to the peripheral gate structure and connected to the peripheral active region; and a peripheral interconnect layer on the peripheral contact plug. The bonding pad structure includes: a conductive barrier layer disposed on a side surface of the spacer structure protruding from the metal-semiconductor compound layer; and a conductive pad pattern disposed on the conductive barrier layer and in contact with the fence structure. The peripheral contact plug includes: a peripheral conductive pattern; a peripheral barrier layer surrounding the side surface and lower surface of the peripheral conductive pattern; and a peripheral metal-semiconductor compound pattern on the lower surface of the peripheral barrier layer. Attached Figure Description

[0010] The above and other aspects, features, and advantages of the present invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0012] Figure 2A It shows Figure 1 Enlarged view of some components of an example embodiment of a semiconductor device in region A;

[0013] Figure 2B It shows Figure 1 Enlarged view of other components in an example embodiment of the semiconductor device, region A;

[0014] Figure 3A Provided along Figure 2A and Figure 2B Cross-sectional views of example embodiments of lines I-I' and II-II';

[0015] Figure 3B It shows along Figure 1 A cross-sectional view of an example embodiment of line III-III';

[0016] Figure 4A It shows Figure 1 Enlarged view of other components in an example embodiment of the semiconductor device, region A;

[0017] Figure 4B It shows along Figure 4A Cross-sectional view of the embodiments of lines IV-IV' and V-V';

[0018] Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A and Figure 9B It shows the manufacturing process. Figure 1 A diagram of an example embodiment of a method for a semiconductor device. Detailed Implementation

[0019] In the following description, exemplary embodiments will be illustrated in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and repeated descriptions of the same components are omitted.

[0020] Figure 1 This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 2A It shows Figure 1Enlarged view of some components of an example embodiment of a semiconductor device in region A. Figure 2B It shows Figure 1 Enlarged view of other components in an example embodiment of region A of the semiconductor device. Figure 2A This is a cross-sectional view showing the cell active region cACT, bit line BL, and word line WL located in the cell region CA. Figure 2B This is a cross-sectional view showing the bonding pad LP, the pad separation pattern NSP, and the fence structure FS set in the cell area CA.

[0021] refer to Figure 1 The semiconductor device 100 may include a substrate 101, which includes a cell region CA and a peripheral circuit region PA. The peripheral circuit region PA may be configured to surround the cell region CA. The cell region CA may refer to the area where a memory cell of a dynamic random access memory (DRAM) device is disposed, and the peripheral circuit region PA may be the area where word line drivers, sense amplifiers, row decoders and column decoders, and control circuitry are disposed.

[0022] refer to Figure 1 , Figure 2A and Figure 2B The semiconductor device 100 may include: a substrate 101 including a cell active region cACT; word lines WL extending in the cell active region cACT of the substrate 101 along a first direction (X direction) and spaced apart from each other in a second direction (Y direction); and bit lines BL extending in the cell active region cACT of the substrate 101 along the second direction (Y direction) and spaced apart from each other in the first direction (X direction). The semiconductor device 100 may include: a fence structure FS extending in the first direction (X direction) and overlapping the word line WL in the vertical direction (Z direction); a pad separation pattern NSP disposed on the bit line BL and spaced apart in the first direction (X direction); and bonding pads LP physically separated by the pad separation pattern NSP and the fence structure FS.

[0023] Substrate 101 may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. Substrate 101 may also include impurities. Substrate 101 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0024] The active region cACT of a cell can be isolated by a pattern of cell elements (e.g., Figure 3AThe cell element isolation pattern 111 is defined within the substrate 101. The cell active region cACT can be strip-shaped and can be configured within the substrate 101 as an island extending in one direction (e.g., along a first diagonal direction (W1 direction)). The first diagonal direction (W1 direction) can be an oblique direction relative to the extension directions of the word line WL and the bit line BL. The cell active regions cACT can be arranged parallel to each other, and the end of one cell active region cACT can be arranged adjacent to the center of another cell active region cACT adjacent to it.

[0025] The fence structures FS can extend in a first direction (X direction) and can be spaced apart from each other in a second direction (Y direction). In the example, each of the fence structures FS can overlap with the letter line WL in the vertical direction (Z direction).

[0026] The pad separation pattern NSP can physically separate the bonding pad LP. The pad separation pattern NSP can extend in a second diagonal direction (W2 direction) and can be alternately set along the first direction (X direction). The second diagonal direction (W2 direction) can be between the first direction (X direction) and the second direction (Y direction).

[0027] Figure 3A It shows along Figure 2A and Figure 2B Cross-sectional views of example embodiments of lines I-I' and II-II'. Figure 3B It shows along Figure 1 A cross-sectional view of an example embodiment of line III-III'.

[0028] refer to Figure 3A The cell region CA of the semiconductor device 100 may include: a cell active region 105; a cell element isolation pattern 111 defining the cell active region 105; a cell gate structure 120 extending across the cell active region 105 in a first direction (X direction) in the substrate 101; a bit line structure 140 extending on the substrate 101 and intersecting with the cell gate structure 120, and each bit line structure 140 including a bit line 145; a spacer structure 150 covering two sidewalls of a corresponding bit line structure 140; a buried contact structure 130 disposed between the bit line structures 140; a metal semiconductor compound layer 135 disposed on the buried contact structure 130; a bonding pad structure 175 disposed on the metal semiconductor compound layer 135; and a fence structure 160 extending in the first direction (X direction) and penetrating the bonding pad structure 175, the metal semiconductor compound layer 135, and the buried contact structure 130. The semiconductor device 100 may also include a pad separation pattern 176 and a capacitor structure 180, wherein the pad separation pattern 176 is physically separated from the pad structure 175.

[0029] The cell active region cACT can be defined within the substrate 101 by a cell element isolation pattern 111. The cell active region cACT can have a first impurity region 105a and a second impurity region 105b at a predetermined depth from the upper surface of the substrate 101. The first impurity region 105a and the second impurity region 105b can be spaced apart from each other. The first impurity region 105a and the second impurity region 105b can be configured as source / drain regions of a transistor formed by a cell gate structure 120. For example, a drain region can be formed between two cell gate structures 120 intersecting a cell active region cACT, and a source region can be formed outside each of the two cell gate structures 120. The source and drain regions are formed by the first impurity region 105a and the second impurity region 105b through doping or ion implantation of substantially the same impurity, and can be referred to interchangeably depending on the circuit configuration of the ultimately formed transistor. Impurities can include dopants having a conductivity type opposite to that of the substrate 101. In an example embodiment, the depths of the first impurity region 105a and the second impurity region 105b in the source and drain regions can be different from each other. The active region 105 of the unit can correspond to Figure 1 The active region of the unit cACT.

[0030] The cell element isolation pattern 111 can be formed using a shallow trench isolation (STI) process. The cell element isolation pattern 111 can surround the cell active region 105 and electrically isolate the cell active regions 105 from each other. The cell element isolation pattern 111 can be made of an insulating material (e.g., silicon oxide, silicon nitride, or a combination thereof). The cell element isolation pattern 111 can include multiple regions with different bottom depths depending on the width of the trench etched on the substrate 101. The upper surface of the cell element isolation pattern 111 can be coplanar with the upper surface of the substrate 101, and the lower surface of the cell element isolation pattern 111 can be disposed at a level lower than the lower surface of the cell gate structure 120.

[0031] Each of the cell gate structures 120 may extend in a first direction (X direction) and be spaced apart from each other in a second direction (Y direction). The cell gate structures 120 may be embedded in the substrate 101. For example, each of the cell gate structures 120 may be disposed within a cell gate trench 120H formed within the substrate 101. The cell gate structure 120 may include a cell gate dielectric layer 122, a cell gate electrode layer 123, and a cell gate capping layer 124 disposed within the cell gate electrode layer 123. The cell gate dielectric layer 122 may be conformally disposed on the inner wall of the cell gate trench 120H. The cell gate electrode layer 123 may be disposed in the lower portion of the cell gate trench 120H, and the cell gate capping layer 124 may be disposed in the upper portion of the cell gate trench 120H and may fill the cell gate trench 120H.

[0032] The unit gate dielectric layer 122 may include silicon oxide or a material with a high dielectric constant. The unit gate dielectric layer 122 may be a layer formed by oxidizing the unit active region 105 or a layer formed by deposition.

[0033] The unit gate electrode layer 123 may include a first unit gate electrode layer 123a and a second unit gate electrode layer 123b on the first unit gate electrode layer 123a. The first unit gate electrode layer 123a may include at least one selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In an example embodiment, the first unit gate electrode layer 123a may include titanium nitride (TiN). The second unit gate electrode layer 123b may include polysilicon. The unit gate capping layer 124 may include silicon nitride. The unit gate structure 120 may correspond to... Figure 1 The letter line WL.

[0034] A first buffer layer 112 and a second buffer layer 114 may be disposed on a substrate 101 to cover the cell active region 105 and the cell element isolation pattern 111. The first buffer layer 112 and the second buffer layer 114 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Each of the first buffer layer 112 and the second buffer layer 114 may comprise a single material or a composite material comprising two or more materials. The second buffer layer 114 may have a higher dielectric constant than the first buffer layer 112.

[0035] The bitline structures 140 may extend in a second direction (Y direction) and may be spaced apart from each other in a first direction (X direction). Each of the bitline structures 140 may have a strip extending in the second direction (Y direction). The bitline structure 140 may include a bitline 145 and a bitline capping layer 146 on the bitline 145.

[0036] Bit line 145 may include a first conductive layer 141, a second conductive layer 143, and a third conductive layer 144 sequentially disposed on a first buffer layer 112 and a second buffer layer 114. Bit line 145 may also include a bit line contact plug 142 disposed below the first conductive layer 141 and connected to a first impurity region 105a. Bit line contact plug 142 may be located within a bit line contact hole 142H. Bit line contact hole 142H may penetrate the first buffer layer 112 and the second buffer layer 114 and may be formed to expose the first impurity region 105a in the cell active region 105. Bit line contact hole 142H may extend into the first impurity region 105a of the cell active region 105. Bit line contact plug 142 may electrically connect the cell active region 105 to the bit line structure 140. Buried insulating pattern 156 may fill a portion of the bit line contact hole 142H and surround the side surface of the bit line contact plug 142. The buried insulating pattern 156 may include silicon nitride.

[0037] The first conductive layer 141 may include polysilicon. The second conductive layer 143 may include a metal semiconductor compound. The metal semiconductor compound may be, for example, a layer silicided on a portion of the first conductive layer 141. For example, the metal semiconductor compound may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides, or may include nitrides such as TiSiN. The third conductive layer 144 may include metallic materials such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). The bit line contact plug 142 may include the same material as the first conductive layer 141.

[0038] Bit line capping layer 146 may include a first capping layer 146a, a second capping layer 146b, and a third capping layer 146c disposed on bit line 145. The side surfaces of the first capping layer 146a and the second capping layer 146b may be coplanar with the side surface of bit line 145. The first capping layer 146a, the second capping layer 146b, and the third capping layer 146c may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and may include, for example, silicon nitride. Bit line structure 140 may correspond to... Figure 1 The bit line BL.

[0039] Spacer structures 150 may be disposed on both sidewalls of each of the bitline structures 140. Spacer structures 150 may cover both sidewalls of the bitline structure 140. Each of the spacer structures 150 may include a first spacer 152, a second spacer 154, and a third spacer 155. The first spacer 152 may be conformally disposed along the sidewall and upper surface of the bitline structure 140, the upper surfaces of the first buffer layer 112 and the second buffer layer 114, and the lower surface of the buried insulating pattern 156 within the bitline contact hole 142H. The second spacer 154 may be disposed on the first spacer 152 to extend between the buried insulating pattern 156 and the first spacer 152 to fill the bitline contact hole 142H. The third spacer 155 may be disposed on the side surface of the second spacer 154 to extend in the vertical direction (Z direction), but may be disposed on the outer surface of the buried insulating pattern 156. In the example, the first spacer 152, the second spacer 154, and the third spacer 155 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0040] The buried contact structure 130 can be disposed between adjacent bit line structures 140 and can contact the spacer structure 150. The buried contact structure 130 can be disposed on the cell gate structure 120 between the bit line structures 140.

[0041] The buried contact structure 130 is disposed on the unit gate structure 120 and may be disposed in the lower part between the spacer structures 150.

[0042] The buried contact hole 130H may have an internal space defined by the cell active region 105 and spacer structures 150 spaced apart in a first direction (X direction). The buried contact hole 130H can be formed by removing a portion of the cell active region 105 and the first buffer layer 112 and the second buffer layer 114, and a buried contact structure 130 can be disposed within the buried contact hole 130H. The lower surface of the buried contact structure 130 may have a shape according to the surface profile of the buried contact hole 130H. The buried contact structure 130 may be electrically connected to a second impurity region 105b of the cell active region 105 of the substrate 101. In the example, the width of the buried contact structure 130 disposed on the cell gate structure 120 in the second direction (Y direction) may narrow as it extends upwards. In the example embodiment, the upper surface of the buried contact structure 130 may be disposed at a level lower than the upper surface of the bit line structure 140, and the lower surface of the buried contact structure 130 may be disposed at a level lower than the upper surface of the substrate 101. A portion of the lower surface of the buried contact structure 130 may contact the upper surface of the unit gate dielectric layer 122 and the upper surface of the unit gate capping layer 124 of the unit gate structure 120. In the example, the buried contact structure 130 may be made of a conductive material and may include at least one of polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In the example embodiment, the buried contact structure 130 may include doped polysilicon and may include n-type impurities such as phosphorus (P), arsenic (As), and antimony (Sb).

[0043] A metal-semiconductor compound layer 135 may be disposed on the upper surface of the buried contact structure 130. The metal-semiconductor compound layer 135 may be disposed on the upper surface of the buried contact structure 130 exposed through the space between the spacer structures 150. In an example, the metal-semiconductor compound layer 135 may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides.

[0044] Bonding pad structures 175 may be disposed on the metal-semiconductor compound layer 135. Bonding pad structures 175 may be disposed on the metal-semiconductor compound layer 135 exposed through the spacer structures 150. Each of the bonding pad structures 175 may include: a conductive barrier layer 171 covering the sidewalls and upper surface of the spacer structure 150 exposed on the metal-semiconductor compound layer 135; a first conductive pad pattern 172 disposed on the conductive barrier layer 171 and the upper surface of the metal-semiconductor compound layer 135; and a second conductive pad pattern 174 disposed on the first conductive pad pattern 172. The conductive barrier layer 171 may be conformally disposed according to the surface profiles of the sidewalls and upper surface of the spacer structure 150. In an example, the width of the bonding pad structure 175 in the second direction (Y direction) may narrow towards the top. The first conductive pad pattern 172 may include a first conductive material, and the second conductive pad pattern 174 may include a second conductive material different from the first conductive material.

[0045] The upper surface of the first conductive pad pattern 172 can be positioned at a level higher than the upper surface of the bit line structure 140, and the height of the first conductive pad pattern 172 in the vertical direction (Z direction) can be greater than the height of the second conductive pad pattern 174 in the vertical direction (Z direction). In this example, the conductive barrier layer 171 may not overlap with the cell gate structure 120 in the vertical direction (Z direction).

[0046] The conductive barrier layer 171 may include at least one of a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN)). The first conductive pad pattern 172 and the second conductive pad pattern 174 may be formed from doped polysilicon, metal, metal silicide, conductive metal nitride, or combinations thereof, and may include, for example, at least one of titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). In an example embodiment, the conductive barrier layer 171 may include titanium nitride (TiN), the first conductive pad pattern 172 may include titanium nitride (TiN), and the second conductive pad pattern 174 may include tungsten (W). Hereinafter, the bonding pad structure 175 may correspond to... Figure 2B The LP is the bonding pad.

[0047] The upper surface of the pad separation pattern 176 may be coplanar with the upper surface of the bonding pad structure 175. The pad separation pattern 176 may extend downward and partially contact the bit capping layer 146 of the bit line structure 140. The pad separation pattern 176 may spatially space and electrically insulate the bonding pad structures 175 from each other in a first direction (X direction). In an example embodiment, each of the pad separation patterns 176 may contact at least a portion of the side surface of the bit capping layer 146 of the bit line structure 140 and the upper portion of the spacer structure 150. In the example, the pad separation pattern 176 may contact the side surface of the fence structure 160. The pad separation pattern 176 may correspond to Figure 2B The pad separation pattern NSP.

[0048] In the example embodiment, when viewed in a plan view, each of the pad separation patterns 176 may be arranged diagonally between a first direction (X direction) and a second direction (Y direction) (e.g., Figure 2B It extends along the second diagonal direction (W2).

[0049] The fence structures 160 may extend in a first direction (X direction) and be spaced apart from each other in a second direction (Y direction). Each of the fence structures 160 may penetrate the bonding pad structure 175, the metal semiconductor compound layer 135, and the buried contact structure 130. The fence structures 160 may overlap with the cell gate structure 120 in the vertical direction (Z direction). The fence structures 160 may spatially separate the bonding pad structures 175 from each other in the second direction (Y direction) and electrically insulate them from each other.

[0050] The side surface of the fence structure 160 can contact the first conductive pad pattern 172, the second conductive pad pattern 174, the metal-semiconductor compound layer 135, and the buried contact structure 130. In an example embodiment, the lower surface of the fence structure 160 can be positioned at a level lower than the lower surface of the buried contact structure 130, the upper surface of the substrate 101, and the upper surface of the cell gate structure 120. In the example, the fence structure 160 can penetrate the upper surface of the cell gate capping layer 124 of the cell gate structure 120, such that the lower surface of the fence structure 160 can be embedded in the cell gate capping layer 124. The lower surface of the fence structure 160 can be covered by the cell gate capping layer 124. The upper surface of the fence structure 160 can be coplanar with the upper surface of the bonding pad structure 175 and the upper surface of the pad separation pattern 176. The fence structure 160 can correspond to Figure 2B The fence structure FS.

[0051] According to the example embodiment, the fence structure 160 of the semiconductor device 100 is formed to extend in a first direction (X direction) after the formation of the buried contact structure 130, the metal semiconductor compound layer 135 and the bonding pad structure 175, while penetrating the buried contact structure 130, the metal semiconductor compound layer 135 and the bonding pad structure 175. Therefore, the first conductive pad pattern 172 and the second conductive pad pattern 174 of the bonding pad structure 175 can directly contact the bonding pad structure 175.

[0052] The semiconductor device 100 may further include an etch stop layer 177 covering the upper surface of the pad structure 175, the pad separation pattern 176, and the fence structure 160. A capacitor structure 180 may be disposed on the pad structure 175, the pad separation pattern 176, and the fence structure 160. The capacitor structure 180 may include a lower electrode 181, a capacitor dielectric layer 182, and an upper electrode 183 connected to the pad structure 175. The lower electrode 181 may penetrate the etch stop layer 177 and contact the upper surface of the pad structure 175. The capacitor dielectric layer 182 may cover the lower electrode 181 and the etch stop layer 177, and the upper electrode 183 may cover the capacitor dielectric layer 182. The capacitor structure 180 may be electrically connected to the pad structure 175, the metal semiconductor compound layer 135, and the buried contact structure 130. The lower electrode 181 and the upper electrode 183 may include at least one of a doped semiconductor, a metal nitride, a metal, and a metal oxide. The lower electrode 181 and the upper electrode 183 may comprise at least one of, for example, polycrystalline silicon, titanium nitride (TiN), tungsten (W), titanium (Ti), ruthenium (Ru), and tungsten nitride (WN). The capacitor dielectric layer 182 may comprise at least one of, for example, a high-k material (e.g., zirconium oxide (ZrO2), aluminum oxide (Al2O3), and hafnium oxide (Hf2O3)).

[0053] refer to Figure 3B The peripheral circuit region PA of substrate 101 may include: a peripheral active region 115; a peripheral element isolation pattern 113 defining the peripheral active region 115; a peripheral gate structure GSp disposed on substrate 101; peripheral gate spacers 50 disposed on two sidewalls of the peripheral gate structure GSp; a peripheral source / drain region SDP disposed in the upper region of the peripheral active region 115; a peripheral contact plug 60 disposed on one side of the peripheral gate structure GSp and connected to the peripheral source / drain region SDP; and a peripheral interconnect layer 66 disposed on the peripheral contact plug 60 and connected to the peripheral contact plug 60.

[0054] In an example embodiment, the peripheral circuit region PA of the substrate 101 may further include: a peripheral gate capping layer 51, conformally formed on the peripheral gate structure GSp, the peripheral gate spacer 50, and the peripheral element isolation pattern 113; a first peripheral interlayer insulating layer 53 disposed on the peripheral active region 115 and covering the peripheral gate capping layer 51; a second peripheral interlayer insulating layer 56 disposed on the first peripheral interlayer insulating layer 53; and an interconnect separation pattern 67 penetrating the peripheral interconnect layer 66.

[0055] The peripheral component isolation pattern 113 may extend downward from the upper surface of the substrate 101. The peripheral component isolation pattern 113 may define a peripheral active region 115. The peripheral component isolation pattern 113 may surround the peripheral active region 115 and separate the peripheral active regions 115 from each other. The peripheral component isolation pattern 113 may include an insulating material. The peripheral component isolation pattern 113 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and may be formed from a single layer or multiple layers.

[0056] The peripheral source / drain region SDp may include a first peripheral source / drain region SDp1 and a second peripheral source / drain region SDp2. The channel region may be located between the first peripheral source / drain region SDp1 and the second peripheral source / drain region SDp2.

[0057] A peripheral gate structure GSp can be disposed on the peripheral active region 115. In the example, the peripheral gate structure GSp can be disposed on the channel region between the first peripheral source / drain region SDp1 and the second peripheral source / drain region SDp2. In the example, the peripheral gate structure GSp can include a first peripheral gate structure GSp1 and a second peripheral gate structure GSp2 spaced apart from the first peripheral gate structure GSp1 in a first direction (X direction). In the example, each of the peripheral gate structures GSp can include a peripheral gate dielectric layer 30, a peripheral gate electrode 40, and a peripheral gate capping pattern 46 sequentially stacked in the vertical direction (Z direction).

[0058] The peripheral gate dielectric layer 30 may be disposed on the channel region between the first peripheral source / drain region SDp1 and the second peripheral source / drain region SDp2. The peripheral gate dielectric layer 30 may include at least one of silicon oxide and a high-k dielectric. The high-k dielectric may have a dielectric constant greater than that of silicon oxide. For example, the peripheral gate dielectric layer 30 may include at least one of silicon oxide, hafnium oxide (HfO), hafnium-based oxide (Hf-based oxide), aluminum oxide (AlO), aluminum-based oxide (Al-based oxide), lanthanum oxide (LaO), lanthanum-based oxide (La-based oxide), magnesium oxide (MgO), and magnesium-based oxide (Mg-based oxide).

[0059] The peripheral gate electrode 40 may include a first conductive pattern 41, a second conductive pattern 42, and a third conductive pattern 43 disposed on the peripheral gate dielectric layer 30 and sequentially stacked along the vertical direction (Z direction). The first conductive pattern 41 may include at least one conductive layer. For example, the first conductive pattern 41 may include at least one of doped polysilicon, TiN, TiAl, TiAlC, TiAlN, TaN, TaAlC, and TaAlN. The second conductive pattern 42 may include a titanium silicon nitride (TiSiN) layer. The third conductive pattern 43 may include a tungsten (W) layer.

[0060] A peripheral gate capping pattern 46 may be disposed on the peripheral gate electrode 40. The peripheral gate capping pattern 46 may include an insulating material, such as silicon nitride.

[0061] The peripheral gate spacer 50 can be disposed on the sidewalls of the peripheral gate structure GSp, and the peripheral gate spacer 50 can cover the sidewalls of the peripheral gate dielectric layer 30, the first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43. The peripheral gate spacer 50 can include at least one of silicon oxide and a low-k dielectric. The low-k dielectric can have a dielectric constant smaller than that of silicon oxide. In the example, the peripheral gate spacer 50 vertically overlaps with the peripheral source / drain region SDp, and the side surface of the peripheral gate spacer 50 can be covered by the peripheral gate capping layer 51.

[0062] The peripheral gate capping layer 51 can extend between the peripheral gate spacer 50 and the peripheral gate dielectric layer 30 to the sidewall of the peripheral gate structure GSp and the peripheral gate capping pattern 46 to cover the upper surface of the peripheral gate capping pattern 46 and the side surface of the peripheral gate spacer 50.

[0063] A first peripheral interlayer insulating layer 53 may fill the space between the peripheral gate spacers 50 on the substrate 101, and the first peripheral interlayer insulating layer 53 may contact the peripheral gate capping layer 51. The upper surface of the first peripheral interlayer insulating layer 53 may be coplanar with the upper surface of the peripheral gate capping layer 51. A second peripheral interlayer insulating layer 56 may be disposed on the first peripheral interlayer insulating layer 53. The first peripheral interlayer insulating layer 53 and the second peripheral interlayer insulating layer 56 may include silicon oxide. In this document, the second peripheral interlayer insulating layer 56 may be referred to as a peripheral insulating layer.

[0064] The peripheral contact plug 60 can penetrate the first peripheral interlayer insulating layer 53 and the second peripheral interlayer insulating layer 56, and is disposed adjacent to the peripheral gate structure GSp, and can be electrically connected to the peripheral source / drain region SDp. The peripheral contact plug 60 may include a peripheral metal semiconductor compound pattern 63, a peripheral conductive pattern 65 disposed on the peripheral metal semiconductor compound pattern 63, and a peripheral barrier layer 61 surrounding the side surface and the bottom surface of the peripheral conductive pattern 65 on the peripheral metal semiconductor compound pattern 63.

[0065] In an example embodiment, the peripheral metal-semiconductor compound pattern 63 may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. In an example embodiment, the peripheral metal-semiconductor compound pattern 63 may include the same material as the metal-semiconductor compound layer 135 of the cell region CA. In this example, the peripheral metal-semiconductor compound pattern 63 may be formed in the same process as the metal-semiconductor compound layer 135.

[0066] In an example embodiment, the peripheral barrier layer 61 may include at least one metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). The peripheral conductive pattern 65 may include at least one conductive material (e.g., titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al)). In this example, the peripheral barrier layer 61 may include the same material as the conductive barrier layer 171 of the bonding pad structure 175, and the peripheral conductive pattern 65 may include the same material as the first conductive pad pattern 172 of the bonding pad structure 175. The peripheral barrier layer 61 may be formed in the same process as the conductive barrier layer 171, and the peripheral conductive pattern 65 may be formed in the same process as the first conductive pad pattern 172.

[0067] A peripheral interconnect layer 66 may be disposed on the second peripheral interlayer insulating layer 56 and connected to the peripheral contact plug 60. The peripheral interconnect layer 66 may include at least one conductive material (e.g., titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al)). In an example, the peripheral interconnect layer 66 may include the same material as the second conductive pad pattern 174 of the bonding pad structure 175. In an example, the peripheral interconnect layer 66 may be formed in the same process as the second conductive pad pattern 174 of the bonding pad structure 175.

[0068] Interconnect separation pattern 67 can electrically insulate adjacent peripheral interconnect layers 66. Interconnect separation pattern 67 can penetrate peripheral interconnect layers 66, and the lower surface of interconnect separation pattern 67 can be embedded in a second peripheral interlayer insulating layer 56. Pad separation pattern 176 can include at least one of silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof. Interconnect separation pattern 67 can include the same material as pad separation pattern 176. Interconnect separation pattern 67 can be formed in the same process as pad separation pattern 176, but is not limited thereto. For example, interconnect separation pattern 67 can be formed in a different process than pad separation pattern 176. In embodiments, interconnect separation pattern 67 can include a void space containing an air layer (e.g., an air gap).

[0069] Figure 4A It shows according to Figure 1 Enlarged view of some other configurations of an embodiment of the semiconductor device in region A. Figure 4B It shows along Figure 4A Cross-sectional view of an embodiment of lines IV-IV' and V-V'. Figure 4A This is a cross-sectional view showing the bonding pad LP'', the pad separation pattern NSP'', and the fence structure FS set in the cell area CA.

[0070] refer to Figure 4A and Figure 4B The semiconductor device 100'' may include a bonding pad LP'', a pad separation pattern NSP'', and a fence structure FS. The remaining configuration besides the bonding pad LP'' and the pad separation pattern NSP'' can be combined with... Figure 3A The configurations shown are the same or corresponding.

[0071] A pad separation pattern NSP'' can physically separate the pad LP''. The pad separation pattern NSP'' can include a first pad separation pattern NSP1 and a second pad separation pattern NSP2. When viewed in a plan view, the first pad separation pattern NSP1 can be a line extending in the second diagonal direction W2 with a positive slope, and the second pad separation pattern NSP2 can be a line intersecting the first pad separation pattern NSP1 with a negative slope. In an example, the first pad separation pattern NSP1 can have a positive slope of a first size, and the second pad separation pattern NSP2 can have a first size but a negative slope, but is not limited thereto. In an example embodiment, a pad separation pattern NSP'' with a grid structure can be formed as the first pad separation pattern NSP1 and the second pad separation pattern NSP2 intersect and are set. The first pad separation pattern NSP1 and the second pad separation pattern NSP2 can physically separate the bonding pad LP'' and insulate the bonding pad LP'', and the bonding pad LP'' can be physically separated by the first pad separation pattern NSP1 and the second pad separation pattern NSP2 and can have an island pattern shape.

[0072] Figure 4A The pad separation pattern NSP'' can correspond to Figure 4B The pad separation pattern is 176'', and Figure 4A The bonding pad LP'' can correspond to Figure 4B The bonding pad structure is 175''.

[0073] The bonding pad structure 175'' may include a conductive barrier layer 171'', a conductive pad pattern 172'' disposed on the upper surface of the conductive barrier layer 171'', and a metal semiconductor compound layer 135. The conductive barrier layer 171'' may be conformally disposed according to the surface profile of the sidewalls and upper surface of the spacer structure 150. The conductive pad pattern 172'' may have a lower surface in contact with the conductive barrier layer 171'' and the metal semiconductor compound layer 135, an upper surface in contact with the lower electrode 181 of the capacitor structure 180, and a side surface in contact with the fence structure 160. In an example embodiment, the conductive barrier layer 171'' may include titanium nitride (TiN), and the conductive pad pattern 172'' may include tungsten (W).

[0074] Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , 8B , Figure 8C, Figure 8D , Figure 9A and Figure 9B It shows the manufacturing process. Figure 1 A diagram of an example embodiment of a method for a semiconductor device. Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A This is a perspective view showing a method for manufacturing a cell region CA of a semiconductor device. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 8C , Figure 8D and Figure 9B The following are shown respectively along Figure 2A and Figure 2B The cross sections intercepted by lines I-I' and II-II', and Figure 5C , Figure 6C and Figure 7C It shows along Figure 1 The cross section intercepted by line III-III'.

[0075] refer to Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A and Figure 9B A method of manufacturing a semiconductor device may include the following: in a cell region of substrate 101 (e.g., Figure 1 The operation of forming a cell gate structure 120 extending in a first direction (X direction) within the cell region CA of the substrate 101; the operation of forming a bit line structure 140 and a spacer structure 150 on the cell region CA of the substrate 101, the bit line structure 140 extending in a second direction (Y direction) and spaced apart from each other in the first direction (X direction), the spacer structure 150 covering the two sidewalls of the bit line structure 140; the operation of forming a buried contact structure 130 connected to the cell active region 105 of the substrate 101 in the lower part of the space between the spacer structures 150 on the substrate 101 (see reference). Figure 5A ); the operation of forming a metal-semiconductor compound layer 135 on the buried contact structure 130 (refer to) Figure 6A ); the operation of forming a pad structure 175 on the metal semiconductor compound layer 135 in the upper part of the space between the spacer structures 150 and on the bit line structure 140 (see reference) Figure 7A ); and the operation of forming a fence structure 160, which penetrates the pad structure 175, the metal semiconductor compound layer 135 and the buried contact structure 130 and extends in a first direction (X direction) (see reference). Figure 8A In an example embodiment, the method of manufacturing a semiconductor device may further include forming a pad separation pattern 176 that physically separates the bonding pad structure 175 in a second direction (Y direction) (see reference). Figure 9A ).

[0076] refer to Figure 5A and Figure 5B This can form a cell region defining the substrate 101 (e.g., Figure 1 The active region 105 within the cell region (CA) has a cell element isolation pattern 111, and a cell gate structure 120 can be formed therein, which extends across the active region 105 in a first direction (X direction) and is spaced apart in a second direction (Y direction) within the substrate 101. A first buffer layer 112 and a second buffer layer 114 can be formed on the cell element isolation pattern 111, the active region 105, and the cell gate structure 120. After forming a bit line contact hole 142H (which penetrates the first buffer layer 112 and the second buffer layer 114 and exposes the first impurity region 105a of the active region 105, and extends in the second direction (Y direction), a bit line contact plug 142, a first conductive layer 141, a second conductive layer 143, and a third conductive layer 144, and a bit line capping layer 146 filling the bit line contact hole 142H can be formed sequentially. A bitline structure 140 can be formed by forming a bitline contact plug 142, a first conductive layer 141, a second conductive layer 143, a third conductive layer 144, and a bitline capping layer 146. A spacer structure 150 can be formed covering the two sidewalls of the bitline structure 140. A buried contact hole 130H can be formed in the space between the bitline structures 140. The buried contact hole 130H can be confined in the space formed by the unit active region 105 and the spacer structure 150 between adjacent bitline structures 140, and the buried contact hole 130H can extend in a second direction (Y direction). A buried contact structure 130 can be formed within the buried contact hole 130H, and the upper surface of the buried contact structure 130 can be formed at a level lower than the upper surface of the bitline structure 140.

[0077] refer to Figure 5CA peripheral element isolation pattern 113 can be formed within the peripheral active region 115 of the peripheral circuit region PA of the substrate 101, and a peripheral gate structure GSp can be formed on the substrate 101 overlapping the channel region between the peripheral source / drain regions SDp. The peripheral gate electrode 40 can be formed in the same process as the first conductive layer 141, the second conductive layer 143, and the third conductive layer 144 of the bit line 145, and the peripheral gate capping pattern 46 can be formed in the same process as the first capping layer 146a of the bit line structure 140. A peripheral gate capping layer 51 and peripheral gate spacers 50 covering the sidewalls of the peripheral gate structure GSp can be formed sequentially. A first peripheral interlayer insulating layer 53 can be formed on the peripheral gate capping layer 51 to fill the space between the peripheral gate spacers 50, and a second peripheral interlayer insulating layer 56 can be formed on the first peripheral interlayer insulating layer 53.

[0078] refer to Figure 6A and Figure 6B A metal semiconductor compound layer 135 may be formed on the buried contact structure 130. The metal semiconductor compound layer 135 may be formed on the buried contact structure 130 extending along a second direction (Y direction). The metal semiconductor compound layer 135 may have a linear shape extending in the second direction (Y direction). The metal semiconductor compound layer 135 may be a layer in which a portion of the buried contact structure 130 is silicided. However, the inventive concept is not limited thereto, and the metal semiconductor compound layer 135 may be formed by various methods. In examples, the metal semiconductor compound layer 135 may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. In an example embodiment, the metal semiconductor compound layer 135 may include cobalt silicide (CoSi). x ).

[0079] refer to Figure 6C A peripheral contact hole H can be formed, which penetrates the first peripheral interlayer insulating layer 53 and the second peripheral interlayer insulating layer 56 and recesses a portion of the substrate 101 to expose the peripheral source / drain region SDp of the substrate 101. A peripheral metal semiconductor compound pattern 63 can be formed on the lower surface of the peripheral contact hole H. In this example, at least one peripheral contact hole H can penetrate the peripheral gate spacer 50 and the peripheral gate capping layer 51 formed on the sidewall of the peripheral gate structure GSp. The lower surface of the peripheral contact hole H can be formed at a level lower than the upper surface of the substrate 101, and a portion of the peripheral source / drain region SDp can be recessed. In this example, the peripheral metal semiconductor compound pattern 63 can be formed with... Figure 6A and Figure 6BThe peripheral metal semiconductor compound layer 63 is formed in the same process as the metal semiconductor compound layer 135. However, the inventive concept is not limited thereto, and the peripheral metal semiconductor compound pattern 63 can be formed by a different process than that of the metal semiconductor compound layer 135. In examples, the peripheral metal semiconductor compound pattern 63 may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides.

[0080] refer to Figure 7A and Figure 7B The bonding pad structure 175 covering the bit line structure 140 can be formed on the metal semiconductor compound layer 135. The buried contact structure 130 can be formed on the lower portion between the spacer structures 150, and the bonding pad structure 175 can be formed on the remaining portion between the spacer structures 150. A conductive barrier layer 171 can be formed to cover the sidewalls and upper surface of the spacer structure 150 exposed on the metal semiconductor compound layer 135. A first conductive pad pattern 172 covering the upper surface of the conductive barrier layer 171 and including a first conductive material can be formed, and a second conductive pad pattern 174 including a second conductive material different from the first conductive material can be sequentially formed on the first conductive pad pattern 172. The sequentially formed conductive barrier layer 171, first conductive pad pattern 172, and second conductive pad pattern 174 can constitute the bonding pad structure 175. In this example, the first conductive pad pattern 172 and the second conductive pad pattern 174 can include different types of conductive materials. However, the inventive concept is not limited thereto, and in the embodiments, the first conductive pad pattern 172 and the second conductive pad pattern 174 may include the same conductive material.

[0081] refer to Figure 6C and Figure 7C A peripheral barrier layer 61 and a peripheral conductive pattern 65 can be sequentially formed on a peripheral metal-semiconductor compound pattern 63 within a peripheral contact hole H. The peripheral barrier layer 61 can be formed on the peripheral metal-semiconductor compound pattern 63 according to the surface profile of the side surface of the peripheral contact hole H. The peripheral conductive pattern 65 can be formed on the peripheral barrier layer 61 and can be surrounded by the peripheral barrier layer 61. The peripheral barrier layer 61 can be... Figure 6A and Figure 6B The conductive barrier layer 171 of the bonding pad structure 175 is formed in the same process as the conductive barrier layer 171, and may include the same material as the conductive barrier layer 171. The peripheral conductive pattern 65 may be formed in the same process as the conductive barrier layer 171. Figure 6A and Figure 6BThe first conductive pad pattern 172 of the bonding pad structure 175 is formed in the same process and may include the same material as the first conductive pad pattern 172. The peripheral contact plug 60 can be configured by sequentially forming the peripheral metal semiconductor compound pattern 63, the peripheral barrier layer 61 and the peripheral conductive pattern 65.

[0082] The peripheral interconnect layer 66 can be formed on the peripheral contact plug 60 and the second peripheral layer interlayer insulating layer 56. The peripheral interconnect layer 66 can be formed with... Figure 6A and Figure 6B The second conductive pad pattern 174 of the bonding pad structure 175 is formed in the same process and may include the same material as the second conductive pad pattern 174.

[0083] refer to Figure 8A A fence structure 160 can be formed, which penetrates the pad structure 175, the metal semiconductor compound layer 135, and the buried contact structure 130, and overlaps with the cell gate structure 120 in the vertical direction (Z direction). The fence structures 160 can extend in a first direction (X direction) and can be spaced apart from each other in a second direction (Y direction). By forming the fence structure 160 that penetrates the pad structure 175, the metal semiconductor compound layer 135, and the buried contact structure 130, the pad structure 175 is physically separated by the fence structure 160, and a first pad structure 175A, a second pad structure 175B, and a third pad structure 175C spaced apart in the second direction (Y direction) can be formed. (Refer to...) Figure 8B , Figure 8C and Figure 8D To describe the method of forming the fence structure 160.

[0084] refer to Figure 8B A first mask pattern M1 may be formed on the bonding pad structure 175. The first mask pattern M1 may have a line extending in a first direction (X direction), and the first mask pattern M1 may include first openings spaced apart in a second direction (Y direction) and exposing the bonding pad structure 175, and each of the first openings may expose the upper surface of the bonding pad structure 175 and may overlap with the cell gate structure 120 in the vertical direction (Z direction).

[0085] refer to Figure 8CBy using a first mask pattern M1, the bonding pad structure 175, the metal-semiconductor compound layer 135, the buried contact structure 130, and the substrate 101 can be removed to form a first trench OPN1 extending in a first direction (X direction) and spaced apart in a second direction (Y direction). The side surfaces of the buried contact structure 130, the bonding pad structure 175, and the metal-semiconductor compound layer 135 can be exposed through the first trench OPN1. The lower surface of each of the first trenches OPN1 can be positioned at a level lower than the upper surface of the cell gate structure 120. Each of the first trenches OPN1 can overlap the cell gate structure 120 in the vertical direction (Z direction) and expose a portion of the cell gate capping layer 124. Each of the first trenches OPN1 can recess a portion of the cell gate capping layer 124 of the cell gate structure 120. In this document, the first trenches OPN1 may be referred to as fence structure trenches.

[0086] refer to Figure 8D An insulating material can be filled into the first trench OPN1 to form a fence structure 160. The insulating material filling the first trench OPN1 may include silicon nitride. In this example, the fence structure 160 may contact the side surfaces of the metal-semiconductor compound layer 135 and the side surfaces of the buried contact structure 130, and when viewed in a plan view, in Figure 8A In the region where the first bonding pad structure 175A, the second bonding pad structure 175B, and the third bonding pad structure 175C intersect with the unit gate structure 120, the fence structure 160 can contact the side surfaces of the conductive barrier layer 171, the first conductive pad pattern 172, and the second conductive pad pattern 174 that respectively constitute the first bonding pad structure 175A, the second bonding pad structure 175B, and the third bonding pad structure 175C.

[0087] According to an example embodiment, a method of manufacturing a semiconductor device may include the operation of forming a fence structure 160 extending in a first direction (X direction) and spaced apart from each other in a second direction (Y direction), so that the bonding pad structure 175 can be physically separated into a first bonding pad structure 175A, a second bonding pad structure 175B and a third bonding pad structure 175C spaced apart from each other in the second direction (Y direction).

[0088] According to an example embodiment, a method of manufacturing a semiconductor device may include forming Figure 7A The bonding pad structure is formed after 175. Figure 8A The operation of the fence structure 160, Figure 8AThe fence structure 160 penetrates the bonding pad structure 175, the metal-semiconductor compound layer 135, and the buried contact structure 130. Therefore, since the bonding pad structure 175 is formed prior to the process of forming the fence structure 160, the difficulty of forming a first conductive pad pattern 172 and a second conductive pad pattern 174 comprising different conductive materials on the conductive barrier layer 171 constituting the bonding pad structure 175 can be reduced. Furthermore, by forming the fence structure 160, the bonding pad structure 175 can be formed as a first bonding pad structure 175A, a second bonding pad structure 175B, and a third bonding pad structure 175C extending in a first direction (X direction) and spaced apart in a second direction (Y direction). Therefore, the process operations for physically separating the bonding pad structure 175 can be significantly reduced. Therefore, by the method of manufacturing a semiconductor device according to the example embodiment, a semiconductor device with improved reliability and increased process efficiency can be provided.

[0089] refer to Figure 9A and Figure 9B A second mask pattern M2 can be formed on the bonding pad structure 175. By using the second mask pattern M2, a second trench OPN2 can be formed to recess the bonding pad structure 175.

[0090] The mask pattern M2 can be in a diagonal direction between the first direction (X direction) and the second direction (Y direction) (e.g., Figure 2B The second mask pattern M2 may include a second opening spaced apart from each other in the second direction (Y direction) and exposing the upper surface of the pad structure 175. The pad structure 175 exposed through the second opening may be recessed to form a second trench OPN2. Through each of the second trenches OPN2, the conductive barrier layer 171, the cross-sections of the first conductive pad pattern 172 and the second conductive pad pattern 174, the upper end of the spacer structure 150, and a cross-section of the fence structure 160 may be exposed.

[0091] The first bonding pad structure 175A, the second bonding pad structure 175B, and the third bonding pad structure 175C are physically separated by the second trench OPN2, and may include 1-1 bonding pad structures 175_1, 1-2 bonding pad structures 175_2, and 1-3 bonding pad structures 175_3 spaced apart in the first direction (X direction). The 1-1 bonding pad structures 175_1, 1-2 bonding pad structures 175_2, and 1-3 bonding pad structures 175_3 may be formed corresponding to the buried contact structure 130. The second trench OPN2 may be referred to as a pad separation trench.

[0092] Next, refer to Figure 3AInsulating material can be formed in the second trench OPN2 to form the pad separation pattern 176. Capacitor structures 180 can be manufactured by forming the bonding pad structure 175, the pad separation pattern 176, and the fence structure 160. Figure 1 Semiconductor device 100.

[0093] As described above, the semiconductor device according to the example embodiment may include a metal semiconductor compound layer connected to a buried contact structure of a cell active region, and a conductive pad pattern on the metal semiconductor compound layer comprising two or more metal materials, thereby providing a semiconductor device with improved electrical characteristics and reliability.

[0094] In the method for manufacturing a semiconductor device according to the example embodiment, since the bonding pads can be separated using a minimum number of process operations, a method for manufacturing a semiconductor device with improved process efficiency is provided.

[0095] In an example embodiment, a method of manufacturing a semiconductor device may include: preparing a substrate including a cell region and a peripheral circuit region; forming a cell gate structure extending in a first direction within the cell region of the substrate; forming a bit line structure and a spacer structure on the cell region of the substrate, the bit line structure extending in a second direction intersecting the first direction and spaced apart from each other in the first direction, the spacer structure covering two sidewalls of the bit line structure; forming a buried contact structure connected to a cell active region of the substrate in the lower portion of the space between the spacer structures on the substrate; forming a metal semiconductor compound layer on the buried contact structure; forming a pad structure on the metal semiconductor compound layer, the pad structure covering the upper portion of the space between the spacer structures and the bit line structure; and forming a fence structure penetrating the pad structure, the metal semiconductor compound layer and the buried contact structure, extending in the first direction, and overlapping the cell gate structure in a vertical direction intersecting the first and second directions.

[0096] In an example embodiment, forming a cell gate structure may include: forming a word line trench from the upper surface of a substrate; forming a cell gate dielectric film in the word line trench; forming a cell gate electrode layer on the cell gate dielectric film; and forming a cell gate capping layer on the cell gate electrode layer.

[0097] In an example embodiment, forming a fence structure may include: forming a fence structure trench that penetrates a pad structure, a metal semiconductor compound layer, a buried contact structure, and a portion of a cell gate capping layer; and filling the fence structure trench with an insulating material.

[0098] In an example embodiment, the method of manufacturing a semiconductor device may further include forming a pad separation pattern that is buried from the upper surface of the bonding pad structure toward a spacer structure formed on a sidewall of the corresponding bit line structure.

[0099] In an example embodiment, forming a pad separation pattern may include: forming a mask pattern extending diagonally between a first direction and a second direction on the pad structure; forming a pad separation trench by removing a portion of the pad structure exposed by the mask pattern from the upper surface of the pad structure and removing a portion of the spacer structure formed on a sidewall of the corresponding bit line structure; and forming an insulating material within the pad separation trench.

[0100] According to an example embodiment, forming a bonding pad structure may include: forming a conductive barrier layer covering a metal semiconductor compound layer, sidewalls of a spacer structure exposed above the space between the spacer structures, and the upper surface of a bit line structure; and forming a conductive pad pattern on the conductive barrier layer.

[0101] According to an example embodiment, the conductive barrier layer and conductive pad pattern can contact the side surface of the fence structure.

[0102] In an example embodiment, the method of manufacturing a semiconductor device may further include: forming a peripheral gate structure on a peripheral circuit region of a substrate and forming peripheral gate spacers on two sidewalls of the peripheral gate structure; forming a peripheral interlayer insulating layer on the peripheral gate structure and the peripheral gate spacers; forming a peripheral contact plug on one side of the peripheral gate structure, the peripheral contact plug penetrating the peripheral interlayer insulating layer and being connected to a peripheral active region of the peripheral circuit region; and forming a peripheral interconnect layer connected to the peripheral contact plug on the peripheral interlayer insulating layer.

[0103] In an example embodiment, forming a peripheral contact plug may include: forming a peripheral contact hole that penetrates a peripheral interlayer insulating layer and exposes a portion of a peripheral circuit region of the substrate; forming a peripheral metal semiconductor compound pattern on the lower surface of the peripheral contact hole; and forming a peripheral barrier layer on the upper surface of the peripheral metal semiconductor compound pattern and the sidewalls of the peripheral contact hole, and forming a peripheral conductive pattern on the peripheral barrier layer.

[0104] In an example embodiment, the metal semiconductor compound layer and the peripheral metal semiconductor compound pattern may include the same material.

[0105] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Substrate, including the active region; A cell gate structure is disposed within the substrate and extends across the active region in a first direction; The bit line structure intersects the cell gate structure and extends in a second direction that intersects the first direction; A spacer structure covers the two sidewalls of the bit line structure; A buried contact structure is disposed on the substrate in the lower part of the space between the spacer structures and connected to the active region; A metal-semiconductor compound layer is disposed on the buried contact structure; A bonding pad structure is disposed on the metal semiconductor compound layer and the bit line structure in the upper part of the space between the spacer structure; as well as The fence structure extends in the first direction by penetrating the buried contact structure, the metal semiconductor compound layer, and the bonding pad structure, and overlaps with the cell gate structure in a vertical direction intersecting the first and second directions. The bonding pad structure includes: a conductive barrier layer disposed on the side surface of the spacer structure protruding from the metal semiconductor compound layer; and a conductive pad pattern disposed on the conductive barrier layer and in contact with the fence structure.

2. The semiconductor device according to claim 1, wherein, The side surface of the fence structure is in contact with the side surface of the buried contact structure, the side surface of the metal semiconductor compound layer, and the side surface of the conductive pad pattern.

3. The semiconductor device according to claim 1, wherein, The lower surface of the fence structure is positioned at a level lower than the lower surface of the buried contact structure.

4. The semiconductor device according to claim 1, wherein, The unit gate structure includes a unit gate trench in the substrate, a unit gate dielectric layer in the unit gate trench, a unit gate electrode layer on the unit gate dielectric layer, and a unit gate capping layer on the unit gate electrode layer. The lower surface of the fence structure is embedded in the unit gate capping layer.

5. The semiconductor device of claim 1, further comprising a capacitor structure on the bonding pad structure and the fence structure. in, The upper surface of the fence structure contacts the lower surface of the capacitor structure.

6. The semiconductor device according to claim 1, wherein, The fence structure has a width that decreases as it extends downwards in the second direction.

7. The semiconductor device according to claim 1, wherein, The conductive pad pattern includes: a first conductive pad pattern covering the side surface of the spacer structure and the upper surface of each of the bit line structures; and a second conductive pad pattern on top of the first conductive pad pattern. Wherein, the first conductive pad pattern includes a first conductive material, and The second conductive pad pattern includes a second conductive material that is different from the first conductive material.

8. The semiconductor device according to claim 7, wherein, The upper surface of the first conductive pad pattern is positioned at a level higher than the upper surface of each of the bit line structures.

9. The semiconductor device according to claim 1, wherein, The metal-semiconductor compound layer includes cobalt silicide (CoSi). x .

10. The semiconductor device according to claim 1, wherein, The conductive barrier layer does not overlap with the unit gate structure in the vertical direction.

11. The semiconductor device of claim 1, further comprising a pad separation pattern that recesses a portion of the bonding pad structure and contacts the spacer structure. in, The pad separation pattern extends diagonally between the first direction and the second direction.

12. The semiconductor device according to claim 1, wherein, The width of the bonding pad structure in the second direction decreases as the bonding pad structure extends upward.

13. A semiconductor device, comprising: Substrate, including the active region; A cell gate structure is disposed within the substrate and extends across the active region in a first direction; The bit line structure intersects the cell gate structure and extends in a second direction that intersects the first direction; A spacer structure covers the two sidewalls of the bit line structure; A buried contact structure is disposed on the substrate in the lower part of the space between the spacer structures and connected to the active region; A bonding pad structure is disposed on the upper part of the space between the spacer structure on the buried contact structure and the bit line structure; as well as The fence structure penetrates the buried contact structure and the bonding pad structure and extends in the first direction, and overlaps with the cell gate structure in a vertical direction intersecting the first and second directions. Wherein, the width of the fence structure in the second direction narrows as the fence structure extends downwards, and The width of the bonding pad structure in the second direction increases as the bonding pad structure extends downward.

14. The semiconductor device according to claim 13, wherein, The lower surface of the fence structure is positioned at a level lower than the lower surface of the buried contact structure.

15. The semiconductor device according to claim 13, wherein, The bonding pad structure includes: a conductive barrier layer on the sidewall of the bit line structure protruding from the buried contact structure; and a conductive pad pattern disposed on the buried contact structure and the conductive barrier layer and in contact with the fence structure.

16. The semiconductor device of claim 13, further comprising a metal-semiconductor compound layer between the buried contact structure and the bonding pad structure. in, The fence structure penetrates the metal semiconductor compound layer.

17. A semiconductor device, comprising: The substrate includes the cell region and the peripheral circuit region; An active region of a cell is disposed on the substrate within the cell region; The peripheral active region is disposed on the substrate within the peripheral circuit region; A cell gate structure is disposed in the substrate within the cell region and extends across the cell active region in a first direction; The bit line structure intersects the cell gate structure and extends in a second direction that intersects the first direction; A spacer structure covers the two sidewalls of the bit line structure; A buried contact structure is disposed on the substrate in the lower part of the space between the spacer structures and on the cell gate structure, and is connected to the active region; A metal-semiconductor compound layer is present on the buried contact structure; A bonding pad structure is disposed on the metal semiconductor compound layer and the bit line structure in the upper part of the space between the spacer structure; The fence structure extends in the first direction, penetrating the buried contact structure, the metal semiconductor compound layer, and the bonding pad structure, and overlaps with the cell gate structure in a vertical direction intersecting the first and second directions; A peripheral gate structure is disposed on the substrate in the peripheral circuit region; A peripheral contact plug is disposed adjacent to the peripheral gate structure and connected to the peripheral active region; as well as Peripheral interconnect layer, on the peripheral contact plug, The bonding pad structure includes: a conductive barrier layer disposed on a side surface of the spacer structure protruding from the metal semiconductor compound layer; and a conductive pad pattern disposed on the conductive barrier layer and in contact with the barrier structure. The peripheral contact plug includes: a peripheral conductive pattern; a peripheral barrier layer surrounding the side and lower surfaces of the peripheral conductive pattern; and a peripheral metal semiconductor compound pattern on the lower surface of the peripheral barrier layer.

18. The semiconductor device of claim 17, further comprising a peripheral insulating layer disposed on the peripheral gate structure and in contact with the lower surface of the peripheral interconnect layer. in, The conductive pad pattern includes: a first conductive pad pattern covering the side surface of the spacer structure and the upper surface of each of the bit line structures; and a second conductive pad pattern on top of the first conductive pad pattern. The peripheral conductive pattern and the first conductive pad pattern include a first conductive material, and The peripheral interconnect layer and the second conductive pad pattern include a second conductive material that is different from the first conductive material.

19. The semiconductor device according to claim 18, wherein, The first conductive material comprises titanium nitride (TiN), and The second conductive material includes tungsten (W).

20. The semiconductor device according to claim 17, wherein, The metal-semiconductor compound layer and the peripheral metal-semiconductor compound pattern include cobalt silicide (CoSi). x .

Images