Memory device with improved sensing margin and leakage immunity

Abstract

The present disclosure relates to memory devices with improved sensing margin and leakage immunity. A memory cell includes a capacitor, a first transistor, and a second transistor. The capacitor has a first plate and a second plate adjacent to the first plate. The first transistor has a channel, a gate terminal, a source terminal, and a drain terminal, where the gate terminal surrounds the channel, one side of the channel is connected to the source terminal, and another side of the channel is connected to the drain terminal. The second transistor has a channel, a gate terminal, a source terminal, and a drain terminal, where the gate terminal surrounds the channel, one side of the channel is connected to the source terminal, and another side of the channel is connected to the drain terminal. The drain terminal of the first transistor is connected to the first plate of the capacitor. The gate terminal of the first transistor and the gate terminal of the second transistor are connected together.

Description

Technical Field

[0001] This disclosure relates to a three-dimensional dynamic random access memory (3D-DRAM) device and a method of manufacturing such a device. Background Technology

[0002] DRAM is a type of volatile memory that stores each bit of data in a separate capacitor within an integrated circuit. In some DRAM designs, a memory cell contains a transistor and a capacitor. Summary of the Invention

[0003] One aspect of this disclosure relates to a memory cell comprising: a capacitor having a first plate and a second plate, wherein the first plate is adjacent to the second plate; a first transistor having a channel, a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal surrounds the channel, one side of the channel is connected to the source terminal, and the other side of the channel is connected to the drain terminal; and a second transistor having a channel, a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal surrounds the channel, one side of the channel is connected to the source terminal, and the other side of the channel is connected to the drain terminal; wherein the drain terminal of the first transistor is connected to the first plate of the capacitor, the gate terminal of the first transistor and the gate terminal of the second transistor are connected together, and the drain terminal of the second transistor is connected to the second plate of the capacitor.

[0004] Another aspect of this disclosure relates to a method of manufacturing a three-dimensional memory device, comprising: providing alternating layers of a first semiconductor material and a second semiconductor material; defining first and second transistor regions in the alternating layers of the first and second semiconductor materials, wherein each of the first and second transistor regions is defined on opposite sides of the alternating layers; forming a gate on each of the first and second transistor regions, the gate comprising a conductive material; forming a capacitor region between each of the first and second transistor regions; connecting each of the first transistor regions to a first end of the capacitor region and connecting each of the second transistor regions to a second end of the capacitor region; forming a bit line including a first bit line connected to a source region in the first transistor region and a second bit line connected to a source region in the second transistor region; and forming a word line connected to the conductive material in each layer of the first and second transistor regions, wherein the word line provides common gate control for the first and second transistor regions in each layer.

[0005] This disclosure relates to a three-dimensional memory device comprising: a plurality of memory cells stacked together to form a stack having a first side and a second side; a first bit line and a second bit line, the first bit line being along the first side of the stack and the second bit line being along the second side of the stack; and a word line connected to each layer of the stack; wherein each memory cell comprises: a capacitor region including a capacitor having a first plate and a second plate, the first plate being adjacent to the second plate; a first transistor region including a first transistor having a channel, a gate terminal connected to the word line, a source terminal connected to the first bit line, and a drain terminal connected to the first plate of the capacitor, one side of the channel being connected to the source terminal and the other side of the channel being connected to the drain terminal; and a second transistor region including a second transistor having a channel, a gate terminal connected to the word line, a source terminal connected to the second bit line, and a drain terminal connected to the second plate of the capacitor, one side of the channel being connected to the source terminal and the other side of the channel being connected to the drain terminal; wherein the first transistor region and the second transistor region are positioned on opposite sides of the capacitor region. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings illustrating embodiments of this disclosure. The drawings are provided to give an understanding of embodiments of this disclosure and are not intended to limit the scope of this disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0007] Figure 1 depicts an example memory cell according to an embodiment of the present disclosure.

[0008] Figure 2 A schematic diagram depicting a memory cell according to an embodiment of the present disclosure.

[0009] Figures 3a to 3o An example process for constructing a three-dimensional memory device according to embodiments of the present disclosure is described.

[0010] Figure 4 A schematic diagram depicting an analog one-transistor-capacitor (1T1C) and two-transistor-capacitor (2T1C) memory cell according to embodiments of the present disclosure.

[0011] Figure 5 A comparison between a 2T1C memory cell and a 1T1C memory cell under ideal conditions is depicted according to embodiments of the present disclosure.

[0012] Figure 6 A comparison between a 2T1C memory cell and a 1T1C memory cell is depicted under a first operating condition according to an embodiment of the present disclosure.

[0013] Figure 7 Flowcharts depicting various processes used during the design and manufacture of integrated circuits according to embodiments of the present disclosure.

[0014] Figure 8 A diagram depicting an example computer system in which embodiments of the present disclosure may operate. Detailed Implementation

[0015] The figures and figures below are for illustrative purposes only and relate to preferred embodiments. It should be noted that, from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily regarded as feasible alternatives that can be employed without departing from the principles claimed.

[0016] Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying drawings. It should be noted that, where feasible, similar or analogous element symbols may be used in the drawings and may indicate similar or analogous functionality. The drawings depict embodiments of the disclosed system (or method) for illustrative purposes only. Alternative embodiments of the structures and methods described herein may be readily recognized by those skilled in the art from the following description, without departing from the principles described herein.

[0017] In some DRAM designs, a memory cell comprises a transistor and a capacitor (1T1C). The capacitor can be charged or discharged to store a bit of information. A charged capacitor represents a logic "1" value, while a discharged capacitor represents a logic "0" value. However, because capacitors leak charge, the information will eventually become incorrect unless the capacitor charge is periodically refreshed. As semiconductor device sizes continue to shrink, DRAM manufacturers have explored 3D architectures to achieve higher memory densities while maintaining acceptable performance characteristics. In some 3D DRAM designs, memory cells are vertically stacked to increase the number of bits that can be stored in a given area. However, such 3D DRAM designs face several challenges, including reduced sense margin, increased leakage current, floating body effects, and susceptibility to interference effects such as hammer attacks. These challenges can lead to performance degradation, reduced reliability, and increased power consumption due to more frequent refresh operations.

[0018] This disclosure relates to a three-dimensional (3D) memory device architecture and its fabrication method, which addresses challenges of other 3D DRAM designs. The systems and methods disclosed herein provide improved sensing margin and enhanced immunity to leakage effects through a two-transistor-one-capacitor (2T1C) memory cell configuration.

[0019] In some aspects, a memory cell includes: a storage capacitor having a first plate and a second plate separated by a dielectric material; and two transistors connected to opposite plates of the capacitor. The first transistor has its drain terminal electrically connected to the first plate of the storage capacitor and its source terminal connected to a first bit line, while the second transistor has its drain terminal electrically connected to the second plate of the storage capacitor and its source terminal connected to a second bit line. The gate terminals of both transistors are connected to a common word line, wherein the first and second bit lines are configured to carry complementary voltage levels during memory operation. This configuration improves the sensing margin by three times compared to other designs and maintains robust operation even in the presence of leakage current.

[0020] In some aspects, a three-dimensional memory device includes multiple memory cells stacked together to form a stack, wherein bit lines are positioned along opposite sides of the stack and word lines are connected to each layer. This vertical integration provides high-density memory while maintaining reliable operation by improving immunity to buoyancy effects and row hammer attacks.

[0021] In some aspects, methods for manufacturing three-dimensional memory devices are provided, including techniques for forming vertically stacked transistor regions, capacitor regions, and their interconnections. The manufacturing methods provide a practical implementation of an improved memory cell architecture while maintaining compatibility with other semiconductor processing technologies.

[0022] The advantages of the disclosed 3D memory device include, for example, improved sensing margin, retention, and immunity to buoyancy and hammer attacks. The 3D memory device comprises vertically stacked 2T1C cells. Within each memory cell, a second transistor is fabricated next to a capacitor to replace the contents of a common ground metal plate in the 1T1C configuration. Two transistors connected to opposite sides of the capacitor share the same word line connection and are driven by two separate bit lines. The word line is used to activate a bit cell in a row of memory cells based on a combination of address bits by turning on the transistor connected to the word line. This allows data stored in the capacitor of the memory cell to be accessed (read / written) via the bit lines. The technical benefits of this approach are as follows: the sensing margin is increased by up to three times (3X), as demonstrated by our SPICE simulations; robustness to leakage and floating bodies in 3D-DRAM, as confirmed by the SPICE simulation method; faster sensing; memory cells may require less capacitance due to the larger sensing signal; multiple adjacent arrays can be addressed simultaneously because one bit line is no longer used as a reference (compared to the 1T1C method); and the 2T1C design saves peripheral area because the sensing amplifier can now be smaller due to the larger differential signal.

[0023] Now for reference Figure 1The description describes an example memory cell 100 according to an embodiment. The memory cell 100 includes a storage capacitor 102, a first transistor 104, and a second transistor 106. The storage capacitor 102 has a first plate 110 and a second plate 112 separated by a dielectric material 108.

[0024] The first transistor 104 has a drain terminal 114, a source terminal 124, a gate terminal 134, and a channel 144. The drain terminal 114 is electrically connected to the first plate 110 of the storage capacitor 102, and the source terminal 124 is electrically connected to the first bit line 150.

[0025] Channel 144 is a region of semiconductor material that forms a critical conductive path between the source and drain terminals. When the transistor is in operation, the channel acts as a controllable bridge, allowing or blocking current flow based on the voltage applied to the gate terminal. The gate terminal surrounds the channel, thereby allowing electrostatic control of the channel's conductivity. This arrangement provides a gate voltage to efficiently modulate the channel's electrical characteristics by attracting or repelling charge carriers across the entire channel cross-section.

[0026] The second transistor 106 has a drain terminal 116, a source terminal 126, a gate terminal 136, and a channel 146. The drain terminal 116 is electrically connected to the second plate 112 of the storage capacitor 102, and the source terminal 126 is electrically connected to the second bit line 152. The gate terminals 143 and 136 of the first transistor 104 and the second transistor 106 are electrically connected to a common word line 154. The first bit line 150 and the second bit line 152 carry complementary voltage levels during memory operation. In some embodiments, the first transistor and the second transistor and the storage capacitor are separated by isolation.

[0027] Isolation region 160 physically and electrically separates the different components of the memory cell (first transistor, second transistor, and capacitor) from each other. Isolation region 160 prevents unwanted electrical interactions between adjacent components, thereby reducing interference and crosstalk. The isolation region may be filled with a dielectric material.

[0028] In operation, the storage capacitor 102 maintains a non-zero voltage difference between the first and second plates in response to charge leakage through one of the first or second transistors. The first plate stores a first voltage level, and the second plate stores a second voltage level different from the first voltage level. When charge leakage through one of the first or second transistors causes a voltage level change induced by capacitive coupling between the plates, the memory cell maintains a non-zero difference between the first and second plates. The capacitive coupling between the first and second plates provides protection against row hammer attacks. The charge leakage may include one of the following: source-to-drain leakage current through the channel of one of the first or second transistors; junction leakage current due to a defect in one of the first or second transistors; leakage current due to a floating body effect in one of the first or second transistors; and gate-to-drain leakage current in one of the first or second transistors.

[0029] According to some embodiments, capacitive coupling between the first and second plates of a storage capacitor causes the voltages at both plates to shift in a coordinated manner in response to charge leakage through one of the first or second transistors. By way of example, the coordination may involve causing the voltages at both plates of the storage capacitor to change together in a correlated and predictable pattern when charge leakage occurs. For instance, when charge leakage occurs through one of the transistors (causing a voltage change at its connecting plate), the capacitive coupling between the two plates causes the voltages at the relative plates to also change in a proportional and / or predictable manner. This coordinated voltage shift means that the relative voltage difference between the two plates is largely preserved when the absolute voltage values ​​at the two plates may change due to leakage. For example, if leakage through the first transistor causes a certain amount of voltage reduction at the first plate, then the capacitive coupling will cause a proportionally related decrease in the voltage at the second plate. This proportional relationship helps maintain the stored information (represented by the voltage difference) even if some charge is lost due to leakage. This coordinated voltage response is one of the advantages of a two-transistor-one-capacitor design over a conventional one-transistor design because it retains a sensing margin despite the leakage effect.

[0030] Unlike 1T1C cells where leakage directly reduces the stored charge and sensing margin, capacitive coupling ensures that the voltage difference remains largely unchanged despite leakage through a single transistor. These characteristics provide resistance to various leakage mechanisms without requiring additional circuitry or power consumption.

[0031] Figure 2The illustration shows an example schematic of a memory cell 200 according to an embodiment. The memory cell 200 includes a storage capacitor 206, wherein a holding transistor 202 is connected in series with one of the capacitor plates and a second holding transistor 204 is connected in series with the other capacitor plate, as shown below. Figure 2 The diagram illustrates the concept. The gate terminals of transistors 202 and 204 are both connected to the same word line (WL). The drain terminals of transistors 202 and 204 are connected to the two opposite plates of capacitor 206. The source terminals of transistors 202 and 204 are connected to two separate bit lines (BL) – BL and BLB – which can carry complementary voltage information during DRAM operation (e.g., if BL is charged at 1 V, then BLB will be charged at 0 V). The same applies to the information stored on both sides of capacitor 206 (e.g., if SN stores 1 V, then SNB will store 0 V).

[0032] By having a second dedicated bit line, multiple adjacent arrays can be addressed simultaneously because adjacent bit lines are not used as references (as opposed to the 1T1C method). On the other hand, having a second dedicated bit line may introduce area / power losses and may introduce more complex wiring.

[0033] In some embodiments, the presence of the second transistor can result in an area loss. Furthermore, the area loss in the cell region can be compensated for in the logic region because the large differential signal provided by the 2T1C configuration (e.g., as demonstrated by SPICE simulation methods) enables the use of a more scaled sense amplifier circuit system.

[0034] Figures 3a to 3o The process for constructing a three-dimensional memory device is described. The process includes providing alternating layers of a first semiconductor material and a second semiconductor material. Figure 3a Alternating layers of a first semiconductor material and a second semiconductor material are shown. The first semiconductor material may comprise silicon (Si), and the second semiconductor material may comprise silicon germanium (SiGe). A bottom layer 350 is a base layer providing structural integrity and mechanical stability for the entire memory device architecture. The bottom layer may be composed of Si. A support layer serves as a substrate on which all subsequent alternating semiconductor layers are deposited and processed during fabrication. These semiconductor materials (e.g., Si and SiGe) are vertically stacked one on top of the other in the alternating layers. The alternating layers serve as the base for the transistor and capacitor regions of the subsequent formation of the memory device. In some embodiments, each layer has a thickness in the range of 10 to 100 nanometers. The stack may comprise between 10 and 100 alternating layers. The alternating layers can be deposited using molecular beam epitaxy to achieve high-quality crystalline semiconductor layers with low defect rates, thereby avoiding amorphous or polycrystalline structures unsuitable for the device channel region.

[0035] The process further includes defining first and second transistor regions in alternating layers of first and second semiconductor materials. Each of the first and second transistor regions is defined on opposite sides of the alternating layer. Figure 3b In this process, a nitride hard mask is applied to the stack to define first and second transistor regions (T1, T2) in alternating layers while protecting the capacitor regions. In some embodiments, the thickness of the nitride hard mask is selected based on the technology node requirements and specifications of the lithography scanner used in the fabrication process. Each of the first and second transistor regions is defined on opposite sides of the alternating layers. The hard mask pattern defines two separate transistor regions positioned on opposite sides of the area reserved for the capacitor regions. As explained in the following paragraphs, the defined transistor regions ultimately form the first and second transistors in a 2T1C memory cell configuration, wherein each transistor is connected to an opposite plate of the storage capacitor.

[0036] The process further includes forming a gate on each layer of the first and second transistor regions. For example, a respective gate is formed by removing a second semiconductor material from each of the first and second transistor regions to expose a first semiconductor material and forming a gate on the exposed first semiconductor material. Figure 3c In this process, a second semiconductor material is removed from each of the first and second transistor regions to expose the first semiconductor material. A gate is formed on the exposed first semiconductor material. The second semiconductor material (e.g., silicon-germanium) is selectively removed from the transistor region using an etching process with a main lateral direction to expose the surface of the first semiconductor material (e.g., silicon), while the capacitor region remains protected by a hard mask. After selective removal, for example, a silicon dioxide gate oxide layer 352 with a thickness of about 5 nanometers can be deposited on the exposed silicon surface. Selective removal of silicon-germanium and formation of the gate oxide can occur while the capacitor region remains protected.

[0037] exist Figure 3d In this embodiment, a conductive metal gate 354 is formed in both the first and second transistor regions (T1, T2) through multiple deposition and isotropic etching cycles. The metal gate 354 may also be formed on top of the capacitor region C. The metal gate formation process comprises several deposition and isotropic etching cycles, using tungsten as the conductive material to provide suitable word line connectivity integrity. The metal gate has a thickness of approximately 10 nanometers (nm) and is highly self-aligned with the spacers. The specific metal material used for the gate is selected and designed to achieve the desired work function, with tungsten used in a preferred embodiment. The process parameters of the deposition and etching cycles are optimized based on the specific fabrication tools and formulations employed.

[0038] The process further includes filling each layer of the first and second transistor regions with a dielectric material, wherein the dielectric material 356 is deposited on at least a portion of the conductive material. Figure 3eIn this process, dielectric material is deposited to fill each layer of the first and second transistor regions (T1, T2). Any metal gate may also be removed from the capacitor region C. In some embodiments, a particular dielectric material is designed to minimize capacitive interference between metal layers while providing structural integrity. The dielectric material is deposited on at least a portion of the conductive metal gate in a single deposition step, thereby completing the formation of a series of vertical transistors in both the right and left regions, while the capacitor region remains protected. In some embodiments, the transistors in these regions are gate-all-around (GAA) transistors whose characteristics are controlled by several parameters: the metal gate work function, gate oxide properties, and channel doping determine the threshold voltage (VT); the source / channel and drain / channel doping profiles and spacer thickness control the leakage current; and these doping profiles also affect the transistor's on-state current, thereby creating a trade-off between leakage and write / read performance.

[0039] The process further includes forming a capacitor region between each of the first and second transistor regions and forming an isolation region between each of the first and second transistor regions and the capacitor region. In forming the isolation region, the process includes forming the isolation region between different capacitor rows after forming the capacitor film and filling the isolation region with a dielectric material.

[0040] exist Figure 3f In this process, photolithographic patterning is applied to define isolation (or spacer) regions 302 that physically separate the transistor regions (T1, T2) from the capacitor region (C). In some embodiments, the process uses appropriate photolithographic patterning and etching steps. An etching process is performed to create physical separation between the transistor and capacitor regions. The spacer width can be controlled to provide a suitable connection between the transistor and capacitor (which may require narrow spacing) while still being achievable through high aspect ratio etching (which may require wider spacing). A minimum spacer length of 10 to 20 nanometers (nm) is maintained to minimize the effect of the gate electric field on the memory node junction, as an excessively large gate electric field in this junction region can lead to increased leakage and poor retention characteristics. In some embodiments, the spacing is substantially the same at both the top and bottom of the structure.

[0041] exist Figure 3gIn this process, a silicon-based epitaxial growth process is used to grow the source and drain regions 304 and 306 of each transistor in the first transistor region T1. The source and drain regions 304 and 306 will connect the active transistor channel to the bit line and the storage capacitor. The epitaxially grown regions are doped to provide good conductivity between the transistor and the bit line and between the transistor and the storage node, thereby achieving suitable read / write performance. In some embodiments, the doping profile is designed to decrease under the isolation region to create a smoother transition between the N-doped region and the P-doped channel, as abrupt junctions can negatively impact leakage and retention characteristics. The process simultaneously creates a physical connection between the semiconductor epitaxial drain regions of both transistors and the metal plate of the capacitor in a single step. After epitaxial growth, a nitride dielectric film is deposited to complete the isolation between the transistor and capacitor regions.

[0042] exist Figure 3h In this process, transistor regions are formed such that their respective drain terminals are configured for electrical connection to a storage capacitor plate, and their source terminals are configured for electrical connection to bit lines. The process forms capacitor regions by converting the silicon in the capacitor regions into titanium silicide (TiSi) 358. The process is designed to convert all available silicon in the capacitor regions into titanium silicide, which has been protected during previous processing steps.

[0043] The process further includes forming a capacitor region by forming a sacrificial film in the capacitor region and, after removing the sacrificial film, forming a capacitor film in the capacitor region. The capacitor film comprises a first plate and a second plate separated by a dielectric material. Figure 3i In this process, the sacrificial film 310 is deposited in the capacitor region using an isotropic deposition process. After the sacrificial film deposition, nitride 308 is deposited to fill the gaps in the structure. In some embodiments, no special interface treatment is provided between the sacrificial film and the nitride deposition because the sacrificial film will be completely removed in a subsequent step to form the capacitor film structure.

[0044] like Figure 3j As shown, the sacrificial film is removed by selective etching to create space for the capacitor film structure. After the sacrificial film is removed, the capacitor film is formed in the space previously occupied by the sacrificial film. The capacitor film structure includes a first plate 360 ​​and a second plate 362 separated by a dielectric material 364, wherein the first plate will be electrically connected to the drain of a first transistor, and the second plate will be electrically connected to the drain of a second transistor. This configuration provides the 2T1C cell with improved sensing margin and enhanced immunity to float and hammer attacks because the two plates of the capacitor will be actively controlled by their respective transistors. Residual nitride continues to fill the gaps in the structure, thereby providing isolation.

[0045] exist Figure 3kIn this configuration, isolation region 312 is formed to separate different capacitor rows. The isolation region is then filled with a dielectric material. The dielectric material provides complete isolation between the capacitor rows. This isolation prevents electrical interference between adjacent capacitor rows in the memory array, thereby enabling each 2T1C memory cell to maintain its stored charge independently of its neighboring cells.

[0046] The process further includes establishing an electrical connection between a transistor region and its corresponding capacitor region. A first transistor region is connected to a first end of a capacitor region, and a second transistor region is connected to a second end of a capacitor region. To connect the first transistor region to the first end of the capacitor region, a first portion of the dielectric material is selectively etched to expose the first end of the capacitor region. Then, a first region is epitaxially grown in these etched first portions of the dielectric material, thereby establishing an electrical connection between the drain region of each first transistor region and the exposed first end of the capacitor region. To connect the second transistor region to the second end of the capacitor region, a second portion of the dielectric material is selectively etched to expose the second end of the capacitor region. Then, a second region is epitaxially grown in these etched second portions of the dielectric material, thereby establishing a capacitor terminal, and then connecting to the corresponding transistor in the second transistor region (T2). These epitaxially grown regions provide a suitable electrical connection between the transistor and its corresponding capacitor plate in the 2T1C memory cell structure.

[0047] Figure 3l The diagram demonstrates how titanium silicide from the capacitor side creates connection points (SN nodes) for transistors in the first transistor region (T1) via epitaxial material. Similarly, titanium nitride can create connection points for the second transistor region (T2) via epitaxial material.

[0048] exist Figure 3m In this process, an epitaxial growth process is performed to establish an electrical connection between the SNB node and the second transistor in the transistor region (T2). These epitaxial connections follow the same process parameters to provide consistent electrical characteristics for the two transistor-to-capacitor connections in the 2T1C memory cell structure.

[0049] The process further includes forming bit lines, such as a first bit line connected to the source region in a first transistor region and a second bit line connected to the source region in a second transistor region. Figure 3n In this design, the vertical bit lines BL and BLB are formed using tungsten as the conductive material. The formation process includes photolithographic patterning, etching, and tungsten deposition steps. The height of the vertical bit lines is determined by the number of stacked memory cells in the structure. The bit lines are arranged vertically according to the layout design, where BL is connected to the source terminal of the first transistor and BLB is connected to the source terminal of the second transistor. These complementary bit lines carry complementary voltage levels during memory operation, thereby providing enhanced sensing margin and improved immunity to floating body effects that characterize this memory cell design.

[0050] The process further includes forming word lines connecting conductive material in each layer of the first and second transistor regions. The word lines provide common gate control for the first and second transistor regions in each layer. Figure 3o In this design, the stepped word line (WL) is formed using tungsten as the conductive material. The stepped configuration is achieved through multiple photolithographic patterning and etching steps. The word line connects to the gate terminals of both the first and second transistors in each layer, thereby providing common gate control for the transistor pair. This common word line control enables simultaneous operation of the two transistors in the 2T1C memory cell structure. This allows for complementary access to the two plates of the storage capacitor during memory operation. The resulting structure comprises vertically stacked 2T1C memory cells that provide improved performance compared to other 1T1C designs, including better sense margin, longer hold time, and greater resistance to both buoyancy effects and hammer attacks.

[0051] The illustrative benefits of this disclosure are highlighted and discussed in the following paragraphs and have been verified using SPICE simulation methods. Figure 4 A schematic diagram illustrating a simulated 1T1C memory cell 400 and a 2T1C memory cell 410 is provided. The performance of the 2T1C memory cell is compared with that of the 1T1C memory cell. The following measurement is provided in the experiment: bit line capacitance C. BL =40 fF, storage node capacitance C SN =4 fF, the storage node voltage V1 associated with the logic "1" bit is 1.0 V.

[0052] It should be noted that the single-sided write / read operation in the 1T1C cell is designed to simplify the difference between the BL (which shares charge with SN) and the reference BL held at V1 / 2 volts (once the holding transistor is enabled / turned on). On the other hand, the double-sided write / read operation in the 2T1C cell is designed to simplify the difference between the BL (which shares charge with SN) and the BLB (which shares charge with SNB) (once the second transistor is enabled / turned on) (once the holding transistor T1 is enabled / turned on).

[0053] Simulation results show that the 2T1C configuration provides a signal three times larger than the 1T1C configuration. These results demonstrate the following advantages of the 2T1C configuration: faster sensing; smaller storage capacitors; and reduced peripheral area due to the smaller sensing amplifier achievable with the larger differential signal.

[0054] The large sensing signal obtained by the 2T1C configuration can be considered a favorable result. However, there are even greater benefits to using 2T1C. To understand and emphasize these benefits, data loss due to leakage during the hold phase was investigated, and the 2T1C configuration was compared with the 1T1C configuration again.

[0055] The results show that the 1T1C configuration is significantly affected by leakage, which reduces the sensing differential. On the other hand, the 2T1C configuration is robust to leakage due to the coupling capacitance that connects both sides of the capacitor and makes their voltages move synchronously, thus maintaining the sensing differential. For the 2T1C configuration to lose differential voltage, both sides of the memory cell should have leakage paths, which is an event with an exponentially lower probability than having a single leakage path.

[0056] The above results demonstrate the following advantages: The refresh cycle of a 2T1C cell can be relaxed and compared to that of a 1T1C cell. 2T1C cells are robust to defects (traps, dislocations, etc.). It is rare for random defects to simultaneously affect both transistors in a 2T1C cell. 2T1C cells are robust to the floating body effect of dynamic leakage in enhanced cells because the floating body is related to hole generation through the defective transistor junction, and the probability of random defects occurring on both sides of the cell is exponentially lower than in a 1T1C cell with only one side. 2T1C cells are also robust to external attacks (such as hammer attacks on word lines and bit lines): this is because an attacker must manipulate both sides of the 2T1C cell to force malicious data loss in the cell. High and robust sense differential allows for the use of a smaller sense amplifier, which makes it possible to recover some of the chip area lost due to the introduction of a second transistor in the 2T1C cell. Alternatively, designers can choose to accept this area loss by increasing the sense speed instead of scaling the sense amplifier area, thus allowing the production of high-performance DRAM.

[0057] Figure 5 This document describes a comparative analysis of the signal behavior between the 2T1C memory cell and the 1T1C memory cell disclosed in this disclosure under ideal operating conditions. Figure 5 The timing diagram shows the various control signals and their corresponding voltage differentials during memory operation. Several key control signals are shown, including the "write data" signal, the "charge sharing" signal, the "balance bit line (BL)" signal, and the "sensing" signal.

[0058] For the 2T1C configuration, simulations demonstrate a large sensing margin of 164 mV differential voltage. This differential is achieved through a two-sided write / read operation, where the voltage difference between the bit line (BL) sharing charge with the storage node (SN) and the complementary bit line (BLB) sharing charge with the complementary storage node (SNB) is measured. In contrast, the 1T1C configuration exhibits a smaller differential voltage of 51 mV. This configuration relies on a one-sided write / read operation, where the voltage difference between the bit line sharing charge with the storage node and a reference bit line maintained at V1 / 2 (half the voltage representing a logic "1") is measured.

[0059] Under ideal conditions (where bit line capacitance CBL = 40 fF, storage node capacitance CSN = 4 fF, and logic "1" voltage V1 = 1.0 V), the 2T1C configuration achieves approximately three times the sense margin of a 1T1C design. This increased differential voltage results in faster sensing capability, reduced storage capacitance requirements, the possibility of smaller sense amplifier circuitry, and more reliable read operations.

[0060] Figure 6 This paper presents a comparative analysis of the signal behavior between 2T1C and 1T1C memory cells under leakage conditions. The figure shows a timing diagram illustrating the various control signals and their corresponding voltage differences during memory operation. The timing diagram shows several key control signals, including write data signals, followed by charge sharing signals and equalization bit line (BL) signals, and then sensing signals.

[0061] For the 2T1C configuration, simulations demonstrate robustness against leakage, maintaining a differential voltage of 164 mV even under leakage conditions. This performance is achieved through capacitive coupling between the two sides of the capacitor, which causes the voltages on both sides to move together in the event of leakage through one of the transistors, thereby maintaining the sensing differential. In contrast, the 1T1C configuration exhibits a significant performance degradation under leakage conditions, where the differential voltage drops to only 26 mV. This substantial reduction is because any charge lost during the hold period directly reduces the sensing margin in a single-sided architecture.

[0062] This comparison demonstrates a key advantage of the 2T1C design over the 1T1C structure: its inherent resistance to leakage effects. The 2T1C configuration maintains its full sensing margin unless both sides of the cell experience leakage simultaneously, which is statistically far less likely than single-sided leakage. Under leakage conditions, this robust performance provides longer refresh cycles and better immunity to defects and float effects, and offers enhanced protection against external attacks such as tumble blows.

[0063] According to some aspects, a sense amplifier is a circuit component that detects and amplifies small voltage differences between bit lines during memory read operations. In the context of this disclosure, when data is read from a memory cell, the sense amplifier detects the voltage difference between a first bit line (BL) connected to a first transistor and a second bit line (BLB) connected to a second transistor. While the memory cell maintains a non-zero differential voltage between the first and second plates, it should be understood that in practical implementations, the sense amplifier's ability to detect and amplify this differential voltage depends on its internal offset voltage. This offset voltage, caused by statistical variations in the threshold voltage between the two branches of the sense amplifier, effectively sets the minimum detectable voltage difference. However, this offset voltage can be minimized through various techniques and design optimizations, enabling the sense amplifier to detect and amplify increasingly smaller voltage differences between the first and second plates of the storage capacitor.

[0064] Figure 7 This describes a set of 700 example processes 700 used during the design, inspection, and fabrication of an integrated circuit (e.g., an electronically manufactured integrated circuit) to transform and inspect design data and instructions representing the integrated circuit. Each of these processes can be constructed and implemented as multiple modules or operations. The term 'EDA' stands for 'Electronic Design Automation'. These processes begin with the creation of a product concept 710 using information provided by the designer, which is then transformed to create an article of art using a set of EDA processes 712. When the design is complete, it is tape-out 734, where the original pattern (e.g., geometric pattern) of the integrated circuit is sent to a fabrication facility to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies are fabricated 736, and packaging and assembly processes 738 are performed to produce the finished integrated circuit 740.

[0065] Specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. Higher representation levels can be used to design circuits and systems using hardware description languages ​​('HDL'), such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be transformed into logic-level register-transfer-level ('RTL') descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower representation level, as a more detailed description, adds more useful details to the design description, such as more details about the modules contained in the description. Lower representation levels, as more detailed descriptions, can be computer-generated, exported from design libraries, or created by another design automation process. An example of a specification language at a lower representation language level for specifying more detailed descriptions is the SPICE simulation method, used to describe circuits with many analog components in detail. Descriptions at each representation level are enabled for use by the corresponding system (e.g., a formal verification system) at that level. The design process can use... Figure 7 The sequence described herein. The described process can be enabled by an EDA product (or EDA system).

[0066] During system design phase 714, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics, such as power consumption, performance, area (physical and / or lines of code), and cost reduction. Dividing the design into different types of modules or components can occur at this stage.

[0067] During logic design and functional verification 716, modules or components in the circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, components of the circuit can be verified to generate outputs that meet the requirements of the specifications for the designed circuit or system. Functional verification can use simulators and other programs (e.g., testbed generators, static HDL checkers, and formal checkers). In some embodiments, a special component system, referred to as a 'simulator' or 'prototype system', is used to accelerate functional verification.

[0068] During the synthesis and testing of the design 718, the HDL code is transformed into a netlist. In some embodiments, the netlist may be a graphical structure, wherein the edges of the graphical structure represent components of the circuit and the nodes of the graphical structure represent the interconnections of the components. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit functions according to a specified design during manufacturing. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify that the integrated circuit meets specification requirements.

[0069] During netlist verification (720), the netlist's compliance with timing constraints and its correspondence with HDL code are checked. During design planning (722), the overall planar diagram of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0070] During layout or physical implementation 724, physical placement (e.g., the positioning of circuit components such as transistors or capacitors) and wiring (connection of circuit components via multiple conductors) occur, and cells can be selected from a library to implement a specific logic function. As used herein, the term 'cell' can specify a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit 'block' can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are enabled as two physical structures and during simulation. Parameters, such as size, are selected for the selected cell (based on 'standard cells') and made accessible in a database for use in EDA products.

[0071] During analysis and extraction 726, circuit functionality is examined at the layout level, allowing for improvements to the layout design. During physical inspection 728, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, and lithographic constraints, and to ensure that the circuit system functionality matches the HDL design specifications. During resolution enhancement 730, the geometry of the layout is transformed to improve the fabrication method of the circuit design.

[0072] During the tape-out process, data is created for producing the photomask (where appropriate, after the application of photolithography enhancement). During mask data preparation 732, the 'tape-out' data is used to produce the photomask used to manufacture the finished integrated circuit.

[0073] Computer systems (e.g.) Figure 8 The storage subsystem of the computer system 800 can be used to store some or all of the EDA products described herein, as well as programs and data structures for developing units for the physical and logical design of libraries and the use of said libraries.

[0074] Figure 8 The example machine of computer system 800 can execute a set of instructions within said computer system to cause the machine to perform any or more of the methodologies discussed herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0075] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, while referring to a single machine, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0076] The example computer system 800 includes a processing device 802 that communicates with each other via a bus 830, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM)), a static memory 806 (e.g., flash memory, static random access memory (SRAM) and the like), and a data storage device 818.

[0077] Processing device 802 represents one or more processors, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 802 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 802 may be configured to execute instructions 826 for performing the operations and steps described herein.

[0078] The computer system 800 may further include a network interface device 808 for communication via a network 820. The computer system 800 may also include a video display unit 810 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), a graphics processing unit 822, a signal generation device 816 (e.g., a speaker), a graphics processing unit 822, a video processing unit 828, and an audio processing unit 832.

[0079] Data storage device 818 may include a machine-readable storage medium 824 (also referred to as a non-transitory computer-readable medium) thereon storing one or more sets of instructions 826 or software embodying any or more of the methodologies or functions described herein. Instructions 826 may also reside wholly or at least partially in main memory 804 and / or processing device 802 during execution by computer system 800, which also constitute machine-readable storage media.

[0080] In some embodiments, instruction 826 includes instructions for implementing functionality corresponding to this disclosure. While machine-readable storage medium 824 is shown as a single medium in example embodiments, the term "machine-readable storage medium" should be considered as including a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as including any medium capable of storing or encoding a set of instructions for machine execution and causing the machine and processing device 802 to perform any or more of the methodologies of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0081] As disclosed herein, and by way of example, a memory cell includes a capacitor, a first transistor, and a second transistor. The capacitor has a first plate and a second plate. The first plate is adjacent to the second plate. The first transistor has a channel, a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal surrounds the channel, one side of the channel is connected to the source terminal, and the other side of the channel is connected to the drain terminal. The second transistor has a channel, a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal surrounds the channel, one side of the channel is connected to the source terminal, and the other side of the channel is connected to the drain terminal. The drain terminal of the first transistor is connected to the first plate of the capacitor. The gate terminal of the first transistor and the gate terminal of the second transistor are connected together. The drain terminal of the second transistor is connected to the second plate of the capacitor.

[0082] In some embodiments, a first bit line is connected to the source terminal of the first transistor, and a second bit line is connected to the source terminal of the second transistor. The first and second bit lines are configured to carry complementary voltage levels. A word line is connected to both the gate terminal of the first transistor and the gate terminal of the second transistor. The capacitor is configured to maintain a non-zero voltage difference between the first and second plates in response to charge leakage through either the first or second transistor.

[0083] The first board is configured to store a first voltage level and the second board is configured to store a second voltage level different from the first voltage level. When a change in voltage level induced by capacitive coupling between the first and second boards occurs due to charge leakage through one of the first or second transistors, the memory cell can maintain (or can be configured to maintain) a non-zero differential between the first and second boards.

[0084] The charge leakage includes one of the following: source-to-drain leakage current through the channel of the first transistor or the second transistor; junction leakage current due to a defect in the first transistor or the second transistor; leakage current due to a floating body effect in the first transistor or the second transistor; and gate-to-drain leakage current in the first transistor or the second transistor.

[0085] The capacitive coupling between the first and second plates provides protection against hammer attacks. The capacitive coupling between the first and second plates of the capacitor causes the voltage at both the first and second plates to change proportionally to charge leakage through either the first or second transistor.

[0086] The first transistor, the second transistor, and the capacitor are separated from each other by an isolation region.

[0087] In some aspects, a method of manufacturing a three-dimensional memory device includes: providing alternating layers of a first semiconductor material and a second semiconductor material; defining first and second transistor regions in the alternating layers of the first and second semiconductor materials, wherein each of the first and second transistor regions is defined on opposite sides of the alternating layers; forming a gate on each of the first and second transistor regions, the gate comprising a conductive material; forming a capacitor region between each of the first and second transistor regions; connecting each of the first transistor regions to a first end of the capacitor region and connecting each of the second transistor regions to a second end of the capacitor region; forming a bit line including a first bit line connected to a source region in the first transistor region and a second bit line connected to a source region in the second transistor region; and forming a word line connected to the conductive material in each layer of the first and second transistor regions, wherein the word line provides common gate control for the first and second transistor regions in each layer.

[0088] The method further includes filling each layer of the first and second transistor regions with a dielectric material, the dielectric material being deposited on at least a portion of the conductive material.

[0089] Forming the gate on each layer of the first and second transistor regions comprises: removing the second semiconductor material from each of the first and second transistor regions to expose the first semiconductor material; and forming the gate on the exposed first semiconductor material.

[0090] The capacitor region may be formed by forming an isolation region between each of the first and second transistor regions and the capacitor region.

[0091] Forming the capacitor region may further include: forming a sacrificial film in the capacitor region; and forming a capacitor film in the capacitor region after removing the sacrificial film, wherein the capacitor film comprises a first plate and a second plate separated by a dielectric material.

[0092] Forming the isolation region may include forming the isolation region between different rows of capacitors after forming the capacitor film and filling the isolation region with a dielectric material.

[0093] Connecting each of the first transistor regions to a first end of the capacitor region may include selectively etching a first portion of the dielectric material to expose the first end of the capacitor region and epitaxially growing a first region in the etched first portion of the dielectric material to connect the drain region of each of the first transistor regions to the exposed first end of the capacitor region.

[0094] Connecting each of the second transistor regions to the second end of the capacitor region may include selectively etching a second portion of the dielectric material to expose the second end of the capacitor region and epitaxially growing a second region in the etched second portion of the dielectric material to connect the drain region of each of the second transistor regions to the exposed second end of the capacitor region.

[0095] In some aspects, a three-dimensional memory device includes a plurality of memory cells, a first bit line, a second bit line, and a word line. The plurality of memory cells are stacked together to form a stack having a first side and a second side. The first bit line is positioned along the first side of the stack. The second bit line is positioned along the second side of the stack. The word line is connected to each layer of the stack. Each memory cell includes a capacitor region, a first transistor region, and a second transistor region. The capacitor region includes a capacitor having a first plate and a second plate. The first plate is adjacent to the second plate.

[0096] The first transistor region includes a first transistor having a channel, a gate terminal connected to a word line, a source terminal connected to the first bit line, and a drain terminal connected to the first plate of the capacitor. One side of the channel is connected to the source terminal, and the other side of the channel is connected to the drain terminal. The second transistor region includes a second transistor having a channel, a gate terminal connected to the word line, a source terminal connected to the second bit line, and a drain terminal connected to the second plate of the capacitor. One side of the channel is connected to the source terminal, and the other side of the channel is connected to the drain terminal. The first transistor region and the second transistor region are located on opposite sides of the capacitor region.

[0097] The disclosed configuration advantageously provides improved sensing margin, improved holding characteristics, and immunity to floating body effects and hammer attacks. Compared to another one-transistor-capacitor (1T1C) circuit, the two-transistor-capacitor (2T1C) design can provide up to three times the sensing margin while maintaining robust operation even in the presence of leakage current.

[0098] Other aspects include components, apparatus, systems, improvements, methods, processes, applications, computer-readable media, and other technologies relating to any of the foregoing.

[0099] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are methods used by those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm can be a sequence of operations that leads to a desired result. An operation is an operation that requires physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0100] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. Unless otherwise expressly indicated as is clearly stated in this disclosure, it should be understood that throughout the description, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data representing physical quantities similarly represented in the memory or registers or other such information storage devices of the computer system.

[0101] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0102] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used in accordance with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to implement the methods. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure described herein.

[0103] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, said instructions being used to program a computer system (or other electronic device) to perform processes according to this disclosure. A machine-readable medium includes any means for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0104] In the foregoing disclosure, embodiments thereof have been described with reference to specific examples of embodiments thereof. It should be understood that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Where elements are referenced in a singular form in this disclosure, more than one element may be depicted in the drawings, and similar elements are labeled with similar numbers. Therefore, this disclosure and the drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory cell comprising: A capacitor having a first plate and a second plate, wherein the first plate is adjacent to the second plate; A first transistor has a channel, a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal surrounds the channel, one side of the channel is connected to the source terminal, and the other side of the channel is connected to the drain terminal; and The second transistor has a channel, a gate terminal, a source terminal and a drain terminal, wherein the gate terminal surrounds the channel, one side of the channel is connected to the source terminal and the other side of the channel is connected to the drain terminal; The drain terminal of the first transistor is connected to the first plate of the capacitor, the gate terminal of the first transistor and the gate terminal of the second transistor are connected together, and the drain terminal of the second transistor is connected to the second plate of the capacitor.

2. The memory cell according to claim 1, further comprising: The first line is connected to the source terminal of the first transistor; and The second bit line is connected to the source terminal of the second transistor.

3. The memory cell of claim 2, wherein the first bit line and the second bit line are configured to carry complementary voltage levels.

4. The memory cell of claim 1, further comprising a word line connected to both the gate terminal of the first transistor and the gate terminal of the second transistor.

5. The memory cell of claim 1, wherein the capacitor is configured to maintain a non-zero voltage difference between the first and second plates in response to charge leakage through one of the first or second transistors.

6. The memory cell of claim 1, wherein the first board is configured to store a first voltage level and the second board is configured to store a second voltage level different from the first voltage level, and is further configured to maintain a non-zero differential between the first board and the second board when a change in voltage level induced by capacitive coupling between the first board and the second board is caused by charge leakage through one of the first transistors or the second transistor.

7. The memory cell of claim 6, wherein the charge leakage comprises one of the following: Source-to-drain leakage current through the channel of either the first transistor or the second transistor; Junction leakage current caused by a defect in one of the first transistors or the second transistor; Leakage current caused by the floating body effect in one of the first transistors or the second transistor; and Gate-drain leakage current in one of the first transistors or the second transistor.

8. The memory cell of claim 6, wherein the capacitive coupling of the first and second boards provides protection against row hammer attacks.

9. The memory cell of claim 1, wherein the first transistor, the second transistor, and the capacitor are separated from each other by an isolation region.

10. The memory cell of claim 1, wherein the capacitive coupling between the first plate and the second plate of the capacitor causes the voltage at both the first plate and the second plate to change proportionally in response to charge leakage through one of the first transistor or the second transistor.

11. A method for manufacturing a three-dimensional memory device, comprising: Provides alternating layers of a first semiconductor material and a second semiconductor material; First and second transistor regions are defined in the alternating layers of the first semiconductor material and the second semiconductor material, wherein each of the first and second transistor regions is defined on opposite sides of the alternating layers; A gate is formed on each layer of the first and second transistor regions, the gate comprising a conductive material; A capacitor region is formed between each of the first and second transistor regions; Each of the first transistor regions is connected to a first end of the capacitor region and each of the second transistor regions is connected to a second end of the capacitor region; A bit line is formed, comprising a first bit line connected to the source region in the first transistor region and a second bit line connected to the source region in the second transistor region; and Word lines are formed connecting the conductive material in each layer of the first and second transistor regions, wherein the word lines provide common gate control for the first and second transistor regions in each layer.

12. The method of claim 11, further comprising: Each layer of the first and second transistor regions is filled with a dielectric material, which is deposited on at least a portion of the conductive material.

13. The method of claim 11, wherein forming the gate on each layer of the first and second transistor regions comprises: The second semiconductor material is removed from each of the first and second transistor regions to expose the first semiconductor material; and The gate is formed on the exposed first semiconductor material.

14. The method of claim 11, wherein forming the capacitor region further comprises: An isolation region is formed between each of the first and second transistor regions and the capacitor region.

15. The method of claim 14, wherein forming the capacitor region further comprises: A sacrificial film is formed in the capacitor region; and After the sacrificial film is removed, a capacitor film is formed in the capacitor region, wherein the capacitor film comprises a first plate and a second plate separated by a dielectric material.

16. The method of claim 14, wherein forming the isolation zone comprises: After the capacitor film is formed, an isolation region is formed between different rows of capacitors; and The isolation region is filled with a dielectric material.

17. The method of claim 11, wherein connecting each of the first transistor regions to a first end of the capacitor region comprises: Selectively etch a first portion of the dielectric material to expose the first end of the capacitor region; and A first region is epitaxially grown in the etched first portion of the dielectric material to connect the drain region of each of the first transistor regions to the exposed first terminal of the capacitor region.

18. The method of claim 11, wherein connecting each of the second transistor regions to a second end of the capacitor region comprises: Selectively etch a second portion of the dielectric material to expose the second end of the capacitor region; and A second region is epitaxially grown in the etched second portion of the dielectric material to connect the drain region of each of the second transistor regions to the exposed second terminal of the capacitor region.

19. A three-dimensional memory device, comprising: Multiple memory cells are stacked together to form a stack having a first side and a second side; A first bit line and a second bit line, wherein the first bit line is along the first side of the stack and the second bit line is along the second side of the stack; and Word lines, which connect to each layer of the stack; Each memory unit includes: A capacitor region, comprising a capacitor having a first plate and a second plate, the first plate being adjacent to the second plate; A first transistor region includes a first transistor having a channel, a gate terminal connected to a word line, a source terminal connected to the first bit line, and a drain terminal connected to the first plate of the capacitor, wherein one side of the channel is connected to the source terminal and the other side of the channel is connected to the drain terminal; and The second transistor region includes a second transistor having a channel, a gate terminal connected to the word line, a source terminal connected to the second bit line, and a drain terminal connected to the second plate of the capacitor, wherein one side of the channel is connected to the source terminal and the other side of the channel is connected to the drain terminal. The first transistor region and the second transistor region are located on opposite sides of the capacitor region.

20. The three-dimensional memory device of claim 19, wherein the capacitor is configured to maintain a non-zero voltage difference between the first and second plates in response to charge leakage through one of the first or second transistors.

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