Semiconductor device and method of forming the same

Abstract

The application discloses a semiconductor device and a forming method thereof. The semiconductor device comprises a stack structure, a transistor and a capacitor structure. The stack structure comprises insulating layers arranged in a stack. The transistor is located between two adjacent insulating layers. The capacitor structure comprises a first electrode, a second electrode and a dielectric layer located between the first electrode and the second electrode. The first electrode is located between two adjacent insulating layers and connected with the transistor in a first direction. A side surface of the first electrode away from the transistor forms a first groove. Two adjacent first electrodes and insulating layers form a second groove in a third direction. The dielectric layer forms a third groove in the second groove and a fourth groove in the first groove. The second electrode is located at least on the inner walls of the third groove and the fourth groove to improve the capacity of the capacitor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Technology

[0002] As the miniaturization of 2D DRAM devices approaches physical limits, issues such as photolithography precision, device leakage current, and edge electric field interference cannot be resolved through planar process optimization. Therefore, the industry is fully shifting towards 3D stacked DRAM architectures. 3D DRAM (3D Dynamic Random Access Memory) constructs memory arrays through the vertical stacking of multiple thin films, overcoming the limitations of planar size miniaturization and significantly increasing memory integration density. In the core structure of 3D DRAM, the effective electrode area, capacitance, and structural stability of the capacitor structure directly determine the device's charge storage capacity, read / write sensing margin, data retention time, and overall array density.

[0003] Existing 3D DRAM capacitors suffer from drawbacks such as small effective electrode area, low capacitance, and large cell area, which severely restrict the development of high-density stacking processes. Summary of the Invention

[0004] This application provides a semiconductor device and a method for forming the same, to improve capacitance and thus increase storage density.

[0005] This application provides a semiconductor device, including: a stacked structure including insulating layers stacked along a third direction; a transistor located between two adjacent insulating layers; a capacitor structure including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode, wherein the first electrode is located between two adjacent insulating layers and connected to the transistor in a first direction, the first direction being perpendicular to the third direction; wherein the surface of the first electrode facing away from the transistor forms a first groove, the two adjacent first electrodes and the insulating layers along the third direction form a second groove, the dielectric layer is in contact with the inner walls of the first groove and the second groove, the dielectric layer forms a third groove in the second groove, the dielectric layer forms a fourth groove in the first groove, and the second electrode is located at least on the inner walls of the third groove and the fourth groove.

[0006] In some embodiments, the semiconductor device further includes: isolation structures extending along the third direction and spaced apart along the second direction, the second direction being perpendicular to the third direction and intersecting the first direction; the transistor being located between two adjacent isolation structures in the second direction; the first electrode and the isolation structure forming a trench in the same layer along the second direction, the dielectric layer contacting the inner wall of the trench, the dielectric layer forming a fifth groove in the trench, and the second electrode being located at least on the inner wall of the fifth groove.

[0007] In some embodiments, the semiconductor device further includes a connection structure connected to the second electrode, the connection structure including a main body and a branch, the main body extending along the third direction and the second direction, and the branch extending along the first direction.

[0008] In some embodiments, the second electrode fills the third groove, and the second electrode and the branch sequentially fill the fourth groove and the fifth groove.

[0009] In some embodiments, the second electrode fills the third and fifth grooves, and the second electrode and the branch sequentially fill the fourth groove.

[0010] In some embodiments, the second electrode and the branch portion sequentially fill the third groove, the fourth groove, and the fifth groove.

[0011] In some embodiments, the second electrode fills the fifth groove, and the second electrode and the branch portion sequentially fill the third groove and the fourth groove.

[0012] In some embodiments, the second electrode fills the third and fourth grooves, and the second electrode and the branch sequentially fill the fifth groove.

[0013] In some embodiments, the second electrode fills the third groove, the fourth groove, and the fifth groove.

[0014] In some embodiments, the second groove and the first groove are alternately arranged along the third direction, and the dimension of the first groove along the first direction is greater than the dimension of the second groove along the first direction.

[0015] In some embodiments, in the first direction, the first electrode includes an extension that extends relative to the second groove and is connected to the insulating layer.

[0016] In some embodiments, the transistor includes a channel layer and a gate layer, the gate layer surrounding a portion of the surface of the channel layer, and the gate layer exposing at least a portion of the sidewalls of the channel layer connected to the first electrode; the semiconductor device further includes a word line extending along the second direction and a bit line extending along the third direction, the word line being connected to the gate layers of a plurality of the transistors, and the channel layer being disposed around the surface of the bit line.

[0017] In some embodiments, a spacer structure is further included, the spacer structure being located between the channel layer and two adjacent insulating layers, and between the gate layer and the first electrode.

[0018] This application also provides a method for forming a semiconductor device, comprising: forming a stacked layer, the stacked layer including an insulating layer and a dielectric layer alternately stacked along a third direction; forming a transistor, the transistor being located between two adjacent insulating layers; forming a capacitor structure, the capacitor structure including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode, the first electrode being located between two adjacent insulating layers and connected to the transistor in a first direction, the first direction being perpendicular to the third direction; the surface of the first electrode facing away from the transistor forming a first groove; the two adjacent first electrodes and insulating layers along the third direction forming a second groove, the dielectric layer contacting the inner walls of the first groove and the second groove, the dielectric layer forming a third groove in the second groove, the dielectric layer forming a fourth groove in the first groove, and the second electrode being located at least on the inner walls of the third groove and the fourth groove.

[0019] In some embodiments, the method of forming a capacitor structure includes: forming a capacitor trench extending through the stacked layer along a third direction, the capacitor trench extending along a second direction perpendicular to the third direction and intersecting the first direction; removing a portion of the dielectric layer through the capacitor trench to form a first initial groove; forming a first electrode and a first groove surrounded by the first electrode on the inner wall of the first initial groove; removing a portion of the insulating layer through the capacitor trench to form a second groove; and sequentially forming a dielectric layer and a second electrode on the inner wall of the first groove and the inner wall of the second groove.

[0020] In some embodiments, the method of forming the semiconductor device further includes: forming an isolation structure that penetrates the stacked layer along the third direction, the isolation structure being located between two adjacent transistors in a second direction; in the process of forming the second trench, removing a portion of the isolation structure to form a trench, the dielectric layer and the second electrode also being formed in the trench.

[0021] In the semiconductor device of this application embodiment, the second electrode is located at least on the inner walls of the third and fourth grooves, that is, the second electrode covers the inner and outer surfaces of the first electrode. The effective coverage area of ​​the capacitor electrode is significantly increased through the composite curved surface structure of the third and fourth grooves, effectively improving the capacitor's storage capacity without increasing the cell layout area. Since the second electrode is located at least within the third groove, the interlayer structure support strength can be optimized, and the pre-occupation of the third groove by the second electrode can also reduce the intrusion of other dielectrics into the capacitor region in subsequent processes.

[0022] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0025] Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 1 ; Figure 2 yes Figure 1 A top view of the semiconductor device at point A-A1; Figure 3 yes Figure 2 A schematic cross-sectional view of the branch of the central connecting structure at point B-B1; Figure 4 yes Figure 1 Another top view of the semiconductor device at point A-A1; Figure 5 yes Figure 4 A schematic cross-sectional view of the branch of the central connecting structure at point B-B1; Figure 6 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 2 ; Figure 7 yes Figure 6 A top view of the semiconductor device at point A-A1; Figure 8 yes Figure 6 Another top view of the semiconductor device at point A-A1; Figure 9 yes Figure 8 A schematic cross-sectional view of the branch of the central connecting structure at point B-B1; Figure 10 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 3 ; Figure 11 yes Figure 10 A top view of the semiconductor device at point A-A1; Figure 12 yes Figure 11 A schematic cross-sectional view of the branch of the central connecting structure at point B-B1; Figure 13 yes Figure 10 Another cross-sectional view of the semiconductor device at A-A1; Figure 14 yes Figure 13 A schematic cross-sectional view of the branch of the central connecting structure at point B-B1; Figure 15 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application; Figure 16 This is a schematic flowchart of a method for forming a semiconductor device provided in some embodiments of this application; Figures 17 to 48 This is a schematic diagram of the semiconductor device during its formation process according to some embodiments of this application.

[0026] Explanation of reference numerals in the attached figures: 10. Stacked structure; 10a. Stacked layer; 11. Insulating layer; 12. Dielectric layer; 20. Transistor; 21. Channel layer; 22. Gate layer; 23. Gate insulating layer; 24. Sacrificial layer; 20a. Through-hole; 21a. Channel hole; 30. Capacitor structure; 31. First electrode; 310. End; 311. Protrusion; 32. Second electrode; 33. Dielectric layer; 31a. First groove; 32a. Second groove; 3 2b, Third groove; 31b, Fourth groove; 311a, First initial groove; 40, Spacing structure; 50, Isolation structure; 50a, Groove; 50b, Fifth groove; 60, Connecting structure; 61, Main body; 62, Branch; 60a, Capacitor slot; 70, Word line; 70a, Word line slot; 71, Word line gap structure; 71a, Word line gap; 80, Bit line; 80a, Bit line hole; 101, Memory cell group. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0028] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 1 , Figure 2 yes Figure 1 A top view of the semiconductor device at point A-A1.

[0029] The semiconductor device includes a stacked structure 10, a transistor 20, and a capacitor structure 30. The stacked structure 10 includes insulating layers 11 stacked along a third direction Z. The transistor 20 is located between two adjacent insulating layers 11. The capacitor structure 30 includes a first electrode 31, a second electrode 32, and a dielectric layer 33 located between the first electrode 31 and the second electrode 32. The first electrode 31 is located between two adjacent insulating layers 11 and is connected to the transistor 20 in a first direction X, which is perpendicular to the third direction Z. The surface of the first electrode 31 facing away from the transistor 20 forms a first groove 31a, and two adjacent layers of the first electrode 31 and the insulating layer 11 along the third direction Z form a second groove 32a. The dielectric layer 33 is in contact with the inner walls of the first groove 31a and the second groove 32a. The dielectric layer 33 forms a third groove 32b in the second groove 32a and a fourth groove 31b in the first groove 31a. The second electrode 32 is located at least on the inner walls of the third groove 32b and the fourth groove 31b.

[0030] In this embodiment, since the second electrode 32 is located on the inner wall of the fourth groove 31b and the third groove 32b, that is, the second electrode 32 covers the inner surface and the outer surface of the first electrode 31, the capacitor storage capacity is effectively improved without increasing the cell layout area.

[0031] In some embodiments, the semiconductor device further includes isolation structures 50 extending along a third direction Z and spaced apart along a second direction Y, the second direction Y being perpendicular to the third direction Z and intersecting the first direction X. The transistor 20 is located between two adjacent isolation structures 50 in the second direction Y. Two adjacent first electrodes 31 on the same layer along the second direction Y form a trench 50a with the isolation structures 50. The dielectric layer 33 contacts the inner wall of the trench 50a and forms a fifth recess 50b within the trench 50a. The second electrode 32 is also located at least on the inner wall of the fifth recess 50b. Figure 2 As shown, at least a portion of the first electrode 31 is located between two adjacent isolation structures 50 in the second direction Y.

[0032] The semiconductor device also includes a connection structure 60 connected to the second electrode 32. The connection structure 60 includes a main body 61 and a branch 62. The main body 61 extends along the third direction Z and the second direction Y, and the branch 62 extends along the first direction X.

[0033] like Figure 1 and Figure 2 As shown, the second electrode 32 and the branch 62 sequentially fill the third groove 32b, the fourth groove 31b, and the fifth groove 50b. That is, the second electrode 32 and the branch 62 together fill the third groove 32b, the second electrode 32 and the branch 62 together fill the fourth groove 31b, and the second electrode 32 and the branch 62 together fill the fifth groove 50b.

[0034] Please see Figure 3 , Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure of the branch of the connecting structure at point B-B1.

[0035] Depend on Figures 1 to 3 It can be seen that the branch 62 extends along the third direction Z in the fifth groove 50b (the area corresponding to the isolation structure 50); while in the area between the corresponding isolation structures 50, since the third groove 32b and the fourth groove 31b are arranged alternately along the third direction Z, the branch 62 in the third groove 32b and the branch 62 in the fourth groove 31b are arranged alternately along the third direction Z.

[0036] It should be noted that, Figure 3 Different patterns are used to distinguish the branches 62 in the third groove 32b and the fourth groove 31b, and the present application embodiment does not limit the size of the branches 62 in the third direction Z in the third groove 32b and the fourth groove 31b.

[0037] Please see Figure 4 and Figure 5 , Figure 4 yes Figure 1 Another top view of the semiconductor device at point A-A1. Figure 5 yes Figure 4 A schematic cross-sectional view of the branch of the connecting structure at point B-B1. This embodiment is similar to... Figure 2 and Figure 3 The difference in the embodiment is that the branch 62 is not located within the fifth groove 50b.

[0038] See Figure 4 The second electrode 32 fills the fifth groove 50b. See also Figure 1 and Figure 4 The second electrode 32 and the branch portion 62 sequentially fill the fourth groove 31b. For example... Figure 1 As shown, the second electrode 32 and the branch portion 62 sequentially fill the third groove 32b.

[0039] See Figure 5 Since the second electrode 32 fills the fifth groove 50b, the branch 62 is not located in the fifth groove 50b, that is, there is no branch 62 extending along the third direction Z. The branch 62 only fills the third groove 32b and the fourth groove 31b.

[0040] It should be noted that "filled" means that no more material can enter the groove, including the case of complete filling, as well as the case where there are air gaps inside the filling structure due to process reasons.

[0041] In some embodiments, the material of the connection structure 60 includes tungsten metal and the material of the second electrode 32 includes titanium nitride. Although tungsten metal has better conductivity than titanium nitride, tungsten intrusion into the capacitor region will introduce a TiN / W dissimilar metal interface, causing fatal reliability problems such as electrochemical potential difference, interface corrosion voids, metal atom diffusion, electric field distortion, capacitance value drift, and dielectric micro-breakdown, which seriously degrades the electrical characteristics of the capacitor and the consistency of the cell.

[0042] Based on this, this application provides a semiconductor device, including: a stacked structure including an insulating layer stacked along a third direction; a transistor located between two adjacent insulating layers; a capacitor structure including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode, wherein the first electrode is located between two adjacent insulating layers and connected to the transistor in a first direction, the first direction being perpendicular to the third direction; wherein the surface of the first electrode facing away from the transistor forms a first groove, the two adjacent first electrodes and the insulating layer along the third direction form a second groove, the dielectric layer is in contact with the inner walls of the first groove and the second groove, the dielectric layer forms a third groove in the second groove, the dielectric layer forms a fourth groove in the first groove, and the second electrode is located at least on the inner walls of the third groove and the fourth groove.

[0043] In the semiconductor device of this application embodiment, the second electrode is located at least on the inner walls of the third and fourth grooves, that is, the second electrode covers the inner and outer surfaces of the first electrode. The effective coverage area of ​​the capacitor electrode is significantly increased through the composite curved surface structure of the third and fourth grooves, effectively improving the capacitor's storage capacity without increasing the cell layout area. Since the second electrode is located at least in the third groove, the interlayer structure support strength can be optimized. Furthermore, the pre-occupancy of the third groove by the second electrode can reduce the intrusion of other dielectrics into the capacitor region during subsequent processes. The high work function, strong dielectric diffusion barrier properties, and excellent electrochemical stability of the second electrode material can be utilized to improve the material uniformity and electric field distribution regularity of the capacitor region.

[0044] The structure of the semiconductor device provided in the above embodiments will be described below with reference to the accompanying drawings.

[0045] Please see Figure 6 and Figure 7 , Figure 6 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 2 , Figure 7 yes Figure 6 A top view of the semiconductor device at point A-A1.

[0046] The semiconductor device 100 includes a stacked structure 10, a transistor 20, and a capacitor structure 30. The stacked structure 10 includes insulating layers 11 stacked along a third direction Z. The transistor 20 is located between two adjacent insulating layers 11. The capacitor structure 30 includes a first electrode 31, a second electrode 32, and a dielectric layer 33 located between the first electrode 31 and the second electrode 32. The first electrode 31 is located between two adjacent insulating layers 11 and is connected to the transistor 20 in a first direction X, which is perpendicular to the third direction Z. The surface of the first electrode 31 facing away from the transistor 20 forms a first groove 31a, and two adjacent layers of the first electrode 31 and the insulating layer 11 along the third direction Z form a second groove 32a. The dielectric layer 33 is in contact with the inner walls of the first groove 31a and the second groove 32a. The dielectric layer 33 forms a third groove 32b in the second groove 32a and a fourth groove 31b in the first groove 31a. The second electrode 32 is located at least on the inner walls of the third groove 32b and the fourth groove 31b.

[0047] and Figure 1 The difference in the embodiments is that, Figure 6 The advantages of the second electrode 32, which fills both the first and second grooves 31a, are self-evident. Alternatively, the second electrode 32 can be said to fill both the third and fourth grooves 32b, preventing the connecting structure 60 from entering them. This avoids the material of the subsequent connecting structure 60 from intruding into the capacitor region. By utilizing the high work function, strong dielectric diffusion barrier properties, and excellent electrochemical stability of the second electrode material, the material uniformity and electric field distribution regularity of the capacitor region are improved.

[0048] See Figure 7 The second electrode 32 also fills the fifth groove 50b, so the branch 62 does not enter the fifth groove 50b, in order to further improve the material uniformity and electric field distribution regularity of the capacitor area.

[0049] Please see Figure 8 and Figure 9 , Figure 8 yes Figure 6 Another top view of the semiconductor device at point A-A1. Figure 9 yes Figure 8 A schematic cross-sectional view of the branch of the connecting structure at point B-B1. This embodiment is similar to... Figure 7 The difference in the embodiment is that the branch 62 is also filled with a fifth groove 50b.

[0050] In this embodiment, the second electrode 32 fills the third groove 32b and the fourth groove 31b, but the second electrode 32 and the branch 62 fill the fifth groove 50b. This achieves a relative balance between reducing contact resistance and improving the material uniformity of the capacitor region.

[0051] The branch 62 of the connecting structure 60 is embedded in the fifth groove 50b, which can increase the contact area with the second electrode 32 and form an integrated electrical conduction structure with the second electrode 32 extending along the second direction Y. This can effectively reduce the parasitic resistance and parasitic capacitance of the electrode interconnection and improve the signal transmission rate and response speed.

[0052] The following provides a detailed explanation of the structures involved in semiconductor devices.

[0053] The stacked structure 10 is formed by stacking multiple insulating layers 11 (e.g., silicon oxide) at equal intervals along the third direction Z, and is prepared by thin film deposition process, resulting in uniform film thickness.

[0054] Transistors 20 are disposed in the space between every two adjacent insulating layers 11. This structural design enables independent switching control of a single-layer memory cell (including transistors 20 and capacitor structure 30). Specifically, the first groove 31a is disposed on the same layer as transistor 20, and the second groove 32a is disposed on the same layer as insulating layer 11.

[0055] The capacitor structure 30 is a metal-insulator-metal (MIM) composite dielectric capacitor, with three layers tightly packed together. The first electrode 31, serving as the inner electrode, is at least partially disposed between the interlayer insulating layers 11 and extends along the first direction X. One end of the first electrode is electrically connected to the transistor 20 to achieve charge read / write transmission. The surface of the first electrode 31 connected to the transistor 20 is called the outer surface, and the surface of the first electrode 31 facing away from the transistor 20 is called the inner surface. The inner surface of the first electrode 31 forms a first groove 31a, constructing a U-shaped electrode structure and significantly increasing the electrode surface area. The second groove 32a is formed by the upper and lower adjacent layers of the first electrode 31 and the insulating layer 11 sandwiched in between, used to achieve electrode extension and filling, and interlayer electrical adaptation. Alternatively, the second groove 32a can be described as being located on the side of the first electrode 31 facing away from the first groove 31a, and the second groove 32a is disposed in the same layer as the insulating layer 11.

[0056] It should be noted that a complete first electrode 31 between two adjacent insulating layers 11 is a first electrode 31 layer, and two adjacent first electrodes 31 refer to two adjacent U-shaped first electrodes 31.

[0057] The dielectric layer 33 completely covers the entire surface of the first electrode 31 and the entire inner wall of the first groove 31a, with no exposed areas, thus providing insulation and improving dielectric performance. The second electrode 32, as the outer common electrode plate, conformally covers the inner walls of the first groove 31a and the second groove 32a together with the dielectric layer 33, and at least fills the third groove 32b. A first electrode 31 and a portion of the second electrode 32 disposed opposite to its inner and outer surfaces constitute a capacitor. Therefore, the capacitor structure 30 includes multiple capacitors spaced Z-spaced along a third direction, and these multiple capacitors share a common outer electrode plate.

[0058] In some embodiments, the materials of the first electrode 31 and the second electrode 32 may include at least one of high work function metallic conductive materials such as titanium nitride (TiN), tantalum nitride, tungsten, ruthenium, and platinum. The material of the dielectric layer 33 may include at least one of high-k dielectric materials and composite stacks such as alumina, hafnium oxide, zirconium oxide, and hafnium silicate.

[0059] In some embodiments, the second groove 32a is located between two adjacent layers of the first groove 31a, and the size of the first groove 31a along the first direction X is larger than the size of the second groove 32a along the first direction X. The first direction X is the connection direction between the first electrode 31 and the transistor 20.

[0060] In the direction of connection between the first electrode 31 and the transistor 20, the second groove 32a between the two layers of first grooves 31a is recessed relative to the first groove 31a. This ensures that the size of the upper and lower first electrodes 31 is maximized and the energy storage area is maximized, while reserving space for the support structure between adjacent first electrodes 31.

[0061] In some embodiments, in the first direction X, the first electrode 31 includes a protrusion 311 extending relative to the second groove 32a, the protrusion 311 being connected to the insulating layer 11. That is, the protrusion 311 overlaps with the upper and lower surfaces of the insulating layer 11, preventing the first electrode 31 from being completely suspended and structurally reducing electrode collapse and deformation.

[0062] In addition, the overlapping insulation layer 11 can isolate the direct coupling between the upper and lower first electrodes 31, which can weaken the interlayer metal coupling effect and block the vertical continuous leakage current channel while keeping the size of the upper and lower first electrodes 31 unchanged at the maximum energy storage area.

[0063] like Figure 6 As shown, the second electrode 32 is in contact with the inner walls of the third groove 32b and the fourth groove 31b. The first electrode 31 includes an end 310 facing away from the transistor 20, and the dielectric layer 33 and the second electrode 32 also cover the end 310 of the first electrode 31.

[0064] In other words, the dielectric layer 33 conformally covers the entire inner wall of the first groove 31a, the entire inner wall of the second groove 32a, and the end 310 of the first electrode 31 (i.e., the left end in the figure), and the dielectric layer 33 is in contact with the sidewall of the insulating layer 11, thereby achieving full-area insulation of the first electrode 31. The dielectric layer 33 extends continuously among the multiple first electrodes 31 arranged along the third direction Z, or in other words, multiple capacitors share the dielectric layer 33.

[0065] After the dielectric layer 33 is deposited, the cavity of the second groove 32a is covered by the dielectric layer 12, further reducing the cavity space and re-forming a smaller and more regular secondary cavity, namely the third groove 32b. The dielectric layer 33 adaptively forms the third groove 32b within the second groove 32a, further optimizing the coverage morphology of the second electrode 32 over the first electrode 31, improving the integrity and insulation performance of the capacitor structure 30, and significantly enhancing the device's withstand voltage and data retention capabilities.

[0066] See Figure 6 The second electrode 32, together with the dielectric layer 33, fills the second groove 32a, and the second electrode 32 fills the third groove 32b, while also covering the end 310 of the first electrode 31, thus forming a common outer electrode plate for multiple capacitors. Since the second groove 32a includes the third groove 32b, filling the third groove 32b with the second electrode 32 is also filling the second groove 32a.

[0067] It should be noted that the third groove 32b and the fourth groove 31b are both nested secondary cavities formed by adaptive molding of dielectric thin film. Their size is adaptively adapted to the filling shape of the second electrode 32, and they are compatible with various structural forms such as wall covering, partial filling, and full filling of the second electrode 32.

[0068] Please see Figures 10 to 12 , Figure 10 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 3 , Figure 11 yes Figure 10 A top view of the semiconductor device at point A-A1. Figure 12 yes Figure 11 A schematic cross-sectional view of the branch of the connecting structure at point B-B1. This embodiment is similar to... Figure 6 The difference in the embodiment is that the branch 62 is also filled with a fourth groove 31b.

[0069] See Figure 10 The second electrode 32 fills the third groove 32b; see also Figure 11 and Figure 12 The second electrode 32 fills the fifth groove 50b. See also Figure 10 and Figure 11The second electrode 32 and the branch 62 sequentially fill the fourth groove 31b.

[0070] The branch 62 of the connecting structure 60 fills the interior of the fourth groove 31b, achieving precise point-to-point connection between the main structure and each layer of capacitor electrodes. The main body 61 and the branch 62 are an integrated conductive structure, which effectively reduces contact resistance, improves electrode potential transmission efficiency, further optimizes device read / write speed, and ensures potential consistency across the entire array of cells.

[0071] In some embodiments, such as Figure 10 As shown, the dimension h1 of the first groove 31a along the third direction Z is greater than the dimension h2 of the second groove 32a along the third direction Z, where the third direction Z is the stacking direction of the insulating layer 11.

[0072] Since the thickness of each film layer is uniform on different surfaces, the dielectric layer 33 and the second electrode 32 are successively covered in the first groove 31a and the second groove 32a. When the first groove 31a has a larger dimension in the third direction Z, the second electrode 32 can fill the second groove 32a (i.e. fill the third groove 32b) while the second electrode 32 does not fill the fourth groove 31b, thereby making the branch 62 fill the fourth groove 31b.

[0073] Please see Figure 13 and Figure 14 , Figure 13 yes Figure 10 Another cross-sectional view of the semiconductor device at point A-A1. Figure 14 yes Figure 13 A schematic cross-sectional view of the branch of the connecting structure at point B-B1. This embodiment is similar to... Figure 11 and Figure 12 The difference in the embodiment is that the branch 62 is also filled with a fifth groove 50b.

[0074] See Figure 10 The second electrode 32 fills the third groove 32b; see also Figure 10 and Figure 13 The second electrode 32 and the branch portion 62 sequentially fill the fourth groove 31b. (See also...) Figure 13 and Figure 14 The second electrode 32 and the branch 62 sequentially fill the fifth groove 50b.

[0075] Please combine Figure 15 , Figure 15 This is a top view schematic diagram of a semiconductor device provided in some embodiments of this application. The difference between this embodiment and the above embodiments is that this embodiment shows more array structures of the semiconductor device.

[0076] In the first direction X, two capacitor structures 30 are symmetrically distributed on both sides of the connecting structure 60, and the two capacitor structures 30 share a single connecting structure 60. Within one capacitor structure 30, multiple capacitors are also arranged at intervals along the second direction Y. The connecting structure 60 extends along the second direction Y to connect the multiple capacitors arranged along the second direction Y.

[0077] It should be noted that the above cross-sectional view only shows that the first electrode 31 of the capacitor structure 30 is separated by the insulating layer 11 in the third direction Z. Figure 15 The embodiment shows that the first electrode 31 is separated by an isolation structure 50 in the second direction Y. The isolation structure 50 is a dielectric isolation wall that runs vertically through the third direction Z and is evenly spaced along the second direction Y to separate adjacent memory cells in the second direction Y. The transistor 20 and the first electrode 31 are both confined within the region between two adjacent isolation structures 50, achieving physical isolation in the second direction Y.

[0078] The second electrode 32 is also located on the sidewall of the isolation structure 50 in the first direction X, near the first electrode 31. In other words, the isolation structure 50 is located on the sidewall of the capacitor structure 30 (i.e., Figure 2 The sidewall of the middle trench 50a is exposed, and the second electrode 32 extends to cover the sidewall area, so as to realize continuous conduction of the entire electrode plate and ensure uniform and stable potential of the array electrode plate.

[0079] In some embodiments, the sidewalls of the isolation structure 50 may be aligned with the sidewalls of the insulating layer 11, except that the isolation structure 50 is a continuous through-structure in the third direction Z, while the insulating layer 11 is an interlayer structure.

[0080] See Figure 15 and Figure 6 The transistor 20 includes a channel layer 21 and a gate layer 22. The gate layer 22 surrounds a portion of the surface of the channel layer 21, and the gate layer 22 exposes at least a portion of the sidewalls of the channel layer 21. The sidewalls are connected to the first electrode 31. The transistor 20 adopts a surround gate structure, which fully covers the channel layer 21, greatly improving the gate control capability. Only one sidewall is reserved as an electrical connection terminal, which is precisely connected to the first electrode 31.

[0081] The transistor 20 also includes a gate insulating layer 23 located between the gate layer 22 and the channel layer 21, the gate insulating layer 23 also exposing the portion of the sidewall of the channel layer 21.

[0082] The semiconductor device further includes a word line 70 extending along a second direction Y and a bit line 80 extending along a third direction Z. The word line 70 is connected to the gate layer 22 of the plurality of transistors 20. The channel layer 21 is disposed around the surface of the bit line 80. The third direction Z is the stacking direction of the insulating layer 11. The second direction Y is perpendicular to the third direction Z.

[0083] Each word line 70 is connected to multiple gate layers 22 located on the same side of the word line 70, and the word line 70 and the multiple gate layers 22 are connected in the same layer. A transistor 20 is disposed between the word line 70 and the capacitor structure 30. The word line 70 controls the conduction and turn-off of the transistor 20. The transistor 20, sandwiched between the word line 70 and the capacitor, acts as a dedicated switch for the capacitor. When on, the bit line 80 can quickly charge and discharge the capacitor to complete data reading and writing; when off, it completely cuts off the path between the capacitor and the external circuit, latching the charge and retaining the data.

[0084] The channel layer 21 may be made of at least one of amorphous AOS oxide semiconductor materials such as indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), and indium zinc oxide (IZO). The gate insulating layer 23 may be made of single-layer or multi-layer composite dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide. The gate layer 22, word line 70, and bit line 80 are made of conductive materials, such as highly conductive and stable materials like tungsten, titanium, titanium nitride, cobalt, and polycrystalline silicon.

[0085] In the embodiments of this application, the semiconductor device adopts a vertical bit line (V-BL) architecture with word lines 70 and bit lines 80 arranged orthogonally. The addressing logic is clear and the array arrangement is regular, which can realize high-density cell precise addressing. It is perfectly adapted to the working mechanism of 3D DRAM vertical stacking and solves the defects of traditional planar transistors such as weak gate control, large leakage current and low array density.

[0086] In some embodiments, the semiconductor device further includes a word line slot structure 71 extending along the second direction Y, consistent with the extension direction of the word line 70. If a capacitor structure 30 and a plurality of transistors 20 on both sides are considered as a memory cell group 101, the word lines 70 between two adjacent memory cell groups 101 in the first direction X are separated by the word line slot structure 71 to avoid signal coupling between them.

[0087] In some embodiments, the semiconductor device further includes a spacer structure 40 located between the channel layer 21 and two adjacent insulating layers 11, and between the gate layer 22 and the first electrode 31.

[0088] By utilizing the space between the insulating layer 11 and the channel layer 21 to set the spacing structure 40, not only can the gate layer 22 and the first electrode 31 be effectively isolated, reducing the risk of short circuit failure between the gate layer 22 and the first electrode 31, but also the channel layer 21 can be protected, interface defects and leakage channels can be repaired, further reducing transistor leakage current and improving the stability and reliability of the device during long-term operation.

[0089] Accordingly, embodiments of this application provide a method for forming a semiconductor device, used to form the aforementioned semiconductor device. Please refer to... Figure 16 , Figure 16 This is a schematic flowchart of a method for forming a semiconductor device according to some embodiments of this application. The method for forming the semiconductor device includes: S1: Forming a stacked layer, the stacked layer comprising an insulating layer and a dielectric layer alternately stacked along a third direction; S2: Forming a transistor, wherein the transistor is located between two adjacent insulating layers; S3: Forming a capacitor structure, the capacitor structure including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode, the first electrode being located between two adjacent insulating layers and connected to the transistor in a first direction, the first direction being perpendicular to the third direction; the surface of the first electrode facing away from the transistor forming a first groove; the two adjacent first electrodes and insulating layers along the third direction forming a second groove, the dielectric layer contacting the inner walls of the first groove and the second groove, the dielectric layer forming a third groove in the second groove, the dielectric layer forming a fourth groove in the first groove, and the second electrode being located at least on the inner walls of the third groove and the fourth groove.

[0090] In the semiconductor device formed by the embodiments of this application, the second electrode is located at least on the inner walls of the third and fourth grooves, that is, the second electrode covers the inner and outer surfaces of the first electrode. The effective coverage area of ​​the capacitor electrode is significantly increased through the composite curved surface structure of the third and fourth grooves, effectively improving the capacitor storage capacity without increasing the cell layout area. Since the second electrode is located at least in the third groove, the interlayer structure support strength can be optimized, and the pre-occupation of the third groove by the second electrode can also reduce the intrusion of other dielectrics in subsequent processes into the capacitor area.

[0091] The method for forming a semiconductor device provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0092] Please see Figures 17 to 48 , Figures 17 to 48 This is a schematic diagram of the semiconductor device during its formation process according to some embodiments of this application.

[0093] Step S1: Form a stacked layer 10a, the stacked layer 10a comprising an insulating layer 11 and a dielectric layer 12 alternately stacked along the third direction Z.

[0094] See Figure 17 and Figure 18 , Figure 18 yes Figure 17 A top view of the structure at point A-A1.

[0095] A substrate 102 is provided, and a stacked layer 10a is formed on the substrate 102. The stacked layer 10a includes an insulating layer 11 and a dielectric layer 12 alternately stacked. An exemplary material for the insulating layer 11 is silicon oxide, and an exemplary material for the dielectric layer 12 is silicon nitride. The insulating layer 11 and the dielectric layer 12 have different etching selectivity. The deposition process for the insulating layer 11 and the dielectric layer 12 can employ, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering, and other methods.

[0096] See Figure 18 and Figure 15 The method of forming the semiconductor device further includes: forming an isolation structure 50 that extends through the stacked layer 10a along the third direction Z, the isolation structure 50 being located between two adjacent transistors 20 in the second direction Y.

[0097] For example, after the stacked layer 10a is formed, an isolation structure 50 is prepared vertically through the third direction Z by deep trench etching and dielectric filling processes. This structure is then arranged at equal intervals along the second direction Y to complete the partitioning and isolation of the memory cells in the second direction Y. The isolation structure 50 is mainly used to isolate the transistor 20 and the first electrode 31, and at least a portion of the isolation structure 50 can provide film-forming space for the dielectric layer 33 and the second electrode 32 of the subsequent capacitor structure 30, so as to form a continuous common outer electrode plate in the second direction Y.

[0098] S2: Forming a transistor 20, the transistor 20 being located between two adjacent insulating layers 11.

[0099] See Figures 19 to 48It should be noted that the top view following each cross-sectional view is the top view of the corresponding semiconductor device at A-A1 (i.e., the layer where dielectric layer 12 is located), and will not be explained one by one.

[0100] The method for forming the transistor 20 includes the following steps.

[0101] See Figures 19 to 22 A through hole 20a is formed that penetrates the stacked layer 10a along the third direction Z. The through hole 20a includes a connected bit line hole 80a and a channel hole 21a. The channel hole 21a is disposed around the sidewall of the bit line hole 80a.

[0102] like Figure 19 and Figure 20 As shown, a bit line via 80a is first formed along the third direction Z through the stacked layer 10a. The bit line via 80a is located between two adjacent isolation structures 50 in the second direction Y. The formation process of the bit line via 80a may include anisotropic dry etching process.

[0103] like Figure 21 and Figure 22 As shown, a portion of the dielectric layer 12 is partially etched through the bit line hole 80a to form a channel hole 21a surrounding the sidewall of the bit line hole 80a. The etching process may include a wet etching process, in which the dielectric layer 12 has a higher etching selectivity than the insulating layer 11.

[0104] See Figures 23 to 26 A gate layer 22, a gate insulating layer 23, and a sacrificial layer 24 are sequentially formed within the through hole 20a, with the gate layer 22 and the gate insulating layer 23 located on the inner wall of the channel hole 21a.

[0105] like Figure 23 and Figure 24 As shown, the formation process of the gate layer 22 may include a deposition process and an etch-back process, so that the gate layer 22 is formed only within the channel via 21a and is disconnected at the sidewall of the bit line via 80a. The formation process of the gate insulating layer 23 includes a deposition process, so the gate insulating layer 23 covers the surface of the gate layer 22, the sidewall of the insulating layer 11, and the bottom of the bit line via 80a.

[0106] like Figure 25 and Figure 26 As shown, the formation process of the sacrificial layer 24 may include a deposition process and a planarization process, so that the sacrificial layer 24 fills the remaining space of the channel via 21a and the bit line via 80a. The sacrificial layer 24 is located on the surface of the gate insulating layer 23.

[0107] In this embodiment, the sacrificial layer 24 is removed after the capacitor structure 30 is formed, followed by the formation of the channel layer 21 and bit line 80. The temporary protection technique of the sacrificial layer 24 and the subsequent channel forming process avoid performance damage to the semiconductor channel material caused by the earlier high-temperature etching process, thus stabilizing the electrical performance of the transistor 20.

[0108] In some embodiments, see Figures 27 to 30 The formation of the semiconductor device also includes forming word lines 70 extending along the second direction Y.

[0109] See Figure 27 and Figure 28 A word line slot 71a extending in the second direction Y is formed on the side of transistor 20 away from capacitor structure 30; a portion of dielectric layer 12 is removed through the word line slot 71a to form word line groove 70a.

[0110] See Figure 29 and Figure 30 A character line 70 is formed in the character line groove 70a, and a character line gap structure 71 is formed in the character line gap 71a.

[0111] See Figure 33 and Figure 34 A portion of the gate layer 22 and a portion of the gate insulating layer 23 are removed to form the first initial groove 311a that exposes the sacrificial layer 24.

[0112] Specifically, the dielectric layer 12 can be removed first through the capacitor trench 60a to expose the gate layer 22 and the gate insulating layer 23; then, part of the gate layer 22 and part of the gate insulating layer 23 can be removed through an etching process.

[0113] The purpose of this step is to expose part of the sacrificial layer 24 so that when the sacrificial layer 24 is subsequently replaced with the channel layer 21, part of the sidewalls of the channel layer 21 can also be exposed so as to connect with the first electrode 31.

[0114] See Figures 45 to 48 Remove the sacrificial layer 24 and form a channel layer 21 connected to the first electrode 31 in the channel hole 21a.

[0115] like Figure 45 and Figure 46 As shown, the entire sacrificial layer 24 can be removed by etching after the entire capacitor structure 30 is formed.

[0116] like Figure 47 and Figure 48 As shown, a channel layer 21 is deposited within the channel hole 21a to achieve precise electrical connection between the channel layer 21 and the first electrode 31. Because... Figure 23The gate insulating layer 23 covers all the exposed surfaces of the gate layer 22, so the gate insulating layer 23 can completely isolate the channel layer 21 from the gate layer 22.

[0117] In some embodiments, a single deposition process can be used to fill the channel hole 21a and cover the sidewall of the bit line hole 80a with the channel layer 21, and the bit line 80 is formed on the surface of the channel layer 21 and fills the bit line hole 80a.

[0118] In other embodiments, the channel layer 21 can be located only within the channel hole 21a by deposition and etch-back processes.

[0119] S3: Forming a capacitor structure 30, the capacitor structure 30 includes a first electrode 31, a second electrode 32, and a dielectric layer 33 located between the first electrode 31 and the second electrode 32. The first electrode 31 is located between two adjacent insulating layers 11 and is connected to the transistor 20 in a first direction X, the first direction X being perpendicular to the third direction Z. The surface of the first electrode 31 facing away from the transistor 20 forms a first groove 31a. Two adjacent layers of the first electrode 31 and the insulating layer 11 along the third direction Z form a second groove 32a. The dielectric layer 33 is in contact with the inner walls of the first groove 31a and the second groove 32a. The dielectric layer 33 forms a third groove 32b in the second groove 32a and a fourth groove 31b in the first groove 31a. The second electrode 32 is located at least on the inner walls of the third groove 32b and the fourth groove 31b.

[0120] See Figures 31 to 44 The method for forming the capacitor structure 30 includes the following steps.

[0121] See Figure 31 and Figure 32 A capacitor groove 60a is formed that penetrates the stacked layer 10a along a third direction Z. The capacitor groove 60a extends along a second direction Y. The third direction Z is the stacking direction of the stacked layer 10a. The second direction Y is perpendicular to the third direction Z and intersects with the first direction X.

[0122] A deep trench etching process is used to form a long strip capacitor trench 60a extending through the entire stacked structure 10 and along the second direction Y, etched along the third direction Z. This opens up the fabrication process window for each capacitor layer. It should be noted that this capacitor trench 60a is filled at the end of the process to form... Figure 15 The main body 61 of the connecting structure 60 shown.

[0123] See Figure 33 and Figure 34A portion of the dielectric layer 12 is removed through the capacitor groove 60a to form a first initial groove 311a.

[0124] By utilizing the etching selectivity ratio between the dielectric layer 12 and the insulating layer 11, a portion of the dielectric layer 12 is selectively etched away through the capacitor trench 60a to form the first initial trench 311a. The partial removal of the gate layer 22 and the gate insulating layer 23, as described above, is also performed through this capacitor trench 60a.

[0125] In some embodiments, see Figure 35 and Figure 36 The method for forming the semiconductor device further includes forming a spacing structure 40 between the channel layer 21 and the two adjacent insulating layers 11, and between the gate layer 22 and the first electrode 31.

[0126] The formation process of the spacer structure 40 includes a deposition process and an etch-back process, which enables the spacer structure 40 to isolate and protect the exposed gate layer 22.

[0127] See Figure 37 and Figure 38 A first electrode 31 and a first groove 31a formed by the first electrode 31 are formed on the inner wall of the first initial groove 311a.

[0128] A first electrode 31 is fabricated on the inner wall of the first initial groove 311a using a conductive thin film conformal deposition process, and the first groove 31a is adaptively formed by the conformal deposition characteristics of the thin film.

[0129] See Figure 39 and Figure 40 A portion of the insulating layer 11 is removed through the capacitor groove 60a to form a second groove 32a.

[0130] By selectively etching the interlayer local insulating layer 11 through the window of the reused capacitor trench 60a, a necked second groove 32a (i.e., recessed relative to the first groove 31a) is formed. It should be noted that after removing part of the insulating layer 11, the stacked layer 10a becomes the stacked structure 10.

[0131] like Figure 40 As shown, the method for forming the semiconductor device further includes: in the process of forming the second groove 32a, removing a portion of the isolation structure 50 to form a trench 50a. The material of the isolation structure 50 is the same as the material of the insulating layer 11.

[0132] See Figures 41 to 44 A dielectric layer 33 and a second electrode 32 are sequentially formed on the inner walls of the first groove 31a and the second groove 32a. Simultaneously, as... Figure 42 and Figure 44As shown, the dielectric layer 33 and the second electrode 32 are also formed within the trench 50a.

[0133] For example, by using the ALD atomic layer deposition process, a dielectric layer 33 and a second electrode 32 are sequentially deposited on the inner wall of the entire double groove to complete the integrated molding of the three-layer structure of the MIM capacitor.

[0134] like Figure 41 As shown, a dielectric layer 33 is first formed, which forms a third groove 32b within the second groove 32a, and a fourth groove 31b within the first groove 31a; as Figure 42 As shown, the dielectric layer 33 forms a fifth groove 50b dielectric layer 33 within the trench 50a.

[0135] like Figure 43 and Figure 44 As shown, a second electrode 32 is formed on the inner wall of the third groove 32b and the fourth groove 31b, and a connection structure 60 is formed on the surface of the second electrode 32.

[0136] In some embodiments, such as Figure 43 As shown, the second electrode 32 fills the third groove 32b, and the second electrode 32 and the branch 62 fill the fourth groove 31b; as Figure 44 As shown, the second electrode 32 and the branch 62 fill the fifth groove 50b.

[0137] In other embodiments, the second electrode 32 can directly fill the fourth groove 31b and / or the fifth groove 50b. For example, if the second electrode 32 can fill the fourth groove 31b, then a shape is formed as follows: Figure 6 The structure corresponding to the embodiment. For example, if the second electrode 32 can fill the fifth groove 50b, then a structure is formed. Figure 7 The structure corresponding to the embodiment.

[0138] It should be noted that by adjusting the spacing between adjacent insulating layers 11, the thickness of the insulating layer 11, and the thickness of the second electrode 32, common outer electrode plates with different structures can be formed. For example, in Figure 43 In the process, if the size of the fourth groove 31b matches the thickness of the second electrode 32, then the second electrode 32 can fill the fourth groove 31b (i.e. fill the first groove 31a).

[0139] Since the entire forming process of capacitor structure 30 reuses the same capacitor slot 60a process window, there is no need for multiple alignments and multiple slottings, which greatly simplifies the process flow, reduces alignment deviations and process complexity, and effectively improves the capacitor forming accuracy and array unit uniformity.

[0140] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. In the above embodiments, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. The embodiments, implementation methods, and related technical features of this application can be combined and substituted with each other without conflict.

[0141] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure, including insulating layers stacked along a third direction; A transistor is located between two adjacent insulating layers; A capacitor structure includes a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode. The first electrode is located between two adjacent insulating layers and is connected to the transistor in a first direction, which is perpendicular to the third direction. Wherein, the surface of the first electrode facing away from the transistor forms a first groove, the two adjacent layers of the first electrode and the insulating layer along the third direction form a second groove, the dielectric layer is in contact with the inner walls of the first groove and the second groove, the dielectric layer forms a third groove in the second groove, the dielectric layer forms a fourth groove in the first groove, and the second electrode is located at least on the inner walls of the third groove and the fourth groove.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: an isolation structure extending along the third direction and spaced apart along the second direction, the second direction being perpendicular to the third direction and intersecting the first direction; The transistor is located between two adjacent isolation structures in the second direction; two adjacent first electrodes in the same layer along the second direction form a trench with the isolation structure, the dielectric layer is in contact with the inner wall of the trench, the dielectric layer forms a fifth groove in the trench, and the second electrode is also located at least on the inner wall of the fifth groove.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a connection structure connected to the second electrode, the connection structure including a main body and a branch, the main body extending along the third direction and the second direction, and the branch extending along the first direction.

4. The semiconductor device according to claim 3, characterized in that, The second electrode fills the third groove, and the second electrode and the branch successively fill the fourth groove and the fifth groove.

5. The semiconductor device according to claim 3, characterized in that, The second electrode fills the third and fifth grooves, and the second electrode and the branch sequentially fill the fourth groove.

6. The semiconductor device according to claim 3, characterized in that, The second electrode and the branch portion sequentially fill the third groove, the fourth groove, and the fifth groove.

7. The semiconductor device according to claim 3, characterized in that, The second electrode fills the fifth groove, and the second electrode and the branch successively fill the third groove and the fourth groove.

8. The semiconductor device according to claim 3, characterized in that, The second electrode fills the third and fourth grooves, and the second electrode and the branch sequentially fill the fifth groove.

9. The semiconductor device according to claim 3, characterized in that, The second electrode fills the third groove, the fourth groove, and the fifth groove.

10. The semiconductor device according to any one of claims 1-9, characterized in that, The second groove and the first groove are arranged alternately along the third direction, and the dimension of the first groove along the first direction is greater than the dimension of the second groove along the first direction.

11. The semiconductor device according to any one of claims 1-9, characterized in that, In the first direction, the first electrode includes a protrusion extending relative to the second groove, the protrusion being connected to the insulating layer.

12. The semiconductor device according to any one of claims 1-9, characterized in that, The transistor includes a channel layer and a gate layer, the gate layer surrounding a portion of the surface of the channel layer, and the gate layer exposing at least a portion of the sidewalls of the channel layer, the portion of the sidewalls being connected to the first electrode; The semiconductor device further includes word lines extending along the second direction and bit lines extending along the third direction, the word lines being connected to the gate layers of the plurality of transistors, and the channel layers being disposed around the surface of the bit lines.

13. The semiconductor device according to claim 12, characterized in that, It also includes a spacer structure located between the channel layer and two adjacent insulating layers, and between the gate layer and the first electrode.

14. A method for forming a semiconductor device, characterized in that, include: A stacked layer is formed, the stacked layer comprising an insulating layer and a dielectric layer alternately stacked along a third direction; A transistor is formed, the transistor being located between two adjacent insulating layers; A capacitor structure is formed, the capacitor structure including a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode. The first electrode is located between two adjacent insulating layers and is connected to the transistor in a first direction, which is perpendicular to the third direction. The surface of the first electrode facing away from the transistor forms a first groove. The two adjacent first electrodes and insulating layers along the third direction form a second groove. The dielectric layer is in contact with the inner walls of the first groove and the second groove. The dielectric layer forms a third groove in the second groove and a fourth groove in the first groove. The second electrode is located at least on the inner walls of the third groove and the fourth groove.

15. The method for forming a semiconductor device according to claim 14, characterized in that, Methods for forming capacitor structures include: A capacitor trench is formed that penetrates the stacked layer along the third direction, the capacitor trench extends along a second direction that is perpendicular to the third direction and intersects the first direction; A portion of the dielectric layer is removed through the capacitor trench to form a first initial groove; A first electrode and a first groove formed by the first electrode are formed on the inner wall of the first initial groove; A second groove is formed by removing part of the insulating layer through the capacitor groove; A dielectric layer and a second electrode are sequentially formed on the inner wall of the first groove and the inner wall of the second groove.

16. The method for forming a semiconductor device according to claim 15, characterized in that, The method for forming the semiconductor device further includes: An isolation structure is formed that extends through the stacked layer along the third direction, and the isolation structure is located between two adjacent transistors in the second direction; In the process of forming the second groove, a portion of the isolation structure is removed to form a trench, and the dielectric layer and the second electrode are also formed within the trench.

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