Semiconductor device and method of forming the same

Abstract

The application discloses a semiconductor device and a forming method thereof, and belongs to the technical field of semiconductors. In the process of forming a channel structure, a patterning process is used to protect a first supporting layer by a first etching stop layer, so that the first supporting layer is prevented from being etched, the electrical isolation and mechanical supporting performance of a first insulating structure to the channel structure are ensured, and the collapse risk of the channel structure is reduced, thereby providing a good implementation basis for a process flow of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Technology

[0002] With the development of semiconductor technology, the process technology of DRAM (Dynamic Random Access Memory) has been advanced to 10nm and below. In order to break through the area bottleneck of the traditional planar 1T1C (1 Transistor 1 Capacitor) structure of 6F² (6 times feature size squared) and achieve higher density and lower cost, the industry has turned to the VCT (Vertical Channel Transistor) architecture, whose theoretical cell area can be reduced to 4F².

[0003] The process and structural stability of the VCT architecture are key concerns for those skilled in the art.

[0004] Therefore, there is an urgent need for a new layout structure that can improve the stability of the process and structure. Summary of the Invention

[0005] This application provides a semiconductor device and a method for forming the same, to at least partially solve the above-mentioned technical problems.

[0006] To achieve the above objectives, according to a first aspect of this application, a semiconductor device is provided, comprising: Base; A plurality of first insulating structures are disposed on one side of the substrate, and the plurality of first insulating structures are arranged at intervals in a first direction; Multiple channel structures are located on both sides of the first insulating structure in the first direction; Multiple word line conductive structures, wherein the channel structure is located between the first insulating structure and the word line conductive structures; The first insulating structure includes a first etch stop layer and a first support layer stacked in a second direction. The first etch stop layer is disposed on the side of the first support layer away from the substrate. The second direction is perpendicular to the plane where the substrate is located, and the first direction is parallel to the plane where the substrate is located.

[0007] Optionally, it further includes: a bit line layer disposed between the channel structure and the substrate, the bit line layer including a plurality of bit line structures, the bit line structures extending in the first direction, and the plurality of bit line structures being spaced apart in a third direction; wherein, the first insulating structure further includes a second etch stop layer disposed between the first support layer and the bit line layer, the third direction being parallel to the plane of the substrate.

[0008] Optionally, the semiconductor device further includes a third insulating structure and a first dielectric layer; along the first direction, the third insulating structure is located between two adjacent word line conductive structures, the third insulating structure extends upward in the third direction, the first dielectric layer covers the third insulating structure, and a portion of the first dielectric layer is disposed between the third insulating structure and the word line conductive structure; wherein, the dielectric constant of the third insulating structure is less than the dielectric constant of the first dielectric layer.

[0009] Optionally, the third insulation structure includes an air gap.

[0010] Optionally, the orthographic projection of the word line conductive structure onto the third insulating structure lies within the third insulating structure.

[0011] Optionally, the plurality of channel structures of the semiconductor device are arranged at intervals along the first direction and in a third direction, and the first insulating structure extends in the third direction.

[0012] Optionally, the semiconductor device further includes a gate insulating layer disposed between the word line conductive structure and the corresponding channel structure; a first partition groove is provided between two adjacent channel structures arranged upward along the third direction, and a portion of the word line conductive structure and a portion of the gate insulating layer are disposed within the first partition groove.

[0013] Optionally, a second partition groove is provided between two adjacent channel structures arranged along the first direction, and a portion of the first medium layer is disposed within the second partition groove.

[0014] Optionally, the dielectric constant of the first support layer is less than the dielectric constant of the first etch stop layer, and the orthogonal projection of the word line conductive structure onto the first insulating structure lies within the first support layer.

[0015] Optionally, the channel structure includes a first channel portion and a second channel portion extending vertically from the first channel portion, the second channel portion extending in the second direction, and the first channel portion extending away from the side corresponding to the first insulation structure.

[0016] Optionally, the side of the word line conductive structure away from the corresponding second channel portion is flush with the side of the corresponding first channel portion away from the corresponding first insulating structure.

[0017] Optionally, along the second direction, the top surface of the first channel portion is higher than the top surface of the second etch stop layer.

[0018] According to a second aspect of this application, a method for forming a semiconductor device is provided, comprising: A plurality of first insulating structures are formed on one side of the substrate and spaced apart along a first direction. Each first insulating structure includes a first support layer disposed along a second direction and a first etch stop layer located on the side of the first support layer away from the substrate. The second direction is perpendicular to the plane in which the substrate is located, and the first direction is parallel to the plane in which the substrate is located. A channel structure and a word line conductive structure are formed on both sides of the first insulating structure in the first direction, wherein the channel structure is located between the first insulating structure and the word line conductive structure.

[0019] Optionally, the method of forming a plurality of first insulating structures spaced apart along a first direction on one side of a substrate includes: providing a substrate; forming a bit line layer on one side of the substrate, the bit line layer including a plurality of bit line structures and a second insulating structure arranged alternately in a third direction; forming a plurality of first insulating structures on the side of the bit line layer away from the substrate, the first insulating structure including a second etch stop layer, a first support layer and the first etch stop layer stacked sequentially.

[0020] Optionally, the method for forming the semiconductor device further includes: forming a first dielectric layer and a third insulating structure between two adjacent word line conductive structures in the first direction, wherein the first dielectric layer covers the third insulating structure.

[0021] In the semiconductor device of this application embodiment, through the above technical solution, a patterning process is performed during the formation of the channel structure. The first etch stop layer is used to protect the first support layer and prevent the first support layer from being etched, so as to ensure the electrical isolation and mechanical support performance of the first insulating structure for the channel structure, reduce the risk of channel structure collapse, and provide a good implementation basis for the semiconductor device process flow.

[0022] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0025] Figure 1 This is a schematic diagram of a first three-dimensional structure of a semiconductor device provided in some embodiments of this application; Figure 2 yes Figure 1 A magnified view of a portion of region A along the third direction upwards; Figure 3 yes Figure 1 A schematic diagram of a structure in which part of the film layer is removed; Figure 4 This is a schematic diagram of a second three-dimensional structure of a semiconductor device provided in some embodiments of this application; Figure 5 This is a schematic diagram of a third three-dimensional structure of a semiconductor device provided in some embodiments of this application; Figure 6 This is a schematic flowchart of a method for forming a semiconductor device provided in some embodiments of this application; Figures 7 to 19 This is a schematic diagram of the semiconductor device during its formation process according to some embodiments of this application.

[0026] Explanation of reference numerals in the attached figures: 10. Semiconductor device; D1. First direction; D2. Second direction; D3. Third direction; 11. Substrate; 20. Bit line layer; 21. Bit line structure; 22. Second insulating structure; 30. First insulating structure; 31. First etch stop layer; 32. First support layer; 33. Second etch stop layer; 34. First etch stop material layer; 35. First support material layer; 36. Second etch stop material layer; 40. Channel structure; 41. First isolation trench; 42. Second isolation trench; 43. Channel material layer; 44. First sacrificial pattern layer; 45. First etched groove; 46. Channel front body; 47. First channel portion; 48. Second channel portion; 50. Word line conductive structure; 51. Word line material layer; 60. Gate insulating layer; 61. Gate insulating material layer; 70. Third insulating structure; 71. Air gap; 72. Third insulating material layer; 80. First dielectric layer; 81. First dielectric material layer; 82. First groove; 83. Second dielectric material layer; 90. Capacitor structure. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0028] Reference Figures 1 to 5 This application provides a semiconductor device 10, including: a substrate 11, a plurality of first insulating structures 30, a plurality of channel structures 40, and a plurality of word line conductive structures 50; the plurality of first insulating structures 30 are disposed on one side of the substrate 11, and the plurality of first insulating structures 30 are spaced apart in a first direction D1; the plurality of channel structures 40 are located on both sides of the first insulating structures 30 in the first direction D1; the channel structures 40 are located between the first insulating structures 30 and the word line conductive structures 50; wherein, the first insulating structure 30 includes a first etch stop layer 31 and a first support layer 32 stacked in a second direction D2, the first etch stop layer 31 is disposed on the side of the first support layer 32 away from the substrate 11, the second direction D2 is perpendicular to the plane where the substrate 11 is located, and the first direction D1 is parallel to the plane where the substrate 11 is located.

[0029] It is understood that the plane containing the first direction D1 and the third direction D3 is parallel to the plane containing the base 11, the second direction D2 is perpendicular to the plane containing the base 11, the second direction D2 is perpendicular to the first direction D1, and the second direction D2 is perpendicular to the third direction D3.

[0030] The word line conductive structure 50 can apply gate voltage control to the channel structure 40 to realize the conduction and turn-off of the channel, ensuring the accurate response of the transistor switching function. The first insulating structure 30 adopts an intermittent arrangement design, which can achieve physical and electrical isolation between adjacent channel structures 40 and word line conductive structures 50 in the first direction D1, effectively preventing crosstalk, leakage, and conduction interference between adjacent device units. During the formation of the channel structure, there will be a patterning process. The first etch stop layer is used to protect the first support layer and prevent the first support layer from being etched, so as to ensure the electrical isolation and mechanical support performance of the first insulating structure for the channel structure, reduce the risk of channel structure collapse, and provide a good implementation basis for the semiconductor device process flow.

[0031] Specifically, the channel structure 40 is made of metal oxide. Metal oxide semiconductor materials have the characteristics of large band width, high carrier mobility and extremely low intrinsic leakage current. They can improve the defects of traditional Si channels, such as narrow band width, significant short channel effect and large leakage current, effectively suppress leakage current problem in the device off state and improve the device switching characteristics and working stability. To leverage its low leakage current advantage, the metal oxide channel structure is relatively thin and requires stable support. The first support layer 32, as the main structure, possesses excellent mechanical strength and provides stable mechanical support for the thin metal oxide channel structure 40, offsetting the stress deformation of the ultra-thin channel film and reducing the risk of channel structure 40 collapsing or breaking. The first etch stop layer 31, located on the top layer, has etch resistance. In subsequent channel patterning, etching, and dielectric layer processing, it can act as a protective layer to prevent etching liquid and plasma from damaging the underlying first support layer 32, protecting the structural integrity of the first support layer 32, ensuring that the first insulating structure 30 continuously possesses reliable electrical isolation and mechanical support capabilities, and improving process compatibility and process yield.

[0032] In some embodiments, please refer to the following for details. Figure 1 The semiconductor device 10 further includes a bit line layer 20 disposed between the channel structure 40 and the substrate 11. The bit line layer 20 includes a plurality of bit line structures 21 extending in the first direction D1 and spaced apart in the third direction D3. The first insulating structure 30 further includes a second etch stop layer 33 disposed between the first support layer 32 and the bit line layer 20. The third direction D3 is parallel to the plane of the substrate 11.

[0033] The bit line layer 20 is integrated below the channel structure 40 to achieve a vertical integration layout of the transistor channel and bit lines. The layered layout of the bottom bit line layer 20 enables a regular arrangement of the memory cell array. The bit line structure 21 and the second insulating structure 22 are arranged alternately to achieve electrical isolation between adjacent bit line structures 21, avoiding signal crosstalk and short circuits between bit line structures 21. A second etch stop layer 33 is added at the bottom of the first support layer 32, so that the first insulating structure 30 forms a complete three-layer protective stack of the second etch stop layer 33, the first support layer 32, and the first etch stop layer 31. When multiple spaced first insulating structures 30 are formed, patterning is performed. The second etch stop layer 33 can precisely control the etching depth to prevent excessive etching from damaging the underlying bit line layer 20, ensuring the integrity and electrical performance of the bit line structure 21.

[0034] For details, please refer to Figure 1The bit line layer 20 also includes a second insulating structure 22 disposed between two adjacent bit line structures 21. The second etch stop layer 33 is made of silicon nitride, and the second insulating structure 22 can be made of silicon oxide. Silicon nitride and silicon oxide have a high etch selectivity ratio, which reduces the risk of over-etching the second insulating structure 22 during the etching process of the first insulating structure 30, thereby reducing the risk of damage to the bit line layer 20 structure. For specific embodiments, please refer to... Figure 1 , Figure 2 The semiconductor device 10 further includes a third insulating structure 70 and a first dielectric layer 80; along the first direction D1, the third insulating structure 70 is located between two adjacent word line conductive structures 50, the third insulating structure 70 extends along the third direction D3, the first dielectric layer 80 covers the third insulating structure 70, and a portion of the first dielectric layer 80 is disposed between the third insulating structure 70 and the word line conductive structure 50; wherein, the dielectric constant of the third insulating structure 70 is less than the dielectric constant of the first dielectric layer 80.

[0035] It is understood that multiple word line conductive structures 50 are located on both sides of the first insulating structure 30 and the channel structure 40 in the first direction D1. The word line conductive structures 50 extend in the third direction D3. The multiple word line conductive structures 50 are arranged at intervals in the first direction D1. Two spaced word line conductive structures 50 are provided between two adjacent first insulating structures 30. A third insulating structure 70 is provided between corresponding adjacent word line conductive structures 50 between two adjacent first insulating structures 30. The third insulating structure 70 is covered by a first dielectric layer 80. The first dielectric layer 80 achieves the filling, fixing and sealing of the overall structure, improving the overall structural compactness and mechanical stability of the device. The low dielectric constant of the third insulating structure 70 can reduce the parasitic capacitance between two adjacent word line conductive structures 50, reduce the WL coupling effect between word line conductive structures 50, reduce the device charging and discharging power consumption and signal delay, and improve the device switching speed and working efficiency.

[0036] Specifically, the material of the third insulating structure 70 can be SiCOH, MSQ (a low dielectric constant material based on silicon-based polymers), SiLK, etc.

[0037] In some embodiments, please refer to the following for details. Figure 4 , Figure 5The third insulating structure 70 includes an air gap 71. The air gap 71 is an insulating medium with the lowest dielectric constant. Compared with conventional solid insulating materials, it can minimize the parasitic capacitance inside the device, reduce the WL coupling effect between word line conductive structures 50, and optimize the performance of the device.

[0038] In some embodiments, please refer to the following for details. Figure 2 The orthographic projection of the word line conductive structure 50 onto the third insulating structure 70 lies within the third insulating structure 70. The thickness of the word line conductive structure 50 in the second direction D2 is represented by the designation V4, and the thickness of the third insulating structure 70 in the second direction D2 is represented by the designation V5. V5 is greater than V4, allowing the low-dielectric third insulating structure 70 to completely cover the projection area of ​​the word line conductive structure 50, maximizing the reduction of parasitic capacitance and WL coupling effects between the word line conductive structures 50, and improving the device's switching speed and operating efficiency.

[0039] In some embodiments, please refer to the following for details. Figure 3 The semiconductor device 10 has multiple channel structures 40 arranged at intervals along the first direction D1 and the third direction D3, and the first insulating structure 30 extends along the third direction D3. The channel structures 40 are arranged in an array to form a regular array of memory transistors, which is compatible with the large-scale array memory architecture of DRAM, realizes high-density and uniform integration of memory cells, and reduces manufacturing costs. The extended first insulating structure 30 can isolate and support the multiple sets of channel structures 40 arranged along the third direction D3, simplifying the device layout and fabrication process. The continuous first insulating structure 30 can improve the mechanical stability of the overall array, distribute the stress of adjacent thin film structures, and ensure the consistency of array cell performance.

[0040] In some embodiments, please refer to the following for details. Figure 1 , Figure 2 , Figure 3 The semiconductor device 10 further includes a gate insulating layer 60 disposed between the word line conductive structure 50 and the corresponding channel structure 40; a first partition groove 41 is provided between two adjacent channel structures 40 arranged along the third direction D3, and a portion of the word line conductive structure 50 and a portion of the gate insulating layer 60 are disposed within the first partition groove 41. The first partition groove 41 can physically isolate adjacent channel structures 40 in the third direction D3; at the same time, the word line conductive structure 50 and the gate insulating layer 60 are embedded inside the first partition groove 41, and multiple channel structures 40 arranged in the third direction D3 correspond to the same word line conductive structure 50, thereby realizing word line sharing and reuse in the third direction D3, reducing the number of word lines and wiring complexity; at the same time, it ensures the insulation between the channel structure 40 and the word line conductive structure 50.

[0041] In some embodiments, please refer to the following for details. Figure 1 , Figure 3 A second isolation groove 42 is provided between two adjacent channel structures 40 arranged along the first direction D1, and a portion of the first dielectric layer 80 is disposed within the second isolation groove 42. The second isolation groove 42 achieves physical isolation between adjacent channel structures 40 in the first direction D1. The second isolation groove 42 and the first isolation groove 41 form an isolation for multiple arrayed channel structures 40, ensuring the independent electrical characteristics of the channel structures 40. The second isolation groove 42 also completely isolates two adjacent word line conductive structures 50 in the first direction D1, avoiding crosstalk between word lines and further improving the integrity and anti-interference capability of word line signals.

[0042] In some embodiments, please refer to the following for details. Figure 2 The dielectric constant of the first support layer 32 is less than that of the first etch stop layer 31. The orthographic projection of the word line conductive structure 50 onto the first insulating structure 30 lies within the first support layer 32. Let V4 represent the thickness of the word line conductive structure 50 in the second direction D2, and let V2 represent the thickness of the first support layer 32 in the second direction D2. V2 is greater than V4. The material of the first support layer 32 can be silicon oxide, and the material of the first etch stop layer 31 can be silicon nitride. The dielectric constant of silicon oxide is less than that of silicon nitride. Two adjacent word line conductive structures 50 are provided on both sides of the first insulating structure 30 in the first direction D1. The orthographic projection of the word line conductive structure 50 completely falls within the range of the first support layer 32. By utilizing the first support layer 32 with its lower dielectric constant, the parasitic capacitance between word lines can be reduced, and the WL coupling effect can be suppressed.

[0043] In some embodiments, please refer to the following for details. Figure 2 The channel structure 40 includes a first channel portion 47 and a second channel portion 48 extending vertically from the first channel portion 47. The second channel portion 48 extends in the second direction D2, and the first channel portion 47 extends away from the side corresponding to the first insulating structure 30. The L-shaped vertical split channel structure 40 employs the vertically extending second channel portion 48 as the core conductive channel, ensuring efficient vertical carrier transport. The horizontally extending first channel portion 47 increases the contact area with the underlying structure, widening the stress support range of the channel structure 40. The mutually perpendicular first channel portion 47 and second channel portion 48 form support forces in two directions, ensuring the stability of the channel structure 40 in three-dimensional space. This improves the stress state of the thin metal oxide channel structure 40, reduces the risk of collapse, and improves the electrical performance and structural stability of the device.

[0044] In some embodiments, please refer to the following for details. Figure 2 The side of the word line conductive structure 50 away from the second channel portion 48 is flush with the side of the first channel portion 47 away from the first insulating structure 30. This flush structure can be formed in a single etching process, simplifying the manufacturing process. This application focuses on the vertical channel structure 40, where the word line conductive structure 50 does not need to extend excessively in the first direction D1. This shortens the size of the word line conductive structure 50 in the first direction D1, reducing material usage and helping to reduce the cell area and increase integration density.

[0045] In some embodiments, please refer to the following for details. Figure 2 The top surface of the first channel portion 47 is higher than the top surface of the second etch stop layer 33. Specifically, the thickness of the second etch stop layer 33 in the second direction D2 is less than or equal to the thickness of the first channel portion 47 in the second direction D2, and the hydrogen content in the second etch stop layer 33 is greater than the hydrogen content in the first support layer 32. It is understood that the first channel portion 47 is represented by the label V3 in the second direction D2, and the second etch stop layer 33 is represented by the label V1 in the second direction D2. V3 is greater than V1. The first channel portion 47 is directly electrically connected to the bit line structure 21. The first channel portion 47 mainly serves as a conductor connection. The second channel portion 48 is the actual channel region. The second etch stop layer 33 is made of silicon nitride, and the first support layer 32 can be made of silicon oxide. The high hydrogen content in silicon nitride will affect the second channel portion 48 and easily cause electrical offset. Therefore, by controlling the thickness of the second etch stop layer 33 to not exceed the thickness of the first channel portion 47, the diffusion depth of hydrogen atoms into the second channel portion 48 can be limited, thereby ensuring the stability of the carrier mobility of the channel structure 40.

[0046] In other embodiments, please refer to the details. Figure 5 The semiconductor device 10 further includes a plurality of capacitor structures 90 located on the side of the channel structure 40 away from the substrate 11. Each capacitor structure 90 corresponds to one channel structure 40, and the capacitor structures 90 extend along the second direction D2. It is understood that... Figure 5 This is a schematic diagram of the structure of some other embodiments of this application. These embodiments are similar to... Figures 1 to 4 The main framework, connection relationships, and working principles of the embodiments are the same, and the same structures and connection relationships will not be described again here.

[0047] Combination Figures 6 to 19 This application also provides a method for forming a semiconductor device 10, including: S1. A plurality of first insulating structures 30 are formed on one side of the substrate 11 at intervals along a first direction D1. Each first insulating structure 30 includes a first support layer 32 disposed along a second direction D2 and a first etch stop layer 31 located on the side of the first support layer 32 away from the substrate 11. The second direction D2 is perpendicular to the plane where the substrate 11 is located, and the first direction D1 is parallel to the plane where the substrate 11 is located.

[0048] S2. A channel structure 40 and a word line conductive structure 50 are formed on both sides of the first insulating structure 30 located in the first direction D1, wherein the channel structure 40 is located between the first insulating structure 30 and the word line conductive structure 50.

[0049] During the formation of the channel structure, a patterning process is used to protect the first support layer with a first etch stop layer, preventing the first support layer from being etched. This ensures the electrical isolation and mechanical support performance of the first insulating structure for the channel structure, reduces the risk of channel structure collapse, and provides a good implementation basis for the semiconductor device process flow.

[0050] In some embodiments, the method of forming the semiconductor device 10 includes: S1. A plurality of first insulating structures 30 are formed on one side of the substrate 11, spaced apart along a first direction D1. Each first insulating structure 30 includes a first support layer 32 disposed along a second direction D2 and a first etch stop layer 31 located on the side of the first support layer 32 away from the substrate 11. The second direction D2 is perpendicular to the plane of the substrate 11, and the first direction D1 is parallel to the plane of the substrate 11. (See details below.) Figures 7 to 10 .

[0051] Please see Figure 7 A substrate 11 is provided. The substrate 11 is the starting step in the fabrication of the semiconductor device 10, providing a physical carrier for all subsequent processes. The substrate 11 can be made of a variety of materials. For example, it can be a P-type or N-type doped single-crystal silicon wafer, which has good electrical properties and mature processing technology; or, in order to achieve better device isolation and reduce parasitic capacitance, an SOI (Silicon-On-Insulator) substrate 11 can be used, in which the upper silicon layer is used to form the device and the lower insulating layer provides natural electrical isolation.

[0052] Please see Figure 7 , Figure 8 A bit line layer 20 is formed on one side of the substrate 11. The bit line layer 20 includes a plurality of bit line structures 21 and a second insulating structure 22 arranged alternately in a third direction D3.

[0053] For details, please refer to Figure 7 , Figure 8 The bit line structure 21 and the second insulation structure 22 extend in the first direction D1. The bit line structure 21 is made of a highly conductive metal material such as tungsten or copper to ensure data read / write speed and signal integrity. The second insulation structure 22 is made of a low dielectric constant material such as silicon oxide to effectively reduce parasitic capacitance and crosstalk between bit lines.

[0054] Please see Figure 9 , Figure 10 A plurality of first insulating structures 30 are formed on the side of the bit line layer 20 away from the substrate 11. The first insulating structure 30 includes a second etch stop layer 33, a first support layer 32 and a first etch stop layer 31 stacked in sequence.

[0055] For details, please refer to Figure 9 A second etch stop material layer 36, a first support material layer 35, and a first etch stop material layer 34 are sequentially formed on the side of the bit line layer 20 away from the substrate 11. Both the first etch stop material layer 34 and the second etch stop material layer 36 are made of materials such as silicon nitride to ensure precise control of the stop position in subsequent etching processes. The first support material layer 35 is made of a low dielectric constant material such as silicon oxide to effectively reduce parasitic capacitance and crosstalk between subsequent word line conductive structures 50. The second etch stop material layer 36, the first support material layer 35, and the first etch stop material layer 34 can be formed using deposition processes. The deposition processes described herein can include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD) methods such as thermal oxidation, evaporation, and sputtering.

[0056] Please see Figure 10 The second etch stop material layer 36, the first support material layer 35, and the first etch stop material layer 34 are patterned to expose the bit line layer 20 and form the first insulating structure 30. The first insulating structure 30 includes a second etch stop layer 33, a first support layer 32, and a first etch stop layer 31 stacked sequentially. This first insulating structure 30 is a key isolation unit and support unit. The patterning process of the first insulating structure 30 can be completed by a combination of photolithography and dry etching. The structural outline is defined by a high-precision mask, and then anisotropic etching is used to ensure that the sidewalls are vertical.

[0057] S2. A channel structure 40 and a word line conductive structure 50 are formed on both sides of the first insulating structure 30 located in the first direction D1. The channel structure 40 is located between the first insulating structure 30 and the word line conductive structure 50. Please refer to [link / reference] for details. Figures 11 to 19 .

[0058] Please see Figure 11 A channel material layer 43 is formed on both sides of the first insulating structure 30 located in the first direction D1.

[0059] Please see Figure 11 Specifically, a channel material layer 43 is formed on the first insulating structure 30 and the bit line layer 20. The channel material layer 43 is made of a metal oxide, such as indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), or indium tin oxide (ITO), whose excellent carrier mobility and on / off ratio ensure the stable performance of the device under high-density integration. The formation process can be a deposition process.

[0060] Please see Figure 12 A first sacrificial pattern layer 44, comprising a plurality of first etched trenches 45, is formed on the channel material layer 43. The first etched trenches 45 extend in the first direction D1, and the plurality of first etched trenches 45 are spaced apart in a third direction D3, which is parallel to the plane containing the substrate 11. The first sacrificial pattern layer 44 may be made of photoresist, carbon-based hard mask, SOC, Poly, etc., and its patterning is achieved by photolithography and anisotropic etching. The first etched trenches 45 are used to etch the channel material layer 43 in subsequent processes.

[0061] Please see Figure 13 Using the first sacrificial pattern layer 44 as a hard mask and the first etch stop layer 31 as a protective layer, the channel material layer 43 is etched to form a plurality of spaced-apart channel precursor portions 46. The channel precursor portions 46 extend along the first direction D1 and are spaced-apart along the third direction D3. During the etching process, the first etch stop layer 31 effectively prevents the underlying first support layer 32 from being etched, ensuring the integrity and support performance of the first insulating structure 30.

[0062] Please see Figure 13 , Figure 14 Using the first sacrificial pattern layer 44 as a hard mask and the first etch stop layer 31 as a protective layer, the channel material layer 43 is etched to form a plurality of first partition grooves 41 and a plurality of channel precursor portions 46 spaced apart. The first partition grooves 41 extend along the first direction D1, and the plurality of first partition grooves 41 are spaced apart in the third direction D3, corresponding to the first etch grooves 45. The first partition grooves 41 divide the channel material layer 43 into a plurality of channel precursor portions 46, which extend continuously in the first direction D1 and are spaced apart in the third direction D3.

[0063] Please see Figure 14 Remove the first sacrificial pattern layer 44. Thoroughly remove residues using an ashing or wet stripping process to avoid introducing impurities and contamination.

[0064] Please see Figure 15 A gate insulating material layer 61 and a word line material layer 51 are sequentially formed above the substrate 11, the first insulating structure 30, and the channel front portion 46. The gate insulating material layer 61 and the word line material layer 51 can be formed using a deposition process. The gate insulating material layer 61 can be made of a high-dielectric-constant oxide, such as HfO. x Al2O3, SiOx, etc., the word line material layer 51 can be made of metal materials or conductive materials such as metal nitrides, such as titanium nitride, tungsten, molybdenum, rubidium, ruthenium, InOx, etc., in single or stacked layers.

[0065] Please see Figure 16 , Figure 17 The channel front portion 46, the word line material layer 51, and the gate insulating material layer 61 are etched to form a channel structure 40, a word line conductive structure 50, and a gate insulating layer 60. The gate insulating layer 60 is located between the word line conductive structure 50 and the channel structure 40, and the channel structure 40 is located between the first insulating structure 30 and the word line conductive structure 50.

[0066] Please see Figure 16 The word line material layer 51 is etched back to remove the word line material layer 51 on the first etch stop layer 31, the word line material layer 51 at the end of the channel front portion 46 away from the substrate 11, and a portion of the word line material layer 51 between two adjacent first insulating structures 30 and closer to the substrate 11, forming a plurality of word line conductive structures 50. The word line conductive structures 50 extend in the third direction D3, and the plurality of word line conductive structures 50 are spaced apart in the first direction D1. Two word line conductive structures 50 are disposed between two adjacent first insulating structures 30, and two word line conductive structures 50 are disposed on each side of the first insulating structure 30.

[0067] Please see Figure 16 The gate insulating material layer 61 is etched to remove the gate insulating material layer 61 on the first etch stop layer 31, the gate insulating material layer 61 on the end of the channel front portion 46 away from the substrate 11, and a portion of the gate insulating material layer 61 between two adjacent first insulating structures 30 and close to the substrate 11, forming a gate insulating layer 60. The gate insulating layer 60 is located between the word line conductive structure 50 and the channel front portion 46.

[0068] Please see Figure 17The channel front portion 46 is etched to form a second partition groove 42 on the side of the channel front portion 46 near the substrate 11. The second partition groove 42 extends along a third direction D3, dividing each channel front portion 46 into two independent channel structures 40 arranged along the first direction D1. A plurality of channel structures 40 are arranged in a spaced array along the first direction D1 and the third direction D3.

[0069] Please see Figure 18 , Figure 19 , Figure 1 A first dielectric layer 80 and a third insulating structure 70 are formed between two adjacent word line conductive structures 50 in the first direction D1, wherein the first dielectric layer 80 covers the third insulating structure 70.

[0070] Specifically, please refer to Figure 18 A first dielectric material layer 81 is formed between two adjacent word line conductive structures 50 in the first direction D1. The first dielectric material layer 81 covers the adjacent sides of the two adjacent word line conductive structures 50 and fills the second isolation groove 42 to form a first groove 82. The first dielectric material layer 81 can be deposited to fill the second isolation groove 42 and cover the side of the word line conductive structure 50 away from the corresponding first insulating structure 30. The first dielectric material layer 81 can be made of silicon oxide.

[0071] Please see Figure 19 A third insulating material layer 72 is filled into the first groove 82.

[0072] Please see Figure 19 A second dielectric material layer 83 is formed on the third insulating material layer 72 and the first dielectric material layer 81. The first dielectric layer 81 and the second dielectric layer 83 form a first dielectric layer 80, which encapsulates the third insulating material layer 72. The second dielectric layer 83 may be made of silicon oxide.

[0073] Please see Figure 4 The third insulating material layer 72 is removed to form an air gap 71 in the first dielectric layer 80, forming a third insulating structure 70. The first dielectric layer 80 covers the air gap 71 and the third insulating structure 70. If it is necessary to remove the third insulating material layer 72 to form the air gap 71 in the first dielectric layer 80, the third insulating material layer 72 can be made of an easily etchable sacrificial layer material such as spin-coated carbon (SOC), and the third insulating material layer 72 can be selectively removed by dry etching or ashing processes.

[0074] Please see Figure 1If it is not necessary to remove the third insulating material layer 72, the third insulating material layer 72 forms a third insulating structure 70, the first dielectric layer 80 wraps the third insulating material layer 72, and the first dielectric layer 80 covers the third insulating structure 70. The third insulating material layer 72 can be made of porous SiCOH, MSQ, SiLK and other low dielectric constant materials to reduce the parasitic capacitance and WL coupling effect between adjacent word line conductive structures 50 and improve device performance.

[0075] Please see Figure 5 A capacitor structure 90 is formed at the end of the channel structure 40 away from the substrate 11. The capacitor structure 90 is electrically connected to the channel structure 40 through a conductive connection layer.

[0076] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0077] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0078] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0079] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A semiconductor device (10), characterized in that, include: Base (11); A plurality of first insulating structures (30) are disposed on one side of the substrate (11), and the plurality of first insulating structures (30) are spaced apart in a first direction (D1); Multiple channel structures (40) are located on both sides of the first insulating structure (30) in the first direction (D1); Multiple word line conductive structures (50), wherein the channel structure (40) is located between the first insulating structure (30) and the word line conductive structures (50); The first insulating structure (30) includes a first etch stop layer (31) and a first support layer (32) stacked in a second direction (D2). The first etch stop layer (31) is located on the side of the first support layer (32) away from the substrate (11). The second direction (D2) is perpendicular to the plane where the substrate (11) is located, and the first direction (D1) is parallel to the plane where the substrate (11) is located.

2. The semiconductor device (10) according to claim 1, characterized in that, Also includes: Bitline layer (20) is disposed between the channel structure (40) and the substrate (11). The bitline layer (20) includes a plurality of bitline structures (21). The bitline structures (21) extend in the first direction (D1) and the plurality of bitline structures (21) are spaced apart in the third direction (D3). The first insulating structure (30) further includes a second etch stop layer (33) disposed between the first support layer (32) and the bit line layer (20), wherein the third direction (D3) is parallel to the plane where the substrate (11) is located.

3. The semiconductor device (10) according to claim 2, characterized in that, The semiconductor device (10) further includes a third insulating structure (70) and a first dielectric layer (80). Along the first direction (D1), the third insulating structure (70) is located between two adjacent word line conductive structures (50), the third insulating structure (70) extends in the third direction (D3), the first dielectric layer (80) covers the third insulating structure (70), and a portion of the first dielectric layer (80) is disposed between the third insulating structure (70) and the word line conductive structure (50). The dielectric constant of the third insulating structure (70) is less than that of the first dielectric layer (80).

4. The semiconductor device (10) according to claim 3, characterized in that, The third insulation structure (70) includes an air gap (71).

5. The semiconductor device (10) according to claim 3 or 4, characterized in that, The orthographic projection of the word line conductive structure (50) onto the third insulating structure (70) lies within the third insulating structure (70).

6. The semiconductor device (10) according to claim 1, characterized in that, The plurality of channel structures (40) of the semiconductor device (10) are arranged at intervals along the first direction (D1) and the third direction (D3), and the first insulating structure (30) extends along the third direction (D3).

7. The semiconductor device (10) according to claim 6, characterized in that, The semiconductor device (10) further includes a gate insulating layer (60) disposed between the word line conductive structure (50) and the corresponding channel structure (40). A first partition groove (41) is provided between two adjacent channel structures (40) arranged along the third direction (D3), and a portion of the word line conductive structure (50) and a portion of the gate insulating layer (60) are disposed within the first partition groove (41).

8. The semiconductor device (10) according to claim 6, characterized in that, A second partition groove (42) is provided between two adjacent channel structures (40) arranged along the first direction (D1), and a portion of the first medium layer (80) is disposed within the second partition groove (42).

9. The semiconductor device (10) according to claim 1, characterized in that, The dielectric constant of the first support layer (32) is less than that of the first etch stop layer (31), and the orthogonal projection of the word line conductive structure (50) on the first insulating structure (30) is located within the first support layer (32).

10. The semiconductor device (10) according to claim 2, characterized in that, The channel structure (40) includes a first channel portion (47) and a second channel portion (48) extending vertically from the first channel portion (47), the second channel portion (48) extending in the second direction (D2), and the first channel portion (47) extending away from the side corresponding to the first insulating structure (30).

11. The semiconductor device (10) according to claim 10, characterized in that, The side of the word line conductive structure (50) away from the corresponding second channel portion (48) is flush with the side of the corresponding first channel portion (47) away from the corresponding first insulating structure (30).

12. The semiconductor device (10) according to claim 10, characterized in that, Along the second direction, the top surface of the first channel portion (47) is higher than the top surface of the second etch stop layer (33).

13. A method for forming a semiconductor device (10), characterized in that, include: A plurality of first insulating structures (30) are formed on one side of the substrate (11) at intervals along a first direction (D1). Each first insulating structure (30) includes a first support layer (32) disposed along a second direction (D2) and a first etch stop layer (31) located on the side of the first support layer (32) away from the substrate (11). The second direction (D2) is perpendicular to the plane in which the substrate (11) is located, and the first direction (D1) is parallel to the plane in which the substrate (11) is located. A channel structure (40) and a word line conductive structure (50) are formed on both sides of the first insulating structure (30) in the first direction (D1), wherein the channel structure (40) is located between the first insulating structure (30) and the word line conductive structure (50).

14. The method for forming the semiconductor device (10) according to claim 13, characterized in that, The method of forming a plurality of first insulating structures (30) spaced apart along a first direction (D1) on one side of the substrate (11) includes: Provide a base (11); A bit line layer (20) is formed on one side of the substrate (11), the bit line layer (20) including a plurality of bit line structures (21) and a second insulating structure (22) arranged in a third direction (D3). A plurality of first insulating structures (30) are formed on the side of the bit line layer (20) away from the substrate (11). The first insulating structure (30) includes a second etch stop layer (33), a first support layer (32) and a first etch stop layer (31) stacked in sequence.

15. The method for forming the semiconductor device (10) according to claim 13, characterized in that, The method for forming the semiconductor device (10) further includes: A first dielectric layer (80) and a third insulating structure (70) are formed between two adjacent word line conductive structures (50) in the first direction (D1), wherein the first dielectric layer (80) covers the third insulating structure (70).

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