Semiconductor memory device

Abstract

Provided is a semiconductor storage device that can be appropriately manufactured. The semiconductor storage device includes: a first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; a first semiconductor member disposed between the first wiring and the second wiring, extending in a third direction intersecting the first and second directions, and electrically connected to the first wiring and the second wiring; a first counter electrode facing both surfaces in the first direction and both surfaces in the second direction of the first semiconductor member; a connection electrode extending in the third direction and connected to the first semiconductor member and the first wiring; a second semiconductor member extending in the third direction along both surfaces in the first direction and both surfaces in the second direction of the connection electrode, and connected to the first counter electrode and the first wiring; and a second counter electrode facing both surfaces in the first direction of the second semiconductor member.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Background Technology

[0002] With the increasing integration of semiconductor memory devices, research is underway related to the three-dimensionalization of semiconductor memory devices. Summary of the Invention

[0003] Provide semiconductor memory devices that can be properly manufactured.

[0004] One embodiment of a semiconductor memory device includes: a first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; a first semiconductor member disposed between the first wiring and the second wiring, extending in a third direction intersecting the first and second directions, and electrically connected to the first wiring and the second wiring; a first opposing electrode facing two surfaces of the first semiconductor member in the first direction and two surfaces in the second direction; a first connecting electrode extending in the third direction and connected to the first semiconductor member and the first wiring; a second semiconductor member extending in the third direction along two surfaces of the first connecting electrode in the first direction and two surfaces in the second direction, and connected to the first opposing electrode and the first wiring; and a second opposing electrode facing two surfaces of the second semiconductor member in the first direction. Attached Figure Description

[0005] Figure 1 This is a schematic circuit diagram illustrating the configuration of a portion of the semiconductor memory device according to the first embodiment.

[0006] Figure 2 This is a schematic circuit diagram used to explain the write operation of the semiconductor memory device according to the first embodiment.

[0007] Figure 3 This is a schematic circuit diagram used to explain the read operation of the semiconductor memory device according to the first embodiment.

[0008] Figure 4 This is a schematic perspective view showing the configuration of a portion of the semiconductor memory device according to the first embodiment.

[0009] Figure 5 This is a schematic perspective view showing the configuration of a portion of the semiconductor memory device according to the first embodiment.

[0010] Figure 6 This is a schematic perspective view showing the configuration of a portion of the semiconductor memory device according to the first embodiment.

[0011] Figure 7 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the first embodiment.

[0012] Figure 8 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the first embodiment.

[0013] Figure 9 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the first embodiment.

[0014] Figure 10 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the first embodiment.

[0015] Figure 11 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0016] Figure 12 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0017] Figure 13 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0018] Figure 14 This is a schematic perspective view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0019] Figure 15 This is a schematic perspective view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0020] Figure 16 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0021] Figure 17 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0022] Figure 18 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0023] Figure 19 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0024] Figure 20This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0025] Figure 21 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0026] Figure 22 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0027] Figure 23 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0028] Figure 24 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0029] Figure 25 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0030] Figure 26 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0031] Figure 27 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0032] Figure 28 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0033] Figure 29 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0034] Figure 30 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0035] Figure 31 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0036] Figure 32 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0037] Figure 33This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0038] Figure 34 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0039] Figure 35 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0040] Figure 36 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0041] Figure 37 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0042] Figure 38 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0043] Figure 39 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0044] Figure 40 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0045] Figure 41 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0046] Figure 42 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0047] Figure 43 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0048] Figure 44 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0049] Figure 45 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0050] Figure 46This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0051] Figure 47 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0052] Figure 48 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0053] Figure 49 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0054] Figure 50 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0055] Figure 51 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0056] Figure 52 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0057] Figure 53 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0058] Figure 54 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0059] Figure 55 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0060] Figure 56 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0061] Figure 57 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0062] Figure 58 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0063] Figure 59This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0064] Figure 60 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0065] Figure 61 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0066] Figure 62 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0067] Figure 63 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0068] Figure 64 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0069] Figure 65 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0070] Figure 66 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0071] Figure 67 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0072] Figure 68 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0073] Figure 69 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0074] Figure 70 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0075] Figure 71 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0076] Figure 72This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0077] Figure 73 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0078] Figure 74 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0079] Figure 75 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0080] Figure 76 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0081] Figure 77 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0082] Figure 78 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0083] Figure 79 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0084] Figure 80 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0085] Figure 81 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0086] Figure 82 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0087] Figure 83 This is a schematic circuit diagram illustrating a portion of the configuration of the semiconductor memory device according to the second embodiment.

[0088] Figure 84 This is a schematic circuit diagram used to explain the read operation of the semiconductor memory device according to the second embodiment.

[0089] Figure 85This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the second embodiment.

[0090] Figure 86 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the second embodiment.

[0091] Figure 87 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0092] Figure 88 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0093] Figure 89 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0094] Figure 90 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0095] Figure 91 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0096] Figure 92 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0097] Figure 93 This is a schematic circuit diagram illustrating a portion of the configuration of the semiconductor memory device according to the second embodiment.

[0098] Figure 94 This is a schematic circuit diagram used to explain the read operation of the semiconductor memory device according to the second embodiment.

[0099] Figure 95 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0100] Figure 96 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0101] Figure 97 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0102] Figure 98This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0103] Figure 99 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0104] Figure 100 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0105] Figure 101 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0106] Figure 102 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0107] Figure 103 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0108] Figure 104 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0109] Figure 105 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0110] Figure 106 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0111] Figure 107 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0112] Figure 108 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0113] Figure 109 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0114] Figure 110 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0115] Figure 111This is a schematic cross-sectional view showing a portion of the configuration of a modified example of the semiconductor memory device according to the second embodiment.

[0116] Figure 112 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the third embodiment.

[0117] Figure 113 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the third embodiment.

[0118] Figure 114 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0119] Figure 115 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0120] Figure 116 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0121] Figure 117 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0122] Figure 118 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0123] Figure 119 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0124] Figure 120 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0125] Figure 121 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0126] Figure 122 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0127] Figure 123 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0128] Figure 124This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0129] Figure 125 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0130] Figure 126 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0131] Figure 127 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0132] Figure 128 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0133] Figure 129 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0134] Figure 130 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0135] Figure 131 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0136] Figure 132 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0137] Figure 133 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0138] Figure 134 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0139] Figure 135 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0140] Figure 136 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0141] Figure 137This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0142] Figure 138 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0143] Figure 139 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0144] Figure 140 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0145] Figure 141 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0146] Figure 142 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0147] Figure 143 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0148] Figure 144 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0149] Figure 145 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0150] Figure 146 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0151] Figure 147 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0152] Figure 148 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0153] Figure 149 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0154] Figure 150This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0155] Figure 151 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0156] Figure 152 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0157] Figure 153 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0158] Figure 154 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0159] Figure 155 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0160] Figure 156 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0161] Figure 157 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0162] Figure 158 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0163] Figure 159 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0164] Figure 160 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0165] Figure 161 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0166] Figure 162 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0167] Figure 163This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0168] Figure 164 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0169] Figure 165 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0170] Figure 166 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0171] Figure 167 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0172] Figure 168 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0173] Figure 169 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0174] Figure 170 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0175] Figure 171 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0176] Figure 172 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0177] Figure 173 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0178] Figure 174 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0179] Figure 175 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0180] Figure 176This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0181] Figure 177 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the fourth embodiment.

[0182] Figure 178 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the fourth embodiment.

[0183] Figure 179 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the fourth embodiment.

[0184] Label Explanation

[0185] Sub... Semiconductor substrate, ML... Memory layer, BL... Bit line, WWL... Write word line, WTr... Write transistor, RWL... Read word line, RTR... Write transistor, SN... Sensing node, 110, 120... Wiring, 130, 140... Transistor structure, 131, 143... Semiconductor component, 132, 144... Insulating layer, 133, 145... Opposing electrode, 141, 151... Connecting electrode. Detailed Implementation

[0186] Next, with reference to the accompanying drawings, the semiconductor memory device according to the embodiments will be described in detail. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Also, sometimes the same reference numerals are used to denote common parts in multiple embodiments, and descriptions are omitted.

[0187] Furthermore, in this specification, the term "semiconductor memory device" sometimes means a memory die, and sometimes it means a memory chip, memory card, SSD (Solid State Drive), or other storage system including a controller die. Moreover, it sometimes refers to a device including a mainframe computer such as a smartphone, tablet, or personal computer.

[0188] Furthermore, in this specification, when the first component and the second component are described as "electrically connected," the first component and the second component may be directly connected, or the first component may be connected to the second component via wiring, a semiconductor component, or a transistor. For example, when three transistors are connected in series, even if the second transistor is in the off state, the first transistor is "electrically connected" to the third transistor.

[0189] Additionally, in this specification, when it is stated that the first component is "electrically connected" to the second and third components, it sometimes means that the first component, the second component, and the third component are connected in series and the second component is electrically connected to the first component and the third component via the first component.

[0190] Furthermore, in this specification, when it is stated that a circuit or the like "conducts" two wires or the like, it sometimes means, for example, that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wires, and that the transistor or the like is in a conducting (ON) state.

[0191] In addition, in this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0192] In addition, in this specification, the direction along the predetermined surface is sometimes referred to as the first direction, the direction along the predetermined surface that intersects the first direction is referred to as the second direction, and the direction that intersects the predetermined surface is referred to as the third direction. These first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond.

[0193] Furthermore, in this specification, the terms "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Additionally, when a configuration is described as "lower surface" or "lower end," it refers to the surface or end point on the substrate side of that configuration; when described as "upper surface" or "upper end," it refers to the surface or end point on the side of that configuration opposite to the substrate. Furthermore, a surface intersecting the X or Y direction is called a side surface, etc.

[0194] Furthermore, in this specification, when referring to the "center position" of a certain configuration, it may mean, for example, the position of the center of the circumcircle of the configuration, or it may mean the center of gravity of the configuration in an image.

[0195] In addition, in this specification, when referring to the material of each component, the elements contained in the material are listed in parentheses, but the composition ratio of the elements is not listed.

[0196] [First Implementation]

[0197] [Circuit Structure]

[0198] Figure 1 This is a schematic circuit diagram illustrating the configuration of a portion of the semiconductor memory device according to the first embodiment. Figure 1 As shown, the semiconductor memory device according to this embodiment includes a memory cell array (MCA). The memory cell array (MCA) includes multiple memory layers (ML) and multiple bit lines (BL) connected to these multiple memory layers (ML).

[0199] Each memory layer ML has a write word line WWL, a read word line RWL, and multiple memory cells MC connected to these write word lines WWL and read word lines RWL. Each memory cell MC has a write transistor WTR, a memory node SN, and a read transistor RTR.

[0200] The write transistor WTr is, for example, a field-effect NMOS transistor. One electrode of the write transistor WTr is connected to the bit line BL. The other electrode of the write transistor WTr is connected to the memory node SN. Both electrodes of the write transistor WTr function as source or drain electrodes depending on the voltage supplied to the write transistor WTr. The gate electrode of the write transistor WTr is connected to the write word line WWL.

[0201] The sense transistor RTr is, for example, a field-effect NMOS transistor. One electrode of the sense transistor RTr is connected to the bit line BL. The other electrode of the sense transistor RTr is connected to the sense word line RWL. One and the other electrodes of the sense transistor RTr function as source or drain electrodes depending on the voltage supplied to the sense transistor RTr. The gate electrode of the sense transistor RTr is connected to the memory node SN.

[0202] Figure 2 This is a schematic circuit diagram used to explain the write operation of the semiconductor memory device according to the first embodiment.

[0203] During a write operation, for example, a voltage equal to the sum of the power supply voltage Vdd and the threshold voltage Vth of the write transistor WTr is supplied to the write word line among the multiple write word lines WWL that is the target of the write operation, and a ground voltage Vss is supplied to the other write word lines. In addition, depending on the data to be written, either the power supply voltage Vdd or the ground voltage Vss is supplied to the bit line among the multiple bit lines BL that is the target of the write operation.

[0204] Therefore, depending on the voltage of the bit line BL, the state of the memory node SN becomes either "H (high level)" or "L (low level)". The read transistor RTr connected to the memory node SN in the "H" state becomes ON, and the read transistor RTr connected to the memory node SN in the "L" state becomes OFF.

[0205] In addition, during a write operation, all bit lines BL within the memory cell array MCA can be used as the object of the write operation, or a portion (e.g., one) of the bit lines BL can be used as the object of the write operation.

[0206] Figure 3 This is a schematic circuit diagram used to explain the read operation of the semiconductor memory device according to the first embodiment.

[0207] During a read operation, for example, a power supply voltage Vdd is supplied to the read word line that is the target of the read operation among multiple read word lines RWL, and a ground voltage Vss is supplied to the other read word lines. As a result, depending on the state of the memory node SN, current flows through the bit line BL, or the bit line BL is charged. By reading this situation through a sense amplifier circuit, the data recorded by the memory cell MC can be obtained.

[0208] In addition, during a read operation, all bit lines BL within the memory cell array MCA can be used as the object of the read operation, or a portion (e.g., one) of the bit lines BL can be used as the object of the read operation.

[0209] [structure]

[0210] Figures 4-6 This is a schematic perspective view showing the configuration of a portion of the semiconductor memory device according to the first embodiment. Figure 5 In the middle, the following was omitted. Figure 4 Part of the structure shown. Figure 6 In the middle, the following was omitted. Figure 5 Part of the structure shown. Figures 7-10 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device. Figure 7 and Figure 4 The XY cross-section shown corresponds to this. Figure 8 and Figure 4 The YZ section shown corresponds to this. Figure 9 and Figure 5 The XZ section shown corresponds to this. Figure 10 and Figure 6 The XZ section shown corresponds to this.

[0211] exist Figure 4 The image shows a portion of a semiconductor substrate Sub and a memory cell array MCA disposed above the semiconductor substrate Sub.

[0212] The semiconductor substrate Sub is, for example, a silicon (Si) semiconductor substrate containing p-type impurities such as boron (B). An insulating layer (not shown) and an electrode layer are provided on the upper surface of the semiconductor substrate Sub. The upper surface of the semiconductor substrate Sub, the insulating layer (not shown), and the electrode layer constitute a control circuit for controlling the semiconductor memory device. For example, a sense amplifier circuit is provided in the region directly below the memory cell array MCA. The sense amplifier circuit is electrically connected to the bit line BL. By detecting changes in voltage or current on the bit line BL during readout operations, the sense amplifier circuit can read out the data stored in the selected memory cell MC.

[0213] The memory cell array MCA has bit line regions R arranged sequentially in the Y direction. BL Write transistor region R WTr Readout transistor region R RTr Connecting electrode region R CN and the readout word line area R RWL In addition, the memory cell array (MCA) has multiple memory layers (MLs) arranged in the Z direction.

[0214] Bit line region R BL It comprises a plurality of wirings 110 extending in the Z direction and arranged in the X direction, and an insulating layer 111 disposed between them. Each of the plurality of wirings 110 functions as a bit line BL. The plurality of wirings 110 include, for example, a barrier conductive film such as titanium nitride (TiN) and a conductive member such as tungsten (W). The insulating layer 111 comprises, for example, silicon oxide (SiO). Additionally, as... Figure 7 as well as Figure 8 As shown, on one side of the wiring 110 in the Y direction (with the read word line area R) RWL On the opposite side, an insulating layer 101 of silicon oxide (SiO) or the like is provided.

[0215] Read out word line area R RWL The device includes a plurality of wirings 120 extending in the X direction and arranged in the Z direction corresponding to a plurality of storage layers ML, and an insulating layer 121 disposed between them. The plurality of wirings 120 function, for example, as read word lines (RWL). The plurality of wirings 120 include, for example, a barrier conductive film such as titanium nitride (TiN) and a conductive member such as tungsten (W). The insulating layer 121 includes, for example, silicon oxide (SiO). Additionally, as... Figure 7 as well as Figure 8 As shown, on one side of the wiring 120 in the Y direction (with the bit line region R) BL On the opposite side, an insulating layer 102 of silicon oxide (SiO) or the like is provided.

[0216] Readout transistor region R RTr For example, like Figure 5 as well as Figure 9 As shown, it includes multiple transistor structures 130 arranged in the X direction corresponding to multiple wirings 110 and in the Z direction corresponding to multiple storage layers ML, as well as multiple insulating layers 134. Figure 9 Additionally, an insulating layer 135, such as silicon oxynitride (SiON), is provided in the area between them.

[0217] Each of the multiple transistor structures 130 has a semiconductor component 131 extending in the Y direction, an insulating layer 132 disposed on the upper and lower surfaces and two sides in the X direction of the semiconductor component 131, and opposing electrodes 133 disposed on the upper and lower surfaces and two sides in the X direction of the insulating layer 132.

[0218] Semiconductor component 131 functions as the channel region of the readout transistor RTR. Semiconductor component 131 may contain, for example, monocrystalline silicon (Si).

[0219] The insulating layer 132 functions, for example, as the gate insulating film of the readout transistor RTr. The insulating layer 132 comprises, for example, silicon oxide (SiO). The insulating layer 132 extends in the Y direction along the upper and lower surfaces of the semiconductor member 131 and both sides in the X direction.

[0220] The opposing electrode 133 functions, for example, as the gate electrode of the readout transistor RTR and the storage node SN. The opposing electrode 133 may contain, for example, titanium nitride (TiN). The opposing electrode 133 extends in the Y direction along the upper and lower surfaces and two sides in the X direction of the insulating layer 132. The opposing electrode 133 faces the upper and lower surfaces and two sides in the X direction of the semiconductor component 131 across the insulating layer 132.

[0221] Multiple insulating layers 134 are each disposed on the upper and lower surfaces and the two sides in the X direction of the multiple transistor structures 130. The insulating layers 134 include, for example, silicon oxide (SiO). The insulating layers 134 extend in the Y direction along the upper and lower surfaces and the two sides in the X direction of the transistor structures 130.

[0222] Write transistor region R WTr For example, like Figure 6 As shown, it includes multiple connection electrodes 141, multiple insulating layers 142, and multiple transistor structures 140 arranged in the X direction corresponding to multiple wirings 110 and in the Z direction corresponding to multiple storage layers ML.

[0223] The connecting electrode 141 is connected to the wiring 110 and the semiconductor component 131, enabling them to conduct electricity. The connecting electrode 141 may contain, for example, single-crystal silicon (Si) containing N-type impurities such as phosphorus (P).

[0224] Multiple insulating layers 142 are each disposed on the upper and lower surfaces and on both sides in the X direction of the multiple connecting electrodes 141. The insulating layers 142 are disposed between the connecting electrodes 141 and the semiconductor component 143, providing electrical insulation between them. The insulating layers 142 may contain, for example, silicon oxide (SiO). The insulating layers 142 extend in the Y direction along the upper and lower surfaces and both sides in the X direction of the connecting electrodes 141. The insulating layers 142 are continuous with the insulating layer 132.

[0225] Each of the multiple transistor structures 140 has a semiconductor component 143 disposed on the upper and lower surfaces and two sides in the X direction of the insulating layer 142, an insulating layer 144 disposed on the upper and lower surfaces and two sides in the X direction of the semiconductor component 143, and opposing electrodes 145 disposed on the upper and lower surfaces and two sides in the X direction of the insulating layer 144.

[0226] Semiconductor component 143 functions as the channel region of the write transistor WTr. Semiconductor component 143 extends in the Y direction along the upper and lower surfaces of insulating layer 142 and both sides in the X direction. Semiconductor component 143 is connected to wiring 110 and opposing electrode 133.

[0227] Semiconductor component 143 may also include an oxide semiconductor, for example. As an oxide semiconductor, a semiconductor material comprising at least one element selected from indium (In), gallium (Ga), zinc (Zn), aluminum (Al), tin (Sn), and titanium (Ti) and oxygen (O) can be used. For example, it may comprise at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors.

[0228] Specific examples of oxide semiconductors include zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), indium gallium silicon oxide (InGaSiO), indium gallium oxide (IGO), and indium tungsten oxide (IWO). Oxide semiconductors can be amorphous or crystalline.

[0229] The insulating layer 144 functions, for example, as a gate insulating film for a write transistor WTr. The insulating layer 144 comprises, for example, silicon oxide (SiO). The insulating layer 144 extends along the upper and lower surfaces of the semiconductor member 143 and along both sides in the X direction in the Y direction. The insulating layer 144 is continuous with the insulating layer 134.

[0230] The opposing electrode 145 functions, for example, as the gate electrode of the write transistor WTr. The opposing electrode 145 comprises, for example, titanium nitride (TiN). The opposing electrode 145 extends in the Y direction along the upper and lower surfaces and two sides in the X direction of the insulating layer 144. The opposing electrode 145 is opposed to the upper and lower surfaces and two sides in the X direction of the semiconductor component 143 across the insulating layer 144.

[0231] Furthermore, the multiple opposing electrodes 145 arranged in the X direction are continuous with each other, forming a wiring extending in the X direction. In other words, the opposing electrodes 145 are part of the wiring extending in the X direction. This wiring functions as a write word line (WWL).

[0232] In addition, such as Figure 7 as well as Figure 8 As shown, an insulating layer 146, such as silicon nitride (SiN), is provided between the opposing electrode 145 and the insulating layer 135, and an insulating layer 147, such as silicon nitride (SiN), is provided between the opposing electrode 145 and the wiring 110. Furthermore, an insulating layer 148, such as silicon oxide (SiO), is provided between two adjacent opposing electrodes 145 in the Z direction.

[0233] Connecting electrode region R CN The device includes multiple connection electrodes 151 arranged in the X direction corresponding to multiple wirings 110 and in the Z direction corresponding to multiple storage layers ML. The connection electrodes 151 are connected to wirings 120 and semiconductor components 131, enabling them to conduct electricity. The connection electrodes 151 may contain, for example, single-crystal silicon (Si) containing N-type impurities such as phosphorus (P). Furthermore, an insulating layer 152, such as silicon nitride (SiN), is provided in the region between them.

[0234] [Manufacturing Method]

[0235] Figures 11-13 as well as Figures 16-82 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 12 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 32 , Figure 34 , Figure 36 , Figure 38 , Figure 41 , Figure 43 , Figure 47 , Figure 49 , Figure 51 , Figure 53 , Figure 55 , Figure 57 , Figure 61 , Figure 63 , Figure 65 , Figure 67 , Figure 69 , Figure 71 , Figure 73 , Figure 75 , Figure 77 , Figure 79 ,as well as Figure 81 Showing with Figure 7 Corresponding cross-sections. Figure 11 , Figure 13 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 33 , Figure 35 , Figure 37 , Figure 39 , Figure 40 , Figure 42 , Figure 44 , Figure 45 , Figure 46 , Figure 48 , Figure 50 , Figure 52 , Figure 54 , Figure 56 , Figure 58 , Figure 62 , Figure 64 , Figure 66 , Figure 68 , Figure 70 , Figure 72 , Figure 74 , Figure 76 , Figure 78 , Figure 80 ,as well as Figure 82 Showing with Figure 8 Corresponding cross-sections. Figure 59 as well as Figure 60 Showing with Figure 10 Corresponding cross-sections. Figure 14 as well as Figure 15 This is a schematic perspective view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0236] In this manufacturing method, for example, like Figure 11 As shown, multiple semiconductor layers MLA and multiple sacrificial layers MLI are alternately formed. The semiconductor layer MLA, for example, comprises single-crystal silicon (Si). The sacrificial layer MLI, for example, comprises single-crystal silicon germanium (SiGe). This process is performed, for example, by epitaxial growth.

[0237] Next, for example, like Figure 12 As shown, in conjunction with multiple insulating layers 111 ( Figure 7 Correspondingly, multiple locations in the Y direction form a groove 111A, which extends in the Z direction and covers the bit line region R through multiple semiconductor layers MLA and multiple sacrificial layers MLI. BL Write transistor region R WTr Readout transistor region R RTr and the connecting electrode region R CN The ground extends in the Y direction. This process is performed, for example, by RIE (Reactive Ion Etching).

[0238] Next, although the illustration is omitted, a sacrificial layer is formed inside the multiple tanks 111A. This process is performed, for example, by CVD (Chemical Vapor Deposition).

[0239] Next, as Figure 13 As shown, in relation to insulating layer 101 ( Figure 7 as well as Figure 8 A groove 101A is formed at a position corresponding to the Y direction. The groove 101A extends in the Z direction and the X direction through multiple semiconductor layers MLA and multiple sacrificial layers MLI. This process is performed, for example, by RIE.

[0240] Additionally, multiple sacrificial layers MLI are disposed in the bit line region R via slot 101A. BL Write transistor region R WTr Readout transistor region R RTr and the connecting electrode region R CN Partial removal. This process is performed, for example, by wet etching.

[0241] Next, the multiple slots 111A ( Figure 12 The sacrificial layer (not shown) inside the part is removed. This process is performed, for example, by wet etching.

[0242] Therefore, as Figure 14 As shown, transistors are formed in the X and Z directions and spread throughout the write transistor region R. WTr Readout transistor region RRTr and the connecting electrode region R CN Multiple semiconductor sections 131A extending in the Y direction.

[0243] Next, as Figures 15-17 As shown, the widths of multiple semiconductor sections 131A in the X and Z directions are reduced. This process is performed, for example, by wet etching.

[0244] Next, as Figure 18 as well as Figure 19 As shown, a portion of an insulating layer 152 is formed on the upper and lower surfaces of the plurality of semiconductor portions 131A, on both sides in the X direction and one side (the trench 101A side) in the Y direction, and on the side in the Y direction of the semiconductor layer MLA and the sacrificial layer MLI. This process is performed, for example, by CVD. Furthermore, in this process, the space between two adjacent semiconductor portions 131A in the X direction and the space between two adjacent semiconductor portions 131A in the Z direction are not filled.

[0245] Next, as Figure 20 as well as Figure 21 As shown, in the write transistor region R WTr Readout transistor region R RTr and the connecting electrode region R CN The remaining space is used to form an insulating layer 135. This process is performed, for example, by CVD. Furthermore, in this process, the space between two adjacent semiconductor sections 131A in the X direction and the space between two adjacent semiconductor sections 131A in the Z direction are filled.

[0246] Next, as Figure 22 as well as Figure 23 As shown, the insulating layer 152 is disposed in the write transistor region R. WTr and the readout transistor region R RTr Partial removal. This process is performed, for example, by wet etching. Through this process, the transistor region R is written... WTr and the readout transistor region R RTr An opening 133A is formed. The opening 133A is arranged in the Z and X directions corresponding to a plurality of semiconductor portions 131A and is separated by an insulating layer 135.

[0247] Next, as Figure 24 as well as Figure 25As shown, an insulating layer is formed on the upper and lower surfaces of the semiconductor portion 131A, the ends of both sides in the X direction and one side (the trench 101A side) in the Y direction, the upper and lower surfaces of the insulating layer 135, the two sides in the X direction and the side of the trench 101A side in the Y direction, and the exposed surface of the insulating layer 152 that exposes to the opening 133A. The readout transistor region R is formed in the portions of this insulating layer formed on the upper and lower surfaces of the semiconductor portion 131A and the two sides in the X direction. RTr The middle part is the insulating layer 132, and the written transistor region R WTr The portion in question is the insulating layer 142. Additionally, the readout transistor region R is located in portions of this insulating layer formed on the upper and lower surfaces and on both sides in the X direction. RTr The middle part is the insulating layer 134, and the written transistor region R WTr The portion in the middle is the insulating layer 144. Additionally, a conductive layer 133B is formed inside the opening 133A. The opening 133A is filled with the conductive layer 133B. This process is performed, for example, by CVD.

[0248] Next, as Figure 26 as well as Figure 27 As shown, the portion of the insulating layer 144 and the conductive layer 133B located on the side of the groove 101A in the Y direction of the insulating layer 135 is removed. Additionally, the portion of the conductive layer 133B located in the write transistor region R... WTr Part of the material is removed. Through this process, multiple opposing electrodes 133 are formed. This process is performed, for example, by wet etching.

[0249] Next, as Figure 28 as well as Figure 29 As shown, a sacrificial layer 143B, such as silicon nitride, is formed inside the opening 133A and on the inner wall surface of the trench 101A. The opening 133A is filled with the sacrificial layer 143B. The trench 101A is not filled with the sacrificial layer 143B. This process is performed, for example, by CVD.

[0250] Next, as Figure 30 as well as Figure 31 As shown, the portion of the sacrificial layer 143B that is disposed on the inner wall surface of the groove 101A is removed. This process is performed, for example, by wet etching.

[0251] Next, as Figure 32 as well as Figure 33 As shown, a portion of the insulating layers 142 and 144 is removed, exposing one end of the semiconductor section 131A in the Y direction (the trench 101A side). This process is performed, for example, by wet etching.

[0252] Next, as Figure 34 as well as Figure 35 As shown, a connection electrode 141 is formed. In this process, an N-type impurity such as phosphorus (P) is implanted into the semiconductor section 131A from one end in the Y direction (the side of trench 101A). The region of the semiconductor section 131A after the impurity has diffused becomes the connection electrode 141. This process is performed, for example, by gas phase doping (GPD).

[0253] Next, as Figure 36 as well as Figure 37 As shown, a sacrificial layer 101B containing carbon (C) or the like is formed inside the tank 101A. This process is performed, for example, by CVD.

[0254] Next, as Figure 38 as well as Figure 39 As shown, in relation to insulating layer 102 ( Figure 7 as well as Figure 8 A trench 102A is formed at the corresponding position. The trench 102A extends in the Z direction and the X direction, penetrating multiple semiconductor layers MLA and multiple sacrificial layers MLI. This process is performed, for example, by RIE.

[0255] Next, as Figure 40 As shown, multiple sacrificial layers (MLI) are removed. This process is performed, for example, by wet etching.

[0256] Next, as Figure 41 as well as Figure 42 As shown, the R region of the read word line is located in multiple semiconductor layers MLA. RWL The width of the portion in the Z direction. This process is performed, for example, by wet etching.

[0257] Next, as Figure 43 as well as Figure 44 As shown, another portion of the insulating layer 152 is formed on one side (the trench 102A side) of the insulating layer 152 in the Y direction, and on the upper and lower surfaces of the semiconductor layer MLA and at one end (the trench 102A side) in the Y direction. This process is performed, for example, by CVD. In this process, the space between two adjacent semiconductor layers MLA in the Z direction is not filled by the insulating layer 152. Therefore, in relation to the plurality of insulating layers 121 ( Figure 8 Multiple openings 121A are formed at the corresponding positions.

[0258] Next, as Figure 45 As shown, multiple insulating layers 121 are formed inside the multiple openings 121A. This process is performed, for example, by CVD and wet etching.

[0259] Next, as Figure 46As shown, a portion of the insulating layer 152 is removed, exposing the end of one side (the trench 102A side) of the plurality of semiconductor layers MLA in the Y direction. This process is performed, for example, by wet etching.

[0260] Next, as Figure 47 as well as Figure 48 As shown, a connection electrode 151 is formed. In this process, an N-type impurity such as phosphorus (P) is implanted into the semiconductor layer MLA from one end in the Y direction (the trench 102A side). The region of the semiconductor layer MLA after impurity diffusion becomes the connection electrode 151. Furthermore, the region of the semiconductor layer MLA between the connection electrode 141 and the connection electrode 151 becomes the semiconductor component 131. This process is performed, for example, by a GPD (Gas Processing Device).

[0261] Next, as Figure 49 as well as Figure 50 As shown, a sacrificial layer 102B containing carbon (C) or the like is formed inside the tank 102A. This process is performed, for example, by CVD or the like.

[0262] Next, as Figure 51 as well as Figure 52 As shown, the sacrificial layer 101B is removed. This process is performed, for example, by wet etching.

[0263] Next, as Figure 53 as well as Figure 54 As shown, the sacrificial layer 143B is removed to form a semiconductor component 143. This process is performed, for example, by wet etching and ALD (Atomic Layer Deposition).

[0264] Next, as Figure 55 as well as Figure 56 As shown, a portion of the insulating layer 135 is removed, and an opening 145A is formed at a position corresponding to the opposing electrode 145 and the insulating layers 146 and 147. This process is performed, for example, by wet etching.

[0265] Next, as Figure 57 as well as Figure 58 As shown, an insulating layer 146 is formed on the upper and lower surfaces of the insulating layer 144, the two sides in the X direction, the exposed surface of the insulating layer 135 that exposes to the opening 145A, and the inner wall surface of the groove 101A. This process is performed, for example, by CVD.

[0266] Here, in the execution reference Figure 57 as well as Figure 58 Before the explained procedures, such as Figure 59 As shown, the distance between two adjacent insulating layers 144 in the X direction is smaller than the distance between two adjacent insulating layers 144 in the Z direction. Additionally, in reference... Figure 57 as well as Figure 58 In the explained process, as follows Figure 60 As shown, the region between two adjacent insulating layers 144 in the X direction is filled by insulating layer 146, while the region between two adjacent insulating layers 144 in the Z direction is not filled by insulating layer 146.

[0267] Next, as Figure 61 as well as Figure 62 As shown, an insulating layer 148 is formed inside the opening 145A and on the inner wall surface of the groove 101A. This process is performed, for example, by CVD.

[0268] Next, as Figure 63 as well as Figure 64 As shown, a portion of the insulating layer 148 is removed. In this process, the portion of the insulating layer 148 formed inside the opening 145A is left, while the rest is removed. This process is performed, for example, by wet etching.

[0269] Next, as Figure 65 as well as Figure 66 As shown, a portion of the insulating layer 146 is removed. This process is performed, for example, by wet etching.

[0270] Next, as Figure 67 as well as Figure 68 As shown, a conductive layer 145B is formed inside the opening 145A and on the inner wall surface of the groove 101A. This process is performed, for example, by CVD.

[0271] Next, as Figure 69 as well as Figure 70 As shown, a portion of the conductive layer 145B is removed. In this process, the portion of the conductive layer 145B corresponding to the insulating layer 147 and the portion formed on the inner wall surface of the trench 101A are removed. Through this process, opposing electrodes 145 are formed. This process is performed, for example, by wet etching.

[0272] Next, as Figure 71 as well as Figure 72 As shown, an insulating layer 147 is formed inside the opening 145A and on the inner wall surface of the groove 101A. This process is performed, for example, by CVD.

[0273] Next, as Figure 73 as well as Figure 74 As shown, the portion of the insulating layer 147 formed on the inner wall surface of the groove 101A is removed. This process is performed, for example, by wet etching.

[0274] Next, as Figure 75 as well as Figure 76As shown, the sacrificial layer 102B is removed. This process is performed, for example, by wet etching.

[0275] Next, as Figure 77 as well as Figure 78 As shown, conductive layers 110A and 120A are formed inside the grooves 101A and 102A. This process is performed, for example, by CVD.

[0276] Next, as Figure 79 as well as Figure 80 As shown, a portion of the conductive layers 110A and 120A is removed. In this process, inside the trench 102A, the end of one side (the trench 102A side) of the plurality of insulating layers 121 in the Y direction is exposed. As a result, the conductive layer 120A is truncated in the Z direction, becoming a plurality of wirings 120 arranged in the Z direction. This process is performed, for example, by wet etching.

[0277] Next, as Figure 81 as well as Figure 82 As shown, insulating layers 101 and 102 are formed inside the grooves 101A and 102A. This process is performed, for example, by CVD.

[0278] Then, the conductive layer 110A is cut in the X direction using methods such as RIE, thereby forming wiring 110. Additionally, an insulating layer 111 is formed between two adjacent wirings 110 in the X direction to create a reference. Figures 4 to 10 Explained semiconductor memory devices.

[0279] [Effect]

[0280] In this embodiment, a semiconductor component 131 comprising monocrystalline silicon (Si) is used as the channel region of the read transistor RTR. Furthermore, a semiconductor component 143 comprising oxide semiconductor is used as the channel region of the write transistor WTR. With this configuration, the current of the read transistor RTR during readout operations can be increased, thus enabling faster and more stable readout operations. Additionally, leakage current through the write transistor WTR can be suppressed. Therefore, the number of refresh operations can be reduced.

[0281] Furthermore, in this embodiment, in order to achieve such a structure, referring to Figure 11 In the described process, multiple semiconductor layers MLA comprising monocrystalline silicon (Si) and multiple sacrificial layers MLI are alternately formed. Furthermore, the monocrystalline silicon contained in the semiconductor layer MLA is used as the channel region for the readout transistor RTR. According to this method, monocrystalline silicon (Si) can be used as the channel region for multiple readout transistors arranged in the Z direction.

[0282] [Second Implementation]

[0283] [Circuit Structure]

[0284] Figure 83 This is a schematic circuit diagram illustrating a portion of the configuration of the semiconductor memory device according to the second embodiment. In the following description, the same reference numerals are used for the same parts as in the second embodiment, and the description is omitted.

[0285] like Figure 83 As shown, the semiconductor memory device according to the second embodiment includes a memory cell array MCA2. The memory cell array MCA2 includes multiple memory layers ML2 and multiple bit lines BL and source lines SL connected to these multiple memory layers ML2.

[0286] Each memory layer ML2 has a write word line WWL, a read word line RWL, and multiple memory cells MC2 connected to these write word lines WWL and read word lines RWL. Each memory cell MC2 has a write transistor WTr, a memory node SN, a read transistor RTr, and a select transistor STr.

[0287] Storage cell MC2 is basically constructed in the same way as storage cell MC.

[0288] However, in the memory cell MC2, the electrode on the other side of the read transistor RTR is not connected to the read word line RWL, but is connected to the electrode on the other side of the select transistor STr.

[0289] The selector transistor STr is, for example, a field-effect NMOS transistor. One electrode of the selector transistor STr is connected to the source line SL. Both electrodes of the selector transistor STr function as source or drain electrodes depending on the voltage supplied to the selector transistor STr. The gate electrode of the selector transistor STr is connected to the read word line RWL.

[0290] The write operation of the semiconductor memory device according to the second embodiment is performed in the same way as the write operation of the semiconductor memory device according to the first embodiment.

[0291] Figure 84 This is a schematic circuit diagram used to explain the read operation of the semiconductor memory device according to the second embodiment.

[0292] During a read operation, for example, a power supply voltage Vdd is supplied to the read word line that is the target of the read operation among multiple read word lines RWL, and a ground voltage Vss is supplied to the other read word lines. Additionally, a ground voltage Vss is supplied to the source line SL. Thus, depending on the state of the memory node SN, current flows through the bit line BL, or the bit line BL is charged. By reading this situation through the sense amplifier circuit, the data recorded in the memory cell MC2 can be obtained.

[0293] In addition, during a read operation, all bit lines BL within the memory cell array MCA2 can be used as the object of the read operation, or a portion (e.g., one) of the bit lines BL can be used as the object of the read operation.

[0294] In the semiconductor memory device according to the first embodiment, all the read transistors RTr connected to the memory node SN in the "H" state may be in the ON state. Therefore, during the read operation, leakage current may flow from the bit line BL to the non-selected read word line RWL through the non-selected memory cell MC, including the memory node SN in the "H" state.

[0295] On the other hand, in the semiconductor memory device according to the second embodiment, regardless of the state of the memory node SN, the selection transistor STr connected to the non-selected read word line RWL can be made to be in an "OFF" state. This significantly suppresses leakage current.

[0296] [structure]

[0297] Figure 85 as well as Figure 86 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the second embodiment.

[0298] Although the illustrations are omitted, the semiconductor memory device according to the second embodiment has the same semiconductor substrate Sub as the semiconductor memory device according to the first embodiment.

[0299] Furthermore, the semiconductor memory device according to the second embodiment includes a memory cell array MCA2 instead of a memory cell array MCA. The memory cell array MCA2 includes bit line regions R arranged sequentially in the Y direction. BL Write transistor region R WTr Readout transistor region R RTr Select transistor region R STr and the source pole region R SL In addition, the memory cell array MCA2 has multiple memory layers ML2 arranged in the Z direction.

[0300] Bit line region R of memory cell array MCA2BL Write transistor region R WTr and the readout transistor region R RTr The structure and bit line region R of the memory cell array MCA in the middle BL Write transistor region R WTr and the readout transistor region R RTr The structure is the same.

[0301] Source pole region R SL The device includes wiring 220 extending in both the Z and X directions. Wiring 220 functions as a source line SL. Wiring 220 may include, for example, a barrier conductive film such as titanium nitride (TiN) and a conductive component such as tungsten (W). Additionally, on one side of wiring 220 in the Y direction (with the bit line region R)... BL An insulating layer 102 of silicon oxide (SiO) or the like is provided on the opposite side.

[0302] Select transistor region R STr It has multiple transistor structures 210 arranged in the X direction corresponding to multiple wirings 110 and in the Z direction corresponding to multiple storage layers ML2.

[0303] Each of the multiple transistor structures 210 has a semiconductor component 211 extending in the Y direction, an insulating layer 212 disposed on the upper and lower surfaces of the semiconductor component 211, and opposing electrodes 213 disposed on the upper and lower surfaces of the insulating layer 212.

[0304] Semiconductor component 211 functions as the channel region of the select transistor STr. Semiconductor component 211 may contain, for example, single-crystal silicon (Si). Semiconductor component 211 is continuous with semiconductor component 131. In addition, semiconductor component 211 is connected to wiring 220 via connection electrode 151.

[0305] The insulating layer 212 functions, for example, as the gate insulating film of the select transistor STr. The insulating layer 212 comprises, for example, silicon oxide (SiO). The insulating layer 212 extends in the Y direction along the upper and lower surfaces of the semiconductor component 211.

[0306] The opposing electrode 213 functions, for example, as the gate electrode of a select transistor STr. The opposing electrode 213 may contain, for example, titanium nitride (TiN). The opposing electrode 213 extends in the Y direction along the upper and lower surfaces of the insulating layer 212. The opposing electrode 213 is oriented opposite to the upper and lower surfaces of the semiconductor component 211 across the insulating layer 212.

[0307] Furthermore, the opposing electrodes 213 in the multiple transistor structures 210 arranged in the X direction are continuous with each other, forming a wiring extending in the X direction. This wiring functions as a read word line (RWL).

[0308] In addition, such as Figure 85 as well as Figure 86 As shown, an insulating layer 214, such as silicon nitride (SiN), is disposed between the opposing electrode 213 and the insulating layer 135, and an insulating layer 214, such as silicon nitride (SiN), is disposed between the opposing electrode 213 and the source line region R. SL An insulating layer 215, such as silicon nitride (SiN), is provided between them. In addition, an insulating layer 216, such as silicon oxide (SiO), is provided between two adjacent opposing electrodes 213 in the Z direction.

[0309] [Manufacturing Method]

[0310] Figures 87-110 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment. Figure 87 , Figure 89 , Figure 91 , Figure 93 , Figure 95 , Figure 97 , Figure 99 , Figure 101 , Figure 103 , Figure 105 , Figure 107 ,as well as Figure 109 It shows the relationship with Figure 85 Corresponding cross-sections. Figure 88 , Figure 90 , Figure 92 , Figure 94 , Figure 96 , Figure 98 , Figure 100 , Figure 102 , Figure 104 , Figure 106 , Figure 108 ,as well as Figure 110 It shows the relationship with Figure 86 Corresponding cross-sections.

[0311] When manufacturing the semiconductor memory device according to the second embodiment, the manufacturing process of the semiconductor memory device according to the first embodiment, including the step of referring to... Figure 32 as well as Figure 33 The processes up to the ones described above.

[0312] Next, as Figure 87 as well as Figure 88 As shown, the sacrificial layer 143B is removed. This process is performed, for example, by wet etching.

[0313] Next, as Figure 89 as well as Figure 90 As shown, a semiconductor component 143 is formed. This process is performed, for example, by an ALD (Alternating Current Device).

[0314] Next, as Figure 91 as well as Figure 92 As shown, a sacrificial layer 101B containing carbon (C) or the like is formed inside the tank 101A. This process is performed, for example, by CVD.

[0315] Next, as Figure 93 as well as Figure 94 As shown, in relation to insulating layer 102 ( Figure 7 as well as Figure 8 The corresponding position forms a groove 102A. This process is performed, for example, by a RIE (Rich Interchange Equipment).

[0316] Next, the manufacturing process of the semiconductor memory device according to the first embodiment is performed, referring to... Figure 40 Explained procedures and references Figure 41 as well as Figure 42 The procedures that have been explained.

[0317] Next, as Figure 95 as well as Figure 96 As shown, the insulating layer 152 is removed. This process is performed, for example, by wet etching.

[0318] Next, as Figure 97 as well as Figure 98 As shown, an insulating layer 212 is formed on a portion of the upper and lower surfaces of the insulating layer 135, on both sides in the X direction and one side (the side of trench 102A) in the Y direction, on one side (the side of trench 102A) in the Y direction of the insulating layers 132 and 134, and on the upper and lower surfaces of the semiconductor layer MLA and one side (the side of trench 102A) in the Y direction, as well as other exposed surfaces. Additionally, a sacrificial layer 217, such as silicon nitride, is formed in the region between two adjacent semiconductor layers MLA in the Z direction where the insulating layer 212 is not formed. This process is performed, for example, by CVD.

[0319] Next, as Figure 99 as well as Figure 100 As shown, a portion of the insulating layer 212 is removed, exposing one end of the semiconductor layer MLA in the Y direction (the trench 102A side). This process is performed, for example, by wet etching.

[0320] Next, as Figure 101 as well as Figure 102 As shown, sacrificial layers 101B and 217 are removed. This process is performed, for example, by wet etching.

[0321] Next, as Figure 103 as well as Figure 104As shown, a portion of the insulating layer 135 is removed, and an opening 145A is formed at a position corresponding to the opposing electrode 145 and the insulating layers 146 and 147. This process is performed, for example, by wet etching.

[0322] Next, the manufacturing process of the semiconductor memory device according to the first embodiment is performed, starting from the reference... Figure 57 as well as Figure 58 The described process is referenced. Figure 73 as well as Figure 74 The processes up to the point where the described processes have been completed. Therefore, as... Figure 105 as well as Figure 106 As shown, opposing electrodes 145 and 213 and insulating layers 146, 147, 148, 214, 215, and 216 are formed.

[0323] Next, as Figure 107 as well as Figure 108 As shown, connecting electrodes 141 and 151 are formed. In this process, N-type impurities such as phosphorus (P) are implanted into the semiconductor layer MLA from one end in the Y direction and the other end. The region of the semiconductor layer MLA after impurity diffusion becomes the connecting electrodes 141 and 151. In addition, the region of the semiconductor layer MLA between the connecting electrodes 141 and 151 becomes the semiconductor components 131 and 211. This process is performed, for example, by a GPD (Gas Processing Device).

[0324] Next, as Figure 109 as well as Figure 110 As shown, a conductive layer 110A is formed inside the trench 101A. Additionally, wiring 220 is formed inside the trench 102A. This process is performed, for example, by CVD.

[0325] Then, by performing the manufacturing process of the semiconductor memory device according to the first embodiment, referring to... Figure 81 as well as Figure 82 The processes described above are used as a reference for subsequent processes. Figure 85 as well as Figure 86 Explained semiconductor memory devices.

[0326] [Modifications of the semiconductor memory device according to the second embodiment]

[0327] The opposing electrode 213 of the semiconductor memory device according to the second embodiment may be facing not only the upper and lower surfaces of the semiconductor component 211, but also the side surface of the semiconductor component 211 in the X direction.

[0328] Figure 111 This is a schematic cross-sectional view showing a portion of the configuration of a modified example of the semiconductor memory device according to the second embodiment. Figure 111The illustrated semiconductor memory device is configured essentially the same as the semiconductor memory device according to the second embodiment. However, in Figure 111 In the illustrated semiconductor memory device, the insulating layer 212 is disposed not only on the upper and lower surfaces of the semiconductor member 211, but also on both sides of the semiconductor member 211 in the X direction. Furthermore, the opposing electrode 213 is disposed not only on the upper and lower surfaces of the insulating layer 212, but also on both sides of the insulating layer 212 in the X direction. Additionally, the opposing electrode 213 faces not only the upper and lower surfaces of the semiconductor member 211, but also the sides of the semiconductor member 211 in the X direction.

[0329] In manufacturing such a structure, for example, consider performing a reference... Figure 36 as well as Figure 37 After the explained process, select transistor region R. STr and the source pole region R SL Multiple grooves are formed. These multiple grooves are formed in conjunction with multiple insulating layers 111 ( Figure 7 Correspondingly, at multiple locations in the X direction, it extends in the Z direction through multiple semiconductor layers MLA and multiple sacrificial layers MLI, and pervades the selection transistor region R. STr and the source pole region R SL The ground extends in the Y direction. Then, a sacrificial layer is formed inside the trench. Next, a reference is established. Figure 38 as well as Figure 39 The described process. Then, the manufacturing process of the semiconductor memory device according to the second embodiment, as described above, is performed. Figure 40 The process following the explained process.

[0330] [Third Implementation]

[0331] [structure]

[0332] Figure 112 as well as Figure 113 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the third embodiment. Figure 112 and X The Y-section corresponds to this. Figure 113 With General Figure 112 The structure shown is cut along line AA′ and corresponds to the YZ section observed in the direction of the arrow.

[0333] The memory cell array (MCA) according to the third embodiment includes write word line regions R arranged sequentially in the Y direction. WWL Write transistor region R WTr Readout transistor region R RTr and the readout word line area R RWL .

[0334] The memory cell array MCA according to the third embodiment includes multiple memory layers ML3 arranged alternately in the Z direction and multiple insulating layers 301. The insulating layers 301 include silicon oxide (SiO) and the like. Additionally, in the write word line region R... WWL With the readout word line area R RWL Between these layers, there are multiple storage layers ML3 extending in the Z and Y directions and arranged alternately in the Z direction, and multiple insulating layers 302 truncated in the X direction. The insulating layers 302 include silicon oxide (SiO) and the like.

[0335] Write word line area R WWL The device comprises a plurality of wirings 310 extending in the X direction and arranged in the Z direction corresponding to a plurality of memory layers ML3, and an insulating layer 301 disposed between them. The plurality of wirings 310 function, for example, as write word lines WWL. The plurality of wirings 310 may include, for example, a barrier conductive film 311 of titanium nitride (TiN) and a conductive member 312 of tungsten (W). The insulating layer 301 may include, for example, silicon oxide (SiO).

[0336] Read out word line area R RWL The device comprises a plurality of wirings 320 extending in the X direction and arranged in the Z direction corresponding to a plurality of storage layers ML, and an insulating layer 301 disposed between them. The plurality of wirings 320 function, for example, as read word lines RWL. The plurality of wirings 320 may include, for example, a conductive oxide film 321, a barrier conductive film 322 such as titanium nitride (TiN), and a conductive member 323 such as tungsten (W). The conductive oxide film 321 may also include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO), iridium oxide (IrO), or other oxygen-containing conductive materials.

[0337] Readout transistor region R RTr The device has a plurality of transistor structures 330 that are arranged alternately in the X direction with a plurality of insulating layers 302 arranged in the X direction and in the Z direction corresponding to a plurality of storage layers ML3.

[0338] Each of the plurality of transistor structures 330 includes a semiconductor component 331 extending in the Y direction, an insulating layer 332 disposed on the upper and lower surfaces and two sides in the X direction of the semiconductor component 331, and opposing electrodes 333 disposed on the upper and lower surfaces and two sides in the X direction of the insulating layer 332. In addition, in this embodiment, the upper and lower surfaces and two sides in the X direction of the transistor structure 330 are covered by the insulating layer 354 and the opposing electrodes 355, which will be described later.

[0339] Semiconductor component 331 functions as the channel region of the readout transistor RTR. Semiconductor component 331 may also comprise, for example, an oxide semiconductor. As an oxide semiconductor, for example, the material exemplified as the material of semiconductor component 143 can be cited.

[0340] The insulating layer 332 functions, for example, as the gate insulating film of the readout transistor RTr. The insulating layer 332 comprises, for example, silicon oxide (SiO). The insulating layer 332 extends in the Y direction along the upper and lower surfaces of the semiconductor member 331 and along both sides in the X direction.

[0341] The opposing electrode 333 functions, for example, as the gate electrode of the readout transistor RTR and the storage node SN. The opposing electrode 333 may contain, for example, titanium nitride (TiN). The opposing electrode 333 extends in the Y direction along the upper and lower surfaces and the two sides in the X direction of the insulating layer 332. The opposing electrode 333 faces the upper and lower surfaces and the two sides in the X direction of the semiconductor component 331 across the insulating layer 332.

[0342] Write transistor region R WTr It has multiple wirings 340 arranged alternately in the X direction with multiple insulating layers 302 arranged in the X direction and extending in the Z direction through multiple storage layers ML3. Additionally, the write transistor region R... WTr It has multiple connection electrodes 351, multiple insulating layers 352, and multiple transistor structures 350 arranged in the X direction corresponding to the multiple wirings 340 and in the Z direction corresponding to the multiple storage layers ML3.

[0343] Multiple wirings 340 are each formed in a generally cylindrical shape. These multiple wirings 340 function, for example, as bit lines BL. The multiple wirings 340 may include, for example, a conductive oxide film 341, a barrier conductive film 342 such as titanium nitride (TiN), and a conductive member 343 such as tungsten (W). The conductive oxide film 341 may also include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO), iridium oxide (IrO), or other oxygen-containing conductive materials. In the illustrated example, the barrier conductive film 342 covers the outer peripheral surface of the conductive member 343. Additionally, the conductive oxide film 341 covers the outer peripheral surface of the barrier conductive film 342.

[0344] The connection electrode 351 is connected to the wiring 340 and the semiconductor component 331, enabling them to conduct electricity. The connection electrode 351 covers the entire circumference of the outer peripheral surface of the wiring 340 and is connected to the entire circumference of the outer peripheral surface of the wiring 340. Additionally, the write word line region R in the Y direction of the connection electrode 351 and the semiconductor component 331... WWLThe sides are connected. The connecting electrode 351 may also contain, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO), iridium oxide (IrO), or other oxygen-containing conductive materials.

[0345] Furthermore, in this embodiment, the connecting electrode 351 is continuous with the conductive oxide film 341 in the wiring 340 and contains the same material as the conductive oxide film 341. For example, the connecting electrode 351 is formed simultaneously with the conductive oxide film 341.

[0346] Multiple insulating layers 352 are respectively disposed on the upper and lower surfaces, the two sides in the X direction, and the write word line region R in the Y direction of multiple connecting electrodes 351. WWL Side surfaces. An insulating layer 352 is disposed between the connecting electrode 351 and the semiconductor component 353, providing electrical insulation between them. The insulating layer 352 may contain, for example, silicon oxide (SiO). The insulating layer 352 extends in the Y direction along the upper and lower surfaces of the connecting electrode 351 and both sides in the X direction.

[0347] Furthermore, in this embodiment, insulating layer 352 is continuous with insulating layer 332 and contains the same material as insulating layer 332. For example, insulating layer 352 is formed simultaneously with insulating layer 332.

[0348] Each of the multiple transistor structures 350 has a top and bottom surface, two sides in the X direction, and a write word line region R in the Y direction disposed on the insulating layer 352. WWL The semiconductor component 353 on the side surface, the upper and lower surfaces of the semiconductor component 353, the two side surfaces in the X direction, and the write word line region R in the Y direction. WWL The insulating layer 354 on the side surface, and the upper and lower surfaces, the two side surfaces in the X direction, and the write word line area R in the Y direction disposed on the insulating layer 354. WWL Opposite electrodes 355 on the side surface.

[0349] Semiconductor component 353 functions as the channel region of the write transistor WTr. Semiconductor component 353 extends in the Y direction along the upper and lower surfaces of the insulating layer 352 and its two sides in the X direction. The end of semiconductor component 353 on the wiring 320 side in the Y direction is connected to the opposing electrode 333. Furthermore, at a height position between the storage layers ML3, semiconductor component 353 covers the entire circumference of the outer peripheral surface of wiring 340 and is connected to wiring 340 throughout the entire circumference.

[0350] Semiconductor component 353 may also include, for example, an oxide semiconductor. As an oxide semiconductor, for example, is a material exemplified as the material used in semiconductor component 143.

[0351] The insulating layer 354 functions, for example, as a gate insulating film for a write transistor WTr. The insulating layer 354 comprises, for example, silicon oxide (SiO). The insulating layer 354 extends in the Y direction along the upper and lower surfaces of the semiconductor member 353 and both sides in the X direction.

[0352] The opposing electrode 355 functions, for example, as the gate electrode of the write transistor WTr. The opposing electrode 355 may contain, for example, titanium nitride (TiN). The opposing electrode 355 extends in the Y direction along the upper and lower surfaces and two sides in the X direction of the insulating layer 354. The opposing electrode 355 is positioned opposite the upper and lower surfaces and two sides in the X direction of the semiconductor component 353, separated by the insulating layer 354.

[0353] Furthermore, in this embodiment, the insulating layer 354 and the opposing electrode 355 extend throughout the write transistor region R. WTr and the readout transistor region R RTr The ground extends in the Y direction. Therefore, as described above, the upper and lower surfaces of the transistor structure 330, as well as the two sides in the X direction, are covered by an insulating layer 354 and a counter electrode 355. With this structure, the counter electrode 355 can function as a shield for the counter electrode 333, and can suppress data interference between two adjacent memory cells MC in the Z direction.

[0354] [Manufacturing Method]

[0355] Figures 114–176 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment. Figure 114 , Figure 116 , Figure 118 , Figure 120 , Figure 122 , Figure 124 , Figure 126 , Figure 128 , Figure 132 , Figure 134 , Figure 136 , Figure 138 , Figure 140 , Figure 142 , Figure 144 , Figure 146 , Figure 148 , Figure 150 , Figure 152 , Figure 154 , Figure 156 , Figure 158 , Figure 160 , Figure 162 , Figure 164 , Figure 166 , Figure 168 , Figure 170 , Figure 173 ,as well as Figure 175 Showing with Figure 112 Corresponding cross-sections. Figure 115 , Figure 117 , Figure 119 , Figure 121 , Figure 123 , Figure 125 , Figure 127 , Figure 129 , Figure 130 , Figure 131 , Figure 133 , Figure 135 , Figure 137 , Figure 139 , Figure 141 , Figure 143 , Figure 145 , Figure 147 , Figure 149 , Figure 151 , Figure 153 , Figure 155 , Figure 157 , Figure 159 , Figure 161 , Figure 163 , Figure 165 , Figure 167 , Figure 169 , Figure 171 , Figure 172 , Figure 174 ,as well as Figure 176 Showing with Figure 113 Corresponding cross-sections.

[0356] In this manufacturing method, for example, like Figure 115 As shown, multiple insulating layers 301 and multiple sacrificial layers MLA3 are alternately formed. The sacrificial layers MLA3 may contain, for example, silicon nitride (SiN). This process is performed, for example, by CVD.

[0357] Next, for example, like Figure 114 As shown, an insulating layer 302 is formed. In this process, for example, an opening is formed at a position corresponding to the insulating layer 302. This opening extends in the Z direction and penetrates the plurality of insulating layers 301 and the plurality of sacrificial layers MLA3 arranged in the Z direction. This process is performed, for example, by RIE (Reinforcing Equipment). After forming the opening, the insulating layer 302 is formed. This process is performed, for example, by CVD (Continuous Chemical Deposition).

[0358] Next, for example, like Figure 116 as well as Figure 117 As shown, grooves 101A and 102A extending along the X and Z directions are formed near the positions corresponding to wirings 310 and 320. Grooves 101A and 102A penetrate the plurality of insulating layers 301 and the plurality of sacrificial layers MLA3 arranged in the Z direction and cut off these structures in the Y direction. This process is performed, for example, by a RIE (Relative Insulation Layer).

[0359] Next, for example, like Figure 118 as well as Figure 119 As shown, openings 310A and 320A are formed. A portion of the upper surface and a portion of the lower surface of the insulating layer 301, a portion of the side surface of the insulating layer 302 in the X direction, and a portion of the side surface of the sacrificial layer MLA3 in the Y direction are exposed inside the openings 310A and 320A. In this process, for example, a portion of the sacrificial layer MLA3 is selectively removed via grooves 101A and 102A. This process is performed, for example, by wet etching.

[0360] Next, for example, like Figure 120 as well as Figure 121 As shown, a sacrificial layer 101B is filled inside the groove 101A and the opening 310A. Additionally, a sacrificial layer 102B is filled inside the groove 102A and the opening 320A. This process is performed, for example, by CVD.

[0361] Next, for example, like Figure 122 as well as Figure 123 As shown, an opening 340A is formed at a position corresponding to the wiring 340. The opening 340A extends through the plurality of insulating layers 301 and the plurality of sacrificial layers MLA3 arranged in the Z direction in the Z direction. This process is performed, for example, by a RIE (Relative Insulation Layer).

[0362] Next, for example, like Figure 124 as well as Figure 125 As shown, the sacrificial layer MLA3 is removed via opening 340A. This process is performed, for example, by wet etching. This process forms opening 351A at a position corresponding to the connecting electrode 351. Additionally, opening 331A is formed at a position corresponding to the semiconductor component 331. A portion of the upper surface and a portion of the lower surface of the insulating layer 301, a portion of the side surface of the insulating layer 302 in the X direction, and a portion of the side surface of the sacrificial layers 101B and 102B in the Y direction are exposed inside openings 351A and 331A.

[0363] Next, for example, like Figure 126 as well as Figure 127 As shown, a conductive layer 355A and a sacrificial layer 340B are formed inside openings 331A, 351A, and 340A. The conductive layer 355A is formed on a portion of the upper surface, a portion of the lower surface, and the side surface (inner peripheral surface of opening 340A) of the insulating layer 301, a portion of the side surface in the X direction of the insulating layer 302, and a portion of the side surface in the Y direction of the sacrificial layers 101B and 102B. Openings 331A and 351A are filled by the sacrificial layer 340B. Opening 340A is not filled by the sacrificial layer 340B. This process is performed, for example, by CVD.

[0364] Next, for example, like Figure 128 as well as Figure 129 As shown, a portion of the sacrificial layer 340B is removed, exposing the portion of the conductive layer 355A formed on the side of the insulating layer 301 (the inner peripheral surface of the opening 340A). This process is performed, for example, by wet etching.

[0365] Next, for example, like Figure 130 As shown, the portion of conductive layer 355A formed on the side surface of insulating layer 301 (inner peripheral surface of opening 340A) is removed. Through this process, conductive layer 355A is truncated in the Z direction. This process is performed, for example, by wet etching.

[0366] Next, for example, like Figure 131 As shown, a sacrificial layer 340B is formed inside the opening 340A. In this process, the opening 340A is filled with the sacrificial layer 340B. This process is performed, for example, by CVD.

[0367] Next, although not shown in the diagram, the sacrificial layer 102B is removed, exposing the portion of the conductive layer 355A formed on the side of the sacrificial layer 340B. This process is performed, for example, by wet etching.

[0368] Next, for example, like Figure 132 as well as Figure 133 As shown, the portion of the conductive layer 355A formed on the side of the sacrificial layer 340B is removed. This process forms the opposing electrode 355. This process is performed, for example, by wet etching.

[0369] Next, for example, like Figure 134 as well as Figure 135 As shown, a sacrificial layer 102B is formed inside the opening 320A and the groove 102A. In this process, the opening 320A and the groove 102A are filled with the sacrificial layer 102B. This process is performed, for example, by CVD.

[0370] Next, for example, like Figure 136 as well as Figure 137 As shown, the sacrificial layer 340B is removed. This process is performed, for example, by wet etching. The sacrificial layer 102B, which is in contact with the end face in the Y direction of the opposing electrode 355, is also removed.

[0371] Next, for example, like Figure 138 as well as Figure 139As shown, an insulating layer 354A, a conductive layer 333A, and a sacrificial layer 340B are formed inside openings 331A, 351A, and 340A. The insulating layer 354A and the conductive layer 333A are respectively formed on the upper surface, lower surface, two side surfaces in the X direction, and one side surface in the Y direction of the conductive layer 355A, as well as a portion of the upper surface, a portion of the lower surface, and one side surface (the inner peripheral surface of opening 340A) of the insulating layer 301. Openings 331A and 351A are filled with the sacrificial layer 340B. Opening 340A is not filled with the sacrificial layer 340B. This process is performed, for example, by CVD.

[0372] Next, for example, like Figure 140 as well as Figure 141 As shown, a portion of the sacrificial layer 340B is removed. In this process, the sacrificial layer 340B, formed in the readout transistor region R... RTr Some of the contents remain inside, while the rest are removed. This process is carried out, for example, by wet etching.

[0373] Next, for example, like Figure 142 as well as Figure 143 As shown, a portion of the conductive layer 333A is removed. In this process, the conductive layer 333A, which is formed in the readout transistor region R... RTr Some of the contents remain inside, while the rest are removed. This process is carried out, for example, by wet etching.

[0374] Next, for example, like Figure 144 as well as Figure 145 As shown, the sacrificial layer 340B is removed. This process is performed, for example, by wet etching.

[0375] Next, for example, like Figure 146 as well as Figure 147 As shown, a semiconductor component 353A and a sacrificial layer 340B are formed inside openings 331A, 351A, and 340A. The semiconductor component 353A is formed on the upper surface, lower surface, two sides in the X direction, and one side in the Y direction of the conductive layer 333A, and on the upper surface, lower surface, two sides in the X direction, one side in the Y direction, and the portion formed on the inner peripheral surface of opening 340A. In this process, openings 331A, 351A, and 340A are filled with the sacrificial layer 340B. This process is performed, for example, by CVD.

[0376] Next, for example, like Figure 148 as well as Figure 149 As shown, the sacrificial layer 102B is removed, exposing the portion of the insulating layer 354A formed on the side of the conductive layer 333A in the Y direction. This process is performed, for example, by wet etching.

[0377] Next, for example, like Figure 150 as well as Figure 151 As shown, the portions of the insulating layer 354A, conductive layer 333A, and semiconductor component 353A formed on the side of the sacrificial layer 340B are removed. Through this process, the insulating layer 354 and the opposing electrode 333 are formed. This process is performed, for example, by wet etching.

[0378] Next, for example, like Figure 152 as well as Figure 153 As shown, the sacrificial layer 340B is formed in the readout transistor region R. RTr The internal parts are removed. This process is performed, for example, by wet etching.

[0379] Next, for example, like Figure 154 as well as Figure 155 As shown, semiconductor component 353A is formed in the readout transistor region R. RTr The internal portion is removed. Through this process, a semiconductor component 353 is formed. This process is performed, for example, by wet etching.

[0380] Next, for example, like Figure 156 as well as Figure 157 As shown, the sacrificial layer 340B is removed to form the opening 351A. This process is performed, for example, by wet etching.

[0381] Next, for example, like Figure 158 as well as Figure 159 As shown, insulating layers 332 and 352 are formed inside openings 331A, 351A, and 340A. Insulating layers 332 and 352 are formed on the upper surface, lower surface, and two side surfaces in the X direction of conductive layer 333; on the upper surface, lower surface, two side surfaces in the X direction, and one side surface in the Y direction of semiconductor component 353; on the inner peripheral surface of opening 340A; a portion of the upper surface, a portion of the lower surface, and one side surface in the Y direction of insulating layer 301; and a portion of the two side surfaces in the X direction and one side surface in the Y direction of insulating layer 302. This process is performed, for example, by CVD.

[0382] Next, although the illustration is omitted, a sacrificial layer 340B is formed inside the openings 331A, 351A, 340A, 320A, and 102A. In this process, the openings 331A, 351A, 340A, 320A, and 102A are filled by the sacrificial layer 340B. This process is performed, for example, by CVD.

[0383] Next, for example, like Figure 160 as well as Figure 161As shown, portions of the sacrificial layer 340B formed within openings 102A, 320A, and 331A are removed. This process is performed, for example, by wet etching.

[0384] Next, for example, like Figure 162 as well as Figure 163 As shown, a semiconductor component 331B is formed inside openings 102A, 320A, and 331A. Opening 331A is filled with semiconductor component 331B. Openings 102A and 320A are not filled with semiconductor component 331B. This process is performed, for example, by CVD.

[0385] Next, for example, like Figure 164 as well as Figure 165 As shown, a portion of the semiconductor component 331B is removed. In this process, the semiconductor component 331B, formed in the readout transistor region R... RTr Part of the semiconductor component 331B remains, while the rest is removed. Thus, the semiconductor component 331B is truncated in the Z direction. Furthermore, the semiconductor component 331B, formed in the readout transistor region R... RTr The internal portion becomes semiconductor component 331. This process is performed, for example, by wet etching.

[0386] Next, for example, like Figure 166 as well as Figure 167 As shown, the sacrificial layer 340B is removed. This process is performed, for example, by wet etching.

[0387] Next, for example, like Figure 168 as well as Figure 169 As shown, a sacrificial layer 102B is formed inside the groove 102A and the opening 320A. Additionally, a sacrificial layer 340B is formed inside the openings 351A and 340A. The openings 320A and 351A are filled with sacrificial layers 102B and 340B. The groove 102A and the opening 340A are not filled with sacrificial layers 102B and 340B. This process is performed, for example, by CVD.

[0388] Next, for example, like Figure 170 as well as Figure 171 As shown, a portion of the sacrificial layer 102B is removed, exposing a portion of the insulating layer 332 that covers the insulating layer 301 in the Y direction (the inner wall surface of the opening 102A). Additionally, a portion of the sacrificial layer 340B is removed, exposing a portion of the insulating layer 352 that forms on the side surface of the semiconductor component 353 (the inner peripheral surface of the opening 340A). This process is performed, for example, by wet etching.

[0389] Next, for example, like Figure 172As shown, the portion of insulating layer 332 formed on the side surface of insulating layer 301 (inner wall surface of opening 102A) is removed. Additionally, the portion of insulating layer 352 formed on the side surface of semiconductor component 353 (inner peripheral surface of opening 340A) is removed. This process is performed, for example, by wet etching.

[0390] Next, for example, like Figure 173 as well as Figure 174 As shown, the sacrificial layers 340B and 102B are removed. This process is performed, for example, by wet etching.

[0391] Next, for example, like Figure 175 as well as Figure 176 As shown, a conductive oxide film 321B is formed inside the openings 102A and 320A. The conductive oxide film 321B is formed on the side surface of the semiconductor component 331 in the Y direction, the upper and lower surfaces of the insulating layer 332, the two side surfaces in the X direction and the side surface in the Y direction, and the side surface of the insulating layer 301 in the Y direction (the inner wall surface of the opening 102A). Furthermore, a connecting electrode 351 is formed inside the opening 351A, and a conductive oxide film 341 is formed inside the opening 340A. This process is performed, for example, by CVD.

[0392] Then, for example, the sacrificial layer 101B is removed by wet etching or the like. In addition, wirings 310, 320, and 340 are formed by CVD and wet etching or the like, thereby manufacturing the semiconductor memory device according to the third embodiment.

[0393] [Fourth Implementation]

[0394] Figure 177 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the fourth embodiment. Figure 177 Corresponding to the YZ section. In the following description, the same reference numerals are used for the parts that are the same as in the third embodiment, and the description is omitted.

[0395] The semiconductor memory device according to the fourth embodiment is configured in essentially the same way as the semiconductor memory device according to the third embodiment. However, the semiconductor memory device according to the fourth embodiment includes a transistor structure 450 instead of a transistor structure 350. The transistor structure 450 is configured in essentially the same way as the transistor structure 350. However, the transistor structure 450 includes a counter electrode 455 instead of a counter electrode 355.

[0396] The opposing electrode 455 is constructed in essentially the same way as the opposing electrode 355. However, the opposing electrode 455 is only disposed in the write transistor region R. WTr Inside, there is no transistor set in the readout transistor region R. RTrTherefore, in this embodiment, the upper and lower surfaces of the transistor structure 330, as well as the two sides in the X direction, are not covered by the opposing electrodes 455.

[0397] Figure 178 as well as Figure 179 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the fourth embodiment. Figure 178 as well as Figure 179 Showing with Figure 177 Corresponding cross-sections.

[0398] The semiconductor memory device according to the fourth embodiment is manufactured in essentially the same manner as the semiconductor memory device according to the third embodiment.

[0399] However, when manufacturing the semiconductor memory device according to the third embodiment, during the execution of the reference... Figure 132 as well as Figure 133 After the explained procedures and following the reference... Figure 134 as well as Figure 135 Before the explained procedures, such as Figure 178 As shown, the sacrificial layer 340B is formed in the readout transistor region R. RTr The internal parts are removed. This process is performed, for example, by wet etching.

[0400] In addition, such as Figure 179 As shown, the electrode 355 is formed in the readout transistor region R. RTr The inner portion is removed. Through this process, opposing electrodes 455 are formed. This process is performed, for example, by wet etching.

[0401] [Other Implementation Methods]

[0402] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and the specific configuration can be appropriately adjusted.

[0403] For example, in the first and second embodiments, a conductive oxide film may be provided between the opposing electrode 133 and the semiconductor component 143. The conductive oxide film may, for example, comprise indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO), iridium oxide (IrO), or other oxygen-containing conductive materials.

[0404] Alternatively, for example, in the first and second embodiments, a metal layer containing ruthenium (Ru), iridium (Ir) or other materials may be provided between the opposing electrode 133 and the semiconductor component 143.

[0405] Furthermore, the manufacturing methods of the semiconductor memory devices according to Embodiments 1 to 4 can also be appropriately adjusted. For example, the order of any two of the above-described steps can be changed, or any two of the above-described steps can be performed simultaneously.

[0406] In addition, the opposing electrode 145 of the semiconductor memory device according to the first embodiment and the second embodiment may be facing not only the upper and lower surfaces of the semiconductor component 143, but also the upper and lower surfaces of the opposing electrode 133.

[0407] In the case of manufacturing such a structure, for example, consider in reference Figure 55 as well as Figure 56 In the described process, not only is the insulating layer 135 placed in the write transistor region R... WTr The portion in the middle is removed, and it will also be set in the readout transistor region R. RTr The part in it is also removed.

[0408] Furthermore, in the semiconductor memory device according to the second embodiment, the write transistor WTr can also be implemented using the transistor structure 350 according to the third embodiment or the transistor structure 450 according to the fourth embodiment. Similarly, the read transistor RTr can also be implemented using the transistor structure 330 according to the third embodiment.

[0409] Furthermore, in the semiconductor memory device according to the first embodiment, the write transistor WTr can also be implemented using the transistor structure 350 according to the third embodiment or the transistor structure 450 according to the fourth embodiment.

[0410] Alternatively, the readout transistor RTr may not be an NMOS transistor, but a PMOS transistor. In this case, the connection electrodes 141 and 151 may not contain N-type impurities such as phosphorus (P), but contain P-type impurities such as boron (B).

[0411] [other]

[0412] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included in the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: The first wiring extends in the first direction; The second wiring extends in a second direction that intersects the first direction; A first semiconductor component is disposed between the first wiring and the second wiring, extends in a third direction intersecting the first direction and the second direction, and is electrically connected to the first wiring and the second wiring; The first opposing electrode is opposite to two surfaces of the first semiconductor component in the first direction and two surfaces in the second direction; A first connecting electrode extends in the third direction and is connected to the first semiconductor component and the first wiring. A second semiconductor component, extending in a third direction along two sides of the first connecting electrode in a first direction and two sides in a second direction, is connected to the first opposing electrode and the first wiring; and The second opposing electrode is opposite to two sides of the second semiconductor component in the first direction.

2. The semiconductor memory device according to claim 1, The second opposing electrode is opposite to two sides of the second semiconductor component in the second direction.

3. The semiconductor memory device according to claim 1, The second opposing electrode is part of a wiring extending in the second direction.

4. The semiconductor memory device according to claim 1, The first semiconductor component comprises silicon, i.e., Si. The second semiconductor component comprises an oxide semiconductor.

5. The semiconductor memory device according to claim 4, The first connecting electrode contains silicon (Si) and N-type or P-type impurities.

6. The semiconductor memory device according to claim 4, The oxide semiconductor contains at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

7. The semiconductor memory device according to claim 1, It has a second connection electrode that extends in the third direction and is connected to the first semiconductor component and the second wiring.

8. The semiconductor memory device according to claim 7, The first semiconductor component comprises silicon, i.e., Si. The second semiconductor component comprises an oxide semiconductor. The first connecting electrode and the second connecting electrode contain silicon (Si) and N-type or P-type impurities.

9. The semiconductor memory device according to claim 1, The first semiconductor component has a third opposing electrode, which is disposed between the first opposing electrode and the second wiring and faces both sides of the first semiconductor component in the first direction.

10. The semiconductor memory device according to claim 9, The third opposing electrode is opposite to two sides of the first semiconductor component in the second direction.

11. The semiconductor memory device according to claim 9, The third opposing electrode is part of a wiring extending in the second direction.

12. The semiconductor memory device according to claim 1, When viewed from the first direction, the first connecting electrode covers the outer peripheral surface of the first wiring. The second semiconductor component covers the side of the first connecting electrode in the third direction opposite to the second wiring. The second opposing electrode covers the side of the second semiconductor component in the third direction opposite to the second wiring.

13. The semiconductor memory device according to claim 1, When viewed from the first direction, the second semiconductor component covers the outer peripheral surface of the first wiring and is in contact with the outer peripheral surface of the first wiring.

14. The semiconductor memory device according to claim 1, It also includes a third wiring, which extends in the second direction and is connected to the surface of the second opposing electrode in the third direction opposite to the second wiring.

15. The semiconductor memory device according to claim 1, The second opposing electrode covers both sides of the first opposing electrode in the first direction.

16. The semiconductor memory device according to claim 1, The first semiconductor component comprises an oxide semiconductor.

17. The semiconductor memory device according to claim 16, The oxide semiconductor contains at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

Images