Memory device

Abstract

A storage device is provided to improve the integration density of the storage device. One embodiment of the storage device includes: a first conductive post, a second conductive post, and a third conductive post, each extending along a first direction; a first semiconductor film surrounding the first conductive post at a first position in the first direction; a second semiconductor film partially surrounding the second conductive post at the first position; a third semiconductor film partially surrounding the third conductive post at the first position; a fourth semiconductor film connected to a first end of the first semiconductor film, the second semiconductor film, and the third semiconductor film, respectively; a first charge storage film disposed between the second conductive post and the second semiconductor film; and a second charge storage film disposed between the third conductive post and the third semiconductor film.

Description

Technical Field

[0001] The implementation involves storage devices. Background Technology

[0002] NAND flash memory is a known storage device capable of storing data non-volatilely. In storage devices like NAND flash memory, a three-dimensional storage structure is employed for high integration and large capacity. Summary of the Invention

[0003] Increase the integration level of storage devices.

[0004] The storage device according to the embodiment includes: a first conductive post, a second conductive post, and a third conductive post, each extending along a first direction; a first semiconductor film surrounding the first conductive post at a first position in the first direction; a second semiconductor film partially surrounding the second conductive post at the first position; a third semiconductor film partially surrounding the third conductive post at the first position; a fourth semiconductor film connected to a first end of the first semiconductor film, the first end of the second semiconductor film, and the first end of the third semiconductor film; a first charge storage film disposed between the second conductive post and the second semiconductor film; and a second charge storage film disposed between the third conductive post and the third semiconductor film. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example of the configuration of a storage system containing storage devices according to an embodiment.

[0006] Figure 2 This is a circuit diagram illustrating an example of the circuit structure of a memory cell array provided by a memory device in an embodiment.

[0007] Figure 3 This is a top view showing an example of the planar layout of a storage cell array according to an implementation method.

[0008] Figure 4 This is an example of a cross-sectional structure of a memory cell array illustrating an implementation method. Figure 3 A cross-sectional view along line IV-IV.

[0009] Figure 5 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0010] Figure 6 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0011] Figure 7 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0012] Figure 8 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0013] Figure 9 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0014] Figure 10 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0015] Figure 11 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0016] Figure 12 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0017] Figure 13 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0018] Figure 14 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0019] Figure 15 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0020] Figure 16 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0021] Figure 17 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0022] Figure 18 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0023] Figure 19 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0024] Figure 20 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0025] Figure 21 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0026] Figure 22This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0027] Figure 23 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0028] Figure 24 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0029] Figure 25 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0030] Figure 26 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0031] Figure 27 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0032] Figure 28 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0033] Figure 29 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0034] Figure 30 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0035] Figure 31 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0036] Figure 32 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0037] Figure 33 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0038] Figure 34 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0039] Figure 35 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0040] Figure 36 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0041] Figure 37 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0042] Figure 38 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0043] Figure 39 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0044] Figure 40 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0045] Figure 41 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0046] Figure 42 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0047] Figure 43 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0048] Figure 44 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0049] Figure 45 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0050] Figure 46 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0051] Figure 47 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0052] Figure 48 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0053] Figure 49 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0054] Figure 50 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0055] Figure 51This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0056] Figure 52 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0057] Figure 53 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0058] Figure 54 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0059] Figure 55 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0060] Figure 56 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0061] Figure 57 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment.

[0062] Figure 58 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment.

[0063] Figure 59 This is a top view showing an example of the planar layout of a modified memory cell array.

[0064] Explanation of reference numerals in the attached figures 1…Storage System 2… Storage Controller 3… Storage devices 10… Storage cell array 11…Instruction Register 12… Address Register 13… Sequence Generator 14…Driver Module 15…line decoder module 16…Readout Amplifier Module 20...Substrate 51, 52, 53, 54… Sacrificial Layer 61, 63, 67, 72, 75, 79, 83, 86… barrier membrane 62, 64, 65, 66, 68, 71, 73, 74, 76, 77, 78, 80, 82, 84, 85, 87, 89… Sacrificial membrane 69, 81, 88, 91, 93… Semiconductor films 70, 90, 92, 94… Insulating film 95, 97… conductive films 96, 98… Conductor layers 99…insulator layer Detailed Implementation

[0065] The embodiments will now be described with reference to the accompanying drawings. The dimensions and scale of the drawings may not be identical to those in reality.

[0066] Furthermore, in the following description, the same reference numerals are used to denote constituent elements that have substantially the same function and structure. Where elements with the same structure are specifically distinguished from each other, different text or numbers may be appended to the end of the same reference numerals.

[0067] 1. Composition 1.1 Storage System Figure 1 This is a block diagram illustrating an example of the configuration of a storage system including the storage device described in the embodiment. Storage system 1 is a storage device configured to connect to an external host (not shown). Storage system 1 is, for example, an SD card. TM Storage systems include memory cards (like memory cards), UFS (universal flash storage), and SSDs (solid state drives). Storage system 1 comprises a storage controller 2 and storage devices 3.

[0068] The storage controller 2 is, for example, an integrated circuit such as a system-on-a-chip (SoC). The storage controller 2 controls the storage device 3 based on requests from the host. Specifically, for example, the storage controller 2 writes data requested by the host to the storage device 3. Additionally, the storage controller 2 reads data requested by the host from the storage device 3 and sends it to the host.

[0069] Storage device 3 is non-volatile memory. Storage device 3 is, for example, NAND flash memory. Storage device 3 stores data non-volatilely.

[0070] The communication between the storage controller 2 and the storage device 3 is, for example, based on the SDR (single data rate) interface, the Toggle DDR (double data rate) interface, or the ONFI (Open NAND flash interface).

[0071] 1.2 Storage devices Next, refer to Figure 1 The block diagram shown illustrates the internal structure of the storage device in the embodiment. The storage device 3 includes, for example, a storage cell array 10, an instruction register 11, an address register 12, a sequence generator 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0072] The storage cell array 10 contains multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). The storage cell array 10 may also contain only one block BLK. A block BLK is a collection of multiple storage cells. A block BLK is used, for example, as a unit for data erasure. Additionally, the storage cell array 10 includes multiple bit lines and multiple word lines. Each storage cell is associated with, for example, one bit line and one word line. Detailed structure of the storage cell array 10 will be described later.

[0073] Instruction register 11 stores instructions (CMD) received by storage device 3 from storage controller 2. Instructions (CMD) may include commands that cause sequence generator 13 to perform read, write, erase, etc.

[0074] Address register 12 stores address information ADD received by storage device 3 from storage controller 2. Address information ADD includes, for example, block address BAd, page address PAd, and column address CAd. For example, block address BAd, page address PAd, and column address CAd are used for selecting block BLK, word lines, and bit lines, respectively.

[0075] The sequence generator 13 controls the overall operation of the storage device 3. For example, the sequence generator 13 controls the driver module 14, the line decoder module 15, and the sense amplifier module 16 based on the instruction CMD stored in the instruction register 11, and performs read operations, write operations, erase operations, etc.

[0076] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Furthermore, the driver module 14 applies the generated voltages, for example, to signal lines corresponding to word lines selected based on page addresses PAd stored in the address register 12.

[0077] The row decoder module 15 selects a block BLK within the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Furthermore, the row decoder module 15, for example, transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block BLK.

[0078] During the write operation, the read amplifier module 16 applies the desired voltage to each bit line based on the write data DAT received from the memory controller 2. Additionally, during the read operation, the read amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit lines and transmits the determination result as read data DAT to the memory controller 2.

[0079] 1.3 Storage Cell Array 1.3.1 Circuit Structure Next, the circuit structure of the memory cell array in the embodiment will be described.

[0080] Figure 2 This is a circuit diagram illustrating an example of the circuit structure of a memory cell array included in a memory device according to an embodiment. Figure 2 The image shows one of the multiple block BLKs contained in the storage cell array 10. For example... Figure 2 As shown, block BLK contains, for example, four string units SU0 to SU3.

[0081] Each string cell SU contains multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). The number of bit lines BL can also be one. Each NAND string NS, for example, contains memory cell transistors MT0 to MT9 and select transistors ST1 and ST2. Each memory cell transistor MT contains a control gate and a charge storage film, storing data non-volatilely. Select transistors ST1 and ST2 are used to select the string cell SU during various operations.

[0082] In each NAND string NS, memory cell transistors MT0 to MT9 form two current paths between select transistors ST1 and ST2. Specifically, memory cell transistors MT0 to MT4 form one current path through series connection. Memory cell transistors MT5 to MT9 form a different current path through series connection. The drain of select transistor ST1 is connected to the associated bit line BL. The source of select transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT4 and one end of the series-connected memory cell transistors MT5 to MT9. The drain of select transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT4 and the other end of the series-connected memory cell transistors MT5 to MT9. The source of select transistor ST2 is connected to the source line SL. That is, memory cell transistors MT0 to MT4 are connected in parallel with memory cell transistors MT5 to MT9 between select transistors ST1 and ST2.

[0083] Within the same memory block (BLK), the control gates of memory cell transistors MT0 to MT9 are connected to word lines WL0 to WL9, respectively. The gates of selection transistors ST1 within serial cells SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. The gates of multiple selection transistors ST2 are connected to selection gate line SGS.

[0084] Different column addresses are assigned to bit lines BL0 to BLm. Each bit line BL is shared by the NAND string NS, which has the same column address assigned across multiple BLK blocks. Word lines WL0 to WL9 are set for each BLK block. Source lines SL are shared across multiple BLK blocks, for example.

[0085] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string cell SU is called a cell group. For example, the storage capacity of a cell group containing memory cell transistors MT that each store 1 bit of data is defined as "1 page of data". A cell group can have a storage capacity of more than 2 pages of data, depending on the number of bits of data stored by the memory cell transistors MT.

[0086] A collection of multiple memory cell transistors MT connected to a common bit line BL within a block BLK is called a layer cell LU. A layer cell LU contains four NAND strings NS. The four NAND strings NS contained in a layer cell LU belong to string cells SU0 to SU3 respectively.

[0087] Furthermore, the circuit structure of the memory cell array 10 provided by the memory device 3 is not limited to the structure described above. For example, the number of string cells SU contained in each BLK can be designed to be any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 contained in each NAND string NS can each be designed to be any number.

[0088] 1.3.2 Floor Plan Next, the planar layout of the storage cell array in the implementation method will be described.

[0089] The memory cell array 10 is disposed above the substrate. Hereinafter, the plane parallel to the surface of the substrate is designated as the XY plane. The direction in which the word line WL extends within the XY plane is designated as the X direction. The direction orthogonal to the X direction within the XY plane is designated as the Y direction. The direction from the substrate toward the memory cell array is designated as the Z direction. The Z direction can also be read as the upward direction.

[0090] Figure 3 This is a top view illustrating an example of the planar layout of a memory cell array according to an implementation method. Figure 3The image shows a top view of the structure constituting the memory cell array 10, which contains a layer of structures that function as NAND strings NS, located at approximately equal positions in the Z direction from the substrate (within the XY plane). Figure 3 The part shown is the same as Figure 2 The circuit diagram shown corresponds to a layer unit LU.

[0091] like Figure 3 As shown, in the same layer, the memory cell array 10 includes multiple conductive pillars WP1, WP2, DP and SP, multiple barrier insulating films WBK, DBK and SBK, multiple charge storage films CSL, multiple tunnel insulating films WTN, DTN and STN, multiple channel films WCH, DCH and SCH, multiple current path films CPL, multiple insulators INS, multiple contacts WV, multiple word lines WL and bit lines BL.

[0092] Multiple conductive pillars WP1, WP2, DP, and SP are each a conductor with a columnar shape extending along the Z-direction. These conductive pillars WP1, WP2, DP, and SP are arranged in a matrix in the XY plane in two directions different from the X and Y directions. Hereinafter, the P direction and Q direction are defined as the arrangement directions of the multiple conductive pillars WP1, WP2, DP, and SP that are different from the X and Y directions.

[0093] exist Figure 3 In the example, the seven conductive pillars DP, WP1, WP1, WP1, WP1, WP1, and SP are arranged sequentially in the P direction. The seven conductive pillars DP, WP2, WP2, WP2, WP2, WP2, and SP are arranged sequentially in the P direction, adjacent to the seven conductive pillars DP, WP1, WP1, WP1, WP1, WP1, and SP arranged in the P direction in the X direction. Furthermore, the groups of seven conductive pillars DP, WP1, WP1, WP1, WP1, and SP arranged in the P direction alternate with the groups of seven conductive pillars DP, WP2, WP2, WP2, WP2, and SP arranged in the P direction in the X direction.

[0094] When viewed from the Q direction, the above configuration is also represented as follows: The seven conductive pillars DP, WP1, WP2, WP1, WP2, WP1, and SP are arranged sequentially in the Q direction. The seven conductive pillars DP, WP2, WP1, WP2, WP1, WP2, and SP are arranged sequentially in the Q direction, adjacent to the seven conductive pillars DP, WP1, WP2, WP1, WP2, WP1, and SP arranged sequentially in the Q direction in the X direction. Furthermore, the groups of seven conductive pillars DP, WP1, WP2, WP1, WP2, WP1, and SP arranged in the Q direction alternate with the groups of seven conductive pillars DP, WP2, WP1, WP2, WP1, WP2, and SP arranged in the Q direction in the X direction.

[0095] Viewed from the Z direction, a barrier insulating film WBK is provided to surround the outer periphery of each of the conductive pillars WP1 and WP2. Two charge storage films CSL are separately provided to partially surround the outer periphery of the barrier insulating film WBK. The two charge storage films CSL partially surrounding the outer periphery of a certain barrier insulating film WBK are opposed to each other in the Q direction. Two portions of the outer periphery of the barrier insulating film WBK that are not surrounded by the charge storage film CSL are opposed to each other in the P direction. A tunnel insulating film WTN is provided to surround the outer periphery of the charge storage film CSL. A channel film WCH is provided to surround the outer periphery of the tunnel insulating film WTN. Thus, two sets of stacked charge storage films CSL, tunnel insulating films WTN, and channel films WCH are separately provided to each other in the Q direction, opposed to each other, relative to the barrier insulating film WBK. Hereinafter, the stacked film of barrier insulating film WBK, charge storage film CSL, tunnel insulating film WTN, and channel film WCH is also referred to as the MT stacked film.

[0096] The conductive post WP1 or WP2, together with an MT layer, functions as a memory cell transistor MT. That is, the conductive post WP1 or WP2 functions as the gate electrode of the memory cell transistor MT, which is electrically connected to the word line WL. Furthermore, the conductive posts WP1 and WP2 are shared as the gate electrodes of two memory cell transistors MT, respectively, which are two memory films that are disposed separately from each other.

[0097] Viewed along the Z-direction, a barrier insulating film SBK is provided to surround the outer periphery of each conductive post SP. A tunnel insulating film STN is provided to surround the outer periphery of the barrier insulating film SBK. A channel film SCH is provided to surround the outer periphery of the tunnel insulating film STN. Thus, for each conductive post SP, a stacked set of barrier insulating film SBK, tunnel insulating film STN, and channel film SCH is provided. Hereinafter, the stacked film of barrier insulating film SBK, tunnel insulating film STN, and channel film SCH is also referred to as the ST stacked film.

[0098] The conductive post SP and an ST layer stack function as a select transistor ST1. That is, the conductive post SP functions as the gate electrode in the select transistor ST1, which is electrically connected to the select gate line SGS.

[0099] Viewed along the Z-direction, a barrier insulating film DBK is provided to surround the outer periphery of each conductive post DP. A tunnel insulating film DTN is provided to surround the outer periphery of the barrier insulating film DBK. A trench film DCH is provided to surround the outer periphery of the tunnel insulating film DTN. Thus, for each conductive post DP, a stacked set of barrier insulating film DBK, tunnel insulating film DTN, and trench film DCH is provided. Hereinafter, the stacked film of barrier insulating film DBK, tunnel insulating film DTN, and trench film DCH is also referred to as the ST stacked film, similar to the stacked film of barrier insulating film SBK, tunnel insulating film STN, and trench film SCH.

[0100] The conductive post DP, together with an ST layer, functions as a select transistor ST2. That is, the conductive post DP functions as the gate electrode in the select transistor ST2, which is electrically connected to the select gate line SGD.

[0101] The two channel films WCH corresponding to conductive post WP1 are connected to the two channel films WCH corresponding to the adjacent conductive post WP1 in the P direction via two separate current path films CPL. The two channel films WCH corresponding to conductive post WP2 are connected to the two channel films WCH corresponding to the adjacent conductive post WP2 in the P direction via two separate current path films CPL. The channel film DCH corresponding to conductive post DP is connected via current path film CPL to one of the two channel films WCH corresponding to the adjacent conductive post WP1 in the P or Q direction and one of the two channel films WCH corresponding to the adjacent conductive post WP2 in the P or Q direction. The channel film SCH corresponding to conductive post SP is connected via current path film CPL to one of the two channel films WCH corresponding to the adjacent conductive post WP1 in the P or Q direction and one of the two channel films WCH corresponding to the adjacent conductive post WP2 in the P or Q direction.

[0102] Thus, the five conductive pillars WP1 arranged in the P direction form two independent current paths extending in the P direction and opposite each other in the Q direction. These two current paths are respectively connected to different sets of channel films DCH and SCH.

[0103] Multiple channel films SCH, corresponding to multiple conductive pillars SP arranged in the X direction, are connected to the source line SL.

[0104] Multiple channel films DCH, corresponding to multiple conductive pillars DP arranged in the X direction, are connected together to the bit line BL.

[0105] With the above structure, the following NAND string NS can be implemented: it has two sets of memory cell transistors MT connected in parallel between a set of select transistors ST1 and ST2. These two sets of memory cell transistors MT are five memory cell transistors MT connected in series in the P direction.

[0106] Furthermore, an insulator INS is provided in the portion surrounded by multiple current path films CPL and multiple channel films WCH. An air gap AG is provided in the portion surrounded by two current path films CPL connecting two adjacent conductive pillars WP1 or WP2 along the P direction and two channel films WCH corresponding to those two conductive pillars WP1 or WP2. An air gap AG is provided in the portion surrounded by two conductive pillars DP and one conductive pillar WP1 or WP2 respectively connected to those two conductive pillars DP. An air gap AG is provided in the portion surrounded by two conductive pillars SP and one conductive pillar WP1 or WP2 respectively connected to those two conductive pillars SP.

[0107] Contacts WV are provided on the upper surfaces of multiple conductive posts WP1 and WP2. Multiple contacts WV, respectively located on the multiple conductive posts WP1 arranged along the X direction, are connected to a common word line WL. Multiple contacts WV, respectively located on the multiple conductive posts WP2 arranged along the X direction, are connected to a common word line WL.

[0108] 1.3.3 Cross-sectional structure Next, the cross-sectional structure of the storage cell array of the embodiment will be described.

[0109] Figure 4 This is an example of a cross-sectional structure of a memory cell array illustrating an implementation method. Figure 3 A cross-sectional view along line IV-IV. Figure 4 The image primarily shows a cross-sectional structure including conductive pillars WP1, WP2, and DP. Furthermore, Figure 4 The conductive pillar WP1 shown is the structure on the left side of the paper, and a cross-section containing the corresponding two memory films is shown. Figure 4 The conductive pillar WP2 shown is the structure in the center of the paper, and a cross-section is shown that does not include the corresponding two memory films (i.e., the cross-section of the part surrounded by the air gap AG). Figure 4 The conductive pillar DP shown is the structure on the right side of the paper, and a cross-section is shown without the corresponding current path film CPL.

[0110] like Figure 4 As shown, the memory cell array 10 includes a substrate 20, sacrificial films 65 and 77, semiconductor films 69, 81, 88, 91 and 93, conductive films 95 and 97, insulating films 70, 90, 92 and 94, conductive layers 96 and 98, and insulating layer 99.

[0111] The substrate 20 is, for example, a semiconductor substrate containing silicon.

[0112] A plurality of conductive films 95 are disposed above the substrate 20. Each of the plurality of conductive films 95 extends in the Z direction. The plurality of conductive films 95 function as conductive pillars WP1, WP2, and DP and conductive pillar SP (not shown). Each of the plurality of conductive films 95 contains, for example, tungsten or molybdenum.

[0113] An insulating film 94 is provided to cover the lower surface and sides of each of the multiple conductive films 95. The insulating film 94 corresponding to the conductive film 95 functioning as conductive pillar WP1 or WP2 functions as a barrier insulating film WBK. The insulating film 94 corresponding to the conductive film 95 functioning as conductive pillar DP functions as a barrier insulating film DBK. The insulating film 94 corresponding to the conductive film 95 functioning as a conductive pillar SP (not shown) functions as a barrier insulating film SBK. Each of the multiple insulating films 94 contains, for example, silicon oxide.

[0114] The insulating films 94 covering the conductive films 95 corresponding to the conductive pillars DP or SP (not shown) are respectively connected to the substrate 20 at their lower portions. Between each insulating film 94 covering the conductive films 95 corresponding to the conductive pillars WP2 and the substrate 20, a sacrificial film 65, a semiconductor film 69, and an insulating film 70 are sequentially stacked from the substrate 20 side. Between each insulating film 94 covering the conductive films 95 corresponding to the conductive pillars WP1 and the substrate 20, a sacrificial film 77 and a semiconductor film 81 are sequentially stacked from the substrate 20 side. The sacrificial films 65 and 77, for example, comprise polycrystalline silicon. The semiconductor films 69 and 81, for example, comprise silicon germanium. The insulating film 70, for example, comprises silicon oxide. The insulating film 70 may also further comprise germanium.

[0115] A conductive film 97 is provided on the upper surface of a conductive film 95 that functions as a conductive post WP1 or WP2. The conductive film 97 functions as a contact WV. A conductive layer 98 is provided on the upper surface of the conductive film 97. The conductive layer 98 functions as a word line WL. The conductive film 97 and the conductive layer 98 are covered, for example, by an insulating layer 99.

[0116] Multiple layers are disposed separately in the Z direction, intersecting each other with multiple conductive films 95 and separated by an air gap AG. Each layer corresponds to a layer unit LU. The structure corresponding to one layer unit LU will be described below.

[0117] First, regarding Figure 4 The structure corresponding to the conductive post DP shown is explained.

[0118] In one layer, an insulating film 92 and a semiconductor film 88 are sequentially stacked on the side of an insulating film 94 corresponding to a conductive pillar DP. The insulating film 92, for example, contains silicon oxide and functions as a tunnel insulating film (DTN). The semiconductor film 88, for example, contains polycrystalline silicon and functions as a channel film (DCH).

[0119] On a portion of the side surface of the semiconductor film 88, a conductive layer 96 and a semiconductor film (not shown) are disposed separately from each other. The conductive layer 96 functions as a bit line BL. The semiconductor film (not shown) functions as a current path film CPL. An air gap AG is provided on the portion of the side surface of the semiconductor film 88 where the conductive layer 96 and the semiconductor film (not shown) are not disposed.

[0120] In a cross-section not shown, the conductive pillar SP is also provided with the same structure as the insulating film 92 and the semiconductor film 88.

[0121] Next, regarding Figure 4 The structure corresponding to the conductive post WP1 shown will be explained.

[0122] In one layer, two semiconductor films 93 are disposed separately on the side of the insulating film 94 corresponding to the conductive pillar WP1. The two semiconductor films 93 each contain, for example, polycrystalline silicon and function as floating gate type charge storage films CSL.

[0123] An insulating film 92 is disposed on each side of the two semiconductor films 93. Each of the two insulating films 92 contains, for example, silicon oxide and functions as a tunnel insulating film (WTN).

[0124] A semiconductor film 91 is disposed on each side of the two insulating films 92. Each of the two semiconductor films 91 contains, for example, polycrystalline silicon and functions as a channel film WCH.

[0125] An insulating film 90 is disposed on each side of the two semiconductor films 91. Each of the two insulating films 90 contains, for example, silicon oxide and functions as an insulator INS.

[0126] In a cross-section not shown, the conductive post WP2 is also provided with the same structure as the two sets of insulating films 90, semiconductor films 91, insulating films 92 and semiconductor films 93.

[0127] Next, regarding Figure 4 The structure corresponding to the conductive post WP2 shown will be explained.

[0128] In one layer, two air gaps AG are provided separately on the side of the insulating film 94 corresponding to the conductive pillar WP2. Furthermore, these two air gaps AG are connected via interlayer air gaps AG.

[0129] At least one of the two air gaps AG is surrounded by two insulating films 94 corresponding to two adjacent conductive pillars WP2 in the P direction, and two semiconductor films 81 connecting the two adjacent conductive pillars WP2 in the P direction. The two semiconductor films 81 are respectively connected to the insulating film 90 on a side facing away from the air gap AG. Figure 4 The image shows one of two semiconductor films 81. Each of the two semiconductor films 81 contains, for example, polycrystalline silicon and functions as a current path film CPL.

[0130] The other of the two air gaps AG mentioned above can be surrounded by an insulating film 94 corresponding to the conductive post WP2, a semiconductor film 88 corresponding to the conductive post DP or SP adjacent to the conductive post WP2 in the P direction, and a semiconductor film 88 corresponding to the conductive post DP or SP adjacent to the conductive post WP2 in the Q direction. Figure 4 The semiconductor film 88 corresponding to the conductive post DP that is adjacent to the conductive post WP2 in the P direction is shown.

[0131] In the cross-section not shown, the same structure corresponding to the air gap AG is also provided for the conductive post WP1.

[0132] 1.2 Manufacturing Method Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 33 , Figure 35 , Figure 37 , Figure 39 , Figure 41 , Figure 43 , Figure 45 , Figure 47 , Figure 49 , Figure 51 , Figure 53 , Figure 55 and Figure 57 This is a top view showing an example of the planar layout of a storage device during the manufacturing process of an embodiment. Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 32 , Figure 34 , Figure 36 , Figure 38 , Figure 40 , Figure 42 , Figure 44 , Figure 46 , Figure 48 , Figure 50 , Figure 52 , Figure 54 , Figure 56 and Figure 58 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device during the manufacturing process of the embodiment. Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 33 , Figure 35 , Figure 37 , Figure 39 , Figure 41 , Figure 43 , Figure 45 , Figure 47 , Figure 49 , Figure 51 , Figure 53 , Figure 55 and Figure 57 The plan layout shown is the same as Figure 3 The upper part of the paper in the plane shown corresponds to this. Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 32 , Figure 34 , Figure 36 , Figure 38 , Figure 40 , Figure 42 , Figure 44 , Figure 46 , Figure 48 , Figure 50 , Figure 52 , Figure 54 , Figure 56 and Figure 58 The sectional views shown are respectively compared with those in Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 33 , Figure 35 , Figure 37 , Figure 39 , Figure 41 , Figure 43 , Figure 45 , Figure 47 , Figure 49 , Figure 51 , Figure 53 , Figure 55 and Figure 57 In the planar layout shown, in relation to Figure 3 The cross-section obtained by taking a section at the same position as the IV-IV line shown corresponds to this.

[0133] First, such as Figure 5 and Figure 6 As shown, a stacked structure is formed on the upper surface of the substrate 20. Specifically, sacrificial layers 51 and 52 are sequentially stacked on the upper surface of the substrate 20. Next, sacrificial layers 53 and 52 are sequentially and repeatedly stacked on the upper surface of sacrificial layer 52. A sacrificial layer 53 is further disposed on the upper surface of the uppermost sacrificial layer 52. In this stacked structure, the position where the sacrificial layer 52 is disposed corresponds to the layer unit LU. Sacrificial layers 51 and 53, for example, contain silicon nitride. Sacrificial layer 52, for example, contains silicon oxide.

[0134] Next, as Figure 7 and Figure 8 As shown, multiple holes H1 are provided in a predetermined area of ​​the laminated structure where multiple conductive pillars WP1, WP2, and DP, and conductive pillar SP (not shown) are to be provided. Specifically, the multiple holes H1 are arranged in a staggered configuration in the P and Q directions when viewed along the Z direction. The multiple holes H1 penetrate sacrificial layers 51, 52, and 53, respectively. The bottom of each of the multiple holes H1 reaches the substrate 20.

[0135] Next, as Figure 9 and Figure 10As shown, multiple holes H1 are filled by a stop film 61 and a sacrificial film 62, respectively. The stop film 61 comprises, for example, amorphous silicon. The sacrificial film 62 comprises, for example, silicon oxide. The portions of the stop film 61 and the sacrificial film 62 that are disposed above the holes H1 (i.e., the upper surface of the sacrificial layer 53) are removed, for example, by CMP (chemical mechanical polishing). Then, a sacrificial layer 54 is disposed on the sacrificial layer 53 and on the upper surfaces of the stop film 61 and the sacrificial film 62 that fill the holes H1. The sacrificial layer 54 comprises, for example, silicon nitride.

[0136] Next, as Figure 11 and Figure 12 As shown, multiple holes H2 are provided in a predetermined region in the laminated structure where multiple conductive pillars DP and conductive pillars SP (not shown) are to be provided. Specifically, the sacrificial film 62 and the stop film 61 provided in the predetermined region where the multiple conductive pillars DP and SP are to be provided are removed. As a result, a sacrificial layer 52 is exposed in each layer inside each of the multiple holes H2. Then, the exposed sacrificial layer 52 in each layer is partially removed through the multiple holes H2. As a result, a groove R1 is formed in each layer that extends concentrically from the center of the multiple holes H2.

[0137] Next, as Figure 13 and Figure 14 As shown, the trenches R1 and multiple holes H2 in each layer are filled with a stop film 63 and a sacrificial film 64, respectively. The stop film 63 contains, for example, silicon nitride. The sacrificial film 64 contains, for example, silicon oxide. For example, the portion of the sacrificial film 64 that is positioned above the holes H2 (i.e., the upper surface of the sacrificial layer 54) is removed by etching back.

[0138] Next, as Figure 15 and Figure 16 As shown, multiple holes H3 are provided in a predetermined area in the laminated structure where multiple conductive pillars WP1 are to be provided. Specifically, the sacrificial film 62 and the barrier film 61 provided in the predetermined area where multiple conductive pillars WP1 are to be provided are removed. As a result, the sacrificial layer 52 is exposed in each layer inside each of the multiple holes H3. Then, the exposed sacrificial layer 52 in each layer is partially removed through the multiple holes H3. As a result, a groove R2 is formed in each layer, extending concentrically from the center of the multiple holes H3. The multiple grooves R2 formed in each layer are connected into one. That is, in the groove R2 of each layer, the barrier film 61 corresponding to all conductive pillars WP2 except those adjacent to conductive pillars DP or SP is fully exposed. In the groove R2 of each layer, the barrier film 61 corresponding to the conductive pillars WP2 adjacent to conductive pillars DP or SP is exposed except for the portion opposite to the conductive pillars DP or SP. In addition, in the groove R2 of each layer, the barrier film 63 corresponding to conductive pillars DP and SP is also partially exposed.

[0139] Next, as Figure 17and Figure 18 As shown, the trenches R2 in each layer are filled with sacrificial films 65 and 66. Sacrificial film 65, for example, comprises amorphous silicon. Sacrificial film 66, for example, comprises silicon oxide. Then, the plurality of holes H3 are filled with a stop film 67 and a sacrificial film 68, respectively. Stop film 67, for example, comprises silicon nitride. Sacrificial film 68, for example, comprises silicon oxide. For example, the portion of sacrificial film 68 positioned above the holes H3 (i.e., the upper surface of sacrificial layer 54) is removed by etching back.

[0140] Next, as Figure 19 and Figure 20 As shown, multiple holes H4 are provided in a predetermined region in the laminated structure where multiple conductive pillars WP2 are to be provided. Specifically, the sacrificial film 62 and the blocking film 61 provided in the predetermined region where multiple conductive pillars WP2 are to be provided are removed. As a result, the sacrificial film 65 is exposed in each layer inside each of the multiple holes H4. Then, the exposed sacrificial film 65 in each layer is partially removed through the multiple holes H4. As a result, a groove R3 is formed in each layer, extending concentrically from the center of the multiple holes H4. The multiple grooves R3 formed in each layer through the multiple holes H4 arranged along the P direction are connected into one. On the other hand, the multiple grooves R3 formed through the multiple holes H4 arranged along the X direction are kept in a state of being disconnected by the sacrificial film 66 corresponding to the conductive pillar WP1 and the sacrificial film 65 remaining when the groove R3 is formed. In the groove R3 of each layer, the exposed portion of the sacrificial film 66 corresponding to the conductive pillar WP1 is divided into two parts by the remaining sacrificial film 65. The exposed portions of the two sacrificial films 66 correspond to the formation sites of the two memory laminated films corresponding to one conductive pillar WP1. Additionally, in the trenches R3 of each layer, the barrier films 63 corresponding to the conductive pillars DP and SP are also partially exposed.

[0141] Next, as Figure 21 and Figure 22 As shown, in each layer, the sacrificial film 66 corresponding to the conductive pillar WP1 is removed via multiple slots R3. Thus, through the space where the sacrificial film 66 has been removed, the multiple slots R3 that were disconnected in each layer are connected into one.

[0142] Next, as Figure 23 and Figure 24 As shown, in each layer, a sacrificial film 65 is selectively grown via trench R3. Thus, the sacrificial film 65 is connected to the stop film 67 corresponding to the two conductive pillars WP1 sandwiching the sacrificial film 65 in the P direction. Therefore, the trench R3 in each layer is divided into multiple sections by the stop film 67 and the sacrificial film 65 corresponding to the conductive pillars WP1. Furthermore, through this selective growth process, a sacrificial film 65 is also provided on the substrate 20 exposed at the bottom of the hole H4.

[0143] Subsequently, in each layer, a semiconductor film 69 is selectively grown on the sacrificial film 65 via multiple trenches R3. Then, an insulating film 70 is formed on the semiconductor film 69 by oxidizing its surface. Furthermore, through this selective growth and oxidation process, the semiconductor film 69 and the insulating film 70 are also stacked on the sacrificial film 65 exposed at the bottom of the hole H4. The semiconductor film 69 may contain, for example, amorphous silicon. The insulating film 70 may contain, for example, silicon oxide.

[0144] After the semiconductor film 69 via the trench R3 is oxidized, the trench R3 of each layer is filled with a sacrificial film 71. The sacrificial film 71 comprises, for example, silicon oxide. Furthermore, the plurality of holes H4 are filled with a stop film 72 and a sacrificial film 73, respectively. The stop film 72 comprises, for example, silicon nitride. The sacrificial film 73 comprises, for example, silicon oxide. For example, the portion of the sacrificial film 73 positioned above the holes H4 (i.e., the upper surface of the sacrificial layer 54) is removed by etching back.

[0145] Next, as Figure 25 and Figure 26 As shown, multiple holes H5 are provided in a predetermined region in the laminated structure where multiple conductive pillars WP1 are to be provided. Specifically, the sacrificial film 68 and the blocking film 67 provided in the predetermined region where multiple conductive pillars WP1 are to be provided are removed. As a result, the sacrificial film 65 is exposed in each layer inside each of the multiple holes H5. Then, the exposed sacrificial film 65 in each layer is removed through the multiple holes H5. As a result, a groove R4 is formed in each layer in the space where the sacrificial film 65 has been removed. The multiple holes H5 arranged along the P direction are connected into one via the multiple grooves R4 formed in each layer. On the other hand, the multiple holes H5 arranged along the X direction are kept disconnected by the sacrificial film 71, etc.

[0146] Next, as Figure 27 and Figure 28 As shown, the trenches R4 of each layer are filled with a sacrificial film 74. The sacrificial film 74 contains, for example, silicon nitride. Then, the surfaces of the semiconductor films 69 exposed in each layer inside the plurality of holes H5 are oxidized.

[0147] After the semiconductor film 69 via the holes H5 is oxidized, the multiple holes H5 are respectively filled by the stop film 75 and the sacrificial film 76. The stop film 75 comprises, for example, amorphous silicon. The sacrificial film 76 comprises, for example, silicon oxide. For example, the portions of the stop film 75 and the sacrificial film 76 that are disposed above the holes H5 (i.e., the upper surface of the sacrificial layer 54) are removed by etching back.

[0148] Next, as Figure 29 and Figure 30As shown, multiple holes H6 are provided in a predetermined region in the laminated structure where multiple conductive pillars WP2 are to be provided. Specifically, the sacrificial film 73 and the blocking film 72 provided in the predetermined region where multiple conductive pillars WP2 are to be provided are removed. As a result, the sacrificial film 71 is exposed in each layer inside each of the multiple holes H6. Then, the exposed sacrificial film 71 in each layer is removed through the multiple holes H6. As a result, a groove R5 is formed in each layer in the space where the sacrificial film 71 has been removed. The multiple holes H6 arranged along the P direction are connected into one via the multiple grooves R5 formed in each layer. On the other hand, the multiple holes H6 arranged along the X direction are kept disconnected by the insulating film 70 and the blocking film 75, etc.

[0149] Next, as Figure 31 and Figure 32 As shown, the trenches R5 in each layer are filled with sacrificial films 77 and 78. Sacrificial film 77, for example, comprises amorphous silicon. Sacrificial film 78, for example, comprises silicon oxide. Then, the plurality of holes H6 are filled with a stop film 79 and a sacrificial film 80, respectively. Stop film 79, for example, comprises silicon nitride. Sacrificial film 80, for example, comprises silicon oxide. For example, the portion of sacrificial film 80 positioned above the holes H6 (i.e., the upper surface of sacrificial layer 54) is removed by etching back.

[0150] Next, as Figure 33 and Figure 34 As shown, multiple holes H7 are provided in a predetermined region in the stacked structure where multiple conductive pillars WP1 are to be provided. Specifically, the sacrificial film 76 provided in the predetermined region where multiple conductive pillars WP1 are to be provided is removed. Then, a portion of the stop film 75 and the sacrificial film 77 in each layer are removed via the multiple holes H7. Furthermore, since the stop film 75 and the sacrificial film 77 contain the same material (e.g., amorphous silicon), they are removed simultaneously by a single etching process. As a result, a groove R6 is formed in each layer, extending concentrically from the center of the multiple holes H7. The multiple grooves R6 formed in each layer via the multiple holes H7 arranged along the P direction are connected into one. On the other hand, the multiple grooves R6 formed via the multiple holes H7 arranged along the X direction are kept disconnected by the sacrificial film 78 corresponding to the conductive pillar WP2 and the sacrificial film 77 remaining when the groove R6 is formed. In the groove R6 of each layer, the exposed portion of the sacrificial film 78 corresponding to the conductive pillar WP2 is divided into two parts by the remaining sacrificial film 77. The exposed portions of the two sacrificial films 77 correspond to the formation sites of the two memory laminates corresponding to one conductive pillar WP2. Additionally, the barrier films 63 corresponding to conductive pillars DP and SP are also partially exposed in the trenches R6 of each layer.

[0151] Next, as Figure 35 and Figure 36As shown, in each layer, the sacrificial film 78 corresponding to the conductive pillar WP2 is removed via multiple slots R6. Thus, through the space where the sacrificial film 78 has been removed, the multiple slots R6 that were disconnected in each layer are connected into one.

[0152] Next, as Figure 37 and Figure 38 As shown, in each layer, a sacrificial film 77 is selectively grown via trench R6. The sacrificial film 77 is then connected to a stop film 79 corresponding to the two conductive pillars WP2 sandwiching the sacrificial film 77 in the P direction. Therefore, the trench R6 in each layer is divided into multiple sections by the stop film 79 and the sacrificial film 77 corresponding to the conductive pillars WP2. Furthermore, through this selective growth process, a sacrificial film 77 is also provided on the substrate 20 exposed at the bottom of the hole H7.

[0153] Subsequently, in each layer, a semiconductor film 81 is selectively grown on the sacrificial film 77 via multiple trenches R6. Furthermore, through this selective growth process, a semiconductor film 81 is also deposited on the sacrificial film 77 exposed at the bottom of the hole H7. The semiconductor film 81 may contain, for example, amorphous silicon.

[0154] After selectively growing the sacrificial film 77 via trench R6, the trenches R6 of each layer are filled with sacrificial film 82. Sacrificial film 82 comprises, for example, silicon oxide. Furthermore, the plurality of holes H7 are filled with stop film 83 and sacrificial film 84, respectively. Stop film 83 comprises, for example, amorphous silicon. Sacrificial film 84 comprises, for example, silicon oxide. For example, portions of the stop film 83 and sacrificial film 84 positioned above the holes H7 (i.e., the upper surface of the sacrificial layer 54) are removed by etching back.

[0155] Next, as Figure 39 and Figure 40 As shown, multiple holes H8 are provided in a predetermined region in the laminated structure where multiple conductive pillars WP2 are to be provided. Specifically, the sacrificial film 80 and the stop film 79 provided in the predetermined region where multiple conductive pillars WP2 are to be provided are removed. As a result, the sacrificial film 77 is exposed in each layer inside each of the multiple holes H8. Then, the exposed sacrificial film 77 in each layer is removed through the multiple holes H8. As a result, a groove R7 is formed in each layer in the space where the sacrificial film 77 has been removed. The multiple holes H8 arranged along the P direction are connected into one via the multiple grooves R7 formed in each layer. On the other hand, the multiple holes H8 arranged along the X direction are kept disconnected by the sacrificial film 82, etc.

[0156] Next, as Figure 41 and Figure 42As shown, the trenches R7 in each layer are filled with a sacrificial film 85. The sacrificial film 85, for example, comprises silicon nitride. Then, the plurality of holes H8 are filled with a stop film 86 and a sacrificial film 87, respectively. The stop film 86, for example, comprises amorphous silicon. The sacrificial film 87, for example, comprises silicon oxide. For example, portions of the stop film 86 and the sacrificial film 87 positioned above the holes H8 (i.e., the upper surface of the sacrificial layer 54) are removed by etching back.

[0157] Next, as Figure 43 and Figure 44 As shown, multiple holes H9 are provided in a predetermined region in the stacked structure where multiple conductive pillars DP and conductive pillars SP (not shown) are to be provided. Specifically, the sacrificial film 64 and the stop film 63 provided in the predetermined region where the multiple conductive pillars DP and SP are to be provided are removed. As a result, the sacrificial layer 52 and the sacrificial film 85 are exposed in each layer inside each of the multiple holes H9. In each layer, a groove R8 is formed that extends concentrically from the center of the multiple holes H9.

[0158] Next, as Figure 45 and Figure 46 As shown, semiconductor films 88 are disposed in the grooves R8 of each layer. The semiconductor film 88 corresponding to the conductive post DP is in contact with the semiconductor film 69 disposed between the conductive post DP and WP1. On the other hand, the semiconductor film 88 corresponding to the conductive post DP is not in contact with the semiconductor film 81 disposed between the conductive post DP and WP2 due to the presence of the insulating film 70. Similarly, the semiconductor film 88 corresponding to the conductive post SP (not shown) is in contact with the semiconductor film 69 disposed between the conductive post DP and WP1. On the other hand, the semiconductor film 88 corresponding to the conductive post SP is not in contact with the semiconductor film 81 disposed between the conductive post DP and WP2 due to the presence of the insulating film 70. The semiconductor film 88 may contain, for example, amorphous silicon.

[0159] Furthermore, the trenches R8 in each layer are not completely filled by the semiconductor film 88. Instead, the trenches R8 and the multiple holes H9 in each layer are filled by the sacrificial film 89. The sacrificial film 89 may contain, for example, silicon oxide. For example, the portion of the sacrificial film 89 that is positioned above the holes H9 (i.e., the upper surface of the sacrificial layer 54) is removed by etching back.

[0160] Next, as Figure 47 and Figure 48As shown, multiple holes H10 are provided in predetermined regions where multiple conductive pillars WP1 and WP2 are to be provided in the stacked structure. Specifically, the sacrificial film 84 and the stop film 83 provided in the predetermined regions where multiple conductive pillars WP1 are to be provided, and the sacrificial film 87 and the stop film 86 provided in the predetermined regions where multiple conductive pillars WP2 are to be provided, are removed. Since the sacrificial films 84 and 87 contain the same material (e.g., silicon oxide), they are removed simultaneously in a single etching process. Since the stop films 83 and 86 contain the same material (e.g., amorphous silicon), they are removed simultaneously in a single etching process. As a result, in each layer inside the multiple holes H10, the semiconductor film 81 and the sacrificial film 82 are exposed. Furthermore, the semiconductor film 69 is not exposed at this stage because it is covered by the insulating film 70.

[0161] Then, the insulating film 70 and the sacrificial film 82 are removed through multiple holes H10. The insulating film 70 and the sacrificial film 82 contain the same material (e.g., silicon oxide), and are therefore removed simultaneously in a single etching process. This creates a trench R9 in each layer, in the space where the insulating film 70 and the sacrificial film 82 have been removed. The semiconductor film 69 is also exposed in the trench R9. All the holes H10 are connected into one via the multiple trenches R9 formed in each layer.

[0162] Next, as Figure 49 and Figure 50 As shown, semiconductor films 69 and 81 are selectively grown in each layer via multiple grooves R9. Thus, the semiconductor film 88 corresponding to the conductive post DP is directly connected to the semiconductor film 81 disposed between conductive posts DP and WP2, either directly or via the semiconductor film 69 disposed between conductive posts DP and WP1. Similarly, the semiconductor film 88 corresponding to the conductive post SP (not shown) is directly connected to the semiconductor film 81 disposed between conductive posts SP and WP2, either directly or via the semiconductor film 69 disposed between conductive posts SP and WP1.

[0163] Furthermore, an insulating film 90 and a semiconductor film 91 are sequentially disposed in the grooves R9 of each layer. The semiconductor film 91 may contain, for example, amorphous silicon. Moreover, the grooves R9 of each layer are not completely filled with the semiconductor film 91. Therefore, around the hole H10 corresponding to the conductive post WP1, two semiconductor films 91 are disposed separately, connecting the semiconductor films 69 arranged along the P direction. Around the hole H10 corresponding to the conductive post WP2, two semiconductor films 91 are disposed separately, connecting the semiconductor films 81 arranged along the P direction. Thus, two independent conductive paths are formed between the semiconductor film 88 corresponding to the conductive post DP and the semiconductor film 88 corresponding to the conductive post SP.

[0164] Next, as Figure 51 and Figure 52As shown, multiple holes H11 are provided in a predetermined region in the stacked structure where multiple conductive pillars DP and conductive pillars SP (not shown) are to be provided. Specifically, the sacrificial film 89 provided in the predetermined region where the multiple conductive pillars DP and SP are to be provided is removed. As a result, a trench R10 is formed in each layer inside each of the multiple holes H11. In the trench R10, the semiconductor film 88 is exposed.

[0165] Next, as Figure 53 and Figure 54 As shown, an insulating film 92 is provided in the grooves R9 and R10 of each layer. Thus, the grooves R10 of each layer are filled with the insulating film 92. However, the grooves R9 of each layer are not completely filled with the insulating film 92.

[0166] Subsequently, semiconductor films 93 are formed in the trenches R9 and the plurality of holes H11 of each layer. Thus, the trenches R9 of each layer are filled with semiconductor films 93. The semiconductor films 93 filling the trenches 9 of each layer are disconnected from each other in the Z direction, for example, by etching back. Furthermore, as described above, the trenches R10 within the holes H11 are filled with insulating films 92. Therefore, the semiconductor films 88 formed within the holes H11 are completely removed by the etching back process. The semiconductor films 93, for example, contain amorphous silicon.

[0167] Next, as Figure 55 and Figure 56 As shown, multiple holes H10 and H11 are filled by the insulating film 94 and the conductive film 95, respectively. For example, the portions of the insulating film 94 and the conductive film 95 that are positioned above the holes H10 and H11 (i.e., the upper surface of the sacrificial layer 54) are removed by back etching.

[0168] Next, as Figure 57 and Figure 58 As shown, sacrificial films 74 and 85 and sacrificial layers 53 and 54 are removed. This forms an air gap AG.

[0169] Next, a process is performed to replace the sacrificial layer 52 remaining on the conductive pillar DP side with a bit line BL, and a process is performed to replace the sacrificial layer 52 remaining on the conductive pillar SP side with a source line SL. Additionally, a process is performed to crystallize amorphous silicon into polycrystalline silicon through heat treatment. Then, contact elements WV and word lines WL are formed. From the above, memory device 3 is formed.

[0170] 2. Effects of the implementation method According to the embodiment, conductive pillars DP, WP1, and WP2 are each surrounded by semiconductor films 88, 91, and 91, respectively. The channel film DCH corresponding to conductive pillar DP, the channel film WCH corresponding to conductive pillar WP1 adjacent to conductive pillar DP in the P direction, and the channel film WCH corresponding to conductive pillar WP2 adjacent to conductive pillar DP in the Q direction are electrically connected by a current path film CPL, which is a continuous film. Thus, two parallel current paths are formed from one conductive pillar DP. Therefore, columns of two series-connected memory cell transistors MT can be arranged side-by-side in a NAND string NS. Therefore, the integration density of the memory device 3 can be improved.

[0171] Furthermore, in each layer, two charge storage films (CSLs) are arranged separately, partially surrounding a conductive pillar (WP1). In each layer, two charge storage films (CSLs) are arranged separately, partially surrounding a conductive pillar (WP2). Additionally, two current path films (CPLs) disposed between two adjacent conductive pillars (WP1) are arranged separately and connected to different channel films (WCH). Similarly, two current path films (CPLs) disposed between two adjacent conductive pillars (WP2) are arranged separately and connected to different channel films (WCH). Thus, for a single conductive pillar (WP1) or (WP2), two memory cell transistors (MTs) can be formed within the same layer. Therefore, the integration density of the memory device 3 can be improved.

[0172] Furthermore, an air gap AG is provided between the two current path films CPL that connect two adjacent conductive pillars WP1 or two adjacent conductive pillars WP2. This suppresses interference between memory cell transistors MT disposed in the same layer.

[0173] In addition, an air gap AG is provided between adjacent layers. This can suppress interference between memory cell transistors MT disposed in one layer and memory cell transistors MT disposed in adjacent layers.

[0174] 3. Variations, etc. Various modifications can be applied to the above-described embodiments.

[0175] For example, in the above embodiment, the case where the NAND string NS has a straight line shape extending along the P direction has been described, but it is not limited to this. For example, the NAND string NS may also have a zigzag shape that alternately extends in the P direction and the Q direction.

[0176] Figure 59 This is a top view showing an example of the planar layout of the memory cell array provided by the modified memory device. Figure 59 Compared with the implementation method Figure 3 correspond.

[0177] like Figure 59 As shown, seven conductive pillars DP, WP1, WP2, WP1, WP2, WP1, and SP are arranged sequentially in the P direction. These seven conductive pillars DP, WP2, WP1, WP2, WP1, WP2, and SP are arranged sequentially in the P direction, adjacent to each other in the X direction. Furthermore, groups of seven conductive pillars DP, WP1, WP2, WP1, WP2, WP1, and SP arranged in the P direction alternate with groups of seven conductive pillars DP, WP2, WP1, WP2, WP1, WP2, and SP arranged in the P direction in the X direction.

[0178] When viewed from the Q direction, the above configuration is also represented as follows: The seven conductive pillars DP, WP1, WP1, WP2, WP2, WP1, and SP are arranged sequentially in the Q direction. The seven conductive pillars DP, WP2, WP2, WP1, WP1, WP2, and SP are arranged sequentially in the Q direction, adjacent to the seven conductive pillars DP, WP1, WP1, WP2, WP2, WP1, and SP arranged sequentially in the Q direction in the X direction. Furthermore, the groups of seven conductive pillars DP, WP1, WP1, WP2, WP2, WP1, and SP arranged in the Q direction alternate with the groups of seven conductive pillars DP, WP2, WP2, WP1, WP1, WP2, and SP arranged in the Q direction in the X direction.

[0179] With the above structure, a NAND string NS can be implemented as follows: two sets of memory cell transistors MT are connected in parallel between a set of select transistors ST1 and ST2. These two sets of memory cell transistors MT are five memory cell transistors MT that are alternately connected in series in the P direction and Q direction. Therefore, in the modified example, similar to the implementation method, it is possible to improve the integration density of the memory device 3 and suppress inter-cell interference.

[0180] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A storage device, characterized in that, have: The first conductive post, the second conductive post, and the third conductive post extend along the first direction, respectively; A first semiconductor film surrounds the first conductive pillar at a first position in the first direction; A second semiconductor film partially surrounds the second conductive pillar at the first location; A third semiconductor film partially surrounds the third conductive pillar at the first location; The fourth semiconductor film is connected to the first end of the first semiconductor film, the first end of the second semiconductor film, and the first end of the third semiconductor film, respectively. A first charge storage film is disposed between the second conductive post and the second semiconductor film; as well as A second charge storage film is disposed between the third conductive post and the third semiconductor film.

2. The storage device according to claim 1, characterized in that, It also has: The fourth conductive post extends along the first direction; A fifth semiconductor film partially surrounds the fourth conductive pillar at the first location; The sixth semiconductor film is connected to the second end of the first semiconductor film and the first end of the fifth semiconductor film, respectively; as well as A third charge storage film is disposed between the fourth conductive post and the fifth semiconductor film.

3. The storage device according to claim 2, characterized in that, It also has: The fifth conductive post extends along the first direction; A seventh semiconductor film partially surrounds the fifth conductive pillar at the first location; The eighth semiconductor film is connected to the second end of the second semiconductor film and the first end of the seventh semiconductor film, respectively; as well as A fourth charge storage film is disposed between the fifth conductive post and the seventh semiconductor film.

4. The storage device according to claim 3, characterized in that, It also has: An insulating film disposed between the second semiconductor film and the third semiconductor film, between the fifth semiconductor film and the seventh semiconductor film, and between the sixth semiconductor film and the eighth semiconductor film.

5. The storage device according to claim 2, characterized in that, It also has: The sixth conductive post extends along the first direction; A ninth semiconductor film surrounds the sixth conductive pillar at the first position; A tenth semiconductor film partially surrounds the second conductive post at the first position in a manner separate from the second semiconductor film; The eleventh semiconductor film is connected to the first ends of the ninth semiconductor film and the tenth semiconductor film, respectively; as well as A fifth charge storage film is disposed between the second conductive post and the tenth semiconductor film.

6. The storage device according to claim 5, characterized in that, It also has: A twelfth semiconductor film partially surrounds the fourth conductive post at the first position in a manner that is separate from the fifth semiconductor film; The thirteenth semiconductor film is connected to the second end of the tenth semiconductor film and the first end of the twelfth semiconductor film, respectively. as well as The sixth charge storage film is disposed between the fourth conductive post and the twelfth semiconductor film in a manner that is separate from the third charge storage film.

7. The storage device according to claim 6, characterized in that, An air gap exists between the sixth semiconductor film and the thirteenth semiconductor film.

8. The storage device according to claim 6, characterized in that, It also has: The seventh conductive post extends along the first direction; The fourteenth semiconductor film partially surrounds the seventh conductive pillar at the first location; as well as A sixth charge storage film is disposed between the seventh conductive post and the twelfth semiconductor film; The eleventh semiconductor film is connected to the first end of the ninth semiconductor film, the tenth semiconductor film, and the fourteenth semiconductor film, respectively.

9. The storage device according to claim 1, characterized in that, It also has: The fifteenth semiconductor film surrounds the first conductive pillar at a second position different from the first position in the first direction; The sixteenth semiconductor film partially surrounds the second conductive pillar at the second location; The seventeenth semiconductor film partially surrounds the third conductive pillar at the second location; The eighteenth semiconductor film is connected to the first end of the fifteenth semiconductor film, the sixteenth semiconductor film, and the seventeenth semiconductor film, respectively; A seventh charge storage film is disposed between the second conductive pillar and the sixteenth semiconductor film; as well as The eighth charge storage film is disposed between the third conductive post and the seventeenth semiconductor film.

10. The storage device according to claim 9, characterized in that, There is an air gap between the first position and the second position.

11. The storage device according to claim 1, characterized in that, The first conductive post and the second conductive post are arranged along a second direction in a plane intersecting the first direction. The first conductive post and the third conductive post are arranged along a third direction that intersects the second direction in the plane.

12. The storage device according to claim 3, characterized in that, The first conductive post, the second conductive post, and the fourth conductive post are arranged along a second direction in a plane intersecting the first direction. The first conductive post, the third conductive post, and the fifth conductive post are arranged along a third direction that intersects the second direction within the plane.

13. The storage device according to claim 3, characterized in that, The first conductive post and the second conductive post are arranged along a second direction in a plane intersecting the first direction. The second conductive post and the fourth conductive post are arranged along a third direction that intersects the second direction within the plane. The first conductive post, the third conductive post, and the fifth conductive post are arranged along the third direction.

14. The storage device according to claim 1, characterized in that, It also has: A first conductive layer, electrically connected to the first conductive pillar; and The second conductive layer is electrically connected to the second conductive pillar and electrically insulated from the first conductive layer.

15. The storage device according to claim 1, characterized in that, The first charge storage film and the second charge storage film comprise polycrystalline silicon.

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