Semiconductor device and method of controlling the same

Abstract

Embodiments of the present application provide a semiconductor device and a control method thereof. The semiconductor device includes a semiconductor layer, a plurality of bit lines and a plurality of memory structures. The plurality of bit lines are located on the semiconductor layer. The memory structure includes a source region, a drain region, a common channel region and two sets of gate structures. The source region, the drain region and the common channel region are located in the semiconductor layer. The common channel region is connected between the source region and the drain region. The two sets of gate structures are located on the common channel region. One set of gate structures includes two sub-gate structures and a common gate. The common gate is located between the two sub-gate structures. The sub-gate structure includes a floating gate and a control gate on the floating gate. The source region and the drain region are connected to two bit lines through conductive connection structures respectively. In this way, the two sets of gate structures of the memory structure share one common channel region, which is conducive to increasing the total number of memory cells in the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its control method. Background Technology

[0002] Split-gate memory is a non-volatile flash memory device that uses a floating gate as the storage layer. This type of memory has gained increasing importance in the memory field due to its advantages such as low cost, low power consumption, high reliability, and fast access speed, and is widely used in consumer electronics. Currently, storage density is a key performance indicator for this type of memory, and how to improve storage density is a technical problem that needs to be solved. Summary of the Invention

[0003] This application provides a semiconductor device and its control method, which helps to improve the storage density of the semiconductor device and at least partially solves the above-mentioned technical problems.

[0004] To achieve the above objectives, according to a first aspect of the embodiments of this application, a semiconductor device is provided. The semiconductor device includes a semiconductor layer, multiple bit lines, and multiple memory structures. The multiple bit lines are located on the semiconductor layer. One of the memory structures includes a source region, a drain region, a common channel region, and two sets of gate structures. The source region, the drain region, and the common channel region are located within the semiconductor layer. The common channel region connects the source region and the drain region. The two sets of gate structures are located on the common channel region. One set of gate structures includes two sub-gate structures and a common gate. One common gate is located between the two sub-gate structures, and one sub-gate structure includes a floating gate and a control gate on the floating gate. The source region and drain region of one of the memory structures are respectively connected to the two bit lines through conductive connection structures.

[0005] In the semiconductor device of this application embodiment, two sets of gate structures share a common channel region, and the source region and drain region of one of the memory structures are respectively connected to two bit lines through conductive connection structures. Thus, the total number of conductive connection structures required for the memory structure is smaller, reducing the area required for laying out the conductive connection structures, thereby providing more space for the memory structure and improving the storage density of the semiconductor device.

[0006] According to a second aspect of this application, embodiments of this application provide a control method for a semiconductor device. The semiconductor device includes multiple memory structures. One memory structure includes one or more pairs of memory cells. The one or more pairs of memory cells in one memory structure share a common channel region. One pair of memory cells includes two memory cells and a common gate. The two memory cells share the common gate, and one memory cell includes a floating gate and a control gate spaced apart. The control method includes: in response to a programming instruction for a selected memory cell in one memory structure, applying a programming control gate signal to the control gate of the selected memory cell, and applying an on control gate signal to the control gates of one or more unselected memory cells in the memory structure, wherein the programming control gate signal reaches a first target value at a first time, and the on control gate signal reaches a second target value at a second time, the first time being earlier than the second time.

[0007] In the semiconductor device control method of this application embodiment, when a programming instruction is executed on a memory cell in a memory structure, a programming control gate signal is applied to the control gate of the selected memory cell, and a conduction control gate signal is applied to the control gate of one or more unselected memory cells in the memory structure. The programming control gate signal reaches a first target value at a first moment. The conduction control gate signal reaches a second target value at a second moment. The first moment is earlier than the second moment. Thus, the time when the conduction control gate signal reaches the second target value is later than the time when the programming control gate signal reaches the first target value, reducing the risk that the conduction control gate signal loaded on the control gate of one or more unselected memory cells in the memory structure is coupled to a higher voltage, and improving the problem of uneven threshold voltage distribution of memory cells caused by high-voltage programming coupled to one or more unselected memory cells. Attached Figure Description

[0008] Figure 1 A block diagram of a semiconductor device provided in an embodiment of this application;

[0009] Figure 2 A schematic diagram of a planar structure of a memory array for a semiconductor device provided in an embodiment of this application;

[0010] Figure 3 Provided for the embodiments of this application Figure 2 The circuit diagram of the storage array shown is shown.

[0011] Figure 4 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of a pair of storage cells.

[0012] Figure 5 A schematic diagram of another planar structure of a memory array for a semiconductor device provided in an embodiment of this application;

[0013] Figure 6 Provided for the embodiments of this application Figure 5 The circuit diagram of the storage array shown is shown.

[0014] Figure 7 A schematic diagram of a planar structure of another memory array for a semiconductor device provided in an embodiment of this application;

[0015] Figure 8 Provided for the embodiments of this application Figure 7 The circuit diagram of the storage array shown is shown.

[0016] Figure 9 For along Figure 7 A partial cross-sectional view of the storage array shown.

[0017] Figure 10 A schematic diagram of another planar structure of a memory array for a semiconductor device provided in this application embodiment;

[0018] Figure 11 Provided for the embodiments of this application Figure 10 The circuit diagram of the storage array shown is shown.

[0019] Figure 12 A schematic diagram of a planar structure of another memory array for a semiconductor device provided in an embodiment of this application;

[0020] Figure 13 Provided for the embodiments of this application Figure 12 The circuit diagram of the storage array shown is shown.

[0021] Figure 14 A schematic diagram of a planar structure of another memory array for a semiconductor device provided in an embodiment of this application;

[0022] Figure 15 Provided for the embodiments of this application Figure 14 The circuit diagram of the storage array shown is shown.

[0023] Figure 16 The signal timing diagram for programming operations of the memory array provided in the embodiments of this application is shown.

[0024] Explanation of reference numerals in the attached diagram:

[0025] 100. Semiconductor devices;

[0026] 200. Storage array; 10. Storage structure; 10A. Storage string; 10B. Storage structure row; 101. Storage cell pair; 102. Storage cell;

[0027] 103A, Gate structure; 103, Divided gate structure; 104, Control gate; 105, Floating gate; 106, Common gate;

[0028] 1071, Source; 1072, Drain; 1081, Source Region; 1082, Drain Region; 109, Common Channel Region;

[0029] 110. Storage unit to row; 111. First storage unit to row; 112. First storage unit to row;

[0030] 11. Semiconductor layer; AA, AA0~AA10, active region;

[0031] 21. First conductive layer;

[0032] BL, BLj~BL(j+8), BLm1~BL(m1+12), bit lines;

[0033] 22. Second conductive layer;

[0034] 231, 231A1~231A4, control signal line group;

[0035] Cg0, first control signal line; Cg1, second control signal line; WL, third control signal line;

[0036] 232, First control signal line subgroup; OCg0, First gate control signal line; OCg1, Second gate control signal line; OWL, Third gate control signal line;

[0037] 233, Second control signal line subgroup; ECg2, Fourth gate control signal line; ECg3, Fifth gate control signal line; EWL, Sixth gate control signal line;

[0038] 24. Conductive connection structure; 241. First conductive connection structure; 242. Second conductive connection structure; 243. Third conductive connection structure; 244. Common conductive connection structure;

[0039] 40. Peripheral circuits; 41. Row drive circuits; 42. Column drive circuits;

[0040] X, first direction; Y, second direction; W, third direction. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0042] Figure 1 A block diagram of a semiconductor device provided in an embodiment of this application.

[0043] like Figure 1 As shown, the semiconductor device 100 includes a memory array 200 and peripheral circuitry 40. The peripheral circuitry 40 includes a row drive circuit 41 and a column drive circuit 42. The row drive circuit 41 is configured to apply a row drive signal to the memory array 200, and the column drive circuit 42 is configured to apply a column drive signal to the memory array 200, thereby enabling at least one of a read operation, an erase operation, and a programmable operation on the memory array 200.

[0044] Figure 2 This is a schematic diagram of a planar structure of a memory array for a semiconductor device provided in an embodiment of this application. Figure 3 Provided for the embodiments of this application Figure 2 The circuit diagram of the storage array shown is shown. Figure 4 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of a pair of storage cells.

[0045] like Figure 2 and Figure 3 As shown, the storage array 200 includes multiple active regions AA, multiple bit lines BL, and multiple control signal line groups 231.

[0046] like Figure 2 As shown, adjacent active regions AA are isolated by an isolation zone (not shown in the figure). For example, multiple active regions AA include active regions AA0 to AA8 that are spaced apart along the first direction X.

[0047] Multiple active regions AA are equipped with multiple storage structures 10. The multiple storage structures 10 are arranged in an array along a first direction X and a second direction Y, with the first direction X intersecting the second direction Y. Each storage structure 10 can be a storage cell pair 101.

[0048] Multiple storage cell pairs 101 constitute multiple storage cell pair rows 110. Along a first direction X, a storage cell pair row 110 includes at least two storage cell pairs 101. Along a second direction Y, the multiple storage cell pair rows 110 are spaced apart.

[0049] At least two memory cell pairs 101 are connected in series along a third direction W to form a memory string 10A. The third direction W intersects with the first direction X. The third direction W may intersect with or be parallel to the second direction Y. For example, the third direction W may intersect with the second direction Y. Multiple memory strings 10A are spaced apart along the first direction X. For two memory cell pairs 101 connected in series, the source 1071 of one memory cell pair 101 is the drain 1072 of the other memory cell pair 101.

[0050] From the perspective of circuit structure, such as Figure 3 As shown, a memory cell pair 101 includes two memory cells 102, a common gate 106, a source 1071, and a drain 1072. The two memory cells 102 share a common gate 106. A memory cell 102 may include a gate-splitting structure 103, which includes a control gate 104 and a floating gate 105, meaning that a memory cell 102 can be a floating-gate metal-oxide-semiconductor field-effect transistor.

[0051] From the perspective of membrane structure, such as Figure 4 As shown, a memory cell pair 101 includes a source region 1081, a drain region 1082, a common channel region 109, a common gate 106, and two gate structures 103. The common channel region 109, source region 1081, and drain region 1082 are all located within an active region AA, with the common channel region 109 connecting the source region 1081 and the drain region 1082. The two gate structures 103 are located on one side of the common channel region 109, and the common gate 106 is located between the two gate structures 103. The two gate structures 103 and the common gate 106 are isolated from the active region AA by an insulating layer. The two gate structures 103 and the common gate 106 are also isolated from each other by an insulating layer. The gate structure 103 includes a floating gate 105 and a control gate 104 located on the floating gate 105.

[0052] It should be noted that the source region 1081 in the film structure corresponds to the source 1071 in the circuit structure, and the drain region 1082 in the film structure corresponds to the drain 1072 in the circuit structure.

[0053] like Figure 2 and Figure 3 As shown, multiple control signal line groups 231 are spaced apart along the second direction Y. Each control signal line group 231 outputs the row drive signal received from the row drive circuit 41 to a storage cell pair row 110 to select a storage cell pair row 110 from the multiple storage cell pairs 102 rows.

[0054] A control signal line group 231 includes a first control signal line Cg0, a second control signal line Cg1, and a third control signal line WL. The third control signal line WL is located between the first control signal line Cg0 and the second control signal line Cg1. For each control signal line group 231, the first control signal line Cg0 and the second control signal line Cg1 are respectively connected to the two control gates 104 of a memory cell pair 101, and the third control signal line WL is connected to the common gate 106 of the memory cell pair 101. Therefore, the row drive circuit 41 applies corresponding control signals to the two control gates of each memory cell pair 101 through the first control signal line Cg0 and the second control signal line Cg1, and applies a corresponding control signal to the common gate 106 of each memory cell pair 101 through the third control signal line WL.

[0055] For example, the plurality of control signal groups 231 include control signal line group 231A1, control signal line group 231A2, control signal line group 231A3 and control signal line group 231A4 arranged sequentially along the second direction Y.

[0056] The control signal line group 231A1 includes a first control signal line Cg0. <0> Second control signal line Cg1 <0> and the third control signal line WL <0> Third control signal line WL <0> Located on the first control signal line Cg0 <0> With the second control signal line Cg1 <0> between.

[0057] The control signal line group 231A2 includes a first control signal line Cg0. <1> Second control signal line Cg1 <1> and the third control signal line WL <1> Third control signal line WL <1> Located on the first control signal line Cg0 <1> With the second control signal line Cg1 <1> Between. Second control signal line Cg1 <1> With the second control signal line Cg1 <0> Adjacent settings.

[0058] The control signal line group 231A3 includes a first control signal line Cg0. <2> Second control signal line Cg1 <2> and the third control signal line WL <2> Third control signal line WL <2> Located on the first control signal line Cg0 <2> With the second control signal line Cg1 <2> Between. First control signal line Cg0 <2> With the first control signal line Cg0 <1> Adjacent settings.

[0059] The control signal line group 231A4 includes a first control signal line Cg0. <3> Second control signal line Cg1 <3> and the third control signal line WL <3> Third control signal line WL <3> Located on the first control signal line Cg0 <3> With the second control signal line Cg1 <3> Between. Second control signal line Cg1 <3> With the second control signal line Cg1 <2> Adjacent settings.

[0060] like Figure 2 and Figure 3 As shown, the source 1071 and drain 1072 of each memory cell pair 101 are connected to two bit lines BL through conductive connection structure 24. The column drive circuit 42 loads a column drive signal to each memory cell pair 101 through the two bit lines BL to select one memory cell pair 101 from at least two memory cell pairs 101 in a memory cell pair row 110.

[0061] In some embodiments, such as Figure 2 and Figure 3 As shown, multiple bit lines BL include bit lines BLj to BL(j+8) arranged sequentially. A memory cell pair row 110 includes an adjacent memory cell pair 101A and a memory cell pair 101B. The source region 1081 and drain region 1082 of the memory cell pair 101A are connected to the bit line BLj and the (j+1) bit line BL(j+1) respectively through two conductive connection structures 24. The source region 1081 and drain region 1082 of the memory cell pair 101B are connected to the bit line BL(j+2) and the bit line BL(j+3) respectively through two conductive connection structures 24. Thus, for two adjacent memory cell pairs 101 in row 110, either of the two bit lines BL connecting the source 1071 and drain 1072 of one memory cell pair 101 is different from the other two bit lines BL connecting the source 1071 and drain 1072 of the other memory cell 102; that is, adjacent memory cell pairs 101 do not share bit lines BL. Therefore, when controlling either of the two adjacent memory cell pairs 101 in row 110, applying voltage to the bit lines BL is simpler, simplifying the control method of the memory array 200.

[0062] In some embodiments, when the bit line BL intersects with the active region AA, each conductive connection structure 24 may contact one of the source region 1081 and the drain region 1082, as well as the bit line BL. In some embodiments, the conductive connection structure 24 may include a conductive contact.

[0063] In some embodiments, such as Figure 2 and Figure 4 As shown, when the bit line BL does not overlap with the active region AA, the conductive connection structure 24 may include a first conductive connection structure 241, a second conductive connection structure 242, and a third conductive connection structure 243. The second conductive connection structure 242 intersects with the active region AA. The first conductive connection structure 241 connects one of the source region 1081 and the drain region 1082 to the second conductive connection structure 242. The third conductive connection structure 243 connects the second conductive connection structure 242 to the bit line BL.

[0064] In some embodiments, such as Figure 2 As shown, the second conductive connection structure 242 can be a conductive bridge, which extends to overlap with the bit line BL and the active region AA. In some embodiments, such as Figure 2 As shown, the second conductive connection structure 242 can be located between two adjacent control signal groups 231.

[0065] In some embodiments, both the first conductive connection structure 241 and the third conductive connection structure 243 may be conductive contacts.

[0066] Therefore, for Figure 2 and Figure 3 The storage array 200 shown simplifies the control method of the storage array 200 by allowing adjacent storage pairs in row 110 to not share the bit line BL.

[0067] Figure 5 This is a schematic diagram of another planar structure of a memory array for a semiconductor device provided in an embodiment of this application. Figure 6 Provided for the embodiments of this application Figure 5 The circuit diagram of the storage array shown is shown.

[0068] Figure 5 and Figure 6 The storage array 200 shown is Figure 2 and Figure 3 The storage array 200 shown is basically similar, and the similarities will not be repeated. The following mainly focuses on... Figure 5 and Figure 6 The differences between them will be described.

[0069] for Figure 5 and Figure 6The storage array 200 shown includes multiple bit lines BL, including the j-th bit line BLj to the (j+8)-th bit line BL(j+8) arranged sequentially. A storage cell pair row 110 includes an adjacent i-th storage cell pair 101A and an (i+1)-th storage cell pair 101B. The source region 1081 and drain region 1082 of the i-th storage cell pair 101A are connected to the j-th bit line BLj and the (j+1)-th bit line BL(j+1) respectively through two conductive connection structures 24. The source region 1081 and drain region 1082 of the (i+1)-th storage cell pair 101B are connected to the (j+1)-th bit line BL(j+1) and the (j+2)-th bit line BL(j+2) respectively through two conductive connection structures 24. Thus, for two adjacent memory cell pairs 101 in a row 110 of a memory cell pair, the two adjacent memory cell pairs 101 share the same bit line BL for connection, reducing the number of bit lines BL connecting the two adjacent memory cell pairs 101, thereby saving the space occupied by the bit lines BL connecting the two adjacent memory cell pairs 101. Furthermore, since the saved space can be allocated to the memory cell pairs 101, it is beneficial to increase the storage density of the semiconductor device 100.

[0070] and Figure 2 and Figure 3 As shown, for a storage cell pair 101 in row 110, the two adjacent storage cell pairs are compared with the four bit lines BL respectively. Figure 5 and Figure 6 In this memory cell, the two adjacent memory cells in row 110 are connected to each other via three bit lines BL. Therefore, Figure 5 and Figure 6 As shown, the number of bit lines BL connecting two adjacent memory cell pairs 101 in row 110 is reduced, thus reducing the space required to lay out the bit lines BL. The reduced space for laying out the bit lines BL provides more space for laying out the memory cell pairs 101, which is beneficial for increasing the storage density of the semiconductor device 100.

[0071] Figure 7 This is a schematic diagram of a planar structure of another type of memory array for a semiconductor device provided in an embodiment of this application. Figure 8 Provided for the embodiments of this application Figure 7 The circuit diagram of the storage array shown is shown. Figure 9 For along Figure 7 A partial cross-sectional view of the storage array is shown.

[0072] like Figure 7 and Figure 9 As shown, the semiconductor device 100 includes a semiconductor layer 11. The semiconductor layer 11 includes a plurality of active regions AA spaced apart, with adjacent active regions AA spaced apart. Exemplarily, the plurality of active regions AA includes active regions AA0 to AA10 arranged sequentially.

[0073] Multiple active regions AA are provided with multiple memory structures 10. Each memory structure 10 includes a source region 1081, a drain region 1082, a common channel region 109, and two sets of gate structures 103A. The source region 1081, the drain region 1082, and the common channel region 109 are located in the active regions AA. The common channel region 109 is connected between the source region 1081 and the drain region 1082.

[0074] Two sets of gate structures 103A are located on and insulated from the common channel region 109. Each set of gate structures 103A includes two sub-gate structures 103 and a common gate 106. The common gate 106 is located between the two sub-gate structures 103, and each sub-gate structure 103 includes a floating gate 105 and a control gate on the floating gate 105.

[0075] Since the memory structure 10 includes four gate structures 103, and one gate structure 103 and the common channel region 109 constitute part of a memory cell 102, the memory structure 10 includes four memory cells 102. Furthermore, a set of gate structures 103A and the common channel region 109 constitute part of a memory cell pair 101, therefore a memory cell pair 101 includes two memory cells 102.

[0076] When a large amount of charge is stored in the floating gate 105 of the storage cell 102, the storage cell 102 is "0 cell" and is in a programmed state. When a small amount of charge is stored in the floating gate 105 of the storage cell 102 or no charge is stored, the storage cell 102 is "1 cell" and is in an unprogrammed state.

[0077] The semiconductor device 100 also includes a first conductive layer 21. The first conductive layer 21 is located on one side of the semiconductor layer 11, and an insulating layer is disposed between the first conductive layer 21 and the semiconductor layer 11. The first conductive layer includes multiple bit lines BL. The source region 1081 and the drain region 1082 of a memory structure 10 are respectively connected to the two bit lines BL through conductive connection structures 24.

[0078] In some embodiments of the semiconductor device 100 of this application, a memory structure 10 includes four memory cells 102, and the source region 1081 and drain region 1082 of the memory structure 10 are respectively connected to two bit lines BL through conductive connection structures 24. Thus, the total number of conductive connection structures 24 required for the memory structure 10 is small, reducing the area required to arrange the conductive connection structures 24, thereby providing more space for the memory structure 10 and improving the memory density of the semiconductor device 100.

[0079] Furthermore, if all four memory cells 102 of memory structure 10 are "1 cell", then the threshold voltages of all four memory cells 102 are negative. In this case, the read current during erase verification of memory structure 10 is very large. However, if even one of the four memory cells 102 of memory structure 10 is "0 cell", the read current during erase verification will decrease. For memory structure 10, an erase operation needs to be performed whenever a "0 cell" appears. Therefore, when erasing verification of memory structure 10 is required, it is only necessary to determine whether the read current decreases, without needing to determine which memory cell 102 of memory structure 10 is "0 cell", to determine whether to erase memory structure 10. Therefore, the four memory cells 102 sharing a common channel region 109 helps to accelerate the erase verification speed of memory structure 10.

[0080] It should be noted that, for Figure 3 and Figure 5 In the storage array 200 shown, four storage cells 102 of adjacent storage cell pairs 101 in storage string 10A are connected to multiple corresponding bit lines BL via three conductive connection structures 24. However, in the storage array 200 of this embodiment, the four storage cells 102 of storage structure 10 are connected to two bit lines BL via two conductive connection structures 24. Therefore, although there are still four storage cells 102, compared to... Figure 3 and Figure 5 The storage array shown. Figures 7 to 9 The design of the storage structure 10 shown can omit one or two conductive connection structures 24, thereby saving the area required to lay out the conductive connection structures 24, providing more area for the storage structure 10, which is beneficial to improving the storage density of the semiconductor device 100.

[0081] like Figure 7 and Figure 8 As shown, the plurality of storage structures 10 include a plurality of storage structure rows 10B, each storage structure row 10B including at least two storage structures 10 arranged side-by-side along a first direction X. The plurality of storage structure rows 10B are arranged along a second direction Y. The first direction X intersects the second direction Y. Each storage structure row 10B includes a first storage cell pair row 111 and a second storage cell pair row 112. Each of the first storage cell pair row 111 and the second storage cell pair row 112 includes at least two storage cell pairs 101 arranged side-by-side along the first direction X. Furthermore, along a third direction W, the plurality of storage structures 10 are connected in series to form a storage string 10A. The third direction W intersects the first direction X. The third direction W is parallel to or intersects the second direction Y. Exemplarily, the third direction W intersects the second direction Y.

[0082] In some embodiments, such as Figure 7 and Figure 8 As shown, the multiple bit lines BL include the m1th bit line BLm1 to the (m1+11th)th bit line BL(m1+11) arranged sequentially. Figure 9 As shown, a memory structure row 10B includes an adjacent n1th memory structure 10a1 and an (n1+1)th memory structure 10a2. The source region 1081 and drain region 1082 of the n1th memory structure 10a1 are connected to the m1th bit line BLm1 and the (m1+1)th bit line BL(m1+1) respectively through conductive connection structure 24. Similarly, the source region 1081 and drain region 1082 of the (n1+1)th memory structure 10a2 are connected to the (m1+2)th bit line BL and the (m1+3)th bit line BL respectively through conductive connection structure 24. Thus, for two adjacent memory structures 10 in a memory structure row 10B, the two bit lines BL connected to one memory structure 10 are different from the two bit lines BL connected to the other memory structure 10, that is, the two adjacent memory structures 10 do not share bit lines BL. Therefore, when controlling any one of two adjacent memory structures 10 in row 10B, it is simpler to apply voltage to the bit line BL, thus simplifying the control method of the memory array.

[0083] In some embodiments, multiple bit lines BL can be parallel to and staggered with multiple active regions AA. For example, multiple bit lines BL extend along the second direction Y and are spaced apart along the first direction X.

[0084] In some embodiments, multiple bit lines BL can intersect with multiple active regions AA. In this case, the bit lines BL can be directly connected to the source region 1081 and the drain region 1082 of the active layer through conductive connection structures 24 such as contacts.

[0085] like Figure 9 As shown, the semiconductor device 100 further includes a second conductive layer 22. The second conductive layer 22 is located on one side of the semiconductor layer 11 and is insulated from the first conductive layer 21 and the semiconductor layer 11. The second conductive layer 22 includes a plurality of control signal lines. The plurality of control signal lines extend along a first direction X and are located on the semiconductor layer 11, and each control signal line connects to at least two memory structures 10 in a memory structure row 10B.

[0086] In some embodiments, the multiple control signal lines are divided into multiple control signal line groups 231. The multiple control signal line groups 231 are arranged along the second direction Y. A control signal line group 231 includes a first control signal line subgroup 232 and a second control signal line subgroup 233.

[0087] The first control signal line subgroup 232 includes a first gate control signal line OCg0, a second gate control signal line OCg1, and a third gate control signal line OWL. The third gate control signal line OWL is located between the first gate control signal line OCg0 and the second gate control signal line OCg1. The first gate control signal line OCg0 and the second gate control signal line OCg1 are respectively connected to the two control gates 104 of each memory cell pair 101 in the first memory cell pair row 111. The third gate control signal line OWL is connected to the common gate 106 of each memory cell pair 101 in the first memory cell pair row 111.

[0088] The second control signal line subgroup 233 includes a fourth gate control signal line ECg2, a fifth gate control signal line ECg3, and a sixth gate control signal line EWL. The sixth gate control signal line EWL is located between the fourth gate control signal line ECg2 and the fifth gate control signal line ECg3. The fourth gate control signal line ECg2 and the fifth gate control signal line ECg3 are respectively connected to the two control gates 104 of each memory cell pair 101 in the second memory cell pair row 112. The sixth gate control signal line EWL is connected to the common gate 106 of each memory cell pair 101 in the second memory cell pair row 112.

[0089] For example, such as Figure 7 As shown, the multiple control signal line groups 231 include control signal line group 231B1, control signal line group 231B2 and control signal line group 231B3 arranged in sequence.

[0090] The control signal line group 231B1 includes the first gate control signal line OCg0 arranged sequentially. <0> Third gate control signal line OWL <0> Second gate control signal line OCg1 <0> Fourth gate control signal line ECg2 <0> Sixth gate control signal line EWL <0> and the fifth gate control signal line ECg3 <0> .

[0091] The control signal line group 231B2 includes a first gate control signal line OCg0 arranged sequentially. <1> Third gate control signal line OWL <1> Second gate control signal line OCg1 <1> Fourth gate control signal line ECg2 <1> Sixth gate control signal line EWL <1> and the fifth gate control signal line ECg3 <1> .

[0092] The control signal line group 231B2 includes a first gate control signal line OCg0 arranged sequentially. <2> Third gate control signal line OWL <2> Second gate control signal line OCg1 <2> Fourth gate control signal line ECg2 <2> Sixth gate control signal line EWL <2> and the fifth gate control signal line ECg3 <2> .

[0093] In some embodiments, such as Figure 7 and Figure 9 As shown, the conductive connection structure 24 includes a first conductive connection structure 241, a second conductive connection structure 242, and a third conductive connection structure 243. The second conductive connection structure 242 intersects with the active region AA. The first conductive connection structure 241 connects one of the source region 1081 and the drain region 1082 to the second conductive connection structure 242. The third conductive connection structure 243 connects the second conductive connection structure 242 to the bit line BL.

[0094] In some embodiments, such as Figure 7 As shown, the second conductive connection structure 242 can be a conductive bridge, which extends to overlap with the bit line BL and the active region AA. In some embodiments, such as Figure 7 As shown, the second conductive connection structure 242 can be located between two adjacent control signal groups 231.

[0095] In some embodiments, both the first conductive connection structure 241 and the third conductive connection structure 243 can be contacts.

[0096] Therefore, Figures 7 to 9 The storage structure 10 shown can increase the storage density of the semiconductor device 100 and increase the speed of erasure verification of the storage array.

[0097] Figure 10 This is a schematic diagram of a planar structure of another type of memory array for a semiconductor device provided in an embodiment of this application. Figure 11 Provided for the embodiments of this application Figure 10 The circuit diagram of the storage array shown is shown.

[0098] Figure 10 and Figure 11 The storage array shown is Figures 7 to 9 The storage arrays shown are basically similar, and the similarities will not be repeated. The following mainly describes the differences.

[0099] In some embodiments, such as Figure 10 and Figure 11As shown, the multiple bit lines BL include the m1-th bit line BLm1, the (m1+1)-th bit line BL(m1+1), and the (m1+2)-th bit line BL(m1+2) arranged sequentially. A memory structure row 10B includes an adjacent n1-th memory structure 10a1 and an (n1+1)-th memory structure 10a2. The source region 1081 and drain region 1082 of the n1-th memory structure 10a1 are connected to the m1-th bit line BLm1 and the (m1+1)-th bit line BL(m1+1) respectively through a conductive connection structure 24. The source region 1081 and drain region 1082 of the (n1+1)-th memory cell 10a2 are connected to the (m1+1)-th bit line BL(m1+1) and the (m1+2)-th bit line BL(m1+2) respectively through a conductive connection structure 24. Thus, for adjacent memory structures 10 in a row 10B of a memory structure, they share a single bit line BL, reducing the number of bit lines BL connecting two adjacent memory structures 10. This saves space occupied by the bit lines BL connecting two adjacent memory structures 10, thereby providing more space for setting up the memory structures 10 and increasing the storage density of the semiconductor device 100. Furthermore, when the area occupied by the memory array is fixed, reducing the number of bit lines BL connecting two adjacent memory structures 10 allows for increasing the width of the bit lines BL, thereby reducing the resistance of the bit lines BL and improving the access speed of the memory array.

[0100] In some embodiments, such as Figure 10 and Figure 11 As shown, one of the source region 1081 and drain region 1082 of the n1th memory structure 10a1 and one of the source region 1081 and drain region 1082 of the (n1+1)th memory structure 10a2 are connected to the (m1+1)th bit line BL (m1+1) through different conductive connection structures 24. Thus, the n1th memory structure 10a1 and the (n1+1)th memory structure 10a2 are connected to the (m1+1)th bit line BL through different conductive connection structures 24, meaning that two adjacent memory structures 10 are connected to the shared bit line BL through different conductive connection structures 24.

[0101] Figure 12 This is a schematic diagram of a planar structure of another type of memory array for a semiconductor device provided in an embodiment of this application. Figure 13 Provided for the embodiments of this application Figure 12 The circuit diagram of the storage array shown is shown.

[0102] Figure 12 and Figure 13 The storage array shown is Figures 10 to 11 The storage arrays shown are basically similar, and the similarities will not be repeated. The following mainly describes the differences.

[0103] In some embodiments, such as Figure 12 As shown, one of the source region 1081 and drain region 1082 of the n1th memory structure 10a1 is connected to the (m1+1)th bit line BL through a first conductive connection structure 241, a second conductive connection structure 242, and a common conductive connection structure 244. Similarly, one of the source region 1081 and drain region 1082 of the (n1+1)th memory structure 10a2 is connected to the (m1+1)th bit line BL through another first conductive connection structure 241, a second conductive connection structure 242, and a common conductive connection structure 244. Thus, adjacent memory structures 10 are connected to a common bit line BL through a shared common conductive connection structure 244 and a second conductive connection structure 242, reducing the number of conductive connection structures 24 and simplifying the fabrication process of the semiconductor device 100.

[0104] Figure 14 This is a schematic diagram of a planar structure of another type of memory array for a semiconductor device provided in an embodiment of this application. Figure 15 Provided for the embodiments of this application Figure 14 The circuit diagram of the storage array shown is shown.

[0105] Figure 14 and Figure 15 The storage array shown is Figures 10 to 11 The storage arrays shown are basically similar, and the similarities will not be repeated. The following mainly describes the differences.

[0106] In some embodiments, such as Figure 14 and Figure 15 As shown, the multiple bit lines BL also include the (m1+3)th bit line BL(m1+3), the (m1+4)th bit line BL(m1+4), and the (m1+5)th bit line BL(m1+5) arranged sequentially. The (m1+3)th bit line BL(m1+3) is adjacent to the (m1+2)th bit line BL(m1+2). A storage structure row 10B also includes adjacent (n1+2)th storage structures 10a3 and (n1+3)th storage structures 10a4, with the (n1+2)th storage structure 10a3 adjacent to the (n1+1)th storage structure 10a4. The (n1+2)th storage structure 10a3 is adjacent to the (n1+1)th storage structure 10a2. The source region 1081 and drain region 1082 of the (n1+2)th memory structure 10a3 are connected to the (m1+3)th bit line BL(m1+3) and the (m1+4)th bit line BL(m1+4), respectively. The source region 1081 and drain region 1082 of the (n1+3)th memory structure 10a4 are connected to the (m1+4)th bit line BL(m1+4) and the (m1+5)th bit line BL(m1+5), respectively.

[0107] The m1-th bit line BLm1, the (m1+1)-th bit line BL(m1+1), and the (m1+2)-th bit line BL(m1+2) constitute a bit line group. When operating on the n1-th storage structure 10a1 and the (n1+1)-th storage structure 10a2, it is only necessary to operate on at least two of the m1-th bit line BL, the (m1+1)-th bit line BL, and the (m1+2)-th bit line BL. Bit line BL(m1+3), bit line BL(m1+4), and bit line BL(m1+5) are treated as a group of bit lines. When operating on memory structures 10a3 (n1+2) and 10a4 (n1+3), only at least two of these three bit lines need to be operated on. Therefore, when operating on memory structure 10, only the corresponding bit line group needs to be controlled, without controlling other bit line groups, thus saving the power consumption required to apply voltage to bit line BL.

[0108] It should be noted that, due to Figures 10 to 15 In the illustrated memory array, the four gate structures 103A of a memory structure 10 share a common channel region 109, and each memory structure 10 is connected to two bit lines BL. Adjacent memory structures 10 share a single bit line. Therefore, Figures 10 to 15 The design of the storage structure 10 shown can increase the storage density of the semiconductor device 100 and improve the speed of erasure verification of the semiconductor device 100. Furthermore, for Figures 7 to 8 as well as Figures 10 to 15 The illustrated memory array allows programming operations to be performed on a selected memory cell 102 within a memory structure 10, thereby reducing the programming voltage. Furthermore, when erasing operations are performed simultaneously on all four memory cells 102 within a memory structure 10, the risk of over-erasing can be reduced.

[0109] Figure 16 The signal timing diagram for programming operations of the memory array provided in the embodiments of this application is shown.

[0110] To describe the technical solution of this application, a storage structure 10 for programming operations is used as an example. Figure 7 and Figure 8 Taking a storage structure 10 as an example, the storage structure 10 is connected to multiple control signal lines and bit lines BLm1 and BL(m1+1) in the control signal line group 231B2. Figure 16The first gate control signal line OCg0 in the control signal line group 231B2 is shown. <1> Third gate control signal line OWL <1> Second gate control signal line OCg1 <1> Fourth gate control signal line ECg2 <1> Sixth gate control signal line EWL <1> and the fifth gate control signal line ECg3 <1> The transmitted signal.

[0111] It is understood that, with compatibility of solutions, the programming operation method of this application embodiment can also be used in other storage arrays of this application embodiment.

[0112] In some embodiments, the peripheral circuitry 40 is configured to perform a programming operation on the memory structure 10, including: applying a programming control gate signal Vpgm to a selected control gate 104 (e.g., within a memory structure 10) in a memory structure 10. Figure 7 and Figure 8 Interchange with the fourth gate control signal line ECg2 <1> The connected control gates) apply the control gate activation signal Vpass to one or more unselected control gates 104 (e.g., Figure 7 and Figure 8 In the first gate control signal line OCg0 <1> Second gate control signal line OCg1 <1> and the fifth gate control signal line ECg3 <1> (At least one of the control gates is connected). The programming control gate signal Vpgm reaches a first target value at a first time t1, and the conduction control gate signal Vpass reaches a second target value at a second time t2. The first time t1 is earlier than the second time t2. Thus, the time when the conduction control gate signal Vpass reaches the second target value is later than the time when the programming control gate signal Vpgm reaches the first target value. This reduces the risk that the conduction control gate signal Vpass loaded on the control gate 104 of one or more unselected memory cells 102 in the memory structure 10 may be coupled to a higher voltage. This improves the problem of uneven threshold voltage distribution in memory cells 102 caused by misprogramming due to high voltage after coupling of one or more unselected memory cells 102.

[0113] In some embodiments, the first target value corresponding to the programmable control gate signal Vpgm can be greater than the second target value corresponding to the turn-on control gate signal Vpass. In some embodiments, the first target value corresponding to the programmable control gate signal Vpgm can be 7V to 9V, and the second target value corresponding to the turn-on control gate signal Vpass can be 4V to 6V.

[0114] In some embodiments, the first target value of the programmable gate signal Vpgm is obtained by a boost. This is done to ensure that the programmable gate signal Vpgm reaches the first target value earlier, thereby improving the coupling effect of the programmable gate signal Vpgm on other signals.

[0115] In some embodiments, the turn-on control gate signal Vpass includes a first-stage control gate signal Vu1 and a second-stage control gate signal following the first-stage control gate signal. The first-stage control gate signal has a first transition value, and the second-stage control gate signal has a second target value. The first transition value is obtained by boosting the first initial value, and the second target value is obtained by boosting the first transition value. Thus, the turn-on control gate signal Vpass reaches the second target value through two boosts, reducing the risk that the programming control gate signal Vpgm will couple the turn-on control gate signal Vpass to a value exceeding the second target value, and reducing the risk that one or more unselected memory cells 102 will be misprogrammed.

[0116] It is understandable that the conduction control gate signal Vpass can also reach the second target value through one or more boosts, as long as the time when the conduction control gate signal Vpass reaches the second target value is later than the time when the programming control gate signal Vpgm reaches the first target value.

[0117] In some embodiments, when the memory array includes memory structure 10, applying a turn-on control voltage to one or more unselected control gates 104 includes: applying a first turn-on control gate signal Vpass1 to two unselected control gates 104 adjacent to the selected control gate 104 (e.g., ...). Figure 7 and Figure 8 The second gate control signal line OCg1 <1> and the fifth gate control signal line ECg3 <1> (Two connected control gates); and, applying the second turn-on control gate signal Vpass2 to other non-selected control gates 104 besides the two non-selected control gates 104 adjacent to the selected control gate 104 (e.g., the two connected control gates); and applying the second turn-on control gate signal Vpass2 to other non-selected control gates 104 besides the two non-selected control gates 104 adjacent to the selected control gate 104 (e.g Figure 7 and Figure 8 In the first gate control signal line OCg0 <1> (Connected control gate), the second target value of the second conduction control gate signal Vpass2 is less than the second target value of the first conduction control gate signal Vpass1.

[0118] For two adjacent unselected control gates 104, a first on-gate control signal with a larger target value is applied to them. For other unselected control gates 104 besides the two adjacent unselected control gates 104, a second on-gate control signal with a smaller target value is applied to them. In this way, the target values ​​of the on-gate control signals on both sides of the selected control gate 104 decrease, which can better suppress the risk of the on-gate control signals being coupled to higher voltages. Furthermore, the decrease in the target values ​​of the on-gate control signals on both sides of the selected control gate 104 also reduces the programming difficulty of the memory cell 102 including the selected control gate 104. In addition, using a second on-gate control signal with a smaller target value not only reduces the risk of misprogramming of the memory cell 102 containing other unselected control gates 104, but also helps to reduce the power consumption required by the semiconductor device 100 during programming operations.

[0119] In some embodiments, the peripheral circuit 40 is further configured to: apply a first turn-on common gate signal VWL1 to a common gate 106 adjacent to the selected control gate 104 (e.g., the sixth gate control signal line EWL) in a storage structure 10. <1> (Connected shared gate), the first conducting shared gate signal VWL1 reaches the third target value at the third time t3, which is earlier than the second time t2 and later than the first time t1. This reduces the risk that the first conducting shared gate signal VWL1 will couple the conduction control gate signal Vpass to a higher voltage, further reducing the risk of the memory cell 102 containing the unselected control gate 104 being misprogrammed. Furthermore, it also reduces the risk that the programming control gate signal Vpgm will couple to the first conducting shared gate signal VWL1.

[0120] In some embodiments, when the control gate signal Vpass includes a first-stage control gate signal Vu1 and a second-stage control gate signal following the first-stage control gate signal, the first transition value rises to the second target value starting from the third time t3.

[0121] In some embodiments, the peripheral circuit 40 is further configured to: apply a second turn-on common gate signal VWL2 to a common gate 106 located between two unselected control gates 104 (e.g., the third gate control signal line OWL) in a storage structure 10. <1> (Connected shared gate), the second conducting shared gate signal VWL2 reaches the fourth target value at the second time t2. This reduces the risk of the second conducting shared gate signal VWL2 being coupled to a higher value by the programmable control gate signal Vpgm.

[0122] In some embodiments, the fourth target value is greater than the third target value. Thus, when the shared gate 106 between the two unselected control gates 104 applies the second conduction shared gate signal VWL2 to the shared channel region 109, the degree of opening of the region of the shared channel region 109 affected by the second conduction shared gate signal VWL2 is better.

[0123] In some embodiments, the conduction control gate signal Vpass applied to the unselected plurality of control gates 104 includes a first conduction control gate signal Vpass1 and a second conduction control gate signal Vpass2. A second target value of the second conduction control gate signal Vpass2 is less than a second target value of the first conduction control gate signal Vpass1; a fourth target value is equal to the second target value of the second conduction control gate signal Vpass2. This ensures that the fourth target value is large enough to guarantee a better degree of activation of the region where the second conduction common gate signal VWL2 acts on the region of the common channel region 109.

[0124] In some embodiments, the second turn-on shared gate signal VWL2 includes a first-stage shared gate signal Vu2 and a second-stage shared gate signal. The first-stage shared gate signal has a second transition value, and the second-stage shared gate signal has a fourth target value. The second transition value is obtained by boosting the second initial value, and the fourth target value is obtained by boosting the second transition value. Thus, the second turn-on shared gate signal VWL2 is obtained through two boosts, reducing the risk that the second turn-on shared gate signal VWL2 will be coupled to a higher voltage by the turn-on control gate signal Vpass.

[0125] In some embodiments, the fourth target value of the second conduction common gate signal VWL2 can also be obtained by raising the initial value one or more times.

[0126] In some embodiments, the peripheral circuit 40 is further configured to apply a first bit line programming signal and a second bit line programming signal to two bit lines BL connected to the memory structure 10, respectively, within the memory structure 10 including the selected control gate 104. Thus, the voltage difference between the first bit line programming signal and the second bit line programming signal allows electrons to be injected into the floating gate 105 below the selected control gate 104, thereby enabling programming of the selected memory cell 102.

[0127] In some embodiments, the first bit line programming signal can be a bit line programming current, and the second bit line programming signal can be a bit line programming voltage. In some embodiments, the bit line programming current can be 1μA to 5μA, and the bit line programming voltage can be 7V to 9V.

[0128] Therefore, some embodiments of this application optimize the programming operation of the above-mentioned memory array. Specifically, the timing of the control signals applied to a memory cell pair 101 or a memory cell 102 in two memory cell pairs 101 of the memory structure 10 is optimized to improve the problem of misprogramming of the unselected memory cell 102, thereby improving the problem of uneven threshold voltage distribution of multiple memory cells 102 in the memory array after programming.

[0129] Some embodiments of this application also provide a method for performing read operations on the above-described storage array. Through the read operation, the stored value stored in a storage cell 102 of the storage structure 10 can be read.

[0130] In some embodiments, when the storage array includes storage structure 10, the process of performing a read operation on the storage array includes the row drive circuit 41 being configured as follows:

[0131] Apply a control gate read signal to the selected control gate 104 in storage structure 10;

[0132] A common gate read signal is applied to the common gate 106 adjacent to the selected control gate 104 in the storage structure 10;

[0133] Apply a read-on control signal to the plurality of unselected control gates 104 in the storage structure 10; and,

[0134] A common gate signal is applied to the common gate 106 between two adjacent unselected control gates 104 in the storage structure 10.

[0135] During the read operation of the storage array, the row drive circuit 41 applies corresponding control signals to multiple control gates 104 and two common gates 106 in the storage structure 10 through multiple control signal lines of the gate control signal line group 231, so as to select the control gate 104 of the storage cell 102 to be read, and make the storage cell 102 where multiple unselected control gates 104 are located in the on state.

[0136] In some embodiments, the process of performing a read operation on the storage array further includes that the column drive circuit 42 is configured to:

[0137] A first bit read signal is applied to a bit line BL connected to the memory structure 10 where the selected control gate 104 is located. A bit line BL is connected to the memory cell pair 101 where the selected control gate 104 is located.

[0138] A second bit line read signal is applied to another bit line BL connected to the memory structure 10 where the selected control gate 104 is located.

[0139] In some embodiments, the voltage value of the first line read signal can be 0V, but is not limited thereto.

[0140] In some embodiments, the voltage value of the second bit line read signal can be 0.6V to 1V, but is not limited thereto.

[0141] Some embodiments of this application also provide a method for performing an erase operation on the above-described storage array. The erase operation clears the data stored in the semiconductor device 100 to facilitate programming operations on the semiconductor device 100.

[0142] In some embodiments, the process of performing an erase operation on the memory array includes the row drive circuit 41 being configured to: apply control gate erase signals to a plurality of control gates 104 of the memory structure 10 containing the selected control gate 104; and apply a common gate erase signal to two common gates 106 of the memory structure 10 containing the selected control gate 104. Thus, the erase operation achieves the erasure of two or four memory cells 102 in the memory structure 10.

[0143] In some embodiments, the voltage value of the control gate erase signal can be 6V to 10V. In some embodiments, the voltage value of the common gate erase signal can be 8V to 10V.

[0144] In some embodiments, the process of performing an erase operation on the memory array further includes that the column drive circuit 42 is configured to apply a bit line erase signal to both bit lines BL connected to the memory structure 10 where the selected control gate 104 is located.

[0145] In some embodiments, the voltage value of the bit line erase signal can be 0V.

[0146] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor layer; Multiple bit lines are located on the semiconductor layer; as well as Multiple memory structures are provided, one of which includes a source region, a drain region, a common channel region, and two sets of gate structures. The source region, the drain region, and the common channel region are located within the semiconductor layer. The common channel region is connected between the source region and the drain region. The two sets of gate structures are located on the common channel region. One set of gate structures includes two sub-gate structures and a common gate. One common gate is located between the two sub-gate structures. One sub-gate structure includes a floating gate and a control gate on the floating gate. The source region and drain region of one memory structure are respectively connected to two bit lines through conductive connection structures.

2. The semiconductor device according to claim 1, characterized in that, The plurality of storage structures include a plurality of storage structure rows, one of the storage structure rows including at least two of the storage structures arranged side by side along the first direction, and the plurality of storage structure rows arranged along a second direction, wherein the first direction intersects the second direction; The semiconductor device further includes multiple control signal lines, which extend along the first direction and are located on the semiconductor layer. Each control signal line is connected to a memory structure in a memory structure row.

3. The semiconductor device according to claim 2, characterized in that, The multiple bit lines include the m1-th bit line, the (m1+1)-th bit line, the (m1+2)-th bit line, and the (m1+3)-th bit line arranged in sequence; A row of the memory structure includes an adjacent n1th memory structure and a (n1+1)th memory structure. The source region and drain region of the n1th memory structure are respectively connected to the m1th bit line and the (m1+1)th bit line through conductive connection structures. The source region and drain region of the (n1+1)th memory structure are respectively connected to the (m1+2)th bit line and the (m1+3)th bit line through conductive connection structures.

4. The semiconductor device according to claim 2, characterized in that, The multiple bit lines include the m1th bit line, the (m1+1)th bit line, and the (m1+2)th bit line arranged in sequence; A row of the memory structure includes an adjacent n1th memory structure and a (n1+1)th memory structure. The source region and drain region of the n1th memory structure are respectively connected to the m1th bit line and the (m1+1)th bit line through conductive connection structures. The source region and drain region of the (n1+1)th memory cell are respectively connected to the (m1+1)th bit line and the (m1+2)th bit line through conductive connection structures.

5. The semiconductor device according to claim 4, characterized in that, One of the source and drain regions of the n1th memory structure and one of the source and drain regions of the (n1+1)th memory structure are respectively connected to the (m1+1)th bit line through different conductive connection structures.

6. The semiconductor device according to claim 4, characterized in that, One of the source and drain regions of the n1th memory structure and one of the source and drain regions of the (n1+1)th memory structure are connected to the (m1+1)th bit line through a common conductive connection structure.

7. The semiconductor device according to claim 4, characterized in that, The multiple bit lines also include the (m1+3)th bit line, the (m1+4)th bit line and the (m1+5)th bit line arranged in sequence, wherein the (m1+3)th bit line is adjacent to the (m1+2)th bit line; Each of the storage structure rows further includes an adjacent (n1+2)th storage structure and a (n1+3)th storage structure, wherein the (n1+2)th storage structure is adjacent to the (n1+1)th storage structure; Wherein, the source region and drain region of the (n1+2)th memory structure are connected to the (m1+3)th bit line and the (m1+4)th bit line, respectively, and the source region and drain region of the (n1+3)th memory structure are connected to the (m1+4)th bit line and the (m1+5)th bit line, respectively.

8. The semiconductor device according to claim 2, characterized in that, A row of the storage structure includes a first row of storage cell pairs and a second row of storage cell pairs, each of the first row of storage cell pairs and the second row of storage cell pairs including at least two pairs of storage cells arranged side by side along the first direction; Multiple control signal lines are divided into multiple control signal line groups, and the multiple control signal line groups are arranged along the second direction. Each control signal line group includes a first control signal line subgroup and a second control signal line subgroup. The first control signal line subgroup includes a first gate control signal line, a second gate control signal line, and a third gate control signal line. The first gate control signal line and the second gate control signal line are respectively connected to the two control gates of each memory cell pair in the first memory cell pair row. The second gate control signal line is connected to the common gate of each memory cell pair in the first memory cell pair row. The second control signal line subgroup includes a fourth gate control signal line, a fifth gate control signal line, and a sixth gate control signal line. The fourth gate control signal line and the fifth gate control signal line are respectively connected to the two control gates of each memory cell pair in the second memory cell pair row, and the sixth gate control signal line is connected to the common gate of each memory cell pair in the second memory cell pair row.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, Also includes: The peripheral circuitry is connected to multiple of the aforementioned storage structures and is configured as follows: In a storage structure, a programming control gate signal is applied to a selected control gate, and an on control gate signal is applied to one or more unselected control gates. The programming control gate signal reaches a first target value at a first time, and the on control gate signal reaches a second target value at a second time, wherein the first time is earlier than the second time.

10. The semiconductor device according to claim 9, characterized in that, The conduction control gate signal includes a first-stage control gate signal and a second-stage control gate signal following the first-stage control gate signal. The first-stage control gate signal has a first transition value, and the second-stage control gate signal has a second target value. The first transition value is obtained by raising the first initial value, and the second target value is obtained by raising the first transition value.

11. The semiconductor device according to claim 9, characterized in that, Applying the conduction control voltage to one or more unselected control gates includes: The first conduction control gate signal is applied to the two unselected control gates adjacent to the selected control gate; The second turn-on control gate signal is applied to other unselected control gates besides the two unselected control gates adjacent to the selected control gate, and the second target value of the second turn-on control gate signal is less than the second target value of the first turn-on control gate signal.

12. The semiconductor device according to claim 9, characterized in that, The peripheral circuit is also configured to: In one of the memory structures, a first turn-on shared gate signal is applied to a shared gate adjacent to the selected control gate, the first turn-on shared gate signal reaching a third target value at a third time point, the third time point being earlier than the second time point and later than the first time point.

13. The semiconductor device according to claim 12, characterized in that, The peripheral circuit is also configured to: In one of the memory structures, a second turn-on common gate signal is applied to a common gate located between two unselected control gates, the second turn-on common gate signal reaching a fourth target value at the second time.

14. The semiconductor device according to claim 13, characterized in that, The fourth target value is greater than the third target value.

15. The semiconductor device according to claim 13, characterized in that, The conduction control gate signal applied to the unselected plurality of control gates includes a first conduction control gate signal and a second conduction control gate signal, wherein the second target value of the second conduction control gate signal is less than the second target value of the first conduction control gate signal; and the fourth target value is equal to the second target value of the second conduction control gate signal.

16. The semiconductor device according to claim 13, characterized in that, The second conduction shared gate signal includes a first-stage shared gate signal and a second-stage shared gate signal. The first-stage shared gate signal has a second transition value, and the second-stage shared gate signal has the fourth target value. The second transition value is obtained by raising the second initial value, and the fourth target value is obtained by raising the second transition value.

17. The semiconductor device according to claim 9, characterized in that, The peripheral circuit is also configured to: In the memory structure including the selected control gate, a first bit line programming signal and a second bit line programming signal are respectively applied to the two bit lines connected to the memory structure.

18. A method for controlling a semiconductor device, characterized in that, The semiconductor device includes multiple memory structures, one of the memory structures includes one or more pairs of memory cells, the one or more pairs of memory cells in one memory structure share a common channel region, one pair of memory cells includes two memory cells and a common gate, the two memory cells share the common gate, and one memory cell includes a floating gate and a control gate spaced apart. The control method includes: In response to a programming instruction for a selected memory cell in a memory structure, a programming control gate signal is applied to the control gate of the selected memory cell, and an on control gate signal is applied to the control gates of one or more unselected memory cells in the memory structure. The programming control gate signal reaches a first target value at a first time, and the on control gate signal reaches a second target value at a second time, wherein the first time is earlier than the second time.

19. The control method for the semiconductor device according to claim 18, characterized in that, One of the memory structures includes two pairs of memory cells; the control gate for applying a programming control gate signal to the selected memory cell includes: The first conduction control gate signal is applied to the control gates of two unselected memory cells adjacent to the control gate of the selected memory cell; The second turn-on control gate signal is applied to the control gate of the non-selected memory cells other than the two non-selected memory cells adjacent to the control gate of the selected memory cell, and the second target value of the second turn-on control gate signal is less than the second target value of the first turn-on control gate signal.

20. The control method for the semiconductor device according to claim 18, characterized in that, The control method further includes: A first conduction common gate signal is applied to a common gate adjacent to the control gate of the selected memory cell. The first conduction common gate signal reaches a third target value at a third time, which is earlier than the second time and later than the first time.

Images