Method of manufacturing a semiconductor device
Patent Information
- Application Number
- CN202610780958.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-01
- Publication Date
- 2026-09-22
AI Technical Summary
[0003]在相关技术中，嵌入式闪存器件与PIP电容器通常采用独立制备流程，需重复进行多晶硅沉积、光刻与刻蚀等步骤，导致工艺步骤增加，且需要增加额外的掩膜，制造成本高，此外，在制备PIP电容器时，常在P型衬底上直接沉积字线（word line，WL）多晶硅来形成PIP电容器的下极板，字线多晶硅与P型衬底间会形成大的寄生电容，影响器件性能
[0032]本申请方法可在衬底上形成嵌入式闪存器件的同时同步完成PIP电容器的制备，工艺简单，无需增加额外的掩膜。此外，本申请采用闪存制造过程中形成的第一氧化层作为PIP电容器下极板与衬底之间的绝缘介质、第一多晶硅层作为PIP电容器下极板、第一栅氧层及第二栅氧层作为PIP电容器上下极板间的绝缘介质，第二多晶硅层作为PIP电容器上极板，可以降低PIP电容器下极板与衬底间的寄生电容，有利于提升器件性能。
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Figure CN122803277A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for manufacturing a semiconductor device. Background Technology
[0002] Polysilicon-insulator-poly (PIP) capacitors are widely used to prevent noise emission and frequency modulation in analog circuits. Their core working principle is based on the polarization induced by an electric field in an insulating medium, thereby storing charge between two layers of polysilicon. Compared to other capacitors, PIP capacitors offer advantages such as high capacitance density, low voltage coefficient, and low parasitic effects. The high capacitance density effectively reduces chip area; therefore, PIP capacitors are often integrated with embedded flash (E-Flash) devices on the same substrate to effectively suppress noise and regulate frequency while achieving integrated circuit data storage functionality.
[0003] In related technologies, embedded flash memory devices and PIP capacitors are usually fabricated using separate processes, requiring repeated polysilicon deposition, photolithography, and etching steps, which increases the number of process steps and requires additional masks, resulting in high manufacturing costs. In addition, when fabricating PIP capacitors, word line (WL) polysilicon is often deposited directly on a P-type substrate to form the lower electrode of the PIP capacitor. This results in a large parasitic capacitance between the word line polysilicon and the P-type substrate, which affects device performance. Summary of the Invention
[0004] This application provides a method for manufacturing a semiconductor device, which can not only complete the fabrication of PIP capacitors during the formation of embedded flash memory devices, but also reduce the parasitic capacitance between the lower plate and the substrate of the PIP capacitor.
[0005] In view of this, this application provides a method for manufacturing a semiconductor device, comprising:
[0006] S1, a substrate is provided, the substrate including a storage region, a logic region and a capacitor region, the logic region including a first device region for forming a first logic device and a second device region for forming a second logic device, the first logic device and the second logic device having different operating voltages, and a flash gate structure is formed on the substrate of the storage region;
[0007] S2, a first oxide film covering the substrate surface is formed in the storage area, logic area, and capacitor area;
[0008] S3, a first polysilicon thin film covering the first oxide thin film and the flash memory gate structure is formed in the storage area, logic area and capacitor area;
[0009] S4, etch away the first oxide film and the first polysilicon film of the logic region, form a first oxide layer in the storage region and the capacitor region, and form a first polysilicon layer on the surface of the first oxide layer and the flash memory gate structure.
[0010] S5, a first gate oxide film covering the first polysilicon layer and the surface of the logic region substrate is formed in the memory region, logic region, and capacitor region;
[0011] S6, etch away the first gate oxide film on the storage region and the second device region, and form the first gate oxide layer in the first device region and the capacitor region;
[0012] S7, a second gate oxide film is formed in the memory region, logic region, and capacitor region, covering the first polysilicon layer of the memory region, the substrate surface of the second device region, and the first gate oxide layer of the capacitor region.
[0013] S8, a second polysilicon thin film covering the second gate oxide thin film and the first gate oxide layer of the first device region is formed in the storage region, logic region and capacitor region;
[0014] S9, etching away a portion of the second gate oxide film and the second polysilicon film, forming the gate structures of the first logic device and the second logic device in the first device region and the second device region respectively, and simultaneously forming a PIP capacitor in the capacitor region.
[0015] Optionally, the flash memory gate structure includes, from bottom to top, a coupling oxide layer, a floating gate layer, an inter-gate dielectric layer, an erase gate layer, a first sidewall, a second sidewall formed on the inner side of the inter-gate dielectric layer, the erase gate layer, and part of the first sidewall, a third sidewall formed on the inner side of the coupling oxide layer, the floating gate layer, and part of the second sidewall, a source line polysilicon layer and a protective layer formed on the inner side of the first sidewall, the second sidewall, and the third sidewall, and a fourth sidewall formed on the outer side of the first sidewall, the erase gate layer, the inter-gate dielectric layer, the floating gate layer, and the coupling oxide layer.
[0016] Optionally, shallow trench isolation structures are formed in the substrate of the storage area, logic area, and capacitor area, wherein the top of the shallow trench isolation structure of the storage area and logic area is higher than the substrate surface, and the top of the shallow trench isolation structure of the capacitor area is flush with the substrate surface.
[0017] Optionally, the thickness of the first gate oxide film is greater than that of the second gate oxide film.
[0018] Optionally, before performing step S5, a step of forming a well region within the substrate of the logic region is also included.
[0019] Optionally, after performing step S9, the method further includes: etching away a portion of the first oxide layer and the first polysilicon layer in the memory region to form a word line oxide layer and a word line polysilicon layer in the memory region.
[0020] Optionally, after performing step S9, the method further includes forming a metal contact plug that is electrically connected to the first polysilicon layer and the second polysilicon layer of the capacitor region, respectively.
[0021] Optionally, a method for forming a flash memory gate structure on the substrate of the storage region includes:
[0022] S11, a stacked structure covering the substrate surface of the memory region and the logic region is formed on the memory region, the logic region and the capacitor region. The stacked structure includes, from bottom to top, a coupling oxide layer, a floating gate layer, an inter-gate dielectric layer and an erase gate layer.
[0023] S12, forming a stacked structure covering the memory area, logic area, and capacitor area, as well as a hard mask layer on the substrate surface of the capacitor area;
[0024] S13, a first opening is formed on the hard mask layer of the storage area, and a first sidewall is formed on the inner side of the first opening;
[0025] S14, dry etching is performed with the inner side of the first sidewall as the self-alignment condition to form a second opening on the erase gate layer and the inter-gate dielectric layer, and the second opening exposes the inner side of the erase gate layer and the inter-gate dielectric layer.
[0026] S15, a second sidewall is formed by self-alignment on the inner surfaces of the inter-gate dielectric layer, the erase gate layer, and part of the first sidewall;
[0027] S16, dry etching is performed with the inner side of the second sidewall as the self-alignment condition to form a third opening on the floating gate layer and the coupling oxide layer, and the third opening exposes the inner side of the floating gate layer and the coupling oxide layer.
[0028] S17, a source line polysilicon layer and a protective layer are self-aligned and formed on a substrate within the first inner side surface formed by the superposition of the inner sides of the first side wall, the second side wall and the third side wall.
[0029] S18, the hard mask layer of the memory area, logic area, and capacitor area and the stacked structure located below the hard mask layer of the memory area and logic area are etched away, and the first outer surface of the memory area, which is formed by the superposition of the outer surface of the first sidewall, the erase gate layer, the inter-gate dielectric layer, the floating gate layer and the coupling oxide layer, is exposed.
[0030] S19, a fourth sidewall is formed by self-alignment on the outer side of the first outer surface.
[0031] The technical solution of this application has at least the following advantages:
[0032] The method described in this application can simultaneously fabricate PIP capacitors while forming embedded flash memory devices on a substrate. The process is simple and requires no additional mask. Furthermore, this application uses a first oxide layer formed during flash memory manufacturing as the insulating medium between the lower electrode of the PIP capacitor and the substrate, a first polysilicon layer as the lower electrode of the PIP capacitor, a first gate oxide layer and a second gate oxide layer as the insulating medium between the upper and lower electrodes of the PIP capacitor, and a second polysilicon layer as the upper electrode of the PIP capacitor. This reduces the parasitic capacitance between the lower electrode of the PIP capacitor and the substrate, which is beneficial for improving device performance. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0034] Figure 1 This is a process flow diagram of a semiconductor device manufacturing method provided in an exemplary embodiment of this application;
[0035] Figure 2 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after forming the flash memory gate structure;
[0036] Figure 3 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after the formation of a first polycrystalline silicon thin film;
[0037] Figure 4 This is a schematic cross-sectional view of the process of forming a first polysilicon layer in a semiconductor device manufacturing method provided in an exemplary embodiment of this application;
[0038] Figure 5 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after the formation of the first polysilicon layer;
[0039] Figure 6 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after the formation of the first gate oxide thin film;
[0040] Figure 7 This is a schematic cross-sectional view of the process of forming a first gate oxide layer in a semiconductor device manufacturing method provided in an exemplary embodiment of this application;
[0041] Figure 8This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after the formation of the first gate oxide layer;
[0042] Figure 9 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after the formation of a first polycrystalline silicon thin film;
[0043] Figure 10 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after forming a PIP capacitor;
[0044] Figure 11 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after forming word line polysilicon and word line oxide layer;
[0045] Figure 12 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after the formation of a stacked structure during the formation of a flash memory gate structure;
[0046] Figure 13 This is a schematic cross-sectional view after forming a hard mask during the formation of a flash memory gate structure in a semiconductor device manufacturing method provided in an exemplary embodiment of this application;
[0047] Figure 14 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after forming a source line polysilicon layer and a protective layer during the formation of a flash memory gate structure;
[0048] Figure 15 This is a schematic cross-sectional view of the first outer surface after it is exposed during the formation of the flash memory gate structure in a semiconductor device manufacturing method provided in an exemplary embodiment of this application;
[0049] Figure label:
[0050] 100. Substrate; 110. Storage area; 120. Logic area; 121. First device area; 122. Second device area; 130. Capacitor area; 140. Shallow trench isolation structure;
[0051] 200, Flash gate structure; 210, Coupling oxide layer; 220, Floating gate layer; 230, Inter-gate dielectric layer; 240, Erase gate layer; 250, Hard mask layer; 261, First sidewall; 262, Second sidewall; 263, Third sidewall; 270, Source line polysilicon layer; 280, Protective layer; 290, Fourth sidewall;
[0052] 300, First oxide film; 310, First oxide layer; 320, Character line oxide layer
[0053] 400. First polycrystalline silicon thin film; 410. First polycrystalline silicon layer; 420. Word line polycrystalline silicon layer
[0054] 500. First photoresist pattern;
[0055] 600, First gate oxide thin film; 610, First gate oxide layer;
[0056] 700. Second photoresist pattern;
[0057] 800, Second gate oxide film; 810, Second gate oxide layer;
[0058] 900, Second polycrystalline silicon thin film; 910, Second polycrystalline silicon layer; Detailed Implementation
[0059] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0060] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0061] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0062] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0063] The following is combined with Figures 1 to 15 This describes an embodiment of the present application.
[0064] refer to Figure 1 The illustration shows an embodiment of this application, providing a method for manufacturing a semiconductor device, comprising:
[0065] S1, a substrate 100 is provided. The substrate 100 includes a storage region 110, a logic region 120 and a capacitor region 130. The logic region 120 includes a first device region 121 for forming a first logic device and a second device region 122 for forming a second logic device. The first logic device and the second logic device have different operating voltages. A flash memory gate structure 200 is formed on the substrate 100 of the storage region 110.
[0066] For example, the substrate 100 may be made of silicon, germanium (Ge), gallium arsenide (GaAs) or other materials suitable for the manufacture of semiconductor devices.
[0067] In some embodiments, the operating voltage of the first logic device may be greater than the operating voltage of the second logic device.
[0068] For example, the first logic device is a high voltage (HV) CMOS device with an operating voltage of 5V, and the second logic device is a low voltage (LV) CMOS device with an operating voltage of 1.2V.
[0069] In some embodiments, the flash gate structure 200 includes, from bottom to top, a coupling oxide layer 210, a floating gate layer 220, an inter-gate dielectric layer 230, an erase gate layer 240, a first sidewall 261, a second sidewall 262 formed on the inner side of the inter-gate dielectric layer 230, the erase gate layer 240, and a portion of the first sidewall 261, a third sidewall 263 formed on the inner side of the coupling oxide layer 210, the floating gate layer 220, and a portion of the second sidewall 262, a source line polysilicon layer 270 and a protective layer 280 formed on the inner side of the first sidewall 261, the second sidewall 262, and the third sidewall 263, and a fourth sidewall 290 formed on the outer side of the first sidewall 261, the erase gate layer 240, the inter-gate dielectric layer 230, the floating gate layer 220, and the coupling oxide layer 210.
[0070] Exemplarily, a method for forming a flash memory gate structure 200 on a substrate of storage region 110 includes:
[0071] S11, a stacked structure covering the substrate surface of the storage region 110 and the logic region 120 is formed on the storage region 110, the logic region 120 and the capacitor region 130. The stacked structure includes, from bottom to top, a coupling oxide layer 210, a floating gate layer 220, an inter-gate dielectric layer 230 and an erase gate layer 240.
[0072] S12, a hard mask layer is formed on the storage region 110, the logic region 120, and the capacitor region 130, covering the stacked structure of the storage region 110, the logic region 120, and the substrate surface of the capacitor region 130.
[0073] S13, a first opening is formed on the hard mask layer of the storage area 110, and a first sidewall 261 is formed on the inner side of the first opening;
[0074] S14, dry etching is performed with the inner side surface of the first sidewall 261 as the self-alignment condition to form a second opening on the erase gate layer 240 and the inter-gate dielectric layer 230, and the second opening exposes the inner side surface of the erase gate layer 240 and the inter-gate dielectric layer 230.
[0075] S15, a second sidewall 262 is formed by self-alignment on the inner surfaces of the inter-gate dielectric layer 230, the erase gate layer 240, and part of the first sidewall 261;
[0076] S16, dry etching is performed with the inner side surface of the second sidewall 262 as the self-alignment condition to form a third opening on the floating gate layer 220 and the coupling oxide layer 210, and the third opening exposes the inner side surface of the floating gate layer 220 and the coupling oxide layer 210.
[0077] S17, a source line polysilicon layer 270 and a protective layer 280 are self-aligned and formed on a substrate 100 within the first inner side surface formed by the superposition of the inner sides of the first side wall 261, the second side wall 262 and the third side wall 263.
[0078] S18, the hard mask layer of the memory region 110, logic region 120, and capacitor region 130 and the stacked structure located below the hard mask layer of the memory region 110 and logic region 120 are etched away, and the first outer surface of the memory region 110, which is formed by the stacking of the outer surfaces of the first sidewall 261, the erase gate layer 240, the inter-gate dielectric layer 230, the floating gate layer 220 and the coupling oxide layer 210, is exposed.
[0079] S19, forming a fourth sidewall 290 by self-alignment on the outer side of the first outer surface.
[0080] It should be noted that during the formation of the flash memory gate structure 200, a source line doped region is formed within the substrate 100. For example, after performing step S16 and before performing step S17, ion implantation is performed using the first inner surface as a self-aligned condition to form a source line doped region within the substrate 100.
[0081] In some embodiments, shallow trench isolation structures 140 are formed in the substrate 100 of the storage region 110, the logic region 120, and the capacitor region 130, wherein the top of the shallow trench isolation structures 140 of the storage region 110 and the logic region 120 is higher than the surface of the substrate 100, and the top of the shallow trench isolation structures 140 of the capacitor region 130 is flush with the surface of the substrate 100.
[0082] S2, a first oxide film 300 is formed on the surface of the substrate in the storage region 110, logic region 120, and capacitor region 130.
[0083] For example, a first oxide film 300 covering the substrate surface can be grown in the storage region 110, logic region 120, and capacitor region 130 using thermal oxidation (TO).
[0084] S3, a first polysilicon thin film 400 covering the first oxide thin film 300 and the flash memory gate structure 200 is formed in the storage region 110, logic region 120, and capacitor region 130.
[0085] For example, a first polycrystalline silicon thin film 400 can be formed in the storage region 110, logic region 120, and capacitor region 130 using chemical vapor deposition (CVD).
[0086] S4, the first oxide film 300 and the first polysilicon film 400 of the logic region 120 are etched away, a first oxide layer 310 is formed in the storage region 110 and the capacitor region 130, and a first polysilicon layer 410 is formed on the surface of the first oxide layer 310 and the flash gate structure 200.
[0087] For example, a first photoresist pattern 500 is first formed by photolithography to expose the substrate surface of logic region 120 (see [link]). Figure 4 Then, etching is performed to remove the first oxide film 300 and the first polysilicon film 400 of the logic region 120. After removing the first oxide film 300 and the first polysilicon film 400 of the logic region 120, the first photoresist pattern 500 can be removed by an ashing process or a wet cleaning process, thereby forming the first polysilicon layer 410 on the surface of the first oxide layer 310 and the flash memory gate structure 200 (see...). Figure 5 ).
[0088] S5, a first gate oxide film 600 is formed in the storage region 110, the logic region 120, and the capacitor region 130, covering the first polysilicon layer 410 and the substrate surface of the logic region 120.
[0089] For example, a first gate oxide film 600 can be formed in the storage region 110, logic region 120, and capacitor region 130 using chemical vapor deposition (CVD).
[0090] In some embodiments, before performing step S5, a step of forming a well region within the substrate 100 of the logic region 120 is further included.
[0091] For example, N-wells and P-wells within the logic region 120 substrate 100 can be constructed by performing a well-doped ion implantation process on the logic region 120 substrate 100.
[0092] S6, etch away the first gate oxide film 600 on the storage region 110 and the second device region 122, and form the first gate oxide layer 610 on the first device region 121 and the capacitor region 130.
[0093] For example, a second photoresist pattern 700 is first formed by photolithography to expose the first gate oxide film 600 on the memory region 110 and the second device region 122 (see [link]). Figure 7 After etching, the first gate oxide film 600 on the storage region 110 and the second device region 122 can be removed. After removing the first gate oxide film 600 on the storage region 110 and the second device region 122, the second photoresist pattern 700 can be removed by an ashing process or a wet cleaning process, thereby forming the first gate oxide layer 610 in the first device region 121 and the capacitor region 130 (see...). Figure 8 ).
[0094] S7, a second gate oxide film 800 is formed on the storage region 110, logic region 120, and capacitor region 130, covering the first polysilicon layer 410 of storage region 110, the substrate 100 surface of the second device region 122, and the first gate oxide layer 610 of capacitor region 130.
[0095] For example, a second oxide film can be grown in the storage region 110, logic region 120, and capacitor region 130 using thermal oxidation (TO).
[0096] In some embodiments, the thickness of the first gate oxide film 600 is greater than that of the second gate oxide film 800.
[0097] S8, a second polysilicon thin film 900 is formed in the storage region 110, the logic region 120, the capacitor region 130, covering the second gate oxide thin film 800 and the first gate oxide layer 610 of the first device region 121.
[0098] For example, a second polysilicon thin film 900 can be formed in the storage region 110, logic region 120, and capacitor region 130 using chemical vapor deposition (CVD).
[0099] S9, etching away a portion of the second polysilicon thin film 900 and the second gate oxide thin film 800, forming the gate structures of the first logic device and the second logic device in the first device region 121 and the second device region 122 respectively, and simultaneously forming a PIP capacitor in the capacitor region 130.
[0100] For example, a third photoresist pattern (not shown in the figure) is first formed by photolithography to expose the second polysilicon thin film 900 and the second gate oxide thin film 800 in the target area. Then, etching is performed to remove the second polysilicon thin film 900 and the second gate oxide thin film 800 in the target area. After removing the second polysilicon thin film 900 and the second gate oxide thin film 800 in the target area, the third photoresist pattern can be removed by an ashing process or a wet cleaning process to form a second polysilicon layer 910 covering the first gate oxide layer 610 in the first device region 121. The second gate oxide layer 810 and the corresponding second polysilicon layer 910 are simultaneously formed in the second device region 122, and the second polysilicon layer 910 is simultaneously formed in the capacitor region 130 as the upper electrode of the PIP capacitor (see [reference]). Figure 10 Thus, while forming the gate structure of the first logic device, the gate structure of the second logic device is simultaneously formed in the second device region 122, and the PIP capacitor is simultaneously formed in the capacitor region 130.
[0101] In some embodiments, after performing step S9, the method further includes: etching away a portion of the first polysilicon layer 410 and the first oxide layer 310 of the storage region 110, and forming a word line polysilicon layer 420 and a word line oxide layer 320 in the storage region 110.
[0102] It should be noted that after forming the word line polysilicon and word line oxide layer 320, a fifth sidewall (not shown in the figure) is formed on the outside of the word line polysilicon layer 420, and a doped region of the bit line is formed in the substrate 100 on the outside of the word line polysilicon layer 420, thereby forming a flash memory device. Source and drain regions are formed in the substrate 100 on both sides of the first gate structure and the second gate structure, thereby forming the first logic device and the second logic device. Since this part is prior art, the embodiments of this application will not be described in detail.
[0103] In some embodiments, after performing step S9, the method further includes forming a metal contact plug that is electrically connected to the first polysilicon layer 410 and the second polysilicon layer 910 of the capacitor region 130, respectively.
[0104] In related technologies, embedded flash memory devices and PIP capacitors are usually fabricated using separate processes, requiring repeated polysilicon deposition, photolithography, and etching steps, which increases the number of process steps and requires additional masks, resulting in high manufacturing costs. In addition, when fabricating PIP capacitors, word line (WL) polysilicon is often deposited directly on the P-type substrate 100 to form the lower electrode of the PIP capacitor. A large parasitic capacitance is formed between the word line polysilicon and the P-type substrate 100, which affects the device performance.
[0105] The method described in this application can simultaneously fabricate a PIP capacitor while forming an embedded flash memory device on the substrate 100. The process is simple and requires no additional mask. Furthermore, this application uses a first oxide layer 310 formed during flash memory manufacturing as the insulating medium between the lower electrode of the PIP capacitor and the substrate 100, a first polysilicon layer 410 as the lower electrode of the PIP capacitor, a first gate oxide layer 610 and a second gate oxide layer 810 as the insulating medium between the upper and lower electrodes of the PIP capacitor, and a second polysilicon layer 910 as the upper electrode of the PIP capacitor. This reduces the parasitic capacitance between the lower electrode of the PIP capacitor and the substrate 100, which is beneficial for improving device performance.
[0106] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: S1, a substrate is provided, the substrate including a storage region, a logic region and a capacitor region, the logic region including a first device region for forming a first logic device and a second device region for forming a second logic device, the first logic device and the second logic device having different operating voltages, and a flash gate structure is formed on the substrate of the storage region; S2, a first oxide film covering the substrate surface is formed in the storage area, logic area, and capacitor area; S3, a first polysilicon thin film covering the first oxide thin film and the flash memory gate structure is formed in the storage area, logic area and capacitor area; S4, etch away the first oxide film and the first polysilicon film of the logic region, form a first oxide layer in the storage region and the capacitor region, and form a first polysilicon layer on the surface of the first oxide layer and the flash memory gate structure. S5, a first gate oxide film covering the first polysilicon layer and the surface of the logic region substrate is formed in the memory region, logic region, and capacitor region; S6, etch away the first gate oxide film on the storage region and the second device region, and form the first gate oxide layer in the first device region and the capacitor region; S7, a second gate oxide film is formed in the memory region, logic region, and capacitor region, covering the first polysilicon layer of the memory region, the substrate surface of the second device region, and the first gate oxide layer of the capacitor region. S8, a second polysilicon thin film covering the second gate oxide thin film and the first gate oxide layer of the first device region is formed in the storage region, logic region and capacitor region; S9, etching away a portion of the second gate oxide film and the second polysilicon film, forming the gate structures of the first logic device and the second logic device in the first device region and the second device region respectively, and simultaneously forming a PIP capacitor in the capacitor region.
2. The method according to claim 1, characterized in that, include: The flash memory gate structure includes, from bottom to top, a coupling oxide layer, a floating gate layer, an inter-gate dielectric layer, an erase gate layer, and a first sidewall; a second sidewall formed on the inner surface of the inter-gate dielectric layer, the erase gate layer, and part of the first sidewall; a third sidewall formed on the inner surface of the coupling oxide layer, the floating gate layer, and part of the second sidewall; a source line polysilicon layer and a protective layer formed on the inner surface of the first sidewall, the second sidewall, and the third sidewall; and a fourth sidewall formed on the outer surface of the first sidewall, the erase gate layer, the inter-gate dielectric layer, the floating gate layer, and the coupling oxide layer.
3. The method according to claim 1, characterized in that, Shallow trench isolation structures are formed in the substrates of the storage area, logic area, and capacitor area. The top of the shallow trench isolation structures in the storage area and logic area is higher than the substrate surface, while the top of the shallow trench isolation structures in the capacitor area is flush with the substrate surface.
4. The method according to claim 1, characterized in that, The thickness of the first gate oxide film is greater than that of the second gate oxide film.
5. The method according to claim 1, characterized in that, Before performing step S5, the process also includes the step of forming a well region within the substrate of the logic region.
6. The method according to claim 1, characterized in that, After performing step S9, the method further includes: etching away a portion of the first oxide layer and the first polysilicon layer in the memory region, and forming a word line oxide layer and a word line polysilicon layer in the memory region.
7. The method according to claim 1, characterized in that, After performing step S9, the process further includes forming metal contact plugs that are electrically connected to the first polysilicon layer and the second polysilicon layer of the capacitor region, respectively.
8. The method according to any one of claims 1-7, characterized in that, Methods for forming flash memory gate structures on the substrate of the storage region include: S11, a stacked structure covering the substrate surface of the memory region and the logic region is formed on the memory region, the logic region and the capacitor region. The stacked structure includes, from bottom to top, a coupling oxide layer, a floating gate layer, an inter-gate dielectric layer and an erase gate layer. S12, forming a stacked structure covering the memory area, logic area, and capacitor area, as well as a hard mask layer on the substrate surface of the capacitor area; S13, a first opening is formed on the hard mask layer of the storage area, and a first sidewall is formed on the inner side of the first opening; S14, dry etching is performed with the inner side of the first sidewall as the self-alignment condition to form a second opening on the erase gate layer and the inter-gate dielectric layer, and the second opening exposes the inner side of the erase gate layer and the inter-gate dielectric layer. S15, a second sidewall is formed by self-alignment on the inner surfaces of the inter-gate dielectric layer, the erase gate layer, and part of the first sidewall; S16, dry etching is performed with the inner side of the second sidewall as the self-alignment condition to form a third opening on the floating gate layer and the coupling oxide layer, and the third opening exposes the inner side of the floating gate layer and the coupling oxide layer. S17, a source line polysilicon layer and a protective layer are self-aligned and formed on a substrate within the first inner side surface formed by the superposition of the inner sides of the first side wall, the second side wall and the third side wall. S18, the hard mask layer of the memory area, logic area, and capacitor area and the stacked structure located below the hard mask layer of the memory area and logic area are etched away, and the first outer surface of the memory area, which is formed by the superposition of the outer surface of the first sidewall, the erase gate layer, the inter-gate dielectric layer, the floating gate layer and the coupling oxide layer, is exposed. S19, a fourth sidewall is formed by self-alignment on the outer side of the first outer surface.