Method for reducing nor flash word line height

Abstract

The application discloses a method for reducing NOR Flash word line height, comprising the following steps: 1) completing N-type / P-type source-drain photoetching, N-type / P-type source-drain injection, N-type / P-type source-drain dry stripping, N-type / P-type source-drain wet stripping, and manufacturing a storage unit area and a peripheral logic area of the NOR Flash; 2) spin-coating a protective layer, filling the storage unit gap pits with the protective layer, covering the storage unit area and the peripheral logic area top with the protective layer, and making the protective layer surface flat; 3) performing overall etching, etching and removing the storage unit top oxide layer and part of the word line, and still existing the protective layer above the peripheral logic area; 4) removing the protective layer; 5) sequentially performing silicide blocking oxide layer deposition and source-drain injection activation rapid thermal annealing process, and forming silicide. The application can avoid bit line-word line bridging and interlayer medium cavity defects in the NOR Flash process, provide high process yield and production efficiency, and guarantee device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a method for reducing the word line height of NOR Flash. Background Technology

[0002] NOR Flash, as a mature and widely used non-volatile semiconductor memory device, boasts advantages such as data retention even when power is off, fast read / write speeds, and high reliability, making it widely used in embedded storage, consumer electronics, and industrial control. In traditional NOR Flash manufacturing processes, the word line (WL) oxidation process forms a relatively wide silicide structure at the top of the word line. This wide silicide significantly reduces the physical distance between the bit line contact (BL CT) and the word line silicide, making it highly susceptible to bit line-word line bridging (BL-WL bridge) leakage or even short-circuit failure in subsequent processes or during operation, severely impacting device yield and reliability.

[0003] Meanwhile, the current process technology results in a relatively high overall height for memory cells, leading to deep and narrow gaps between cells. During the interlayer dielectric (ILD) deposition and filling process, the high aspect ratio structure significantly reduces filling uniformity and conformity, easily forming ILD voids within the gaps. These voids can cause fatal defects in subsequent contact hole fabrication processes, such as contact hole bridging, abnormally high contact resistance, and decreased withstand voltage, further restricting device performance and mass production yield.

[0004] In existing technologies, to avoid word line pitting (WL) damage caused by high-temperature processes or subsequent etching, a certain thickness of oxide (OX) protective layer is usually required at the top of the word line. This oxide layer is difficult to completely remove using conventional etching processes, resulting in the inability to effectively reduce the word line height and the inability to shrink the silicide width at the top of the word line. This makes it difficult to fundamentally solve the aforementioned BL-WL bridging and ILD void problems. Furthermore, existing process adjustment methods fail to effectively utilize the natural height difference between the memory cell region and the peripheral logic region. Any etching or thin-film adjustment targeting the memory cell region can easily cause etching damage, dimensional drift, or performance degradation to the lower-height, more structurally sensitive peripheral logic devices, resulting in poor process compatibility and an extremely narrow adjustment window. Summary of the Invention

[0005] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] The technical problem to be solved by this invention is the bit line-to-line bridging and interlayer dielectric void defects that exist in existing NOR Flash processes.

[0007] To address the aforementioned technical problems, this invention provides a method for reducing NOR Flash word line height without affecting the performance of peripheral logic area devices and without requiring additional masks, comprising the following steps: 1) Complete N-type / P-type source / drain photolithography, N-type / P-type source / drain injection, N-type / P-type source / drain dry stripping, and N-type / P-type source / drain wet stripping to fabricate the NOR Flash memory cell area and peripheral logic area; 2) Spin-coating a protective layer to fill the gaps and pits between memory cells, and to cover the tops of both the memory cell area and the peripheral logic area, with a smooth surface. 3) Perform full etching to remove the oxide layer on top of the memory cell and some word lines, and there is also a protective layer above the outer logic area; 4) Remove the protective layer; 5) Perform silicide barrier oxide deposition, source / drain implantation activation, and rapid thermal annealing (RTA) processes sequentially to form silicide.

[0008] Preferably, in a further improvement to the method of reducing the word line height of NOR Flash, the protective layer is an anti-reflective coating (BARC).

[0009] Preferably, the method for reducing the word line height of NOR Flash is further improved by removing the anti-reflective coating in step 4), which includes ashing and wet stripping.

[0010] Preferably, in a further improved method for reducing the word line height of NOR Flash, the full etching in step 3) only applies to the memory cell area, while the peripheral logic area is protected by the anti-etching layer and is not etched.

[0011] Preferably, the method for further improving the NOR Flash word line height does not require additional masks compared to existing processes.

[0012] The working principle of this invention is as follows: This invention leverages the excellent spin-coating fluidity and gap-filling properties of the bottom anti-reflective coating. An anti-reflective coating is spin-coated before the deposition of the silicide barrier layer, ensuring it fully fills the gaps and pits between memory cells. The surface smoothing effect of the anti-reflective coating after film formation creates a coplanar, flat surface between the top of the memory cell region and the top of the peripheral logic region. Subsequently, a comprehensive etching (BT ET) process simultaneously removes the residual oxide layer and part of the word line polysilicon structure at the top of the memory cell, precisely reducing the overall height of the memory cell and eliminating the large "top" structure at the top of the word line. Utilizing the natural height difference between the memory cell region and the peripheral logic region, the anti-reflective coating effectively shields and protects the peripheral logic region during comprehensive etching, completely avoiding etching damage risks. After selective etching, the anti-reflective coating is thoroughly removed through ashing and wet stripping processes. Then, conventional subsequent processes such as SAB oxide deposition and source / drain implantation activation rapid thermal annealing (RTA) are sequentially performed to form low-resistivity silicide on the word line surface. The entire process requires no additional masks; it only involves adding simple steps such as anti-reflective coating application, full etching, and anti-reflective coating removal to the existing mature process. The process is highly compatible and easy to implement.

[0013] Compared with the prior art, the present invention can achieve at least the following technical effects: 1) In the prior art, a certain thickness of oxide layer needs to be retained at the top of the word line to prevent pitting (WL Pitting). This oxide layer cannot be completely removed by conventional processes, resulting in an excessively wide silicide when it is formed later. The wide silicide significantly reduces the physical distance between the bit line contact hole (BL CT) and the word line silicide, which can easily cause bridging defects such as leakage and short circuit, seriously reducing the device yield and operating stability.

[0014] This invention completely removes the oxide layer at the top of the word line and reduces the word line height through a comprehensive etching process, forming a narrow-width silicide at the top of the word line. This effectively increases the distance between the bit line contact hole and the word line silicide, thus avoiding the BL-WL bridging problem at its source. In contrast, existing technologies are limited by residual oxide layers and cannot reduce the width of the silicide, thus failing to completely eliminate this defect.

[0015] 2) Under the current process, the overall height of the memory cell is relatively high, and the gap between cells has a high aspect ratio. It is difficult to achieve full and uniform filling during the deposition of interlayer dielectric (ILD), which easily forms void defects inside the gap. Voids will further cause problems such as contact hole bridging, abnormal contact resistance, and reduced withstand voltage performance, which restricts device performance and mass production yield.

[0016] This invention precisely reduces the height of memory cells through a full etching process, thereby reducing the aspect ratio of the cell gaps and significantly improving the filling environment during ILD deposition. This facilitates uniform and dense filling of the interlayer medium and eliminates void defects. Existing technologies cannot effectively reduce the height of memory cells, cannot improve the gap filling conditions, and are unable to avoid the risk of ILD voids.

[0017] 3) In the prior art, the oxide layer remaining at the top of the word line will hinder the full growth of silicide on the surface of the word line, resulting in incomplete silicide coverage and poor continuity, which will eventually increase the contact resistance of the word line and degrade its conductivity.

[0018] This invention completely removes the oxide layer on the top of the word line through a full etching process, providing a clean, oxide-free surface for silicide growth. This allows silicides to form fully and uniformly on the word line surface, significantly reducing word line resistance and improving device signal transmission efficiency and electrical stability. Existing technologies require the retention of the oxide layer to prevent word line pitting, which prevents the full growth of silicides and makes it difficult to reduce word line resistance.

[0019] 4) Existing processes focus on adjusting the height or optimizing the etching of the memory cell area, but lack specific protection measures for the peripheral logic area (peri area). This makes it easy to cause etching damage, size drift, or performance degradation to the polysilicon of the peripheral logic area, which has a lower height and a more sensitive structure, thus disrupting the normal function of the logic device. The process adjustment window is extremely narrow.

[0020] This invention fully utilizes the natural height difference between the memory cell area and the peripheral logic area. During BT ET etching, the BARC covering the surface of the peripheral logic area can form an effective physical barrier, completely blocking the etching action from damaging the logic device and ensuring that the performance of the peripheral logic area device is not affected in any way. Existing technologies do not have such selective protection mechanisms, and process adjustments will inevitably affect the logic device, resulting in poor compatibility.

[0021] 5) To address defects such as high word line resistance, existing technologies require the addition of dedicated masks to achieve zoned process control. Mask preparation, photolithography, and inspection processes will significantly increase production costs and process complexity, and extend the production cycle.

[0022] This invention adds only simple process steps such as BARC coating, BT ET etching, and BARC removal to the existing standard process. No additional masks are required throughout the process, resulting in minimal process changes, low implementation costs, and significantly reduced mass production difficulty, while ensuring process yield and production efficiency. Attached Figure Description

[0023] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0024] Figure 1 This is a schematic diagram of the process of this invention.

[0025] Figure 2 This is a schematic diagram of the intermediate structure of the present invention. Figure 1 .

[0026] Figure 3 This is a schematic diagram of the intermediate structure of the present invention. Figure 2 .

[0027] Figure 4 This is a schematic diagram of the intermediate structure of the present invention. Figure 3 .

[0028] Figure 5 This is a schematic diagram of the intermediate structure of the present invention. Figure 4 . Detailed Implementation

[0029] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements. Example

[0030] refer to Figure 1As shown, this embodiment provides a method for reducing the word line height of NOR Flash, which includes the following steps: 1) Pre-processing: NP source / drain photolithography, NP source / drain implantation, NP source / drain dry lift-off, and NP source / drain wet lift-off processes are performed sequentially to complete the basic fabrication of the source / drain region. (Refer to...) Figure 2 As shown 2) Spin-coating a BARC layer: After completing the preprocessing steps and before depositing the SAB oxide layer, a BARC layer is spin-coated. BARC has good flowability and can fully fill the gaps and pits between memory cells, ensuring that the BARC surface at the top of the memory cell area and the top of the peripheral logic area remains flat. (Refer to...) Figure 3 As shown 3) Full-scale etching (BT ET): A single BT ET process is used to uniformly etch the wafer surface. This etching process removes the oxide layer on top of the memory cell and part of the word line, effectively reducing the overall height of the memory cell and eliminating the wide structure at the top of the word line. Since the height of the polysilicon in the peripheral logic area is lower than that of the memory cell and the surface is covered with BARC, it will not be damaged during the etching process, as shown in Figure 4. 4) Remove the BARC coating by performing asher and wet stripping processes in sequence to completely remove the BARC coating on the wafer surface, exposing the device structure of the memory cell area and the peripheral logic area, as shown in Figure 5. 5) Subsequent process fabrication: SAB oxide layer deposition and source / drain implantation activation RTA process are performed sequentially to form silicide on the word line surface, completing the fabrication of the NOR Flash device core structure.

[0031] In this embodiment, all process parameters are conventional parameters for semiconductor manufacturing. Those skilled in the art can adjust them according to actual process requirements and reproduce the process scheme of the present invention without additional creative effort.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0033] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for reducing the word line height of NOR Flash, characterized in that, Includes the following steps: 1) Complete N-type / P-type source / drain photolithography, N-type / P-type source / drain injection, N-type / P-type source / drain dry stripping, and N-type / P-type source / drain wet stripping to fabricate the NOR Flash memory cell area and peripheral logic area; 2) Spin-coating a protective layer to fill the gaps and pits between memory cells, and to cover the tops of both the memory cell area and the peripheral logic area, with a smooth surface. 3) Perform full etching to remove the oxide layer on top of the memory cell and some word lines, and there is also a protective layer above the outer logic area; 4) Remove the protective layer; 5) Perform silicide barrier oxide deposition, source / drain implantation activation, and rapid thermal annealing (RTA) processes sequentially to form silicide.

2. The method for reducing NOR Flash word line height according to claim 1, characterized in that: The protective layer is an anti-reflective coating.

3. The method for reducing the word line height of NOR Flash according to claim 2, characterized in that: Step 4) involves removing the anti-reflective coating, which includes ashing and wet stripping.

4. The method for reducing the word line height of NOR Flash according to claim 1, characterized in that: In step 3), the full etching only applies to the memory cell area, while the surrounding logic area is protected by the anti-etching layer and is not etched.

5. The method for reducing the word line height of NOR Flash according to claim 1, characterized in that: It requires no additional mask compared to existing processes.

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