Multiple-time-programmable non-volatile memory structure, array, and method of operation

Abstract

The application provides a multi-time programmable nonvolatile memory structure, array and operation method, which comprises the following steps: forming N-type and P-type deep well regions and a first isolation structure for spacing the N-type and P-type deep well regions in a substrate; forming a first region P-type and a first region N-type doped region in the N-type deep well region, wherein the first, second and third P-type doped regions in the first region P-type doped region are spaced from each other; a gate structure is located on the substrate between the first and second P-type doped regions; a first floating gate structure is located on the substrate between the second and third P-type doped regions; a second region N-type and a second region P-type doped region are located in the P-type deep well region; a second isolation structure is used for spacing the second region N-type and the second region P-type doped region; a second floating gate structure is located on the P-type deep well region beside the second region N-type doped region, the first and second floating gate structures are short-circuited, compatible with a standard I / O voltage, and the area of the memory structure is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a reprogrammable non-volatile memory structure, array, and operation method. Background Technology

[0002] Multiple-time programmable (MTP) non-volatile memory retains stored data after power loss and can be erased and programmed multiple times. Existing MTP non-volatile memory cells primarily utilize the Fowler-Nordheim (FN) tunneling mechanism to inject or release electrons into the floating gate. During erasure or programming, a relatively high voltage needs to be applied across the oxide layer of the floating gate to create an oxide layer electric field typically greater than 10 MV / cm. This allows electrons to pass through the oxide layer and change the charge state of the floating gate, thus achieving non-volatile data storage.

[0003] However, on the one hand, to ensure a sufficiently high tunneling potential for the floating gate, the coupling ratio between the control gate and the floating gate typically needs to reach over 90%, thus requiring a larger control gate area, resulting in a larger memory cell area, which is detrimental to high-density integration. On the other hand, the oxide layer thickness in the floating gate is typically 120–140 angstroms, and the erase or programming voltage required to achieve FN tunneling is typically 17–19V, while the breakdown voltage between the P-well and N-well of the I / O device is typically only about 14V. To meet the high-voltage operation requirements, existing designs often require additional non-well isolation regions between the N-well and P-well to increase the breakdown voltage to over 19V, further increasing the cell area and process layout complexity. Therefore, how to enable MTP memory cells to achieve reliable erasure and programming within the conventional I / O voltage range of standard BCD processes, such as 6–9V, while simultaneously reducing the memory cell area, is one of the technical problems that urgently needs to be solved in the current technology.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a reprogrammable non-volatile memory structure, array and operation method to solve the problem of low integration of MTP memory cells in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a reprogrammable non-volatile memory structure, comprising:

[0007] The substrate includes an N-type deep well region, a P-type deep well region, and a first isolation structure located on the upper surface of the substrate, wherein the N-type deep well region and the P-type deep well region are separated by the first isolation structure.

[0008] The first region is a P-type doped region located on the upper surface of the N-type deep well region. The first region includes a first P-type doped region, a second P-type doped region, and a third P-type doped region. The first P-type doped region, the second P-type doped region, and the third P-type doped region are spaced apart from each other.

[0009] A gate structure is located on a substrate between the first P-type doped region and the second P-type doped region;

[0010] The first floating gate structure is located on the substrate between the second P-type doped region and the third P-type doped region;

[0011] The first region is an N-type doped region, located on the upper surface of the N-type deep well region on one side of the first region's P-type doped region;

[0012] The second region is an N-type doped region located on the upper surface of the P-type deep well region;

[0013] The second region, a P-type doped region, is located on the upper surface of the P-type deep well region and is spaced apart from the second region, an N-type doped region.

[0014] The second isolation structure is located within the substrate between the N-type doped region of the second region and the P-type doped region of the second region;

[0015] The second floating gate structure is located on the P-type deep well region next to the N-type doped region in the second region;

[0016] In this configuration, the first N-type doped region is led out through a first lead-out structure as an N-type well region terminal, the first P-type doped region is led out through a second lead-out structure as a bit line terminal, the gate structure is led out through a third lead-out structure as a word line terminal, the third P-type doped region is led out through a fourth lead-out structure as a common terminal, the first floating gate structure and the second floating gate structure are shorted, the second N-type doped region is led out through a fifth lead-out structure as an erase gate terminal, and the second P-type doped region is led out through a sixth lead-out structure as a P-type well region terminal.

[0017] In one embodiment, the first floating gate structure and the second floating gate structure are fabricated from the same polysilicon, the polysilicon and the N-type deep well region having a first overlapping area in a first direction, and the polysilicon and the P-type deep well region having a second overlapping area in the first direction.

[0018] In one embodiment, the overlap area between the first P-type doped region, the second P-type doped region and the gate structure is zero; the overlap area between the third P-type doped region, the second P-type doped region and the first floating gate structure is zero.

[0019] Secondly, this application also provides a repeatedly programmable non-volatile memory array, comprising:

[0020] At least one storage block, the storage block comprising a first storage unit, a second storage unit, a third storage unit, and a fourth storage unit; wherein the first storage unit, the second storage unit, the third storage unit, and the fourth storage unit are implemented using a multiple-programmable non-volatile storage structure as described in any one of the embodiments of this application; the first storage unit and the third storage unit, and the second storage unit and the fourth storage unit are arranged in a centrally symmetrical manner, and the centers of symmetry of the first storage unit and the third storage unit overlap; the first storage unit and the second storage unit, and the third storage unit and the fourth storage unit are all arranged in an axisymmetric manner in a second direction, and the axes of symmetry of the first storage unit and the second storage unit overlap; the first storage unit and the fourth storage unit, and the second storage unit and the third storage unit are all arranged in an axisymmetric manner in a third direction, and the axes of symmetry of the first storage unit and the fourth storage unit overlap; the first direction, the second direction, and the third direction are mutually perpendicular;

[0021] In this configuration, the first and second storage units share a first N-type well region terminal, the third and fourth storage units share a second N-type well region terminal, the first bit line terminal of the first storage unit and the fourth bit line terminal of the fourth storage unit are connected to the first bit line, the second bit line terminal of the second storage unit and the third bit line terminal of the third storage unit are connected to the second bit line, the first and second storage units share a first word line terminal and are connected to the first word line, the third and fourth storage units share a second word line terminal and are connected to the second word line, the first and second storage units share a first common terminal and the third and fourth storage units share a second common terminal and are connected to the first common line, the first and fourth storage units share a first erase gate terminal and the second and third storage units share a second erase gate terminal and are connected to the first erase line, and the first, second, third, and fourth storage units share a first P-type well region terminal.

[0022] In one embodiment, the storage block includes: a first storage block, a second storage block, a third storage block, and a fourth storage block; the first storage block and the third storage block, as well as the second storage block and the fourth storage block, are arranged in a centrally symmetrical manner, and the centers of symmetry of the first storage block and the third storage block overlap with the centers of symmetry of the second storage block and the fourth storage block; the first storage block and the second storage block, as well as the third storage block and the fourth storage block, are all arranged in an axisymmetric manner in a second direction, and the axes of symmetry of the first storage block and the second storage block overlap with the axes of symmetry of the third storage block; the first storage block and the fourth storage block, as well as the second storage block and the third storage block, are all arranged in an axisymmetric manner in a third direction, and the axes of symmetry of the first storage block and the fourth storage block overlap with the axes of symmetry of the second storage block and the third storage block.

[0023] The N-type deep well regions of the third and fourth memory cells in the first memory block are connected to the N-type deep well regions of the first and second memory cells in the fourth memory block. The N-type deep well regions of the third and fourth memory cells in the second memory block are connected to the N-type deep well regions of the first and second memory cells in the third memory block. The P-type deep well regions of the first, second, third, and fourth memory cells in the first memory block are connected to the P-type deep well regions of the first, second, third, and fourth memory cells in the second memory block. The P-type deep well regions of the first, second, third, and fourth memory cells in the third memory block are connected to the P-type deep well regions of the first, second, third, and fourth memory cells in the fourth memory block.

[0024] In one embodiment, the first and fourth storage units in the first storage block share the first bit line with the first and fourth storage units in the fourth storage block; the second and third storage units in the first storage block share the second bit line with the second and third storage units in the fourth storage block; the first and fourth storage units in the second storage block share the third bit line with the first and fourth storage units in the third storage block; and the second and third storage units in the second storage block share the fourth bit line. The units share the first word line; the third and fourth storage units in the first storage block and the third and fourth storage units in the second storage block share the second word line; the first and second storage units in the third storage block and the first and second storage units in the fourth storage block share the third word line; the third and fourth storage units in the third storage block and the third and fourth storage units in the fourth storage block share the fourth word line; the first storage block and the second storage block share the first erase line; the third storage block and the fourth storage block share the second erase line; the first storage block and the fourth storage block share the first common line; and the second storage block and the third storage block share the second common line.

[0025] Thirdly, this application also provides a method for operating a multiple-programmable non-volatile memory structure as described in any one of the embodiments of this application, characterized in that it includes:

[0026] A first positive voltage is applied to the N-type well region and the bit line, a second positive voltage is applied to the erase gate, and the word line and the common terminal are grounded to program the multiple programmable non-volatile memory structure based on the hot carrier injection effect; wherein, the second positive voltage is less than the first positive voltage;

[0027] The N-type well region terminal, the word line terminal, and the common terminal are grounded, the bit line terminal is floated, a third positive voltage is applied to the erase gate terminal, and the P-type well region terminal is grounded or a first negative voltage is applied to the P-type well region terminal to perform an erase operation on the multiple programmable non-volatile memory structure based on the gate leakage current effect.

[0028] A fourth positive voltage is applied to the N-type well region end and the common end, a second negative voltage is applied to the word line end, the erase gate end and the P-type well region end are grounded, and the bit line end is connected to the detection line to perform a read operation on the multiple programmable non-volatile memory structure.

[0029] In one embodiment, the first positive voltage includes 6 volts to 9 volts; the second positive voltage includes 2.5 volts to 5.5 volts.

[0030] In one embodiment, the third positive pressure includes 6 volts to 9 volts; the first negative pressure includes -2 volts to 0 volts.

[0031] In one embodiment, the fourth positive pressure includes 1.8 volts to 3 volts; the second negative pressure includes -2 volts to 0 volts.

[0032] As described above, the reprogrammable non-volatile memory structure, array, and operation method of the present invention have the following beneficial effects:

[0033] The present invention discloses a reprogrammable non-volatile memory structure, array, and operation method, comprising: a substrate including an N-type deep well region, a P-type deep well region, and a first isolation structure located on the upper surface of the substrate, wherein the N-type deep well region and the P-type deep well region are separated by the first isolation structure; a first region of P-type doped region located on the upper surface of the N-type deep well region, the first region of P-type doped region including a first P-type doped region, a second P-type doped region, and a third P-type doped region; wherein the first P-type doped region, the second P-type doped region, and the third P-type doped region are spaced apart from each other; a gate structure located on the substrate between the first P-type doped region and the second P-type doped region; a first floating gate structure located on the substrate between the second P-type doped region and the third P-type doped region; a first region of N-type doped region located on the upper surface of the N-type deep well region on one side of the first region of P-type doped region; and a second region of N-type doped region located on the upper surface of the N-type deep well region. The first region is located on the upper surface of the P-type deep well region; the second region is located on the upper surface of the P-type deep well region and is spaced apart from the second region N-type doped region; the second isolation structure is located in the substrate between the second region N-type doped region and the second region P-type doped region; the second floating gate structure is located on the P-type deep well region next to the second region N-type doped region; wherein, the first region N-type doped region is led out through the first lead structure as the N-type well region end, the first P-type doped region is led out through the second lead structure as the bit line end, the gate structure is led out through the third lead structure as the word line end, the third P-type doped region is led out through the fourth lead structure as the common terminal, the first floating gate structure and the second floating gate structure are shorted, the second region N-type doped region is led out through the fifth lead structure as the erase gate end, and the second region P-type doped region is led out through the sixth lead structure as the P-type well region end. This invention utilizes the hot carrier injection effect to program the memory structure and the gate-induced leakage current effect to erase the memory structure, thereby avoiding the use of high voltage in programming and erasing, being compatible with standard I / O voltage, and reducing the area of ​​the memory structure. In addition, the multi-programmable non-volatile memory structure based on the hot carrier effect and the gate-induced leakage current effect has a lower requirement for the coupling ratio between the erase transistor and the floating gate transistor, further reducing the area of ​​the memory structure. Attached Figure Description

[0034] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0035] Figure 1 This is a schematic diagram of a multiple programmable non-volatile memory structure provided in one embodiment of this application;

[0036] Figure 2 This is an equivalent circuit diagram of a multiple programmable non-volatile memory structure provided in one embodiment of this application;

[0037] Figure 3 This is a top view of a multiple programmable non-volatile memory structure provided in an embodiment of this application, viewed in a first direction.

[0038] Figure 4 This is an equivalent circuit diagram of a non-volatile memory structure that can be programmed multiple times in a programmed state, as provided in one embodiment of this application.

[0039] Figure 5 This is an equivalent circuit diagram of a non-volatile memory structure that can be programmed multiple times in an erased state, as provided in one embodiment of this application.

[0040] Figure 6 This is a top view of a multi-programmable non-volatile memory array provided in an embodiment of this application, viewed in a first direction.

[0041] Figure 7 This is an equivalent circuit diagram of a multiple programmable non-volatile memory array provided in one embodiment of this application. Detailed Implementation

[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0044] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0045] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0046] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0047] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0049] Please refer to Figure 1This application provides a reprogrammable non-volatile memory structure, including: a substrate 10, a first region P-type doped region 20, a gate structure 224, a first floating gate structure 226, a first region N-type doped region 208, a second region N-type doped region 218, a second region P-type doped region 222, a second isolation structure 220, and a second floating gate structure 228; wherein, the substrate 10 includes an N-type deep well region 204, a P-type deep well region 202, and a first isolation structure 216 located on the upper surface of the substrate 10, and the N-type deep well region 204 and the P-type deep well region 202 are connected by the first isolation structure 220. 16. The first P-type doped region 20 is located on the upper surface of the N-type deep well region 204. The first P-type doped region 20 includes a first P-type doped region 210, a second P-type doped region 212, and a third P-type doped region 214. The first P-type doped region 210, the second P-type doped region 212, and the third P-type doped region 214 are spaced apart from each other. The gate structure 224 is located on the substrate 10 between the first P-type doped region 210 and the second P-type doped region 212. The first floating gate structure 226 is located on the substrate 10 between the second P-type doped region 212 and the third P-type doped region 214. A first N-type doped region 208 is located on the upper surface of an N-type deep well region 204 on one side of a first P-type doped region 20; a second N-type doped region 218 is located on the upper surface of a P-type deep well region 202; a second P-type doped region 222 is located on the upper surface of a P-type deep well region 202 and is spaced apart from the second N-type doped region 218; a second isolation structure 220 is located within the substrate 10 between the second N-type doped region 218 and the second P-type doped region 222; a second floating gate structure 228 is located on the P-type deep well region 202 beside the second N-type doped region 218; the first N-type doped region... The first P-type doped region 208 is led out through the first lead-out structure 302 as the N-type well region terminal, the first P-type doped region 210 is led out through the second lead-out structure 304 as the bit line terminal, the gate structure 224 is led out through the third lead-out structure 306 as the word line terminal, the third P-type doped region 214 is led out through the fourth lead-out structure 308 as the common terminal, the first floating gate structure 226 and the second floating gate structure 228 are shorted, the second region N-type doped region 218 is led out through the fifth lead-out structure 310 as the erase gate terminal, and the second region P-type doped region 222 is led out through the sixth lead-out structure 312 as the P-type well region terminal.

[0050] As an example, the substrate 10 may include a substrate 102 and a buried layer 104 and an epitaxial layer 106 sequentially deposited on the substrate 102, wherein a first region P-type doped region 20, a gate structure 224, a first floating gate structure 226, a first region N-type doped region 208, a second region N-type doped region 218, a second region P-type doped region 222, a second isolation structure 220, a second floating gate structure 228, etc. are located within the epitaxial layer 106.

[0051] As an example, the multiple-programmable non-volatile memory structure may also include a fourth isolation structure 206, which isolates the N-type deep well region 204 from other regions. A third isolation structure (not shown) may also be disposed on the upper surface of the N-type deep well region 204 between the first N-type doped region 208 and the first P-type doped region 20, which isolates the first N-type doped region 208 and the first P-type doped region 20. The first isolation structure 216, the second isolation structure 220, the third isolation structure, and the fourth isolation structure 206 may include shallow trench isolation structures.

[0052] Please refer to the following: Figure 2 A first P-type doped region 210, a second P-type doped region 212, and a gate structure 224 constitute a selector transistor 402; wherein, the first P-type doped region 210 is the source of the selector transistor 402, and the second P-type doped region 212 is the drain of the selector transistor 402. A second P-type doped region 212, a third P-type doped region 214, and a first floating gate structure 226 constitute a floating gate transistor 404; wherein, the second P-type doped region 212 is the source of the floating gate transistor 404, and the third P-type doped region 214 is the drain of the floating gate transistor 404. A second region N-type doped region 218 and a second floating gate structure 228 constitute an eraser transistor 406.

[0053] As an example, the control gate 402 and the floating gate 404 are turned on, and the eraser 406 is turned off. Based on the hot carrier injection effect, the channel holes in the floating gate 404 are accelerated into hot carriers under the high transverse electric field at the drain end, and electron-hole pairs are excited at the drain end. Electrons are injected into the floating gate 404, thereby realizing the programming of the floating gate 404. When the gate selector 402 is turned off, no current is generated in the channel of the floating gate 404 and the gate selector 402. A high voltage is applied to the eraser 406. Based on the gate leakage current effect, strong band bending occurs in the P-type deep well region 202 and the second region N-type doped region 218, which induces band tunneling and generates initial electron-hole pairs. The initial electrons are accelerated under the action of the strong electric field and undergo secondary collision ionization to generate holes. These holes overcome the gate oxide barrier in the eraser 406 and are injected into the floating gate 404 under the action of the longitudinal electric field, neutralizing the electrons in the floating gate 404 and thus erasing the floating gate 404.

[0054] In some embodiments, please refer to Figure 3 The first floating gate structure 226 and the second floating gate structure 228 are made of the same polysilicon. The polysilicon and the N-type deep well region 204 have a first overlapping area in the first direction, and the polysilicon and the P-type deep well region 202 have a second overlapping area in the first direction.

[0055] As an example, the N-type deep well region 204 and the P-type deep well region 202 are arranged sequentially in the third direction. The N-type deep well region 204 has a right-angle hook-shaped structure in the top view in the first direction, and the opening of the right-angle hook shape is away from the P-type deep well region 202. The P-type deep well region 202 is rectangular in the top view in the first direction. The gate structure 224 is made of the first polysilicon 502. The first floating gate structure 226 and the second floating gate structure 228 are made of the second polysilicon 504. The second polysilicon 504 is rectangular in the top view in the first direction, and the second polysilicon 504 extends along the third direction and spans across the N-type deep well region 204 and the P-type deep well region 202.

[0056] As an example, the width of the first overlapping area in the third direction is greater than or equal to 0.25 micrometers, for example, 0.25 micrometers, 0.3 micrometers, etc.; the length of the first overlapping area in the second direction is greater than or equal to 0.3 micrometers, for example, 0.3 micrometers, 0.35 micrometers, etc. The width of the second overlapping area in the third direction is greater than or equal to 0.11 micrometers, for example, 0.11 micrometers, 0.12 micrometers, etc.; the length of the second overlapping area in the second direction is greater than or equal to 0.215 micrometers, for example, 0.215 micrometers, 0.22 micrometers, etc. The first polysilicon 502 and the N-type deep well region 204 have a third overlapping area in the first direction, the width of the third overlapping area in the third direction is greater than or equal to 0.4 micrometers, for example, 0.4 micrometers, 0.45 micrometers, etc.; the length of the third overlapping area in the second direction is greater than or equal to 0.28 micrometers, for example, 0.28 micrometers, 0.3 micrometers, etc.

[0057] In some embodiments, please refer to Figure 1 The overlap area between the first P-type doped region 210, the second P-type doped region 212 and the gate structure 224 is zero; the overlap area between the third P-type doped region 214, the second P-type doped region 212 and the first floating gate structure 226 is zero, which facilitates the occurrence of hot carrier injection effect.

[0058] This application also provides an operation method for a reproducible non-volatile memory structure as described in any one of the embodiments of this application, comprising: applying a first positive voltage to the N-type well region end and the bit line end, applying a second positive voltage to the erase gate end, and grounding the word line end and the common end to perform a programming operation on the reproducible non-volatile memory structure based on the hot carrier injection effect; wherein the second positive voltage is less than the first positive voltage; and / or, grounding the N-type well region end, the word line end, and the common end, floating the bit line end, applying a third positive voltage to the erase gate end, grounding the P-type well region end or applying a first negative voltage to the P-type well region end to perform an erasure operation on the reproducible non-volatile memory structure based on the gate-induced leakage current effect; and / or, applying a fourth positive voltage to the N-type well region end and the common end, applying a second negative voltage to the word line end, grounding the erase gate end and the P-type well region end, and connecting the bit line end to a detection line (not shown) to perform a read operation on the reproducible non-volatile memory structure.

[0059] For example, please refer to Figure 4 Based on the hot carrier injection effect, a programmable non-volatile memory structure is programmed. A first positive voltage is applied to the N-type well region and the word line is grounded. Since the selector 402, which is composed of the first P-type doped region 210, the second P-type doped region 212, and the gate structure 224, is a P-channel, the selector 402 is turned on. A second positive voltage is applied to the erase gate, and the second positive voltage is less than the first positive voltage. The floating gate 404, which is composed of the second P-type doped region 212, the third P-type doped region 214, and the first floating gate structure 226, is turned on. A first positive voltage is applied to the bit line and the common terminal is grounded, forming a current from the first P-type doped region 210 to the second P-type doped region 212 and from the second P-type doped region 212 to the third P-type doped region 214. The hot carrier injection effect occurs, and electrons tunnel into the first floating gate structure 226.

[0060] For example, please refer to Figure 5The erase operation is performed on the multi-programmable non-volatile memory structure based on the gate leakage current effect. The N-type well region, word line, and common terminal are grounded, the bit line is floated, and a third positive voltage is applied to the erase gate. The selector 402 and the floating gate 404 are turned off. Due to the application of the third positive voltage to the erase gate, the P-type well region is grounded or a first negative voltage is applied to the P-type well region, causing strong band bending in the P-type deep well region 202 and the second region N-type doped region 218, initiating band tunneling and generating initial electron-hole pairs. The initial electrons are accelerated under the action of a strong electric field, undergo secondary collision ionization, and generate holes. These holes overcome the oxide barrier and are injected into the floating gate 404 under the action of a longitudinal electric field. That is, the electrons in the floating gate 404 escape from the erase tube 406 composed of the second region N-type doped region 218 and the second floating gate structure 228, forming a gate leakage current. Applying a first negative voltage to the P-type well region 202 can further increase the voltage difference between the P-type deep well region 202 and the second region N-type doped region 218, thereby improving the erasure efficiency.

[0061] As an example, a fourth positive voltage is applied to the N-type well region end, a second negative voltage is applied to the word line end, the selector 402 is turned on, a fourth positive voltage is applied to the common end, the erase gate end is grounded, and the bit line end is connected to the detection line. When electrons are stored in the floating gate 404, the floating gate 404 is turned on, and a current change can be detected at the bit line end. When no electrons are stored in the floating gate 404, the floating gate 404 is not turned on, and no current change can be detected at the bit line end.

[0062] In some embodiments, the first positive voltage includes 6 volts to 9 volts, for example, 6 volts, 7 volts, 8 volts, 9 volts, etc.; the second positive voltage includes 2.5 volts to 5.5 volts, for example, 2.5 volts, 3 volts, 3.5 volts, 4 volts, 4.5 volts, 5 volts, 5.5 volts, etc.

[0063] In some embodiments, the third positive voltage includes 6 volts to 9 volts, for example, 6 volts, 7 volts, 8 volts, 9 volts, etc.; the first negative voltage includes -2 volts to 0 volts, for example, -2 volts, -1.5 volts, -1 volt, -0.5 volts, 0 volts, etc.

[0064] In some embodiments, the fourth positive voltage includes 1.8 volts to 3 volts, such as 1.8 volts, 2 volts, 2.5 volts, 3 volts, etc.; the second negative voltage includes -2 volts to 0 volts, such as -2 volts, -1.5 volts, -1 volt, -0.5 volts, 0 volts, etc.

[0065] Please refer to Figure 6 and Figure 7This application also provides a reproducible programmable non-volatile memory array, comprising: at least one memory block, the memory block including a first memory cell 602, a second memory cell 604, a third memory cell 606, and a fourth memory cell 608; wherein the first memory cell 602, the second memory cell 604, the third memory cell 606, and the fourth memory cell 608 are respectively implemented using a reproducible programmable non-volatile memory structure as described in any of the embodiments of this application; the first memory cell 602 and the third memory cell 606, and the second memory cell 604 and the fourth memory cell 608 are arranged in a centrally symmetrical manner, and the center of symmetry of the first memory cell 602 and the third memory cell 606 is... The centers of symmetry of the second storage unit 604 and the fourth storage unit 608 overlap; the first storage unit 602 and the second storage unit 604, as well as the third storage unit 606 and the fourth storage unit 608, are all arranged axially symmetrically in the second direction, and the axes of symmetry of the first storage unit 602 and the second storage unit 604 and the third storage unit 606 overlap; the first storage unit 602 and the fourth storage unit 608, as well as the second storage unit 604 and the third storage unit 606, are all arranged axially symmetrically in the third direction, and the axes of symmetry of the first storage unit 602 and the fourth storage unit 608 and the second storage unit 604 and the third storage unit 606 overlap. The axes of symmetry overlap; the first direction, the second direction, and the third direction are mutually perpendicular; wherein, the first storage cell 602 and the second storage cell 604 share a first N-type well region terminal (not shown), the third storage cell 606 and the fourth storage cell 608 share a second N-type well region terminal (not shown), the first bit line terminal 702 of the first storage cell 602 and the fourth bit line terminal 710 of the fourth storage cell 608 are connected to the first bit line, the second bit line terminal 704 of the second storage cell 604 and the third bit line terminal 708 of the third storage cell 606 are connected to the second bit line, the first storage cell 602 and the second storage cell 604 share a first word line terminal (not shown) and are connected to the first word line, the third storage cell 606 and the fourth storage cell 608 share a first word line terminal (not shown) and are connected to the first word line, the third storage cell 606 and the fourth storage cell 608 share a first word line terminal (not shown) and are connected to the first word line, the third storage cell 606 and the fourth storage cell 608 share a first word line terminal (not shown) and the fourth ... Unit 606 and the fourth storage unit 608 share a second word line terminal (not shown) and are connected to the second word line. The first storage unit 602 and the second storage unit 604 share a first common terminal 706, and the third storage unit 606 and the fourth storage unit 608 share a second common terminal 712 and are connected to the first common line. The first storage unit 602 and the fourth storage unit 608 share a first erase gate terminal 714, and the second storage unit 604 and the third storage unit 606 share a second erase gate terminal 716 and are connected to the first erase line. The first storage unit 602, the second storage unit 604, the third storage unit 606 and the fourth storage unit 608 share a first P-type well region terminal (not shown).

[0066] In some embodiments, please refer to Figure 6 and Figure 7The reprogrammable non-volatile memory array includes: a first memory block 62, a second memory block 64, a third memory block 66, and a fourth memory block 68; the first memory block 62 and the third memory block 66, and the second memory block 64 and the fourth memory block 68 are arranged in a centrally symmetrical manner, and the center of symmetry of the first memory block 62 and the third memory block 66 overlaps with the center of symmetry of the second memory block 64 and the fourth memory block 68; the first memory block 62 and the second memory block 64, and the third memory block 66 and the fourth memory block 68 are all axially aligned in a second direction. The arrangement is such that the axes of symmetry of the first storage block 62 and the second storage block 64 overlap with the axes of symmetry of the third storage block 66 and the fourth storage block 68; the first storage block 62 and the fourth storage block 68, as well as the second storage block 64 and the third storage block 66, are all arranged axially symmetrically in the third direction, and the axes of symmetry of the first storage block 62 and the fourth storage block 68 overlap with the axes of symmetry of the second storage block 64 and the third storage block 66; the N-type deep well region 204 of the third storage cell 606 and the fourth storage cell 608 in the first storage block 62 is aligned with the fourth storage cell 608. The N-type deep well regions 204 of the first storage cell 602 and the second storage cell 604 in storage block 68 are connected. The N-type deep well regions 204 of the third storage cell 606 and the fourth storage cell 608 in the second storage block 64 are connected to the N-type deep well regions 204 of the first storage cell 602 and the second storage cell 604 in the third storage block 66. The P-type deep well regions 202 of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the fourth storage cell 608 in the first storage block 62 are connected to the second storage cell 604. The P-type deep well regions 202 of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the fourth storage cell 608 in the storage block 64 are connected. The P-type deep well regions 202 of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the fourth storage cell 608 in the third storage block 66 are connected to the P-type deep well regions 202 of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the fourth storage cell 608 in the fourth storage block 68.

[0067] As an example, the N-type deep well regions 204 of the third storage cell 606 and the fourth storage cell 608 in the first storage block 62 are connected to the N-type deep well regions 204 of the first storage cell 602 and the second storage cell 604 in the fourth storage block 68, and are arranged in a loop shape in the top view in the first direction. The N-type deep well regions 204 of the third storage cell 606 and the fourth storage cell 608 in the second storage block 64 are connected to the N-type deep well regions 204 of the first storage cell 602 and the second storage cell 604 in the third storage block 66, and are arranged in a loop shape in the top view in the first direction. The P-type deep well regions 202 of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the fourth storage cell 608 in the first storage block 62 are connected to the P-type deep well regions 202 of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the fourth storage cell 608 in the second storage block 64, and are rectangular in the top view in the first direction. The P-type deep well regions 202 of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the fourth storage cell 608 in the third storage block 66 are connected to the P-type deep well regions 202 of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the fourth storage cell 608 in the fourth storage block 68, and are rectangular in the top view in the first direction.

[0068] In some embodiments, the first storage cell 602 and the fourth storage cell 608 in the first storage block 62 share a first bit line with the first storage cell 602 and the fourth storage cell 608 in the fourth storage block 68; the second storage cell 604 and the third storage cell 606 in the first storage block 62 share a second bit line with the second storage cell 604 and the third storage cell 606 in the fourth storage block 68; the first storage cell 602 and the fourth storage cell 608 in the second storage block 64 share a third bit line with the first storage cell 602 and the fourth storage cell 608 in the third storage block 66; the second storage cell 604 and the third storage cell 606 in the second storage block 64 share a fourth bit line; and the first storage cell 602 and the second storage cell 604 in the first storage block 62 share a second bit line with the first storage cell 604 and the third storage cell 606 in the second storage block 68. Unit 602 and the second storage unit 604 share a first word line. The third storage unit 606 and the fourth storage unit 608 in the first storage block 62 share a second word line with the third storage unit 606 and the fourth storage unit 608 in the second storage block 64. The first storage unit 602 and the second storage unit 604 in the third storage block 66 share a third word line with the first storage unit 602 and the second storage unit 604 in the fourth storage block 68. The third storage unit 606 and the fourth storage unit 608 in the third storage block 66 share a fourth word line with the third storage unit 606 and the fourth storage unit 608 in the fourth storage block 68. The first storage block 62 and the second storage block 64 share a first erase line. The third storage block 66 and the fourth storage block 68 share a second erase line. The first storage block 62 and the fourth storage block 68 share a first common line. The second storage block 64 and the third storage block 66 share a second common line.

[0069] As an example, the first storage cell 602 and the fourth storage cell 608 in the first storage block 62 share the first bit line with the first storage cell 602 and the fourth storage cell 608 in the fourth storage block 68. This includes: the first bit line terminal 702 of the first storage cell 602 in the first storage block 62 and the fourth bit line terminal 710 of the fourth storage cell 608 are connected to the first bit line; the first storage cell 602 and the fourth storage cell 608 in the fourth storage block 68 share the fourth bit line terminal 710; and the fourth bit line terminal 710 of the fourth storage cell 608 in the fourth storage block 68 is connected to the first bit line. The second storage cell 604 and the third storage cell 606 in the first storage block 62 share a second bit line with the second storage cell 604 and the third storage cell 606 in the fourth storage block 68. This includes: the second bit line terminal 704 of the second storage cell 604 in the first storage block 62 and the third bit line terminal 708 of the third storage cell 606 are connected to the second bit line; the second storage cell 604 in the fourth storage block 68 and the third storage cell 606 in the first storage block 62 share a third bit line terminal 708; and the third bit line terminal 708 of the third storage cell 606 in the fourth storage block 68 is connected to the second bit line. The first storage cell 602 and the fourth storage cell 608 in the second storage block 64 share a third bit line with the first storage cell 602 and the fourth storage cell 608 in the third storage block 66. This includes: the first bit line terminal 702 of the first storage cell 602 in the second storage block 64 and the fourth bit line terminal 710 of the fourth storage cell 608 are connected to the third bit line; the first storage cell 602 in the third storage block 66 shares the fourth bit line terminal 710 with the fourth storage cell 608 in the second storage block 64; and the fourth bit line terminal 710 of the fourth storage cell 608 in the third storage block 66 is connected to the third bit line. The second storage cell 604 and the third storage cell 606 in the second storage block 64 share a fourth bit line with the second storage cell 604 and the third storage cell 606 in the third storage block 66. This includes: the second bit line terminal 704 of the second storage cell 604 in the second storage block 64 and the third bit line terminal 708 of the third storage cell 606 are connected to the second bit line; the second storage cell 604 and the third storage cell 606 in the third storage block 66 share the third bit line terminal 708; and the third bit line terminal 708 of the third storage cell 606 in the third storage block 66 is connected to the second bit line.

[0070] As an example, the first storage cell 602 and the second storage cell 604 in the first storage block 62 share a first word line with the first storage cell 602 and the second storage cell 604 in the second storage block 64. This includes: the first storage cell 602 and the second storage cell 604 in the first storage block 62 share a first word line terminal (not shown) and are connected to the first word line; the first storage cell 602 and the second storage cell 604 in the second storage block 64 share a first word line terminal and are connected to the first word line. The third storage cell 606 and the fourth storage cell 608 in the first storage block 62 share a second word line terminal (not shown) and are connected to the second word line; the third storage cell 606 and the fourth storage cell 608 in the second storage block 64 share a second word line terminal and are connected to the second word line. The first storage cells 602 and 604 in the third storage block 66 and the first storage cells 602 and 604 in the fourth storage block 68 share a third word line, including: the first storage cells 602 and 604 in the third storage block 66 share a first word line terminal and are connected to the third word line, and the first storage cells 602 and 604 in the fourth storage block 68 share a first word line terminal and are connected to the third word line. The third storage cells 606 and 608 in the third storage block 66 and the third storage cells 606 and 608 in the fourth storage block 68 share a fourth word line, including: the third storage cells 606 and 608 in the third storage block 66 share a second word line terminal and are connected to the fourth word line, and the third storage cells 606 and 608 in the fourth storage block 68 share a second word line terminal and are connected to the fourth word line.

[0071] As an example, the first storage block 62 and the second storage block 64 share a first erase line, including: the first storage cell 602 and the fourth storage cell 608 in the first storage block 62 share a first erase gate terminal 714, and the second storage cell 604 and the third storage cell 606 share a second erase gate terminal 716 and are connected to the first erase line; the first storage cell 602 and the fourth storage cell 608 in the second storage block 64 share a second erase gate terminal 716 with the second storage cell 604 and the third storage cell 606 in the first storage block 62; and the second storage cell 604 and the third storage cell 606 in the second storage block 64 share a second erase gate terminal 716 and are connected to the first erase line. The third storage block 66 and the fourth storage block 68 share a second erase line, including: the first storage cell 602 and the fourth storage cell 608 in the third storage block 66 share a first erase gate terminal 714 and the second storage cell 604 and the third storage cell 606 share a second erase gate terminal 716 and are connected to the second erase line; the first storage cell 602 and the fourth storage cell 608 in the fourth storage block 68 share the second erase gate terminal 716 with the second storage cell 604 and the third storage cell 606 in the third storage block 66; and the second storage cell 604 and the third storage cell 606 in the fourth storage block 68 share the second erase gate terminal 716 and are connected to the second erase line.

[0072] As an example, the first storage block 62 and the fourth storage block 68 share a first common line, including: the first storage unit 602 and the second storage unit 604 in the first storage block 62 share a first common terminal 706, and the third storage unit 606 and the fourth storage unit 608 share a second common terminal 712 and are connected to the first common line; the first storage unit 602 and the second storage unit 604 in the fourth storage block 68 share a first common terminal 706, and the third storage unit 606 and the fourth storage unit 608 share a second common terminal 712 to the first common line. The second storage block 64 and the third storage block 66 share a second common line, including: the first storage unit 602 and the second storage unit 604 in the second storage block 64 share a first common terminal 706, and the third storage unit 606 and the fourth storage unit 608 share a second common terminal 712 and are connected to the second common line; the first storage unit 602 and the second storage unit 604 in the third storage block 66 share a first common terminal 706, and the third storage unit 606 and the fourth storage unit 608 share a second common terminal 712 and are connected to the second common line.

[0073] As an example, during programming, the first word line terminals of the first storage cell 602 and the second storage cell 604 in the first storage block 62 are grounded based on the first word line; a first positive voltage is applied to the second word line terminals of the third storage cell 606 and the fourth storage cell 608 in the first storage block 62 based on the second word line; a first positive voltage is applied to the first bit line terminal 702 of the first storage cell 602 and the fourth bit line terminal 710 of the fourth storage cell 608 in the first storage block 62 based on the first bit line; the second bit line terminal 704 of the second storage cell 606 and the third bit line terminal 708 of the third storage cell 606 in the first storage block 62 are made to float based on the second bit line; and the first erase gate terminal 714 of the first storage cell 602 and the fourth storage cell 608 in the first storage block 62, the second storage cell 604, and the third storage cell 608 are made to float based on the first erase line. A second positive voltage is applied to the second erase gate terminal 716 of element 606. Based on the first common line, the first common terminal 706 of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the second common terminal 712 of the fourth storage cell 608 in the first storage block 62 are grounded. A first positive voltage is applied to the first N-type well region terminal of the first storage cell 602 and the second storage cell 604 in the first storage block 62. A first positive voltage is applied to the second N-type well region terminal of the third storage cell 606 and the fourth storage cell 608 in the first storage block 62. The first P-type well region terminal of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the fourth storage cell 608 in the first storage block 62 is grounded. In this way, the programming operation of the first storage cell 602 in the first storage block 62 is realized.

[0074] As an example, during the erase operation, the first word line terminals of the first storage cell 602 and the second storage cell 604 in the first storage block 62 are grounded based on the first word line; the second word line terminals of the third storage cell 606 and the fourth storage cell 608 in the first storage block 62 are grounded based on the second word line; the first bit line terminal 702 of the first storage cell 602 and the fourth bit line terminal 710 of the fourth storage cell 608 in the first storage block 62 are floated based on the first bit line; the second bit line terminal 704 of the second storage cell 606 and the third bit line terminal 708 of the third storage cell 606 in the first storage block 62 are floated based on the second bit line; and a third bit line is applied to the first erase gate terminal 714 of the first storage cell 602 and the fourth storage cell 608, and the second erase gate terminal 716 of the second storage cell 604 and the third storage cell 606 in the first storage block 62 based on the first erase line. Positive voltage is applied to the first common terminal 706 of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the second common terminal 712 of the fourth storage cell 608 in the first storage block 62, based on the first common line. The first N-type well region terminals of the first storage cell 602 and the second storage cell 604 in the first storage block 62 are grounded, and the second N-type well region terminals of the third storage cell 606 and the fourth storage cell 608 in the first storage block 62 are grounded or a first negative voltage is applied. In this way, the erase operation of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the fourth storage cell 608 in the first storage block 62 is realized.

[0075] As an example, during a read operation, a second negative pressure is applied to the first word line terminals of the first storage cell 602 and the second storage cell 604 in the first storage block 62 based on the first word line; a second positive pressure is applied to the second word line terminals of the third storage cell 606 and the fourth storage cell 608 in the first storage block 62 based on the second word line; the first bit line terminal 702 of the first storage cell 602 and the fourth bit line terminal 710 of the fourth storage cell 608 in the first storage block 62 are connected to the detection terminal based on the first bit line; the second bit line terminal 704 of the second storage cell 606 and the third bit line terminal 708 of the third storage cell 606 in the first storage block 62 are made to float based on the second bit line; and the first erase gate terminal 714 of the first storage cell 602 and the fourth storage cell 608 in the first storage block 62, the second storage cell 604 and the third storage cell 606 are made to float based on the first erase line. The second erase gate terminal 716 of unit 606 is grounded. A fourth positive voltage is applied to the first common terminal 706 of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the second common terminal 712 of the fourth storage cell 608 in the first storage block 62 based on the first common line. A fourth positive voltage is applied to the first N-type well region terminal of the first storage cell 602 and the second storage cell 604 in the first storage block 62. A fourth positive voltage is applied to the second N-type well region terminal of the third storage cell 606 and the fourth storage cell 608 in the first storage block 62. The first P-type well region terminal of the first storage cell 602, the second storage cell 604, the third storage cell 606, and the fourth storage cell 608 in the first storage block 62 is grounded. In this way, the read operation of the first storage cell 602 in the first storage block 62 is realized.

[0076] In summary, the reprogrammable non-volatile memory structure, array, and operation method of the present invention include: a substrate comprising an N-type deep well region, a P-type deep well region, and a first isolation structure located on the upper surface of the substrate, wherein the N-type deep well region and the P-type deep well region are separated by the first isolation structure; a first region of P-type doped region located on the upper surface of the N-type deep well region, the first region of P-type doped region comprising a first P-type doped region, a second P-type doped region, and a third P-type doped region; wherein the first P-type doped region, the second P-type doped region, and the third P-type doped region are spaced apart from each other; a gate structure located on the substrate between the first P-type doped region and the second P-type doped region; a first floating gate structure located on the substrate between the second P-type doped region and the third P-type doped region; a first region of N-type doped region located on the upper surface of the N-type deep well region on one side of the first region of P-type doped region; and a second region of N-type doped region located on the upper surface of the N-type deep well region. The doped region is located on the upper surface of the P-type deep well region; the second P-type doped region is located on the upper surface of the P-type deep well region and is spaced apart from the second N-type doped region; the second isolation structure is located in the substrate between the second N-type doped region and the second P-type doped region; the second floating gate structure is located on the P-type deep well region next to the second N-type doped region; wherein, the first N-type doped region is led out through the first lead structure as the N-type well region end, the first P-type doped region is led out through the second lead structure as the bit line end, the gate structure is led out through the third lead structure as the word line end, the third P-type doped region is led out through the fourth lead structure as the common terminal, the first floating gate structure and the second floating gate structure are shorted, the second N-type doped region is led out through the fifth lead structure as the erase gate end, and the second P-type doped region is led out through the sixth lead structure as the P-type well region end. This invention utilizes the hot carrier injection effect to program the memory structure and the gate-induced leakage current effect to erase it, thereby avoiding the use of high voltage in programming and erasing, ensuring compatibility with standard I / O voltages, and reducing the area of ​​the memory structure. Furthermore, the multiple-programmable non-volatile memory structure based on the hot carrier effect and gate-induced leakage current effect reduces the coupling ratio requirement to 20%, further reducing the memory structure area. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A reprogrammable non-volatile memory structure, characterized in that, include: The substrate includes an N-type deep well region, a P-type deep well region, and a first isolation structure located on the upper surface of the substrate, wherein the N-type deep well region and the P-type deep well region are separated by the first isolation structure. The first region is a P-type doped region located on the upper surface of the N-type deep well region. The first region includes a first P-type doped region, a second P-type doped region, and a third P-type doped region. The first P-type doped region, the second P-type doped region, and the third P-type doped region are spaced apart from each other. A gate structure is located on a substrate between the first P-type doped region and the second P-type doped region; The first floating gate structure is located on the substrate between the second P-type doped region and the third P-type doped region; The first region is an N-type doped region, located on the upper surface of the N-type deep well region on one side of the first region's P-type doped region; The second region is an N-type doped region located on the upper surface of the P-type deep well region; The second region, a P-type doped region, is located on the upper surface of the P-type deep well region and is spaced apart from the second region, an N-type doped region. The second isolation structure is located within the substrate between the N-type doped region of the second region and the P-type doped region of the second region; The second floating gate structure is located on the P-type deep well region next to the N-type doped region in the second region; In this configuration, the first N-type doped region is led out through a first lead-out structure as an N-type well region terminal, the first P-type doped region is led out through a second lead-out structure as a bit line terminal, the gate structure is led out through a third lead-out structure as a word line terminal, the third P-type doped region is led out through a fourth lead-out structure as a common terminal, the first floating gate structure and the second floating gate structure are shorted, the second N-type doped region is led out through a fifth lead-out structure as an erase gate terminal, and the second P-type doped region is led out through a sixth lead-out structure as a P-type well region terminal.

2. The reprogrammable non-volatile memory structure according to claim 1, characterized in that, The first floating gate structure and the second floating gate structure are fabricated from the same polysilicon. The polysilicon and the N-type deep well region have a first overlapping area in a first direction, and the polysilicon and the P-type deep well region have a second overlapping area in the first direction.

3. The reprogrammable non-volatile memory structure according to claim 1, characterized in that, The overlap area between the first P-type doped region, the second P-type doped region and the gate structure is zero; the overlap area between the third P-type doped region, the second P-type doped region and the first floating gate structure is zero.

4. A reusable programmable non-volatile memory array, characterized in that, include: At least one storage block, the storage block comprising a first storage unit, a second storage unit, a third storage unit, and a fourth storage unit; wherein the first storage unit, the second storage unit, the third storage unit, and the fourth storage unit are respectively implemented using a multiple-programmable non-volatile storage structure as described in any one of claims 1-3; the first storage unit and the third storage unit, and the second storage unit and the fourth storage unit are arranged in a centrally symmetrical manner, and the centers of symmetry of the first storage unit and the third storage unit overlap; the first storage unit and the second storage unit, and the third storage unit and the fourth storage unit are all arranged in an axisymmetric manner in a second direction, and the axes of symmetry of the first storage unit and the second storage unit overlap; the first storage unit and the fourth storage unit, and the second storage unit and the third storage unit are all arranged in an axisymmetric manner in a third direction, and the axes of symmetry of the first storage unit and the fourth storage unit overlap; the first direction, the second direction, and the third direction are mutually perpendicular; In this configuration, the first and second storage units share a first N-type well region terminal, the third and fourth storage units share a second N-type well region terminal, the first bit line terminal of the first storage unit and the fourth bit line terminal of the fourth storage unit are connected to the first bit line, the second bit line terminal of the second storage unit and the third bit line terminal of the third storage unit are connected to the second bit line, the first and second storage units share a first word line terminal and are connected to the first word line, the third and fourth storage units share a second word line terminal and are connected to the second word line, the first and second storage units share a first common terminal and the third and fourth storage units share a second common terminal and are connected to the first common line, the first and fourth storage units share a first erase gate terminal and the second and third storage units share a second erase gate terminal and are connected to the first erase line, and the first, second, third, and fourth storage units share a first P-type well region terminal.

5. The reprogrammable non-volatile memory array according to claim 4, characterized in that, include: A first storage block, a second storage block, a third storage block, and a fourth storage block; the first storage block and the third storage block, as well as the second storage block and the fourth storage block, are arranged in a centrally symmetrical manner, and the centers of symmetry of the first storage block and the third storage block overlap with the centers of symmetry of the second storage block and the fourth storage block; the first storage block and the second storage block, as well as the third storage block and the fourth storage block, are all arranged in an axisymmetric manner in the second direction, and the axes of symmetry of the first storage block and the second storage block overlap with the axes of symmetry of the third storage block; the first storage block and the fourth storage block, as well as the second storage block and the third storage block, are all arranged in an axisymmetric manner in the third direction, and the axes of symmetry of the first storage block and the fourth storage block overlap with the axes of symmetry of the second storage block and the third storage block. The N-type deep well regions of the third and fourth memory cells in the first memory block are connected to the N-type deep well regions of the first and second memory cells in the fourth memory block. The N-type deep well regions of the third and fourth memory cells in the second memory block are connected to the N-type deep well regions of the first and second memory cells in the third memory block. The P-type deep well regions of the first, second, third, and fourth memory cells in the first memory block are connected to the P-type deep well regions of the first, second, third, and fourth memory cells in the second memory block. The P-type deep well regions of the first, second, third, and fourth memory cells in the third memory block are connected to the P-type deep well regions of the first, second, third, and fourth memory cells in the fourth memory block.

6. The reprogrammable non-volatile memory array according to claim 5, characterized in that, The first and fourth storage units in the first storage block share the first bit line with the first and fourth storage units in the fourth storage block. The second and third storage units in the first storage block share the second bit line with the second and third storage units in the fourth storage block. The first and fourth storage units in the second storage block share the third bit line with the first and fourth storage units in the third storage block. The second and third storage units in the second storage block share the fourth bit line with the second and third storage units in the third storage block. The first and second storage units in the first storage block share the... The first word line is described above. The third and fourth storage units in the first storage block share the second word line with the third and fourth storage units in the second storage block. The first and second storage units in the third storage block share the third word line with the first and second storage units in the fourth storage block. The third and fourth storage units in the third storage block share the fourth word line with the third and fourth storage units in the fourth storage block. The first storage block and the second storage block share the first erase line. The third storage block and the fourth storage block share the second erase line. The first storage block and the fourth storage block share the first common line. The second storage block and the third storage block share the second common line.

7. An operation method of a repeatedly programmable non-volatile memory structure as described in any one of claims 1 to 3, characterized in that, include: A first positive voltage is applied to the N-type well region and the bit line, and a second positive voltage is applied to the erase gate. The word line and the common terminal are grounded to program the multiple-programmable non-volatile memory structure based on the hot carrier injection effect; wherein the second positive voltage is less than the first positive voltage; and / or, Ground the N-type well region terminal, the word line terminal, and the common terminal; float the bit line terminal; apply a third positive voltage to the erase gate terminal; ground the P-type well region terminal or apply a first negative voltage to the P-type well region terminal to perform an erase operation on the multiple programmable non-volatile memory structure based on the gate-induced leakage current effect; and / or, A fourth positive voltage is applied to the N-type well region end and the common end, a second negative voltage is applied to the word line end, the erase gate end and the P-type well region end are grounded, and the bit line end is connected to the detection line to perform a read operation on the multiple programmable non-volatile memory structure.

8. The method of operating the reprogrammable non-volatile memory structure according to claim 7, characterized in that, The first positive voltage includes 6 volts to 9 volts; the second positive voltage includes 2.5 volts to 5.5 volts.

9. The method of operating the reprogrammable non-volatile memory structure according to claim 7, characterized in that, The third positive pressure includes 6 volts to 9 volts; the first negative pressure includes -2 volts to 0 volts.

10. The method of operating the reprogrammable non-volatile memory structure according to claim 7, characterized in that, The fourth positive pressure includes 1.8 volts to 3 volts; the second negative pressure includes -2 volts to 0 volts.

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