Semiconductor device, method of manufacturing the same, and memory system

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing the same, the method comprising: forming a first semiconductor structure, the first semiconductor structure comprising: a first semiconductor layer, a stack structure disposed on a first surface of the first semiconductor layer, a first insulating layer disposed on the first semiconductor layer and the stack structure, and a first contact structure penetrating through the first insulating layer and the first semiconductor layer; forming a second insulating layer on a second surface of the first semiconductor layer opposite to the first surface; and simultaneously forming a second contact structure penetrating through the second insulating layer and a source contact, the source contact being in contact with the first semiconductor layer, the second contact structure being in contact with the first contact structure.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on December 10, 2021, with application number 202111506280.X and title "Semiconductor device and manufacturing method thereof and memory system". Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a method of manufacturing the same, and a memory system. Background Technology

[0003] Through improvements in process technology, circuit design, programming algorithms, and manufacturing processes, planar semiconductor devices, such as memory cells, have been shrunk to smaller sizes. However, as the feature size of semiconductor devices approaches its lower limit, planar processes and manufacturing technologies become more challenging and costly. Three-dimensional (3D) semiconductor device architectures can address some of the density limitations in planar semiconductor devices. Summary of the Invention

[0004] According to embodiments of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first semiconductor structure, the first semiconductor structure including: a first semiconductor layer, a stacked structure disposed on a first surface of the first semiconductor layer, a first insulating layer disposed on the first semiconductor layer and the stacked structure, and a first contact structure penetrating the first insulating layer and the first semiconductor layer; forming a second insulating layer on a second surface of the first semiconductor layer opposite to the first surface; and simultaneously forming a second contact structure penetrating the second insulating layer and a source contact, the source contact contacting the first semiconductor layer, and the second contact structure contacting the first contact structure.

[0005] In some embodiments, the first semiconductor structure includes a channel structure extending through the stacked structure, the channel structure including a functional layer and a semiconductor channel, the semiconductor channel being in contact with the first semiconductor layer.

[0006] In some embodiments, forming the first semiconductor layer includes: providing a substrate; forming a sacrificial semiconductor layer on the substrate, the stacked structure being disposed on a first surface of the sacrificial semiconductor layer, the first contact structure penetrating the first insulating layer and the sacrificial semiconductor layer; removing the substrate and the sacrificial semiconductor layer, removing a portion of the functional layer and exposing a portion of the semiconductor channel; and depositing the first semiconductor layer.

[0007] In some embodiments, prior to forming the second insulating layer, the method further includes: forming a second semiconductor structure; and bonding the first semiconductor structure and the second semiconductor structure.

[0008] In some embodiments, forming the second semiconductor structure includes forming a peripheral circuit on a substrate, the peripheral circuit including a plurality of transistors.

[0009] In some embodiments, after bonding the first semiconductor structure and the second semiconductor structure, the first contact structure is connected to the transistor in the second semiconductor structure via an interconnect structure.

[0010] In some embodiments, the first semiconductor layer comprises doped polycrystalline silicon.

[0011] In some embodiments, simultaneously forming a second contact structure and a source contact penetrating the second insulating layer includes: patterning the second insulating layer to form openings in the second insulating layer at positions corresponding to the first contact structure and at positions corresponding to the first semiconductor layer; and filling the openings with a metallic material to form the second contact structure and the source contact, respectively.

[0012] In some embodiments, the metallic material includes tungsten.

[0013] According to embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising forming a sacrificial semiconductor layer; forming a stacked structure on a first surface of the sacrificial semiconductor layer; forming a channel structure extending through the stacked structure to the sacrificial semiconductor layer, the channel structure including a functional layer and a semiconductor channel; forming a first insulating layer on the stacked structure and the sacrificial semiconductor layer; forming a first contact structure extending through the first insulating layer and the sacrificial semiconductor layer; removing the sacrificial semiconductor layer and a portion of the functional layer to expose a portion of the semiconductor channel; and depositing a first semiconductor layer in contact with the semiconductor channel.

[0014] In some embodiments, the method further includes: forming a second insulating layer on a second surface of the first semiconductor layer away from the stacked structure; and simultaneously forming a second contact structure and a source contact through the second insulating layer, the source contact contacting the first semiconductor layer and the second contact structure contacting the first contact structure.

[0015] According to embodiments of this disclosure, a semiconductor device is provided, comprising: a first semiconductor structure, the first semiconductor structure including an array region and a peripheral region, the first semiconductor structure including: a first semiconductor layer located in the array region and the peripheral region; a stacked structure located on a first surface of the first semiconductor layer in the array region; a first insulating layer located on the first semiconductor layer and the stacked structure in the peripheral region; a first contact structure penetrating the first insulating layer and the first semiconductor layer; a second insulating layer located on a second surface of the first semiconductor layer opposite to the first surface; and a second contact structure penetrating the second insulating layer and a source contact, wherein the source contact contacts the first semiconductor layer, and the second contact structure contacts the first contact structure.

[0016] In some embodiments, the semiconductor device further includes a second semiconductor structure bonded to the first semiconductor structure.

[0017] In some embodiments, the second semiconductor structure includes a substrate and peripheral circuitry disposed on the substrate, the peripheral circuitry including a plurality of transistors.

[0018] In some embodiments, the first contact structure is connected to the transistor via an interconnect structure.

[0019] In some embodiments, the first semiconductor structure includes a channel structure extending through the stacked structure, the channel structure including a functional layer and a semiconductor channel, the semiconductor channel being in contact with the first semiconductor layer.

[0020] In some embodiments, the semiconductor device further includes a third insulating layer and a second semiconductor layer, the third insulating layer being disposed on the first surface of the first semiconductor layer, and the second semiconductor layer being disposed between the third insulating layer and the stacked structure.

[0021] In some embodiments, the first semiconductor layer comprises doped polycrystalline silicon.

[0022] In some embodiments, the first insulating layer comprises any one or a combination of silicon oxide, silicon nitride, and silicon oxynitride.

[0023] In some embodiments, the second insulating layer comprises silicon oxide, silicon nitride, silicon oxynitride, and / or other low-k dielectrics.

[0024] In some embodiments, the materials of the second contact structure and the source contact include tungsten.

[0025] In some embodiments, the semiconductor device further includes contact pads that are electrically connected to the second contact structure and the source contact, respectively.

[0026] In some embodiments, the material of the contact pads includes aluminum.

[0027] According to embodiments of the present disclosure, a memory system is provided, comprising: a memory device configured to store data and including a semiconductor device according to embodiments of the present disclosure; and a memory controller coupled to the memory device and configured to control the memory device.

[0028] In some embodiments, the memory system further includes a host coupled to the memory controller and configured to send or receive data. Attached Figure Description

[0029] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0030] Figure 1(a)-1(e) This discloses a manufacturing process for forming contact structures in a 3D memory device according to an embodiment of the present disclosure, the contact structures including source contacts connected to a semiconductor layer in a memory array and contact structures connected to peripheral circuitry in a CMOS array; Figures 2(a)-2(f) This illustrates a manufacturing process for forming a contact structure in a 3D memory device according to another embodiment of the present disclosure, the contact structure including source contacts connected to a semiconductor layer in a memory array and contact structures connected to peripheral circuitry in a CMOS array; Figure 3 This is a flowchart illustrating a method for forming a contact structure in a 3D memory device according to an embodiment of the present disclosure; Figure 4 This shows a cross-sectional view of a 3D memory device according to an embodiment of the present disclosure; Figure 5 A block diagram of an exemplary system having a memory device according to some aspects of this disclosure is shown; Figure 6A Figures are shown of an exemplary memory card having a memory device according to some aspects of this disclosure; and Figure 6B A diagram of an exemplary solid-state drive (SSD) having a memory device according to some aspects of this disclosure is shown.

[0031] Various embodiments will be described with reference to the accompanying drawings. Detailed Implementation

[0032] The subject matter described herein will now be discussed with reference to exemplary embodiments. It should be understood that these embodiments are discussed merely to enable those skilled in the art to better understand and implement the subject matter described herein, and are not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various processes or components may be omitted, substituted, or added as needed in the various examples. For example, the described methods may be performed in a different order than described, and steps may be added, omitted, or combined. Furthermore, features described in some examples may be combined in other examples.

[0033] It should be noted that the use of terms such as "one embodiment," "embodiment," or "some embodiments" in the specification indicates that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such wording does not necessarily refer to the same embodiment. Additionally, when describing specific features, structures, or characteristics in conjunction with embodiments, implementing such features, structures, or characteristics in conjunction with other embodiments, whether explicitly described or not, should be within the knowledge scope of those skilled in the art.

[0034] Generally, terms can be understood at least partly by the context in which they are used. For example, the word "one or more" can be used, at least partly according to context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, words such as "a," "one," or "the" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the word "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the existence of other factors that are not necessarily explicitly stated, again at least partly depending on the context.

[0035] It should be readily understood that “on,” “above,” and “above” in this disclosure should be interpreted in the broadest manner, such that “on” means not only directly on something, but also contained on something with an intermediate feature or layer therebetween, and that “above” or “above” means not only contained on or above something, but also contained on or above something without an intermediate feature or layer therebetween (i.e., directly on something).

[0036] In addition, for ease of explanation, spatial relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used in the text shall be interpreted accordingly.

[0037] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned, or it can remain unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0038] In 3D memory devices formed by fabricating memory arrays and CMOS arrays on different substrates and bonding them together, various contact structures are required to form electrical connections between memory cells in the memory array and peripheral circuitry in the CMOS array, and / or between the 3D memory device and external circuitry. For example, these contact structures include source contacts connected to semiconductor layers in the memory array and contact structures connected to peripheral circuitry in the CMOS array.

[0039] Figure 1(a)-1(e) This discloses a manufacturing process for forming a contact structure in a 3D memory device 100 according to an embodiment of the present disclosure. The contact structure includes a source contact 118 connected to a semiconductor layer 152 in a first semiconductor structure (also referred to as a memory array) 103 and a second contact structure 116 connected to peripheral circuitry in a second semiconductor structure (also referred to as a CMOS array) 107. An external power supply can be connected to the semiconductor layer 152 via the source contact 118. The semiconductor layer 152 is in contact with the semiconductor channel of a NAND memory string 117 in the first semiconductor structure 103, thereby enabling the application of a source voltage to the source terminals of the NAND memory string 117.

[0040] As shown in FIG1(a), after bonding the first semiconductor structure 103 and the second semiconductor structure 107 together and removing the substrate of the first semiconductor structure 103, photoresist 101 is applied over the insulating layer 153 exposed by removing the substrate of the first semiconductor structure 103, and an opening 154 through the photoresist 101 to the insulating layer 153 is patterned by a patterning process. In some embodiments, the material of the insulating layer 153 may include silicon oxide, but is not limited thereto.

[0041] As shown in FIG1(b), using the opening 154 in FIG1(a) as a mask, an appropriate dry etching and / or wet etching process is selected to etch the insulating layer 153 and the semiconductor layer 152 until the end of the first contact structure 115 is exposed to form the opening 154'. In some embodiments, the semiconductor layer 152 may be a doped polysilicon layer.

[0042] As shown in Figure 1(c), a dielectric material is deposited on the insulating layer 153 to form a dielectric layer 158, at which time the opening 154' is also filled with a dielectric material, such as silicon oxynitride. Then, as in Figure 1(a), a photoresist 101 is coated on the dielectric layer 158, and an opening 155 through the photoresist 101 to the dielectric layer 158 is patterned by a patterning process.

[0043] As shown in Figure 1(d), using the opening 155 in Figure 1(c) as a mask, an appropriate dry etching and / or wet etching process is selected to etch the dielectric layer 158 and the insulating layer 153 until the semiconductor layer 152 is exposed to form the opening 155'. Then, the remaining dielectric material is etched away using an appropriate dry etching and / or wet etching process to expose the opening 154'.

[0044] As shown in FIG1(e), openings 154' and 155' are filled with a metallic material to form a second contact structure 116 connected to the first contact structure 115 and a source contact 118 connected to the semiconductor layer 152. In some embodiments, the metallic material includes tungsten, but is not limited thereto. In some embodiments, filling openings 154' and 155' with the metallic material can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0045] like Figure 1(a)-1(e) As shown, in order to form a second contact structure 116 that connects to peripheral circuitry (not shown) in the second semiconductor structure 107 via a first contact structure 115, the second contact structure 116 needs to "penetrate" through the semiconductor layer 152, which serves as the array common source for applying source voltage to the NAND memory string 117, thereby connecting to the first contact structure 115 located below the semiconductor layer 152, where the first contact structure 115 can be further connected to peripheral circuitry in the second semiconductor structure 107. Alternatively, in order to form a source contact 118 connected to the semiconductor layer 152, the source contact 118 only needs to remain on the semiconductor layer 152 without "penetrating" it.

[0046] exist Figure 1(a)-1(e)In the manufacturing process shown, two masks and two photolithography processes are required to form the second contact structure 116 and the source contact 118. Because masks are expensive, [the process utilizes...] Figure 1(a)-1(e) The manufacturing process shown to form the second contact structure 116 and the source contact 118 is relatively complex and relatively expensive.

[0047] Figures 2(a)-2(f) This discloses a manufacturing process for forming a contact structure in a 3D memory device 200 according to another embodiment of the present disclosure. The contact structure includes a source contact 218 connected to a first semiconductor layer 252 in a first semiconductor structure (memory array) 203 and a second contact structure 216 connected to peripheral circuitry in a second semiconductor structure (CMOS array) 207 via an interconnect structure. An external power supply (not shown) can be connected to the first semiconductor layer 252 via the source contact 218. The first semiconductor layer 252 is in contact with the semiconductor channel of a NAND memory string 217 in the first semiconductor structure 203, thereby enabling the application of a source voltage to the source terminals of the NAND memory string 217.

[0048] As shown in FIG2(a), a first semiconductor structure 203 and a second semiconductor structure 207 are bonded together. The first semiconductor structure 203 has an array region 108 and a peripheral region 110. As shown in FIG2(a), the first semiconductor structure 203 is bonded to the second semiconductor structure 207 at a bonding interface 209. The second semiconductor structure 207 may include a substrate 202, a device layer 204, an interconnect layer 205, and a bonding layer 206. The first semiconductor structure 203 may include a substrate 201, a bonding layer 208, an interconnect layer 210, and an array stack 212. The array stack 212 may include a dielectric layer 250, a sacrificial semiconductor layer 251, an insulating layer 256, a semiconductor layer 257, and a plurality of alternating gate conductive layers 239 and dielectric layers 240. The array stack 212 may also include an array of NAND memory strings 217 extending vertically in the plurality of alternating gate conductive layers 239 and dielectric layers 240. The first semiconductor structure 203 may further include one or more first contact structures 215 that extend vertically through the dielectric layer 250 and the sacrificial semiconductor layer 251 and are coupled to the interconnect layer 210. The NAND memory string 217 may be located in the array region 108, and the first contact structures 215 may be located in the peripheral region 110.

[0049] To form the first semiconductor structure 203, a dielectric layer 250, a sacrificial semiconductor layer 251, an insulating layer 256, and a semiconductor layer 257 are sequentially formed on a substrate 201. The substrate 201 can be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. The substrate may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI oxide semiconductors. In some embodiments, the dielectric layer 250, the sacrificial semiconductor layer 251, the insulating layer 256, and the semiconductor layer 257 may be formed by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, the dielectric layer 250 may include silicon oxide. In some embodiments, the sacrificial semiconductor layer 251 may include polycrystalline silicon, but is not limited thereto. In some embodiments, there may be no dielectric layer 250 between the substrate 201 and the sacrificial semiconductor layer 251; that is, the sacrificial semiconductor layer 251 is located directly on the substrate 201. In some embodiments, the insulating layer 256 may include silicon oxide, but is not limited thereto. In some embodiments, the semiconductor layer 257 may include polysilicon, but is not limited thereto.

[0050] Then, a stacked structure is formed on the semiconductor layer 257, for example, a stacked structure comprising multiple alternating gate conductive layers 239 and dielectric layers 240. In some embodiments, a dielectric stack comprising alternating sacrificial layers (not shown) and dielectric layers is formed on the semiconductor layer 257. In some embodiments, the sacrificial layer comprises, for example, silicon nitride, and the dielectric layer comprises, for example, silicon oxide. The alternating sacrificial layer and dielectric layer may be formed by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Subsequently, the stacked structure can be formed by a gate replacement process, for example, by etching the sacrificial layer using a selective wet / dry etching relative to the dielectric layer and replacing the sacrificial layer with a conductive layer to fill the resulting recesses. In some embodiments, the conductive layer may comprise a metal layer, for example, a W layer. It should be understood that in some embodiments, the stacked structure may also be formed by alternating deposition of conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without requiring a gate replacement process. As shown in FIG2(a), the gate conductive layer 239 may extend laterally as a word line to form one or more stepped structures in the array stack 212 located in a stepped region that is part of the array region 108. A plurality of word line contact structures 237 may be formed that extend vertically and fall on the stepped structures, thereby forming an electrical connection between the gate conductive layer 239 and the interconnect layer 210 to be formed.

[0051] NAND memory strings 217 can be formed in the array stack 212. The NAND memory strings 217 extend vertically through the stack structure, and the source ends of the NAND memory strings 217 are in contact with the sacrificial semiconductor layer 251. In some embodiments, the fabrication process of forming the NAND memory strings 217 includes forming channel holes through the stack structure and into the sacrificial semiconductor layer 251 using dry etching and / or wet etching (e.g., deep reactive ion etching (DRIE)), followed by filling the channel holes with multiple layers using a thin film deposition process such as ALD, CVD, PVD, or any combination thereof, for example, the multiple layers may be memory films (e.g., tunneling layers, storage layers, and barrier layers) and semiconductor channels.

[0052] In some embodiments, an interconnect layer 210 is formed over an array of NAND memory strings 217. The interconnect layer 210 may include multiple interconnects located within one or more interlayer dielectric (ILD) layers. The interconnect layer 210 may include mid-process (MEOL) interconnects and / or back-process (BEOL) interconnects located within one or more ILD layers to form electrical connections to the NAND memory strings 217. The interconnects in the interconnect layer 210 also include local interconnects such as bit line contact structures and word line contact structures. In some embodiments, the interconnect layer 210 includes multiple ILD layers formed by various processes and interconnects therein. For example, the interconnects in the interconnect layer 210 may include a conductive material deposited by one or more thin-film deposition processes, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof, and the thin-film deposition processes including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The ILD layer may include a dielectric material deposited by one or more thin-film deposition processes, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-dielectric-constant (low-k) dielectrics, or any combination thereof, and the thin-film deposition processes include but not limited to CVD, PVD, ALD, or any combination thereof. The illustrated ILD layer and interconnects may be collectively referred to as interconnect layer 210. In some embodiments, the interconnects in interconnect layer 210 may include W.

[0053] In some embodiments, a bonding layer 208 is formed over the interconnect layer 210. The bonding layer 208 may include a plurality of bonding contacts 231 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 210 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Then, bonding contacts 231 that penetrate the dielectric layer and contact the interconnects in the interconnect layer 210 can be formed by first patterning contact holes through the dielectric layer using a patterning process (photolithography of the dielectric material in the dielectric layer and dry / wet etching). The contact holes can then be filled with a conductor (e.g., Cu).

[0054] To form the second semiconductor structure 207, a device layer 204 is formed on the substrate 202. The device layer 204 may include a plurality of transistors (not shown) located on the substrate 202. The substrate 202 may be a silicon substrate having monocrystalline silicon. The transistors may be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. These transistors may function as part or all of the peripheral circuitry for controlling the NAND memory string 217. It should be understood that the details used to manufacture the transistors may vary depending on the type of transistor, and therefore, exhaustive details are not given for the purpose of description.

[0055] In some embodiments, an interconnect layer 205 is formed over device layer 204. Interconnect layer 205 may include multiple interconnects located in one or more ILD layers. Interconnect layer 205 may include MEOL interconnects and / or BEOL interconnects located in the multiple ILD layers to achieve electrical connections to transistors in device layer 204. In some embodiments, interconnect layer 205 may include multiple ILD layers formed by various processes and interconnects therein. The ILD layers in interconnect layer 205 may include a dielectric material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The illustrated ILD layers and interconnects may be collectively referred to as interconnect layer 205. In some embodiments, the interconnects in interconnect layer 205 include W.

[0056] In some embodiments, a bonding layer 206 is formed over the interconnect layer 205. The bonding layer 206 may include a plurality of bonding contacts 233 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the top surface of the interconnect layer 205 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Then, bonding contacts 233 that penetrate the dielectric layer and contact the interconnects in the interconnect layer 205 can be formed by first patterning contact holes through the dielectric layer using a patterning process (photolithography of the dielectric material in the dielectric layer and dry / wet etching). The contact holes may be filled with a conductor (e.g., Cu).

[0057] As shown in FIG2(a), the first semiconductor structure 203 (e.g., array stack 212 and NAND memory string 217 formed therethrough) is inverted. The downward bonding layer 208 is bonded to the upward bonding layer 206, i.e., face-to-face, thereby forming a bonding interface 209. That is, the bonding contacts 231 in the bonding layer 208 and the bonding contacts 233 in the bonding layer 206 are bonded at the bonding interface 209. In some embodiments, the bonding surfaces are surface-treated prior to bonding, for example, by plasma treatment, wet treatment, and / or local heat treatment. As a result of bonding (e.g., hybrid bonding), the bonding contacts 231 and 233 located on opposite sides of the bonding interface 209 can be fused together. After bonding, the bonding contacts 231 in bonding layer 208 and the bonding contacts 233 in bonding layer 206 are aligned and in contact with each other, so that the first contact structure 215 and the NAND memory string 217 can be coupled to the transistor in device layer 204 through the bonding contacts across the bonding interface 209.

[0058] As shown in FIG2(b), substrate 201 is removed to expose dielectric layer 250. As shown in FIG2(b), the removal of substrate 201 also exposes the end of the first contact structure 215 in peripheral region 110. In some embodiments, the removal of substrate 201 includes any suitable etching process (e.g., dry etching and / or wet etching) and / or planarization process (e.g., chemical mechanical polishing or CMP).

[0059] As shown in Figure 2(c), the dielectric layer 250 and the sacrificial semiconductor layer 251 exposed in the peripheral region 110 and the array region 108 are removed by selective wet etching (the sacrificial semiconductor layer 251 is removed without the dielectric layer 250), so that the source end protrudes from the first contact structure 215 and the NAND memory string 217. As shown in Figure 2(c), while removing the dielectric layer 250 and the sacrificial semiconductor layer 251, a portion of the memory film (e.g., tunneling layer, storage layer, and barrier layer) is also removed, thereby exposing a portion of the semiconductor channel.

[0060] As shown in Figure 2(d), a first semiconductor 252 is deposited on the surface of the insulating layer 256 exposed by removing the dielectric layer 250 and the sacrificial semiconductor layer 251, and the first contact structure 215 and the first semiconductor layer 252 are planarized. In some embodiments, the first semiconductor 252 is deposited on the surface of the insulating layer 256 by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, the first semiconductor layer 252 is a doped polycrystalline silicon layer, but this embodiment is not limited to this. In some embodiments, the planarization process includes, for example, chemical mechanical polishing. Chemical mechanical polishing can control the first semiconductor layer 252 to a desired thickness, for example, 30 nm-300 nm.

[0061] As shown in FIG2(e), an insulating material is deposited on the first semiconductor layer 252 to form a second insulating layer 253. The insulating material may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or other low-k dielectrics. In some embodiments, the second insulating layer 253 may be deposited on the first semiconductor layer 252 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, after depositing the second insulating layer 253, a patterning process (photolithography and dry / wet etching of the insulating material in the second insulating layer 253) is performed to simultaneously form openings 254 and 255 in the second insulating layer 253 at the locations corresponding to the first contact structure 215 and at the locations where the source contact 218 will be formed. In FIG2(e), openings 254 and 255 are formed in the same patterning process, therefore, according to... Figure 1(a)-1(e) Compared to other embodiments, only one mask is needed.

[0062] As shown in FIG2(f), openings 254 and 255 are filled with a metallic material to form a second contact structure 216 connected to the first contact structure 215 and a source contact 218 connected to the first semiconductor layer 252. In some embodiments, the metallic material includes tungsten, but it should be understood that the metallic material can be other metals.

[0063] After forming the second contact structure 216 connected to the first contact structure 215 and the source contact 218 connected to the first semiconductor layer 252, a first contact pad 219 conductively connected to the second contact structure 216 and a second contact pad 221 conductively connected to the source contact 218 may also be formed. In some embodiments, the first and second contact pads 219 and 221 may comprise aluminum, but it should be understood that this disclosure is not limited thereto, and the first and second contact pads 219 and 221 may also be made of other metallic materials. The steps of forming the first and second contact pads 219 and 221 may include depositing an insulating layer on the second insulating layer 253, then forming openings in the insulating layer at locations corresponding to the first and second contact pads 219 and 221 by, for example, a wet etching process, and finally filling the openings with a suitable metallic material to form the first and second contact pads 219 and 221. It should be noted that the insulating material used for electrically isolating the first and second contact pads 219 and 221 is not shown in FIG2(f).

[0064] and Figure 1(a)-1(e) Compared to the manufacturing process shown, in Figures 2(a)-2(f) In the manufacturing process shown, in order to form the second contact structure 216 connected to the first contact structure 215 and the source contact 218 connected to the first semiconductor layer 252, only one mask and one photolithography process are needed to simultaneously form the second contact structure 216 and the source contact 218, thereby simplifying the process and saving costs.

[0065] Figure 3 This is a flowchart illustrating a method 300 for forming a contact structure in a 3D memory device according to an embodiment of the present disclosure. It should be understood that the operations shown in method 300 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a manner different from... Figure 3 The execution is performed in the order shown.

[0066] refer to Figure 3 Method 300 begins with operation 310, in which a first semiconductor structure is formed, the first semiconductor structure comprising: a first semiconductor layer, a stacked structure disposed on a first surface of the first semiconductor layer, a first insulating layer disposed on the first semiconductor layer and the stacked structure, and a first contact structure penetrating the first insulating layer and the first semiconductor layer. Figure 2(d) shows the corresponding structure, except that it also includes a second semiconductor structure 207 bonded to the first semiconductor structure 203.

[0067] In operation 320, a second insulating layer is formed on the second surface of the first semiconductor layer opposite to the first surface. Figure 2(e) shows the corresponding structure, except that it also shows openings 254, 255 for forming the second contact structure 216 and the source contact 218 in the second insulating layer 253.

[0068] In operation 330, a second contact structure and a source contact are simultaneously formed penetrating the second insulating layer. The source contact contacts the first semiconductor layer, and the second contact structure contacts the first contact structure. Figure 2(f) shows the corresponding structure, except that it also shows the first and second contact pads 219 and 221 connected to the second contact structure 216 and the source contact 218.

[0069] Figure 4 This is a cross-sectional view showing a 3D memory device 400 according to an embodiment of the present disclosure. Figure 4 As shown, the 3D memory device 400 includes a memory array 403 and a CMOS array 407 stacked in different planes in the vertical direction.

[0070] like Figure 4 As shown, the memory array 403 and the CMOS array 407 are bonded face-to-face at the bonding interface 409. The CMOS array 407 may include a substrate 402 and a device layer 404 located on and in contact with the substrate 402. The substrate 402 may include silicon (e.g., single-crystal silicon, i.e., c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material. In some embodiments, the device layer 404 includes peripheral circuitry (…). Figure 4 (Not shown in the image). Peripheral circuitry may include any suitable digital, analog, and / or mixed-signal circuitry for assisting in the operation of the memory cell array in memory array 403. For example, peripheral circuitry may include one or more of page buffers, decoders (e.g., row decoders or column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuitry, charge pumps, voltage sources, or voltage generators. In some embodiments, peripheral circuitry includes multiple transistors, and these transistors may include, for example, planar transistors and 3D transistors.

[0071] like Figure 4 As shown, the CMOS array 407 also includes an interconnect layer 405 located above the device layer 404 to transmit electrical signals to and from peripheral circuits in the device layer 404. Figure 4As shown, interconnect layer 405 may be located vertically between bonding interface 409 and device layer 404. Interconnect layer 405 may include multiple interconnects, including lateral lines and vias. The interconnects may be coupled to transistors of peripheral circuitry in device layer 404. Interconnect layer 405 may also include one or more interlayer dielectric (ILD) layers, in which the lateral lines and vias may be formed. That is, interconnect layer 405 may include lateral lines and vias located in one or more ILD layers. In some embodiments, devices in device layer 404 are coupled to each other through interconnects in interconnect layer 405. Interconnects in interconnect layer 405 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. ILD layers in interconnect layer 405 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0072] like Figure 4 As shown, the CMOS array 407 further includes a bonding layer 406 located above and in contact with the interconnect layer 405. The bonding layer 406 may include a plurality of bonding contacts 433 and a dielectric material electrically isolating the bonding contacts 433. The bonding contacts 433 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts 433 of the bonding layer 406 include Cu. The remaining regions of the bonding layer 406 may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 433 in the bonding layer 406 and the surrounding dielectric can be used for hybrid bonding (also known as “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal (e.g., Cu to Cu) bonding and dielectric-to-dielectric (e.g., SiO2 to SiO2) bonding.

[0073] like Figure 4As shown, the memory array 403 may include a bonding layer 408 located above and in contact with the bonding interface 409. For example, the bonding layer 408 is located on the opposite side of the bonding interface 409 relative to the bonding layer 406 in the CMOS array 407. The bonding layer 408 may include a plurality of bonding contacts 431 and a dielectric that electrically isolates the bonding contacts 431. The bonding contacts 431 may include a conductive material, such as Cu. The remaining regions of the bonding layer 408 may be formed using a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 431 in the bonding layer 408 and the surrounding dielectric may be used for hybrid bonding. In some embodiments, the bonding interface 409 is where the bonding layers 408 and 406 meet and bond. In practice, the bonding interface 409 may be a layer of a certain thickness including the top surface of the bonding layer 406 and the bottom surface of the bonding layer 408.

[0074] like Figure 4 As shown, the memory array 403 also includes an interconnect layer 410 located above and in contact with the bonding layer 408 for transmitting electrical signals. The interconnect layer 410 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 410 may also include local interconnects such as bit line contact structures and word line contact structures. The interconnect layer 410 also includes one or more ILD layers, in which lateral lines and vias may be formed. The interconnects in the interconnect layer 410 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The one or more ILD layers in the interconnect layer 410 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0075] like Figure 4As shown, the memory array 403 may include an array stack 412 located above and in contact with the interconnect layer 410, the array stack 412 including an array of memory cells, such as an array of NAND memory strings 417. Each NAND memory string 417 extends vertically through multiple pairs of gate conductive layers 439 and dielectric layers 440. The stacked and alternating gate conductive layers 439 and dielectric layers 440 are also referred to herein as a stacked structure. Except at the top or bottom of the stacked structure, each gate conductive layer 439 may be adjacent to two dielectric layers 440 on both sides, and each dielectric layer 440 may be adjacent to two gate conductive layers 439 on both sides. The gate conductive layers 439 may all have the same thickness or different thicknesses. Similarly, the dielectric layers 440 may all have the same thickness or different thicknesses. The gate conductive layers 439 may extend laterally as word lines to form one or more stepped structures in the array stack 412. The stepped structure located in the stepped region, which is part of the array region 108, can contact the multiple word line contact structures 437 used to apply voltage to the gate conductive layer 439.

[0076] The number of pairs of gate conductive layers 439 and dielectric layers 440 in the array stack 412 can be one of the factors determining the number of memory cells in the memory cell array. The gate conductive layer 439 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, the gate conductive layer 439 may include a metal layer, such as a tungsten layer. In some embodiments, the gate conductive layer 439 may include a doped polysilicon layer. In some embodiments, the dielectric layer 440 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0077] like Figure 4As shown, each NAND memory string 417 includes a channel structure extending vertically through the stacked structure. In some embodiments, the channel structure includes channel vias filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a columnar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the column to the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In some embodiments, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). The channel structure may further include a channel plug located at the drain terminal of the NAND memory string 417. The channel plug may include polysilicon and may be in contact with a semiconductor channel. In some embodiments, each NAND memory string 417 is a "charge-trapping" type NAND memory string. It should be understood that the NAND memory string 417 is not limited to a "charge-trapping" type NAND memory string, and in other embodiments may be a "floating-gate" type NAND memory string.

[0078] In some embodiments, the NAND memory string 417 may not have any semiconductor plugs located on its source terminals. Instead, the array stack 412 includes a first semiconductor layer 452 located on the stack structure and in contact with the source terminals of the NAND memory string 417. The first semiconductor layer 452 may be in contact with the sidewalls of the semiconductor channel of the channel structure at the source terminal of each NAND memory string 417. The first semiconductor layer 452 may include a semiconductor material, such as doped polysilicon. In some embodiments, the first semiconductor layer 452 may be doped with an N-type dopant, such as phosphorus and / or arsenic. In some embodiments, the first semiconductor layer 452 and the source contacts (not shown) located in the slot structure together act as an array common source (ACS) to apply an erase voltage to the source terminals of the NAND memory string 417, for example, during an erase operation. Additionally, as Figure 4 As shown, a third insulating layer 456 is provided on the surface of the first semiconductor layer 452 facing the stacked structure, and a second semiconductor layer 457 is also provided between the third insulating layer 456 and the stacked structure.

[0079] like Figure 4As shown, in the peripheral region 110 of the memory array 403, the memory array 403 further includes one or more first contact structures 415. These one or more first contact structures 415 extend vertically through the first semiconductor layer 452, the third insulating layer 456, and the second semiconductor layer 457, and are coupled to interconnects in the interconnect layer 410 to achieve electrical connections with peripheral circuitry in the CMOS array 407. In some embodiments, the first contact structure 415 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the first contact structure 415 includes W. In some embodiments, each of the first contact structures 415 may be a through-silicon via (TSC) with a depth on the order of micrometers.

[0080] like Figure 4 As shown, the memory array 403 also includes a second insulating layer 453 located above and in contact with the first semiconductor layer 452. That is, the first semiconductor layer 452 is disposed vertically between the second insulating layer 453 and the NAND memory string 417. The second insulating layer 453 includes a second contact structure 416 directly located above and in contact with the first contact structure 415, and a plurality of source contacts 418 in contact with the first semiconductor layer 452. Figure 4 As shown, the storage array 403 also includes a first contact pad 419 located on and in contact with the second contact structure 416, and a second contact pad 421 located on and in contact with the source contact 418.

[0081] In some embodiments, the first and second contact pads 419 and 421 are capable of transmitting electrical signals between the 3D memory device 400 and an external device. In some embodiments, the second insulating layer 453 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or any combination thereof. The second insulating layer 453 may be a single-layer structure or a multi-layer structure. In some embodiments, the second contact structure 416, the first and second contact pads 419 and 421, and the source contact 418 may all include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or any combination thereof.

[0082] Figure 5 A block diagram of an exemplary system 500 having a memory device according to some aspects of this disclosure is shown. System 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Figure 5 As shown, system 500 may include a host 508 and a memory system 502 having one or more memory devices 504 and a memory controller 506. The host 508 may be a processor of an electronic device such as a central processing unit (CPU), or a system-on-a-chip (SoC) such as an application processor (AP). The host 508 may be configured to send data to or receive data from the memory device 504. In addition to data, the host 508 may also send instructions to the memory system 502 in order to send or receive data to or from the memory device 504.

[0083] Memory device 504 can be any memory device disclosed in this disclosure, such as the 3D memory device 400 disclosed in detail above.

[0084] According to some embodiments, a memory controller 506 is coupled to a memory device 504 and a host 508 and is configured to control the memory device 504. The memory controller 506 can manage data stored in the memory device 504 and communicate with the host 508. In some embodiments, the memory controller 506 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 506 is designed for high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMC) used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 506 can be configured to control the operation of the memory device 504 (e.g., read, erase, and program operations). For example, based on instructions received from host 508, memory controller 506 can transmit various commands such as programming commands, read commands, erase commands, etc., to memory device 504 to control the operation of memory device 504.

[0085] The memory controller 506 can also be configured to manage various functions relating to data stored or to be stored in the memory device 504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 506 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 504. The memory controller 506 can also perform any other suitable functions, such as formatting the memory device 504. The memory controller 506 can communicate with external devices (e.g., the host 508) according to specific communication protocols. For example, the memory controller 506 can communicate with external devices via at least one of the following various interface protocols: for example, USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0086] The memory controller 506 and one or more memory devices 504 can be integrated into various types of storage devices, such as within the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). In other words, the memory system 502 can be implemented and packaged into different types of end electronic products. Figure 6A In one example shown, a memory controller 506 and a single memory device 504 can be integrated into a memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 602 may also include a connection between the memory card 602 and a host computer (e.g., Figure 5 The host 508 is coupled to the memory card connector 604. In such a... Figure 6B In another example shown, the memory controller 506 and multiple memory devices 504 can be integrated into the SSD 606. The SSD 606 may also include interfaces between the SSD 606 and a host (e.g., ...). Figure 5 The host 508 is coupled to the SSD connector 608. In some embodiments, the storage capacity and / or operating speed of the SSD 606 is greater than the storage capacity and / or operating speed of the memory card 602.

[0087] According to embodiments of this disclosure, after removing the substrate of the first semiconductor structure 203 and undergoing subsequent etching, deposition, and planarization processes, the first contact structure 215 formed in the peripheral region 110 of the first semiconductor structure 203 is flush with the first semiconductor layer 252, which serves as the common source of the array for applying source voltage to the NAND memory string 217. Therefore, an opening can be formed in the second insulating layer 253 deposited on the first semiconductor layer 252 using a patterning process. The opening is then filled with conductive metal to simultaneously form a second contact structure 216 penetrating the second insulating layer 253 and a source contact 218. Thus, only one photolithography process with a single mask is needed to simultaneously form the source contact 218 connected to the first semiconductor layer 252 and the second contact structure 216 connected to the first contact structure 215, thereby simplifying the process and significantly reducing costs.

[0088] It should be noted that the steps described above for each process and intermediate step are not mandatory, and some steps can be omitted or added as needed. The execution order of each step is also not fixed and can be determined as needed. For example, the bonding of the memory array 203 to the CMOS array 207 shown in Figure 2(a) can be performed after the formation of the source contact 218 connected to the first semiconductor layer 252, which serves as the common source of the array for applying the source voltage to the NAND memory string 217, and the second contact structure 216 connected to the first contact structure 215.

[0089] The foregoing description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is consistent with the widest scope of the principles and novel features disclosed herein.

Claims

1. A semiconductor device, comprising: The stacked structure includes multiple conductive layers and dielectric layers alternating along a first direction; A first insulating layer is located on one side of the stacked structure along a second direction perpendicular to the first direction; A first semiconductor layer, a third insulating layer, and a second semiconductor layer are stacked along the first direction and located on one side of the stacked structure and the first insulating layer along the first direction. The third insulating layer is located between the first semiconductor layer and the second semiconductor layer along the first direction. A first contact structure extends in the first insulating layer along the first direction, and the dimension of the first contact structure along the first direction is larger than the dimension of the stacked structure along the first direction.

2. The semiconductor device according to claim 1, wherein, The first contact structure is spaced apart from both the first semiconductor layer and the second semiconductor layer.

3. The semiconductor device according to claim 1, wherein, The first contact structure passes through the first semiconductor layer, the third insulating layer, and the second semiconductor layer.

4. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a second insulating layer; the first semiconductor layer is located between the second semiconductor layer and the third insulating layer along the first direction; The first contact pad includes a portion of the second insulating layer located on the side away from the first semiconductor layer. The first contact pad is connected to the first contact structure via a second contact structure that passes through the second insulating layer.

5. The semiconductor device according to claim 4, wherein, The number of the first contact structures includes multiple ones, and the first contact pads are coupled to multiple first contact structures.

6. The semiconductor device according to claim 4, wherein, The materials of the first contact pad and the second contact structure include aluminum.

7. The semiconductor device according to claim 4, wherein, The semiconductor device further includes: a second contact pad; the second contact pad is located on the side of the second insulating layer away from the first semiconductor layer, and the second contact pad is connected to the first semiconductor layer through a source contact; the source contact passes through the second insulating layer and is coupled to the first semiconductor layer.

8. The semiconductor device according to claim 7, wherein, The number of source contacts includes multiple ones, and all of the multiple source contacts are located on the surface of the first semiconductor layer.

9. The semiconductor device according to claim 7, wherein, The source contact and the second contact pad are made of aluminum.

10. The semiconductor device according to any one of claims 1-9, wherein, The second semiconductor layer is located along the first direction on the side of the third insulating layer that is close to the stacked structure and the first insulating layer; The dimension of the first semiconductor layer along the first direction is greater than the dimension of the second semiconductor layer along the first direction.

11. The semiconductor device according to any one of claims 1-9, wherein, The second semiconductor layer is located along the first direction on the side of the third insulating layer that is close to the stacked structure and the first insulating layer; The dimension of the first semiconductor layer along the first direction is larger than the dimension of the third insulating layer along the first direction.

12. The semiconductor device according to any one of claims 1-9, wherein, The materials of the first semiconductor layer and the second semiconductor layer include polycrystalline silicon.

13. The semiconductor device according to any one of claims 1-9, wherein, The second semiconductor layer is located along the first direction on the side of the third insulating layer that is close to the stacked structure and the first insulating layer; The semiconductor device further includes a channel structure that passes through the stacked structure, the second semiconductor layer and the third insulating layer, and extends to the first semiconductor layer.

14. The semiconductor device according to claim 13, wherein, The channel structure includes a functional layer and a semiconductor channel, wherein the semiconductor channel is in contact with the first semiconductor layer in the first direction and the second direction, respectively.

15. The semiconductor device according to any one of claims 1-9, wherein, The semiconductor device further includes peripheral circuitry; the peripheral circuitry is located on the side of the stacked structure and the first insulating layer away from the first semiconductor layer along the first direction.

16. A semiconductor device, comprising: The stacked structure includes multiple conductive layers and dielectric layers alternating along a first direction; A first semiconductor layer, a third insulating layer, and a second semiconductor layer are stacked along the first direction and located on one side of the stacked structure along the first direction. The third insulating layer is located between the first semiconductor layer and the second semiconductor layer along the first direction. The second insulating layer is located on the side of the first semiconductor layer away from the third insulating layer along the first direction; The source contact passes through the second insulating layer and is coupled to the first semiconductor layer.

17. The semiconductor device according to claim 16, wherein, The number of source contacts includes multiple ones, and all of the multiple source contacts are located on the surface of the first semiconductor layer.

18. The semiconductor device according to claim 16, wherein, The semiconductor device further includes a second contact pad; the second contact pad is located on the side of the second insulating layer away from the first semiconductor layer, and the second contact pad is connected to the first semiconductor layer through a source contact.

19. The semiconductor device according to claim 18, wherein, The source contact and the second contact pad are made of aluminum.

20. The semiconductor device according to claim 16, wherein, The semiconductor device further includes: A first insulating layer is located on one side of the stacked structure along a second direction perpendicular to the first direction; the first semiconductor layer, the third insulating layer, and the second semiconductor layer are also located on one side of the first insulating layer along the first direction; and A first contact structure extends in the first insulating layer along the first direction, and the dimension of the first contact structure along the first direction is larger than the dimension of the stacked structure along the first direction.

21. The semiconductor device according to claim 20, wherein, The first contact structure is spaced apart from both the first semiconductor layer and the second semiconductor layer.

22. The semiconductor device according to claim 20, wherein, The first contact structure passes through the first semiconductor layer, the third insulating layer, and the second semiconductor layer.

23. The semiconductor device according to claim 20, wherein, The semiconductor device further includes a first contact pad, the first contact pad including a portion located on the side of the second insulating layer away from the first semiconductor layer, the first contact pad being connected to the first contact structure via a second contact structure, the second contact structure passing through the second insulating layer.

24. The semiconductor device according to claim 23, wherein, The number of the first contact structures includes multiple ones, and the first contact pads are coupled to multiple first contact structures.

25. The semiconductor device according to claim 23, wherein, The materials of the first contact pad and the second contact structure include aluminum.

26. The semiconductor device according to any one of claims 16-25, wherein, The second semiconductor layer is located along the first direction on the side of the third insulating layer closer to the stacked structure; The dimension of the first semiconductor layer along the first direction is greater than the dimension of the second semiconductor layer along the first direction.

27. The semiconductor device according to any one of claims 16-25, wherein, The second semiconductor layer is located along the first direction on the side of the third insulating layer closer to the stacked structure; The dimension of the first semiconductor layer along the first direction is larger than the dimension of the third insulating layer along the first direction.

28. The semiconductor device according to any one of claims 16-25, wherein, The materials of the first semiconductor layer and the second semiconductor layer include polycrystalline silicon.

29. The semiconductor device according to any one of claims 16-25, wherein, The second semiconductor layer is located along the first direction on the side of the third insulating layer closer to the stacked structure; The semiconductor device further includes a channel structure that passes through the stacked structure, the second semiconductor layer and the third insulating layer, and extends to the first semiconductor layer.

30. The semiconductor device according to claim 29, wherein, The channel structure includes a functional layer and a semiconductor channel, wherein the semiconductor channel is in contact with the first semiconductor layer.

31. The semiconductor device according to any one of claims 16-25, wherein, The semiconductor device further includes peripheral circuitry; the peripheral circuitry is located on the side of the stacked structure away from the first semiconductor layer along the first direction.

32. A memory system, comprising: A memory device configured to store data and comprising a semiconductor device according to any one of claims 1-15 or 16-31; as well as A memory controller is coupled to the memory device and configured to control the memory device.

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