Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device capable of suppressing a leakage current and a manufacturing method thereof are provided. The semiconductor device of the present embodiment includes a first configuration and a second configuration. The first configuration includes a plurality of first semiconductor elements. The second configuration is stacked on the first configuration. The second configuration includes a substrate including a first surface and a second surface located on the opposite side of the first surface, a first well region of a first conductivity type provided on the first surface side of the substrate, a second well region of a second conductivity type provided on the first surface side of the substrate in a manner adjacent to the first well region, and a first impurity layer of the first conductivity type provided on at least the second surface side of the first well region and having an impurity concentration higher than that of the first well region. A first conductor is provided between the first configuration and the second configuration and is electrically separated from the substrate.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] NAND flash memory and other semiconductor storage devices sometimes have a stacked structure of an array chip with a storage cell array and a CMOS chip with CMOS (Complementary Metal Oxide Semiconductor) circuitry. Summary of the Invention

[0003] This invention provides a semiconductor device capable of suppressing leakage current and a method for manufacturing the same.

[0004] The semiconductor device of this embodiment includes a first structure and a second structure. The first structure is provided with a plurality of first semiconductor elements. The second structure is stacked on the first structure. The second structure includes: a substrate including a first surface and a second surface located on the opposite side of the first surface; a first well region of a first conductivity type disposed on the first surface side of the substrate; a second well region of a second conductivity type disposed adjacent to the first well region on the first surface side of the substrate; and a first impurity layer of the first conductivity type disposed at least on the second surface side of the first well region, having an impurity concentration higher than that of the first well region. A first conductor is disposed between the first structure and the second structure, electrically isolated from the substrate. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example of the configuration of the storage device according to the first embodiment.

[0006] Figure 2 This is a block diagram illustrating an example of the configuration of the storage device according to the first embodiment.

[0007] Figure 3 This is a perspective view showing an example of the configuration of the storage device according to the first embodiment.

[0008] Figure 4 This is a conceptual diagram illustrating a configuration example of the storage device according to the first embodiment.

[0009] Figure 5 This is a cross-sectional view showing an example of the configuration of the storage device according to the first embodiment.

[0010] Figure 6 This is a cross-sectional view showing an example of the configuration of the memory column of the storage device according to the first embodiment.

[0011] Figure 7 This is a cross-sectional view showing a portion of the first structure of the first embodiment and a configuration example of the second structure.

[0012] Figure 8 This is a cross-sectional view showing an example of a manufacturing method for a second structure of the storage device according to the first embodiment.

[0013] Figure 9 It means to continue Figure 8 A cross-sectional view of an example of the manufacturing method of the second structure.

[0014] Figure 10 It means to continue Figure 9 A cross-sectional view of an example of the manufacturing method of the second structure.

[0015] Figure 11 It means to continue Figure 10 A cross-sectional view of an example of the manufacturing method of the second structure.

[0016] Figure 12 It means to continue Figure 11 A cross-sectional view of an example of the manufacturing method of the second structure.

[0017] Figure 13 It means to continue Figure 12 A cross-sectional view of an example of the manufacturing method of the second structure.

[0018] Figure 14 It means to continue Figure 13 A cross-sectional view of an example of the manufacturing method of the second structure.

[0019] Figure 15 It means to continue Figure 14 A cross-sectional view of an example of the manufacturing method of the second structure.

[0020] Figure 16 This is a cross-sectional view showing an example of a manufacturing method for a second structure of the storage device according to the second embodiment.

[0021] Figure 17 This is a cross-sectional view showing an example of a manufacturing method for a second structure of the storage device according to the second embodiment.

[0022] Figure 18 This is a cross-sectional view showing an example of a manufacturing method for a second structure of the storage device according to the second embodiment.

[0023] Figure 19 This is a cross-sectional view showing a configuration example of the second structure of the storage device according to the fourth embodiment.

[0024] Figure 20 This is a cross-sectional view showing a configuration example of the second structure of the storage device according to the fifth embodiment.

[0025] Figure 21 This is a cross-sectional view showing an example of the configuration of the storage device according to the sixth embodiment.

[0026] Figure 22 This is a table showing the relationship between the impurity concentration of the impurity layer that has not formed an inversion layer and the distance from the conductor to the p-well region. Detailed Implementation

[0027] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual. In the description and drawings, the same elements are labeled with the same reference numerals.

[0028] In this specification and claims, the term "connected" to a first element and another second element includes the first element being directly, consistently, or selectively connected to the second element via an element that is conductive. Furthermore, in this specification and figures, the +Z direction is represented as upward and the -Z direction as downward, but as... Figure 8 and Figure 9 As shown, sometimes the -Z direction is set upwards and the +Z direction is set downwards, which is the opposite.

[0029] (First Implementation)

[0030] Figure 1 This is a block diagram illustrating a configuration example of the storage device according to the first embodiment. Storage device 1, as an example of a semiconductor device, is a device that uses storage cells to store data. Storage device 1 is, for example, a NAND flash memory. Storage device 1 is controlled by an external memory controller. Storage device 1 operates, for example, based on instructions CMD and address information ADD received from the memory controller. Storage device 1 receives written data DAT and outputs the data stored in storage device 1.

[0031] The storage device 1 includes components such as a storage cell array 10, a line decoder 11, a register 12, a sequencer 13, a voltage generation circuit 14, a driver 15, and a sensing amplifier 17.

[0032] The memory cell array 10 is a collection of arranged memory cells. The memory cell array 10 contains multiple memory blocks (BLKs). Each BLK contains multiple memory cell transistors MT (refer to...). Figure 2 The area containing the memory cell array 10 also includes word lines WL (see reference). Figure 2 ) and bit line BL (refer to Figure 2 Wiring, etc.

[0033] The line decoder 11 is a circuit used to select a block BLK. The line decoder 11 transmits the voltage supplied from the driver 15 to a block BLK selected based on the block address received by the line decoder 11 from the register 12.

[0034] Register 12 is a circuit that holds the instruction CMD and address information ADD received from storage device 1. The instruction CMD directs the sequencer 13 to perform various actions, including data reading, data writing, and data deletion. The address information ADD specifies the access object in storage cell array 10.

[0035] The sequencer 13 is a circuit that controls the overall operation of the storage device 1. Based on the instruction CMD received by the sequencer 13, the sequencer 13 controls the line decoder 11, the driver 15, and the sense amplifier 17 to perform various actions including data reading, data writing, and data deletion.

[0036] The voltage generation circuit 14 is a circuit that generates multiple voltages of different magnitudes. The voltage generation circuit 14 receives a power supply voltage from an external source of the storage device 1 and generates multiple voltages based on the power supply voltage. The voltage generation circuit 14 supplies the generated voltages to components such as the storage cell array 10, the driver 15, and the sense amplifier 17.

[0037] The driver 15 is a circuit that applies various voltages required for the operation of the storage device 1 to several components. The driver 15 receives multiple voltages from the voltage generation circuit 14 and supplies a selected voltage from the multiple voltages to one or more line decoders 11.

[0038] The sense amplifier 17 is a circuit that outputs a signal based on the data stored in the memory cell array 10. The sense amplifier 17 senses the state of the memory cell transistor MT (hereinafter also simply referred to as the memory cell) and generates read data based on the sensed state. The sense amplifier 17 applies a voltage based on the write data to the bit line BL.

[0039] Figure 2 This is a block diagram illustrating an example configuration of the storage device according to the first embodiment. Multiple block BLKs, for example, all block BLKs contain... Figure 2 The constituent elements and connections are shown.

[0040] A block BLK contains multiple string units SU. Figure 2 This represents an example of five string units SU_0 to SU_4.

[0041] like Figure 2 As shown, m bit lines BL_0 to BL_m-1 are connected to a NAND string NS from each string unit SU_0 to SU_4 in each BLK block. m is a positive integer.

[0042] Each NAND string NS contains one select-gate transistor ST, n memory cell transistors MT (MT_0 to MT_n-1), and one select-gate transistor DT (DT_0, DT_1, DT_2, DT_3, or DT_4). n is a positive integer. The memory cell transistor MT functions as a memory cell, a non-volatile data storage element. The memory cell transistor MT includes a control gate electrode or gate electrode (word line WL) and a charge accumulation film insulated from the surroundings. Data is stored non-volatilely based on the charge in the charge accumulation film. Data is written to the memory cell transistor MT by injecting electrons into the charge accumulation film.

[0043] Select gate transistor ST, memory cell transistors MT_0 to MT_n-1, and select gate transistor DT are connected in series between source line SL and a bit line BL.

[0044] Multiple NAND strings NS connected to different bit lines BL constitute a string cell SU. In each string cell SU, the control gate electrodes of the memory cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1 respectively. The group of memory cell transistors MT that share word line WL in a string cell SU is called a single cell CU.

[0045] Gate transistors DT_0 to DT_4 are selected to belong to serial units SU_0 to SU_4, respectively. Figure 2 In the diagram, the gate select transistors DT_2, DT_3, and DT_4 are omitted from the illustration. The gates of the gate select transistors DT0 for each of the multiple NAND strings NS in string unit SU_0 are connected to the gate select line SGDL_0. Similarly, the gates of the gate select transistors DT_1, DT_2, DT_3, and DT_4 for each of the multiple NAND strings NS in string units SU_1, SU_2, SU_3, and SU_4 are connected to the gate select lines SGDL_1, SGDL_2, SGDL_3, and SGDL_4, respectively.

[0046] The gate of the select gate transistor ST is connected to the select gate line SGSL.

[0047] Figure 3 This is a perspective view showing a configuration example of the storage device according to the first embodiment. The storage device 1 includes a first structure 100, a second structure 200, and a third structure 300. The first structure 100, the second structure 200, and the third structure 300 extend along the XY plane and are stacked in the Z direction. The second structure 200 is located on the surface (upper surface) of the first structure 100 in the Z direction. The third structure 300 is located on the upper surface of the second structure 200.

[0048] The first structure 100, the second structure 200, and the third structure 300 each include a plurality of semiconductors, a plurality of various conductors, and a plurality of insulators formed on a substrate using a substrate. The first structure 100, the second structure 200, and the third structure 300 each include a plurality of elements and wiring implemented by semiconductors, conductors, and insulators. The first structure 100, the second structure 200, and the third structure 300 each include a circuit containing elements and wiring. The elements and wiring in the first structure 100, the second structure 200, and the third structure 300 are electrically connected to each other. The first structure 100, the second structure 200, and the third structure 300 are each formed as a separate semiconductor chip. The first structure 100, the second structure 200, and the third structure 300 are bonded together to form a semiconductor chip for a storage device 1.

[0049] The first configuration 100 and the second configuration 200 both include a line decoder 11, a register 12, a sequencer 13, a voltage generation circuit 14, a driver 15, and a sense amplifier 17. The first configuration 100 includes any of the following components: the line decoder 11, the register 12, the sequencer 13, the voltage generation circuit 14, the driver 15, and the sense amplifier 17. The second configuration 200 includes any of the following components: the line decoder 11, the register 12, the sequencer 13, the voltage generation circuit 14, the driver 15, and the sense amplifier 17. For example, the first configuration 100 includes semiconductor elements constituting the line decoder 11, the register 12, the sequencer 13, the voltage generation circuit 14, and the driver 15. The second configuration 200 includes semiconductor elements constituting the sense amplifier 17. The line decoder 11, register 12, sequencer 13, voltage generation circuit 14, driver 15, and sense amplifier 17 are composed of CMOS (Complementary Metal-Oxide Semiconductor) circuits including p-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and n-type MOSFETs. The first configuration 100 and the second configuration 200 are, for example, CMOS chips containing such CMOS circuits.

[0050] The third structure 300 is, for example, an array chip including a memory cell array 10 and a plurality of external connection terminals PD. The external connection terminals PD are exposed on the upper surface of the third structure 300.

[0051] Figure 4 This is a conceptual diagram illustrating a configuration example of the storage device according to the first embodiment. Figure 4 Will Figure 3 The decomposition representation of .

[0052] The first configuration 100 includes a plurality of conductive connection terminals BP1. The connection terminals BP1 are exposed on the upper surface of the first configuration 100. The connection terminals BP1 are connected to components in the first configuration 100.

[0053] The second structure 200 includes multiple conductive connection terminals BP2L and multiple conductive connection terminals BP2U. The connection terminals BP2L are exposed on the -Z direction side (lower surface) of the second structure 200. The connection terminals BP2L are connected to components in the second structure 200. The connection terminals BP2L have the same layout as the connection terminals BP1 of the first structure 100. The connection terminals BP2L are arranged such that when the first structure 100 and the second structure 200 are connected, each connection terminal BP2L contacts one of the connection terminals BP1 of the first structure 100 corresponding to that connection terminal BP2L. A specific connection terminal BP2L and the connection terminal BP1 of the first structure 100 corresponding to that specific connection terminal BP2L are elements that function as the same node in the circuit.

[0054] The engagement terminal BP2U is exposed on the upper surface of the second structure 200. The engagement terminal BP2U is connected to the components in the second structure 200.

[0055] The third structure 300 includes a plurality of conductive connection terminals BP3. The connection terminals BP3 are exposed on the lower surface of the third structure 300. The connection terminals BP3 are connected to components in the third structure 300. The connection terminals BP3 have the same layout as the connection terminals BP2U of the second structure 200. The connection terminals BP3 are arranged such that when the second structure 200 and the third structure 300 are joined, each connection terminal BP3 contacts one of the connection terminals BP2U of the second structure 200 corresponding to that connection terminal BP3. A particular connection terminal BP3 and the connection terminal BP2U of the second structure 200 corresponding to that particular connection terminal BP3 are elements that function as the same node in the circuit.

[0056] In addition, the connection between the first to third structures 100 to 300 is sometimes achieved by through electrode TSV instead of using a joint terminal.

[0057] Figure 5 This is a cross-sectional view showing an example of the configuration of the storage device according to the first embodiment. The first structure 100 is attached to and stacked on the second surface F2 side of the substrate W2 of the second structure 200. The third structure 300 is attached to and stacked on the first surface F1 side of the substrate W2 of the second structure 200.

[0058] The first structure 100 further includes a substrate W1, a transistor Tr1, contacts CS1, C0, C1, C2 and C3, conductors L0, L1, L2 and L10, and an insulator 21. In the following description, the conductors may also comprise metallic materials or semiconductors that are conductive by containing impurities. In one example, the substrate W1 comprises silicon. In one example, the contacts CS1, C0, C1, C2 and C3, and the conductors L0, L1, L2 and L10 comprise copper or tungsten. In one example, the insulator 21 comprises silicon oxide.

[0059] Transistor Tr1 is located above and near the upper surface of substrate W1. Transistor Tr1 includes a gate insulator on the upper surface of substrate W1, a gate electrode on the upper surface of the gate insulator, and a pair of source / drain regions sandwiching the lower region of the gate electrode. Transistor Tr1 is electrically connected to one of conductors (e.g., word lines WL) 31, 33, and 36 via a conductor (e.g., wiring) L10 and a through electrode TSV. Thus, transistor Tr1 of the first configuration 100 can constitute a driver (driving circuit) 15 for controlling the voltage of conductors 31, 33, and 36.

[0060] Each contact C0 has its lower surface in contact with the upper surface of the gate electrode of a transistor Tr1. Each contact CS1 has its lower surface in contact with a source / drain region.

[0061] Each conductor L0 is in contact with a contact C0 or CS1 on its lower surface. Each contact C1 is in contact with the upper surface of a conductor L0 on its lower surface.

[0062] Each conductor L1 has its lower surface in contact with the upper surface of a contact C1. Each contact C2 has its lower surface in contact with the upper surface of a conductor L1.

[0063] Each conductor L2 has its lower surface in contact with the upper surface of a contact C2. Each contact C3 has its lower surface in contact with the upper surface of a conductor L2.

[0064] Each conductor L10 has its lower surface in contact with the upper surface of a contact C3. In one example, the conductor L10 comprises copper (Cu), aluminum (Al), and / or tungsten (W). The through electrode TSV has its lower surface in contact with the upper surface of one of the conductors L10. The conductor L10 and Figure 1 The voltage generating circuit 14 is electrically connected and receives a high positive voltage. A conductor L10 is disposed on the surface of the substrate W1 through an insulator 21. The conductor L10 is electrically connected to the transistor Tr1 of the first structure 100 via contacts C1 to C3, etc. In addition, the conductor L10 is electrically connected to the conductors 31, 33 or 36 of the third structure 300 via through electrodes TSV, etc.

[0065] The transistor Tr1, contacts CS1, C0, C1, C2 and C3, and conductors L0, L1, L2 and L10 form the circuit included in the first configuration 100. Therefore, the first configuration 100 has transistors Tr1, contacts CS1, C0, C1, C2 and C3, and conductors L0, L1, L2 and L10 of arbitrary shape and configuration that implement the circuit included in the first configuration 100.

[0066] The insulator 21 is provided from the height of the upper surface of the substrate W1 to the height of the upper surface of the contact C3. The insulator 21 is embedded in the area of ​​the first structure 100 where no constituent elements are provided, that is, the area where transistor Tr1, contacts CS1, C0, C1, C2 and C3, and conductors L0, L1, L2 and C10 are not provided.

[0067] exist Figure 5 In the example, the connection between the first structure 100 and the second structure 200 is achieved using a through electrode TSV. Of course, as shown in reference... Figure 4 As explained, the bonding terminal BP1 can also be disposed within the insulator 21 and connected to the bonding terminal BP2L of the second configuration 200. In this case, the insulator 21 is embedded in the area where neither the through electrode TSV nor the bonding terminal BP1 is disposed.

[0068] The second structure 200 further includes a substrate W2, a transistor Tr2, contacts CS2, CS5, C7, C8, C9 and C10, conductors L4, L5 and L6, and insulators 25, 26 and 27. The substrate W2 includes a first surface F1 and a second surface F2 located opposite to the first surface F1. In one example, the substrate W2 contains silicon. The thickness of the substrate W2 is, for example, 0.2 to 2 μm. In one example, contacts CS2, CS5, C7, C8, C9 and C10, and conductors L4, L5 and L6 contain copper or tungsten. In one example, insulators 25, 26 and 27 contain silicon oxide. The upper surface of the second structure 200 is located on the first surface F1 side of the substrate W2, and the lower surface of the second structure 200 is located on the second surface F2 side of the substrate W2.

[0069] As mentioned above, in Figure 5 In the example, the connection between the first structure 100 and the second structure 200 is achieved using a through electrode TSV. Of course, as shown in reference... Figure 4 As explained, the bonding terminal BP2L can also be disposed within the insulator 25 and connected to the bonding terminal BP1 of the first configuration 100. In this case, the insulator 25 is embedded in the area where neither the through electrode TSV nor the bonding terminal BP2L is disposed.

[0070] An insulator 25 extends from the height of the upper surface of the insulator 21 of the first structure 100 to the second surface F2. The insulator 25 is disposed between the impurity layer AR and the conductor L10. The insulator 25 is embedded in the region above the insulator 21 of the first structure 100 where no through electrode TSV is disposed.

[0071] Substrate W2 is located on the upper surface of insulator 25. Through electrode TSV extends through substrate W2, passing over its first surface F1 and second surface F2. Through electrode TSV contacts the lower surface of conductor L4 on its upper surface. Through electrode TSV contacts the upper surface of conductor L10 within the first structure 100 on its lower surface. Insulator SP extends through substrate W2, passing over both its upper and lower surfaces. Each insulator SP covers a side of one through electrode TSV. Through electrode TSV is electrically separated from substrate W2 through insulator SP.

[0072] Transistor Tr2 is disposed on the first surface F1 side of substrate W2. Transistor Tr2 includes a gate insulator on the upper surface of substrate W2, a gate electrode on the upper surface of the gate insulator, and a pair of source / drain regions sandwiching the lower region of the gate electrode. Transistor Tr2 is electrically connected to a semiconductor layer SM of memory pillar MP. Thus, transistor Tr2 of the second configuration 200 constitutes a sense amplifier 17 for detecting data stored in the memory cell via the semiconductor layer SM of memory pillar MP.

[0073] Each contact C7 has its lower surface in contact with the upper surface of the gate electrode of a transistor Tr2. Each contact CS2 has its lower surface in contact with a source / drain region. Each contact CS5 has its lower surface in contact with the upper surface of a conductor L4.

[0074] Each conductor L4 has its lower surface in contact with the upper surface of a contact C7, CS2, or TSV. Each contact C8 has its lower surface in contact with the upper surface of a conductor L4.

[0075] Each conductor L5 has its lower surface in contact with the upper surface of a contact C8. Each contact C9 has its lower surface in contact with the upper surface of a conductor L5.

[0076] Each conductor L6 has its lower surface in contact with the upper surface of a contact C9. Each contact C10 has its lower surface in contact with the upper surface of a conductor L6.

[0077] The transistor Tr2, contacts CS2, CS5, C7, C8, C9 and C10, and conductors L4, L5 and L6 form the circuit included in the second configuration 200. Therefore, the second configuration 200 has transistors Tr2, contacts CS2, CS5, C7, C8, C9 and C10, and conductors L4, L5 and L6 of arbitrary shape and configuration that implement the circuit included in the second configuration 200.

[0078] The insulator 26 extends from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10. The insulator 26 is embedded in the area from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10 where no constituent elements are provided, that is, in the area where transistor Tr2, contacts CS2, CS5, C7, C8, C9 and C10, and conductors L4, L5 and L6 are not provided.

[0079] Each mating terminal BP2U contacts the upper surface of a contact C10 on its lower surface. The insulator 27 is embedded in the area of ​​the layer containing the mating terminal BP2U where no mating terminal BP2U is provided.

[0080] The third structure 300 also includes contacts C11, C12 and C13, conductors L7, L8, 31, 33, 36 and 38, insulators 29, 34, 35, 37, 40 and 41, and memory pillars MP.

[0081] Each bonding terminal BP3 is located in the lowest layer of the third structure 300. The insulator 29 is embedded in the area of ​​the layer where the bonding terminal BP3 is located where no bonding terminal BP3 is provided.

[0082] Each contact C11 is in contact with the upper surface of a mating terminal BP3 on its lower surface.

[0083] Each conductor L7 has its lower surface in contact with the upper surface of a contact C11. Each contact C12 has its lower surface in contact with the upper surface of a conductor L7.

[0084] Each conductor L8 is in contact with the upper surface of a contact C12 on its lower surface.

[0085] Conductor 31 is located above conductor L8. Conductor 31 has a plate-like shape along the XY plane. Conductor 31 functions as at least a part of the select gate line SGDL. The lower surface of conductor 31 is exposed at its end and has a stepped surface.

[0086] Insulator 32 is located on the upper surface of conductor 31. Insulator 32 has a plate-like shape along the XY plane.

[0087] Conductors 33 and insulators 34 are stacked alternately one on one along the Z-direction on the upper surface of insulator 32 to form a laminate. Conductors 33 and insulators 34 have a plate-like shape along the XY plane. Each conductor 33 functions as at least a part of the word line WL. Figure 5 This represents an example where n=8, meaning the number of memory cell transistors MT is 8. Conductors 33, from bottom to top, function as at least a portion of word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7. The lower surface of each conductor 33 is exposed at its end and has a stepped surface.

[0088] The insulator 35 is located on the upper surface of the uppermost conductor 33.

[0089] Conductor 36 is located on the upper surface of insulator 35. Conductor 36 functions as at least a part of the select gate line SGSL.

[0090] Insulator 37 is located on the upper surface of conductor 36. Conductor 38 is located on the upper surface of insulator 37. The lower surface of conductor 38 is exposed at its end and has a stepped surface. Conductor 38 functions, for example, as a source layer.

[0091] Memory pillars MP extend along the Z-axis, penetrating the stack of conductors 31, 33, and 36, and insulators 32, 34, 35, and 37. Each memory pillar MP includes an insulator CI, a semiconductor layer SM, and a memory film SS penetrating the stack. The semiconductor layer SM covers the side surface of the insulator CI. The memory film SS covers the side surface of the semiconductor layer SM and is disposed between the semiconductor layer SM and the stack. The memory film SS has an opening at the upper end of the memory pillar MP. A portion of the semiconductor layer SM is located in the opening and contacts the conductor 38 on its upper surface.

[0092] Alternatively, the upper part of the memory column MP may be located in the conductor 38, and the memory film SS may have an opening in the part facing the conductor 38, with a part of the conductor 38 located in the opening.

[0093] The portion of each memory pillar MP facing conductor 31 functions as a select gate transistor DT. The portion of each memory pillar MP facing conductor 33 functions as a memory cell transistor MT. That is, the memory pillar MP forms a memory cell at the intersection with one of the multiple conductors 33. The portion of each memory pillar MP facing conductor 36 functions as a select gate transistor ST. The lower surface of the semiconductor layer SM is exposed on the lower surface of each memory pillar MP. The lower surface of the semiconductor layer SM is exposed on the upper surface of each memory pillar MP. Thus, the third configuration 300 is configured as an array chip containing an array of memory cells.

[0094] Each contact C13 is in contact with the upper surface of a conductor L8 on its lower surface. Several contacts C13 are in contact with the lower surface of the semiconductor layer SM of a memory pillar MP on their upper surfaces. Several contacts C13 are in contact with the lower surface of a portion of a stepped surface of conductors 31, 33 and 36 on their upper surfaces.

[0095] The insulator 40 extends from the height of the upper surface of the insulator 29 to the height of the upper surface of the conductor 38. The insulator 40 is embedded in the area of ​​the third structure 300 where no constituent elements are provided, namely, the area where contacts C11, C12 and C13, conductors L7, L8, 31, 33, 36, 38, insulators 40, 32, 34, 35, 37 and memory pillar MP are not provided.

[0096] Insulator 41 is located on the upper surface of conductor 38 and insulator 40 respectively.

[0097] Figure 6 This is a cross-sectional view showing an example of the configuration of the memory column of the storage device according to the first embodiment. Figure 6 This represents the construction of a cross-section of the memory column along the XY plane. In one example, the memory film SS comprises a tunnel insulator TI, a charge storage film CA, and a barrier insulator BI.

[0098] The tunnel insulator TI surrounds the sides of the semiconductor layer SM. The charge storage film CA surrounds the sides of the tunnel insulator TI. The barrier insulator BI surrounds the sides of the charge storage film CA. Conductors 31, 33, or 36 surround the sides of the barrier insulator BI.

[0099] The semiconductor layer SM functions as a current path for the memory cell transistor MT and the select gate transistors DT and ST. In one example, the tunnel insulator TI and the barrier insulator BI are both composed of silicon oxide. The charge storage film CA stores charge. In one example, the charge storage film CA is composed of silicon nitride.

[0100] Figure 7 This is a cross-sectional view showing a portion of the first structure of the first embodiment and a configuration example of the second structure. Figure 7 This refers to the substrate W2 of the second structure 200 and the structure around it.

[0101] The second structure 200 also includes a device separation section STI (Shallow Trench Isolation), an n-well region nw, a p-well region pw, and an impurity layer AR. The number of p-well regions pw and n-well regions nw is not particularly limited.

[0102] The substrate W2 contains p-type impurities. Examples of p-type impurities include boron (B).

[0103] The n-well region nw is located between two adjacent element separation sections (STI). The n-well region nw extends from the upper surface of the substrate W2 to the lower surface. The n-well region nw contains n-type impurities. Examples of n-type impurities include phosphorus (P) and arsenic (As).

[0104] The p-well region pw is located between two adjacent element separation sections STI. The p-well region pw extends from the upper surface of the substrate W2 to the lower surface. The p-well region pw contains p-type impurities. In one example, the p-well region pw contains 1 × 10⁻⁶ impurities in the region including the boundary with the insulator 25. 14 atoms / cm 3 Above and 2×10 16 atoms / cm 3 The following are concentrations of p-type impurities. In one example, the impurity concentration is the average concentration.

[0105] The component separation section (STI) is disposed between multiple adjacent transistors Tr2_p and Tr2_n, extending along the -Z direction from the first surface F1 of the substrate W2 toward the second surface F2. As an example, the component separation section STI is made of an insulating material such as silicon oxide. Thus, the component separation section STI electrically separates the adjacent n-well region nw and p-well region pw near the first surface F1.

[0106] An impurity layer AR is disposed at the bottom of the second surface F2 side of both the n-well region nw and the p-well region pw. Alternatively, the impurity layer AR can be disposed on the entire second surface F2 of the substrate W2. That is, the impurity layer AR is located between the substrate W2 and the insulator 25. The impurity layer AR is a p-type impurity layer with a higher p-type impurity concentration than the p-well region pw. + Type of impurity layer. The impurity layer AR contains, for example, boron as an impurity. The appropriate impurity concentration of the impurity layer AR depends on the distance from the conductor L10 to the p-well region pw (the film thickness of the insulators 21 and 25), but is within the range of... Figure 22 The relationship, as shown in the curve graph, is preferably at least 5.0 × 10⁻⁶. 16 atoms / cm 3 The peak impurity concentration in the impurity layer AR is located near the second surface F2 of substrate W2. This will be discussed later. Figure 22 Describe the impurity concentration in the impurity layer AR.

[0107] The impurity layer AR can contain some carbon. Carbon can suppress the diffusion of p-type impurities, keeping the thickness of the impurity layer AR thin and the impurity concentration high.

[0108] The impurity layer AR can also be maintained at the same voltage as the p-well region pw. For example, the impurity layer AR can also be set to ground voltage. Alternatively, the impurity layer AR can also be in a floating state.

[0109] Transistor Tr2 comprises a p-type transistor Tr2_p and an n-type transistor Tr2_n. Transistors Tr2_p and Tr2_n are MOSFETs constituting the aforementioned CMOS. Transistors Tr2_p and Tr2_n can be constructed using LV (Low Voltage) transistors with relatively low threshold voltages and VLV (Very Low Voltage) transistors with even lower threshold voltages. In this case, the impurity concentrations in the n-well region nw and the p-well region pw are relatively low. Therefore, with a high voltage across conductor L10, the p-well region pw (or the n-well region nw) becomes easily inverted. However, in this embodiment, a high concentration of p-type impurities is provided on the second surface F2 of the p-well region pw. + The impurity layer AR is a type of impurity. Therefore, even if the conductor L10 transmits a high voltage, the impurity layer AR can suppress the inversion of the pw in the p-well region.

[0110] Transistor Tr2_p is disposed in the active region between two adjacent element separation sections STI. Transistor Tr2_p is located within and above the n-well region nw. Transistor Tr2_p includes a gate insulator GO, a gate electrode GC, and a pair of source / drain regions SD_p. The gate insulator GO is located on the upper surface of substrate W2. In one example, the gate insulator GO comprises silicon oxide. The gate electrode GC is located on the upper surface of the gate insulator GO. In one example, the gate electrode GC comprises polysilicon that has become conductive by introducing impurities. The source / drain regions SD_p sandwich the portion below the gate electrode GC in the region comprising the upper surface of substrate W2. The source / drain regions SD_p contain p-type impurities.

[0111] Transistor Tr2_n is disposed in the active region between two adjacent element separation sections STI. Transistor Tr2_n is located within and above the p-well region pw. Transistor Tr2_n includes a gate insulator GO, a gate electrode GC, and a pair of source / drain regions SD_n. The source / drain regions SD_n sandwich the portion below the gate electrode GC in the region containing the upper surface of the substrate W2. The source / drain regions SD_n contain n-type impurities.

[0112] Contacts CS2, CS5, and C7, the component separation section STI, and the through electrode TSV have a tapered shape. The tapered components have a larger area at the upper end than at the lower end, decreasing in size as they move from the upper end to the lower end (in the -Z direction). That is, the ends of contacts CS2, CS5, and C7, the component separation section STI, and the through electrode TSV have a larger area at the +Z direction end than at the -Z direction end.

[0113] Next, the manufacturing method of the storage device 1 according to the first embodiment will be described.

[0114] The manufacturing process of the storage device 1 includes the process of individually manufacturing the first structure 100, the second structure 200, and the third structure 300, and the process of bonding the manufactured first structure 100, second structure 200, and third structure 300 together. Hereinafter, the manufacturing method of the second structure 200 of this embodiment will be described.

[0115] Figures 8-15 This is a cross-sectional view showing an example of a manufacturing method for a second structure of the storage device according to the first embodiment.

[0116] like Figure 8 As shown, a thin insulating material 25 (e.g., silicon oxide) for protection is deposited on the second surface F2 of substrate W2. Substrate W2 is, for example, a semiconductor substrate such as a silicon substrate. Next, using ion implantation, a high concentration of p-type impurities (e.g., boron) is introduced into the second surface F2 of substrate W2 through the insulating material 25. Thus, a p-type impurity is formed on the second surface F2 of substrate W2. + Type AR impurity layer. The impurity concentration of the AR impurity layer is preferably at least 5.0 × 10⁻⁶. 16 atoms / cm 3 above.

[0117] When carbon is also introduced into the impurity layer AR, firstly, carbon is introduced into the second surface F2 of the substrate W2 through the insulator 25 using ion implantation. The carbon concentration is preferably, for example, 1.0 × 10⁻⁶. 19 atoms / cm 3 That concludes the above. Next, using ion implantation as described above, a high concentration of p-type impurities is introduced into the second surface F2 of the substrate W2. This suppresses the diffusion of p-type impurities, resulting in a thinner, high-concentration impurity layer AR formed on the second surface F2.

[0118] Next, as Figure 9 As shown, the material of the insulator 25 is further deposited on the insulator 25 of the second surface F2 of the substrate W2.

[0119] Next, the first structure 100, manufactured separately from the second structure 200, is attached to the insulator 25 on the second surface F2 side of the second structure 200. Figure 9 The image shows only the upper part of the first structure 100. The first structure 100 includes a conductor L10 disposed within the insulator 21. Additionally, at this stage, a support substrate different from the first structure 100 may be attached to the insulator 25 of the second structure 200. In this case, in a subsequent process, the support substrate is peeled off from the second structure 200, and the first structure 100 is attached to the second surface F2 side of the second structure 200.

[0120] Next, the first surface F1 of the substrate W2 is polished using CMP (Chemical Mechanical Polishing) and other methods to thin the substrate W2.

[0121] Next, photolithography and ion implantation techniques are used, such as... Figure 11 As shown, an n-well region nw and a p-well region pw are formed on the substrate W2. The n-well region nw is formed, for example, by introducing an n-type impurity such as phosphorus (P) or arsenic (As) from the first surface F1. The p-well region pw is formed, for example, by introducing a p-type impurity such as boron (B) from the first surface F1. The n-well region nw and the p-well region pw are formed adjacent to each other.

[0122] Either the n-well region nw or the p-well region pw can be formed first.

[0123] Next, the material of the hard mask 52 is deposited on the first surface F1 of the substrate W2. Using photolithography and etching techniques, the material of the hard mask 52 in the formation area of ​​the component separation section STI is selectively removed.

[0124] Next, using the hard mask 52 as a mask, the substrate W2 is etched from the first surface F1 towards the second surface F2 using etching techniques such as RIE (Reactive Ion Etching). This forms a trench 51 in the area where the component separation section STI is formed. That is, as... Figure 12 As shown, a trench 51 is formed in the boundary region between adjacent p-well regions pw and n-well regions nw, extending from the first surface F1 toward the second surface F2. The side of the trench 51 is tapered in such a way that the area of ​​the trench 51 in the XY plane decreases as it moves from the first surface F1 toward the second surface F2 along the -Z direction.

[0125] Next, the insulating material of the component separation section STI is deposited on the substrate W2 using methods such as CVD (Chemical Vapor Deposition), and then polished using methods such as CMP (Chemical Mechanical Polishing). Thus, as... Figure 13 As shown, a component separation section STI is formed in the trench 51.

[0126] The component separation section STI is shaped to follow the shape of the trench 51. That is, the component separation section STI extends from the first surface F1 of the substrate W2 toward the second surface F2 along the -Z direction. The side of the component separation section STI is tapered in such a way that the area of ​​the trench 51 in the XY plane decreases as it moves from the first surface F1 toward the second surface F2 along the -Z direction.

[0127] Next, after removing the hard mask 52, as... Figure 14As shown, a gate insulator GO, a gate electrode GC, a sidewall insulator SW, an insulator 26, and contacts CS2, CS5, and C7 are formed.

[0128] For example, the gate insulator GO can be formed by thermal oxidation. The gate electrode GC can be formed, for example, by photolithography and anisotropic etching after depositing the gate electrode GC material using CVD. The sidewall insulator SW can be formed by anisotropic etching back after depositing the sidewall insulator SW material using CVD.

[0129] Next, using the gate electrode GC and the sidewall insulating film SW as a mask, source / drain regions SD_n and SD_p are formed on the substrate W2 by ion implantation. The source / drain region SD_n is formed, for example, by introducing n-type impurities such as phosphorus (P) or arsenic (As) from the first surface F1 into the p-well region pw. The source / drain region SD_p is formed, for example, by introducing p-type impurities such as boron (B) from the first surface F1 into the n-well region nw.

[0130] Either the source / drain regions SD_n and SD_p can be formed first.

[0131] Next, an insulator 26 is deposited on the gate electrode GC and other structures.

[0132] Next, contact holes for contacts CS2, CS5, and CS7 are formed using photolithography and etching techniques. Then, contacts CS2, CS5, and CS7 are formed by embedding conductive material within the contact holes.

[0133] Next, using hard mask, photolithography, and etching techniques, a through electrode TSV is formed in the region where the through electrode TSV is formed. Figure 15 The trench 53 is shown. The trench 53 penetrates the insulator 26, extends from the first surface F1 toward the second surface F2 along the -Z direction through the substrate W2, and reaches the conductor L10 of the first structure 100. The side of the trench 53 is tapered in such a way that the area of ​​the trench 53 in the XY plane decreases as it extends from the first surface F1 toward the second surface F2 along the -Z direction.

[0134] Next, as Figure 7 As shown, an insulator (e.g., a spacer film) SP is formed on the inner wall of trench 53. Then, the insulator SP at the bottom of trench 53 is removed by back etching, exposing the conductor L10 at the bottom of trench 53. Next, a material (e.g., tungsten) for the through-electrode TSV is formed inside the insulator SP of trench 53. Thus, as... Figure 7 As shown, the through electrode TSV is formed to be electrically connected to the conductor L10 in a state of being electrically separated from the substrate W2.

[0135] Next, the third structure 300 is attached to the first surface F1 side of the second structure 200. Alternatively, if the support substrate is attached to the second surface F2 side of the second structure 200, the first structure 100 can be attached to the second surface F2 side after the support substrate is peeled off.

[0136] By cutting the attached first to third structures 100 to 300, a semiconductor chip having the first to third structures 100 to 300 is monolithically formed. Thus, the storage device 1 of this embodiment is completed.

[0137] According to the first embodiment, the p-well region pw of the second configuration 200 has a higher impurity concentration than the p-well region pw of the second configuration 200. + An inversion layer AR is provided at least at the bottom of the second surface F2 side of the p-well region pw. The inversion layer AR is provided on the entire surface of the second surface F2 of the substrate W2 and is located between the substrate W2 and the insulator 25. The inversion layer AR is electrically isolated from the conductor L10 through the insulators 21 and 25. That is, the inversion layer AR is provided between the conductor L10 and the p-well region pw in a state of being electrically isolated from the conductor L10. Therefore, even if a high voltage (e.g., +30V) is applied to the conductor L10, the formation of an inversion layer in the p-well region pw can be suppressed. As a result, leakage current between adjacent n-well regions nw can be suppressed.

[0138] Similarly, if the conductivity type of the impurities in the impurity layer AR is set to n-type, then even if a negative voltage is applied to the conductor L10, the formation of an inversion layer in the n-well region nw can be suppressed. As a result, leakage current between adjacent p-well regions pw can be suppressed.

[0139] For example, such as Figure 5 As shown, in the case where the first to third structures 100 to 300 are stacked, in the second structure 200, a conductor L10 connected to the first or third structures 100, 300 via a through electrode TSV is sometimes provided near the substrate W2. If a high voltage (e.g., +30V) is applied to such a conductor L10, an inversion layer may sometimes form on the second surface F2 of the p-well region pw. In this embodiment, since an impurity layer AR is provided at the bottom of the p-well region pw, the formation of such an inversion layer in the p-well region pw can be suppressed. Therefore, almost no leakage current flows between adjacent n-well regions nw.

[0140] Furthermore, if an impurity layer AR is placed between the n-well region nw and the p-well region pw, there are concerns about a decrease in the breakdown voltage between the semiconductor element in the n-well region nw and the p-well region pw, or between the semiconductor element in the p-well region pw and the n-well region nw. Additionally, the parasitic capacitance between the semiconductor element in the n-well region nw and the p-well region pw and the impurity layer AR increases.

[0141] In contrast, according to this embodiment, an impurity layer AR is disposed on the second surface F2 side of the substrate W2, and this impurity layer AR is separated from the active regions of the n-well region nw and the p-well region pw on the first surface F1 side where the semiconductor element is formed by the thickness of the substrate W2. Therefore, the breakdown voltage between the semiconductor element in the n-well region nw and the p-well region pw, or the breakdown voltage between the semiconductor element in the p-well region pw and the n-well region nw, hardly decreases. In addition, the parasitic capacitance between the semiconductor element in the n-well region nw and the p-well region pw and the impurity layer AR hardly increases. As a result, the memory device 1 of this embodiment operates stably and its reliability is improved.

[0142] (Second Implementation)

[0143] Figures 16-18 This is a cross-sectional view illustrating an example of a manufacturing method for the second structure of the storage device according to the second embodiment. In the second embodiment, the impurity layer AR of the second structure 200 is formed from the first surface F1 side of the substrate W2.

[0144] For example, using ion implantation, such as Figure 16 As shown, a high concentration of p-type impurities (e.g., boron) is introduced into the first surface F1 of substrate W2. This forms a p-type impurity within substrate W2. + The impurity layer AR is a type of impurity layer. The position of the impurity layer AR in the Z direction is set such that the thickness of the substrate W2 from the first surface F1 to the impurity layer AR is equal to the thickness required for the p-well region pw, the n-well region nw, and the semiconductor device. The impurity concentration of the impurity layer AR is the same as in the first embodiment, for example, 2 × 10⁻⁶. 17 atoms / cm 3 The above. More preferably, the impurity concentration of the AR layer is, for example, 5 × 10⁻⁶. 17 atoms / cm 3 above.

[0145] When carbon is also introduced into the impurity layer AR, firstly, carbon is introduced from the first surface F1 of the substrate W2 to the formation site of the impurity layer AR using ion implantation. Next, as described above, a high concentration of p-type impurities is introduced from the first surface F1 of the substrate W2 using ion implantation. This suppresses the diffusion of p-type impurities, resulting in a thinner and more concentrated impurity layer AR within the substrate W2.

[0146] Next, methods such as CMP are used. Figure 17 As shown, the substrate W2 is polished from the second side F2 to expose the impurity layer AR.

[0147] Next, the first structure 100, manufactured separately from the second structure 200, is attached to the impurity layer AR on the second surface F2 side of the second structure 200. Figure 18The image shows only the upper part of the first structure 100. The first structure 100 includes a conductor L10 disposed within an insulator 21. Alternatively, an insulator 25 may be deposited on the impurity layer AR on the second side F2 of the substrate W2, and the first structure 100 may be attached to the insulator 25.

[0148] The steps following the second embodiment can be the same as those in the first embodiment. Figures 11-15 The described procedures are the same. Therefore, the second embodiment can manufacture the same configuration as the first embodiment.

[0149] Alternatively, after attaching the first structure 100 to the second surface F2 of the substrate W2, the thickness of the substrate W2 can be adjusted by grinding the first surface F1 of the substrate W2 using CMP (Chemical Mechanical Polishing), introducing impurities from the first surface F1 of the substrate W2, and forming an impurity layer AR on the second surface F2 side of the substrate W2. In this case, subsequent processes can also be the same as those described in the first embodiment. Figures 11-15 The procedures described are the same.

[0150] (Third Implementation)

[0151] An example of a manufacturing method for the second structure of the storage device according to the third embodiment will be described. In the third embodiment, after referring to... Figure 16 After the described process, before attaching the first structure 100 to the substrate W2, it is referenced... Figures 11-15 and Figure 7 The described process involves forming a p-well region pw, an n-well region nw, and a semiconductor element on the first surface F1 side of the substrate W2.

[0152] Next, using CMP or similar methods, the substrate W2 is polished from the second surface F2 to expose the impurity layer AR, and the first structure 100 is attached to the impurity layer AR on the second surface F2 side of the second structure 200. Alternatively, an insulator 25 may be deposited on the impurity layer AR on the second surface F2 side of the substrate W2, and the first structure 100 may be attached to the insulator 25.

[0153] The manufacturing method of the third embodiment can also manufacture the same configuration as the first embodiment.

[0154] (Fourth Implementation)

[0155] Figure 19 This is a cross-sectional view showing a configuration example of the second structure of the storage device according to the fourth embodiment. In the fourth embodiment, the impurity layer AR is provided corresponding to the p-well region pw in the second surface F2 of the substrate W2, and the n-well region nw is not provided.

[0156] When a high voltage (e.g., +30V) is applied to the word line WL via conductor L10, it is sufficient to suppress the formation of an inversion layer in the p-well region pw. In this case, no inversion layer is formed in the n-well region nw.

[0157] Therefore, the p well region pw of the second structure 200 has a higher impurity concentration than the p well region pw of the second structure 200. + The impurity layer AR can be provided at least at the bottom of the second surface F2 side of the p-well region pw. In the fourth embodiment, the impurity layer AR is provided only corresponding to the p-well region pw in the second surface F2 of the substrate W2. In this way, leakage current between adjacent n-well regions nw can also be suppressed.

[0158] Furthermore, the impurity layer AR in the fourth embodiment only needs to be in reference Figure 8 In the described process of forming the impurity layer AR, a photolithography step is added to selectively introduce p-type impurities (e.g., boron) into the formation region of the p-well region pw. To suppress the diffusion of p-type impurities, carbon may also be introduced. Other manufacturing steps in the fourth embodiment can be the same as those in the first embodiment. Thus, the second structure 200 of the fourth embodiment can be formed. Alternatively, the second structure 200 of the fourth embodiment can also be formed using the second or third embodiment.

[0159] (Fifth Implementation)

[0160] Figure 20 This is a cross-sectional view showing a configuration example of the second structure of the storage device according to the fifth embodiment. In the fifth embodiment, the impurity layer AR is partially provided in the p-well region pw of the second surface F2 of the substrate W2. Furthermore, similar to the fourth embodiment, the impurity layer AR is not provided in the n-well region nw.

[0161] An impurity layer AR is partially disposed in the p-well region pw on the second surface F2 of the substrate W2. In this case, the p-well region pw on the second surface F2 where the impurity layer AR is not disposed sometimes forms an inversion layer. However, since no inversion layer is formed in the portion where the impurity layer AR is disposed, the inversion layer formed in the p-well region pw does not electrically connect adjacent n-well regions nw. Therefore, almost no leakage current flows between adjacent n-well regions nw.

[0162] Furthermore, the impurity layer AR in the fifth embodiment also only needs to be referenced. Figure 8 In the described impurity layer AR formation process, a photolithography process is added, and p-type impurities (e.g., boron) are selectively introduced into the formation region of the p-well region pw. To suppress the diffusion of p-type impurities, carbon may also be introduced. Other manufacturing processes in the fifth embodiment can be the same as those in the first embodiment. Thus, the second structure 200 of the fifth embodiment can be formed. Alternatively, the second structure 200 of the fifth embodiment can also be formed using the second or third embodiment.

[0163] (Sixth Implementation Method)

[0164] Figure 21 This is a cross-sectional view showing a configuration example of the storage device according to the sixth embodiment. In the sixth embodiment, instead of the conductor L10, a conductor L3 facing the p-well region pw and transmitting a positive high voltage is located in the second configuration 200.

[0165] The first configuration 100 does not include the conductor L10 and the contact C15. On the other hand, the second configuration 200 includes the conductor L3 and the contacts C4 and C5.

[0166] The lower surface of contact C4 contacts the upper surface of a mating terminal BP2L.

[0167] The bonding terminal BP2L is located in the bottom layer of the second structure 200. The insulator 24 is embedded in the area of ​​the layer where the bonding terminal BP2L is located where the bonding terminal BP2L is not located.

[0168] Conductor L3 contacts the upper surface of a contact C4 on its lower surface. In one example, conductor L3 comprises copper (Cu), aluminum (Al), and / or tungsten (W). Each contact C5 contacts the upper surface of a conductor L3 on its lower surface. Conductor L3 is electrically connected to voltage generation circuit 14 and receives a high positive voltage. Conductor L3 is disposed on the second surface F2 side of substrate W2 via insulator 25. Conductor L3 is electrically connected to transistor Tr1 of first structure 100 via contact C4, etc. Conductor L3 is disposed between first structure 100 and second structure 200 and is electrically insulated from substrate W2 by insulator 25. In addition, conductor L3 is electrically connected to conductors 31, 33, or 36 of third structure 300 via through electrode TSV, etc.

[0169] The first configuration 100 has a contact terminal BP1 on its lower surface in contact with the upper surface of a contact member C3. An insulator 22 is embedded in the layer containing the contact terminal BP1 in an area where the contact terminal BP1 is not located. The contact terminal BP1 is electrically connected to the contact terminal BP2L.

[0170] The other configurations of the sixth embodiment can be the same as those of the first embodiment. Therefore, the sixth embodiment can achieve the same effects as the first embodiment.

[0171] (Regarding the impurity concentration of the AR layer)

[0172] Figure 22This table shows the relationship between the impurity concentration of the impurity layer AR (without an inversion layer) and the distance from conductor L10 or L3 to the p-well region pw. In this simulation, the distance between the impurity layer AR and conductor L10 or L3 was set to 0.2 μm, 0.5 μm, 1.0 μm, and 1.5 μm, and the voltage applied to conductor L10 or L3 was set to +33V. The distance between the impurity layer AR and conductor L10 or L3 is the thickness of the insulator (e.g., silicon oxide film) 21, 25 between conductor L10 or L3 and the p-well region pw. The inversion layer is considered to form when the hole density is greater than the electron density at the interface of the second surface F2 of the p-well region pw.

[0173] The result, such as Figure 22 As shown, when the distance between the impurity layer AR and the conductor L10 or conductor L3 is 0.2 μm, if the p-type impurity concentration of the impurity layer AR is 2.1 × 10⁻⁶... 18 atoms / cm 3 Therefore, no inversion layer forms in the impurity layer AR or the p-well region pw. When the distance between the impurity layer AR and the conductor L10 or L3 is 0.5 μm, if the p-type impurity concentration of the impurity layer AR is 4.0 × 10⁻⁶... 17 atoms / cm 3 Therefore, no inversion layer forms in the impurity layer AR or the p-well region pw. When the distance between the impurity layer AR and the conductor L10 or L3 is 1.0 μm, if the p-type impurity concentration of the impurity layer AR is 9.0 × 10⁻⁶... 16 atoms / cm 3 Therefore, no inversion layer forms in the impurity layer AR or the p-well region pw. When the distance between the impurity layer AR and the conductor L10 or L3 is 1.5 μm, if the p-type impurity concentration of the impurity layer AR is 5.0 × 10⁻⁶... 16 atoms / cm 3 Therefore, no inversion layer is formed in the impurity layer AR or the p-well region pw.

[0174] The distance between the impurity layer AR and the conductor L10 or L3 is typically less than 1.5 μm; therefore, the p-type impurity concentration of the impurity layer AR is preferably at least 5.0 × 10⁻⁶. 16 atoms / cm 3 above.

[0175] The description up to this point is based on the example of a memory device using the semiconductor device described in the above embodiments. The above embodiments can be applied to structures such as the first structure 100 and the second structure 200, which are interconnected and include transistor Tr2 and conductor L10 (or L3). Examples of other semiconductor devices include image sensors and integrated circuits (ICs). In this case, the third structure 300 is not provided. Alternatively, the third structure 300 has semiconductor elements other than the memory cell array.

[0176] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention as set forth in the claims and its equivalents.

[0177] Explanation of reference numerals in the attached figures

[0178] 100 First Construction

[0179] 200 Second Construction

[0180] 300 Third Construction

[0181] BP1, BP2L, BP2U, PB3 joint terminals

[0182] W1, W2 substrate

[0183] Tr1 and Tr2 transistors

[0184] CS1, CS2, CS5, C0~C13 contacts

[0185] Conductors L0 to L8, 31, 33, 36, 38

[0186] 21, 22, 24, 25, 26, 27, 29, 32, 34, 35, 37, 40, 41 Insulator nw n-well region

[0187] pw p well region

Claims

1. A semiconductor device comprising: The first structure includes a plurality of first semiconductor elements; A second structure, stacked on top of the first structure, includes: a substrate having a first surface and a second surface opposite to the first surface; a first well region of a first conductivity type disposed on the first surface side of the substrate; a second well region of a second conductivity type disposed adjacent to the first well region on the first surface side of the substrate; and a first impurity layer of the first conductivity type disposed at least on the second surface side of the first well region, having an impurity concentration higher than that of the first well region; and A first conductor is disposed between the first structure and the second structure, and is electrically isolated from the substrate.

2. The semiconductor device according to claim 1, wherein, The first impurity layer is disposed on the entire second surface of the substrate.

3. The semiconductor device according to claim 1, wherein, The first impurity layer is disposed on the second surface of the substrate relative to the first well region, but not relative to the second well region.

4. The semiconductor device according to claim 1, wherein, The first impurity layer is disposed locally on the second surface of the substrate relative to the first well region.

5. The semiconductor device according to claim 1, wherein, The peak value of the impurity concentration in the first impurity layer is located near the second surface of the substrate.

6. The semiconductor device according to claim 1, wherein, The first impurity layer contains boron as an impurity.

7. The semiconductor device according to claim 1, wherein, The impurity concentration of the first impurity layer is 5 × 10⁻⁶. 16 atoms / cm 3 above.

8. The semiconductor device according to claim 6, wherein, The first impurity layer contains carbon.

9. The semiconductor device according to claim 1, wherein, It also includes a first insulator disposed between the first impurity layer and the first conductor.

10. The semiconductor device according to claim 6, wherein, The first impurity layer is maintained at the same voltage as the first well region or at ground voltage.

11. The semiconductor device according to claim 1, wherein, It also includes a component separation section, which is disposed between the first well region and the second well region, and is disposed in the substrate from the first surface toward the second surface.

12. The semiconductor device according to claim 1, wherein, The first structure is attached to the second side of the second structure.

13. The semiconductor device according to any one of claims 1 to 12, wherein, It also has a third structure, which is stacked on the first side of the second structure and includes a memory cell array.

14. The semiconductor device according to claim 13, wherein, It also has a through electrode that penetrates the substrate and is electrically separated from the substrate, thereby electrically connecting the memory cell array to the first conductor.

15. The semiconductor device according to claim 13, wherein, The storage cell array includes: A laminate, formed by alternately stacking multiple second conductors and multiple second insulators; and A plurality of columnar bodies include a semiconductor layer penetrating the stack and a memory layer disposed between the stack and the semiconductor layer, and memory cells are formed at the intersection positions where they intersect with the plurality of second conductors. The first configuration includes a plurality of first transistors electrically connected to any one of the plurality of second conductors.

16. The semiconductor device according to claim 15, wherein, The plurality of first transistors constitute a drive circuit that controls the voltage applied to any one of the plurality of second conductors.

17. The semiconductor device according to claim 15, wherein, The second configuration includes a plurality of second transistors electrically connected to the semiconductor layer of any one of the plurality of pillars.

18. The semiconductor device according to claim 17, wherein, The plurality of second transistors constitute a detection circuit for detecting data stored in the storage unit.

19. A method for manufacturing a semiconductor device, wherein, It has the following processes: A first impurity layer is formed by introducing an impurity of a first conductivity type into the second surface of a substrate that includes a first surface and a second surface located on the opposite side of the first surface; A first well region of a first conductivity type and a second well region of a second conductivity type are formed on the first surface side of the substrate. as well as Semiconductor devices are formed in the first well region and the second well region. The first impurity layer is disposed at least on the second surface side of the first well region and has an impurity concentration that is higher than that of the first well region.

20. The method of manufacturing a semiconductor device according to claim 19, wherein, It also has the following processes: After the first impurity layer is formed A first insulator is formed on the first impurity layer. The first insulator having a first conductor is attached to the second side of the substrate such that the first conductor is at least opposite to the first well region.

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