Memory device

Abstract

The present invention reduces manufacturing costs of a memory device. A memory device (1) of an embodiment includes a plurality of conductor layers (24), an insulating film (51), and a plurality of contact plugs (CC) arranged throughout tiers (T LCA ) and tiers (T UCA ). Each of the plurality of conductor layers (24) has a high dielectric film (54). An upper surface of the insulating film (51) has a stepped difference in a stepped shape formed along the plurality of conductor layers (24a) included by tiers (T LCA ). The insulating film (51) is provided thicker than the conductor layers (24a) and includes a high dielectric film (52) of the same material as the high dielectric film (54). The plurality of contact plugs includes a plurality of contact plugs (CCa) respectively connected to the plurality of conductor layers (24a). Each of the plurality of contact plugs (CCa) includes a sub contact plug (LCC) having a portion through tiers (T LCA ) and the insulating film (51), and a sub contact plug (UCC) having a portion through tiers (T UCA ).

Description

Technical Field

[0001] The implementation relates to a memory device. Background Technology

[0002] A type of NAND flash memory capable of storing data non-volatilely is known. Summary of the Invention

[0003] This reduces the manufacturing cost of memory devices. The memory device of this embodiment includes multiple conductive layers, memory pillars, an insulating film, and multiple contact plugs. The multiple conductive layers are arranged in a first region and a second region in a first direction, separated from each other in a second direction intersecting the first direction, and are configured to extend across multiple layers including a first layer and a second layer above the first layer. Each of the multiple conductive layers has a platform portion in the second region that does not overlap with a conductive layer disposed on top of it in the same layer, and a first high-dielectric film. The memory pillars are arranged in the first region and in the second direction through the multiple conductive layers, with one intersection with the multiple conductive layers functioning as a memory cell. The upper surface of the insulating film has a stepped shape formed along the multiple platform portions of the multiple first conductive layers included in the first layer. The insulating film is thicker than the first conductive layers and includes a second high-dielectric film made of the same material as the first high-dielectric film. In the second region, multiple contact plugs are respectively connected to multiple platform portions of multiple conductive layers. The multiple contact plugs include multiple first contact plugs respectively connected to multiple first conductive layers. Each of the multiple first contact plugs includes a first sub-contact plug having a portion containing an insulating film within the first layer that passes through the first layer, and a second sub-contact plug having a portion that passes through the second layer. Attached Figure Description

[0004] Figure 1 This is a block diagram illustrating an example of the overall configuration of a memory system equipped with the memory device of the first embodiment.

[0005] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array provided in the memory device of the first embodiment.

[0006] Figure 3 This is a top view showing an example of the planar layout of the memory cell array provided in the memory device of the first embodiment.

[0007] Figure 4 This is a cross-sectional view showing an example of the cross-sectional structure of the memory region of the memory cell array provided by the memory device of the first embodiment.

[0008] Figure 5This is an example of the cross-sectional structure of the memory cylinders provided in the memory device of the first embodiment. Figure 4 A cross-sectional view of the VV line.

[0009] Figure 6 This is a cross-sectional view showing an example of the cross-sectional structure of the contact area of ​​the memory cell array provided in the memory device of the first embodiment.

[0010] Figure 7 This is a cross-sectional view showing an example of the cross-sectional structure of the contact area of ​​the memory cell array provided in the memory device of the first embodiment.

[0011] Figure 8 This is a cross-sectional view showing an example of a detailed cross-sectional structure of the contact area of ​​the memory cell array provided in the memory device of the first embodiment.

[0012] Figure 9 This is an example of the cross-sectional structure of the contact plug provided with the memory device of the first embodiment. Figure 8 A cross-sectional view of the IX-IX line.

[0013] Figure 10 This is an example of the cross-sectional structure of the contact plug provided with the memory device of the first embodiment. Figure 8 A cross-sectional view along the XX line.

[0014] Figure 11 This is an example of the cross-sectional structure of the contact plug provided with the memory device of the first embodiment. Figure 8 A cross-sectional view along line XI-XI.

[0015] Figure 12 This is a flowchart illustrating an example of a method for manufacturing a memory device according to the first embodiment.

[0016] Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0017] Figure 14 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0018] Figure 15 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0019] Figure 16 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0020] Figure 17This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0021] Figure 18 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0022] Figure 19 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0023] Figure 20 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0024] Figure 21 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0025] Figure 22 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0026] Figure 23 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0027] Figure 24 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0028] Figure 25 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0029] Figure 26 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment.

[0030] Figure 27 This is a cross-sectional view illustrating an example of the cross-sectional structure of the manufacturing process of the memory device in step ST107.

[0031] Figure 28 This is a cross-sectional view illustrating an example of the cross-sectional structure of the manufacturing process of the memory device in step ST107.

[0032] Figure 29 This is a cross-sectional view illustrating an example of the cross-sectional structure of the manufacturing process of the memory device in step ST107.

[0033] Figure 30 This is a cross-sectional view illustrating an example of the cross-sectional structure of the manufacturing process of the memory device in step ST107.

[0034] Figure 31 This is a cross-sectional view illustrating an example of the cross-sectional structure of the manufacturing process of the memory device in step ST107.

[0035] Figure 32 This is a cross-sectional view illustrating an example of the cross-sectional structure of the manufacturing process of the memory device in step ST113.

[0036] Figure 33 This is a cross-sectional view illustrating an example of the cross-sectional structure of the manufacturing process of the memory device in step ST113.

[0037] Figure 34 This is a cross-sectional view illustrating an example of the cross-sectional structure of the manufacturing process of the memory device in step ST113.

[0038] Figure 35 This is a cross-sectional view illustrating an example of the cross-sectional structure of the manufacturing process of the memory device in step ST113.

[0039] Figure 36 This is a cross-sectional view illustrating an example of the cross-sectional structure of the manufacturing process of the memory device in step ST115.

[0040] Figure 37 This is a cross-sectional view illustrating an example of the cross-sectional structure of the manufacturing process of the memory device in step ST115.

[0041] Figure 38 This is a cross-sectional view showing an example of the cross-sectional structure of the contact area of ​​the memory cell array in the first variation of the first embodiment.

[0042] Figure 39 This is a cross-sectional view showing an example of the cross-sectional structure of the manufacturing process of the memory device in the second variation of the first embodiment.

[0043] Figure 40 This is a cross-sectional view showing an example of the cross-sectional structure of the manufacturing process of the memory device in the second variation of the first embodiment.

[0044] Figure 41 This is a cross-sectional view showing an example of the cross-sectional structure of the contact area of ​​the memory cell array in the second variation of the first embodiment.

[0045] Figure 42 This is a cross-sectional view showing an example of the cross-sectional structure of the manufacturing process of the memory device in the third variation of the first embodiment.

[0046] Figure 43 This is a cross-sectional view showing an example of the cross-sectional structure of the manufacturing process of the memory device in the third variation of the first embodiment.

[0047] Figure 44 This is a cross-sectional view showing an example of the cross-sectional structure of the contact area of ​​the memory cell array in the third variation of the first embodiment.

[0048] Figure 45 This is a cross-sectional view showing an example of the cross-sectional structure of the contact area of ​​the memory cell array in the fourth variation of the first embodiment.

[0049] Figure 46 This is a cross-sectional view showing an example of the cross-sectional structure of the memory region of the memory cell array provided by the memory device of the second embodiment.

[0050] Figure 47 This is a cross-sectional view showing an example of the cross-sectional structure of the contact area of ​​the memory cell array provided in the memory device of the second embodiment.

[0051] Figure 48 This is a flowchart illustrating an example of a method for manufacturing a memory device according to the second embodiment.

[0052] Figure 49 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment.

[0053] Figure 50 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment.

[0054] Figure 51 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment.

[0055] Figure 52 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment.

[0056] Figure 53 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment.

[0057] Figure 54 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment.

[0058] Figure 55 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment.

[0059] Figure 56 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment.

[0060] Figure 57This is a cross-sectional view showing an example of the cross-sectional structure of the contact area of ​​the memory cell array provided in the memory device of the third embodiment.

[0061] Figure 58 This is a flowchart illustrating an example of a method for manufacturing a memory device according to the third embodiment.

[0062] Figure 59 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the third embodiment.

[0063] Figure 60 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the third embodiment.

[0064] Figure 61 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the third embodiment.

[0065] Figure 62 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the third embodiment.

[0066] Figure 63 This is a cross-sectional view showing an example of the cross-sectional structure of the contact area of ​​the memory cell array provided in the memory device of the fourth embodiment.

[0067] Figure 64 This is a flowchart illustrating an example of a method for manufacturing a memory device according to the fourth embodiment.

[0068] Figure 65 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fourth embodiment.

[0069] Figure 66 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fourth embodiment.

[0070] Figure 67 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fourth embodiment.

[0071] Figure 68 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fourth embodiment.

[0072] Figure 69 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fourth embodiment.

[0073] Figure 70 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fourth embodiment.

[0074] Figure 71 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fourth embodiment.

[0075] Figure 72 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fourth embodiment.

[0076] Figure 73 This is a cross-sectional view showing an example of the cross-sectional structure near the boundary of the laminate during the manufacturing process of the memory device of the first comparative example.

[0077] Figure 74 This is a cross-sectional view showing an example of the cross-sectional structure near the boundary of the laminate during the manufacturing process of the memory device of the fourth embodiment.

[0078] Figure 75 This is a top view showing an example of the planar layout of the memory cell array provided in the memory device of the fifth embodiment.

[0079] Figure 76 This is a cross-sectional view showing an example of the cross-sectional structure of the memory region of the memory cell array provided in the memory device of the fifth embodiment.

[0080] Figure 77 This is a cross-sectional view showing an example of the cross-sectional structure of the contact area of ​​the memory cell array provided in the memory device of the fifth embodiment.

[0081] Figure 78 This is a flowchart illustrating an example of a method for manufacturing a memory device according to the fifth embodiment.

[0082] Figure 79 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fifth embodiment.

[0083] Figure 80 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fifth embodiment.

[0084] Figure 81 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fifth embodiment.

[0085] Figure 82 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fifth embodiment.

[0086] Figure 83 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the fifth embodiment.

[0087] Figure 84 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second comparative example during its manufacturing process.

[0088] Figure 85 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second comparative example during its manufacturing process.

[0089] Figure 86 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second comparative example during its manufacturing process.

[0090] Figure 87 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second comparative example during its manufacturing process.

[0091] Figure 88 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second comparative example during its manufacturing process.

[0092] Figure 89 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second comparative example during its manufacturing process.

[0093] Figure 90 This is a cross-sectional view showing an example of the cross-sectional structure of the memory region of the memory cell array provided by the memory device in the fifth embodiment.

[0094] Figure 91 This is a cross-sectional view showing an example of a cross-sectional structure containing memory pillars and near the boundary.

[0095] Figure 92 This is a cross-sectional view showing an example of a cross-sectional structure containing a contact plug and near the boundary. Detailed Implementation

[0096] Hereinafter, various embodiments will be described with reference to the accompanying drawings. Each embodiment illustrates an apparatus or method for embodying the technical concept of the invention. The drawings are schematic or conceptual. The dimensions or proportions of the drawings may not be identical to those of the actual objects. Illustrations of the structure are appropriately omitted. The shading added to the top view may not be related to the material or characteristics of the constituent elements. In this specification, constituent elements having substantially the same function and structure are given the same reference numerals. Numbers or text, etc., attached to reference numerals are referenced by the same reference numerals and are used to distinguish similar elements from each other.

[0097] <1> First Embodiment

[0098] The memory device 1 of the first embodiment is a type of three-dimensional stacked NAND flash memory having a structure in which storage cell transistors (MTs) are three-dimensionally stacked on a semiconductor substrate. Hereinafter, details of the memory device 1 of the first embodiment will be described.

[0099] <1-1> Composition

[0100] First, the configuration of the memory device 1 in the first embodiment will be described.

[0101] <1-1-1> Overall Structure of Memory Device 1

[0102] Figure 1 This is a block diagram illustrating an example of the overall configuration of a memory system equipped with the memory device 1 of the first embodiment. For example... Figure 1 As shown, the memory device 1 is controlled by an external memory controller 2. The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequence generator 14, a driver circuit 15, a line decoder module 16, and a sense amplifier module 17.

[0103] The storage cell array 10 contains multiple blocks BLK0 to BLKn (where "n" is an integer greater than or equal to 1). A block BLK is a collection of multiple storage cells. A block BLK, for example, corresponds to a data erasure unit. A block BLK contains multiple pages. A page corresponds to a unit for performing data reading and writing. Although not illustrated, the storage cell array 10 is provided with multiple bit lines BL0 to BLm (where "m" is an integer greater than or equal to 1) and multiple word lines WL. Each storage cell is associated with, for example, one bit line BL and one word line WL.

[0104] Input / output circuit 11 is an interface circuit that manages the transmission and reception of input / output signals between the input / output circuit and the memory controller 2. Input / output signals include, for example, data DAT, status information, address information, and instructions. Input / output circuit 11 can input and output data DAT between the sense amplifier module 17 and each of the memory controller 2. Input / output circuit 11 can output status information transmitted from register circuit 13 to memory controller 2. Input / output circuit 11 can output address information and instructions transmitted from memory controller 2 to register circuit 13 respectively.

[0105] The logic controller 12 controls the input / output circuit 11 and the sequence generator 14 based on the control signals input from the memory controller 2. For example, the logic controller 12 controls the sequence generator 14 to enable the memory device 1. The logic controller 12 also notifies the input / output circuit 11 that the received input / output signals are instructions or address information, etc. The logic controller 12 commands the input / output circuit 11 to input or output signals.

[0106] Register circuit 13 temporarily stores status information, address information, and instructions. The status information is updated based on the control of sequence generator 14 and transmitted to input / output circuit 11. Address information includes block address, page address, column address, etc. Instructions contain commands related to various operations of memory device 1.

[0107] The sequence generator 14 controls the overall operation of the memory device 1. Based on the instruction and address information stored in the register circuit 13, the sequence generator 14 performs read operations, write operations, erase operations, etc.

[0108] The driver circuit 15 generates the voltage used for read, write, and erase operations. Furthermore, the driver circuit 15 supplies the generated voltage to the line decoder module 16 or the sense amplifier module 17, etc.

[0109] The row decoder module 16 is a circuit used to select the block BLK of the action object or to transmit voltage to wiring such as word lines WL. The row decoder module 16 contains multiple row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with blocks BLK0 to BLKn respectively for the selection of blocks BLK. Each row decoder RD transmits the voltage generated by the driver circuit 15 to various wirings provided in the memory cell array 10.

[0110] The sensing amplifier module 17 is a circuit used to transmit voltage to each bit line BL or to read data. The sensing amplifier module 17 includes multiple sensing amplifier units SAU0 to SAUm. Each sensing amplifier unit SAU0 to SAUm is associated with one of the multiple bit lines BL0 to BLm. Each sensing amplifier unit SAU includes a sensing amplifier capable of determining data based on the voltage of the associated bit line BL, or a latching circuit for temporarily storing data.

[0111] Alternatively, the combination of memory device 1 and memory controller 2 can also constitute a semiconductor device. An example of such a semiconductor device is an SD card. TM Memory cards such as memory cards, or SSDs (solid-state drives), etc. Furthermore, the memory device 1 may also have multiple memory cell arrays 10. Moreover, the memory device 1 may also have a line decoder module 16 and a sense amplifier module 17 for each memory cell array 10. A group of memory cell arrays 10, line decoder modules 16, and sense amplifier modules 17 is, for example, referred to as a "plane". That is, the memory device 1 may also have multiple planes.

[0112] <1-1-2> Circuit configuration of memory cell array 10

[0113] Figure 2This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 10 included in the memory device 1 of the first embodiment. Figure 2 This shows two blocks, BLK0 and BLK1, from the multiple blocks BLK contained in the storage cell array 10. (Example...) Figure 2 As shown, in the memory cell array 10, the gate lines SGD and SGS, and word lines WL0 to WL(N-1) (where N is an integer greater than or equal to 2) are selected and set for each block BLK. The bit lines BL0 to BLm and the source line SL are shared by multiple blocks BLK, for example.

[0114] Each BLK block contains multiple NAND strings NS. Each NAND string NS is associated with bit lines BL0 to BLm. Each NAND string NS is connected between the associated bit line BL and the source line SL. Each NAND string NS contains, for example, N memory cell transistors MT0 to MT(N-1) and select transistors STD and STS. Each memory cell transistor MT is a memory cell with a control gate and a charge accumulation layer, non-volatilely storing data. The select transistors STD and STS are used to select the BLK block.

[0115] In each NAND string NS, the select transistor STD, memory cell transistors MT(N-1) to MT0, and select transistor STS are connected in series in the order described above. Specifically, the drain and source terminals of the select transistor STD are connected to the associated bit line BL and the drain terminal of the memory cell transistor MT(N-1), respectively. The drain and source terminals of the select transistor STS are connected to the source terminal of the memory cell transistor MT0 and the source line SL, respectively.

[0116] Each select gate line SGD is connected to the gate terminal of each of the multiple select transistors STD contained in the associated block BLK. The select gate line SGS is connected to the gate terminal of each of the multiple select transistors STS contained in the associated block BLK. Word lines WL0 to WL(N-1) are respectively connected to the control gate terminals of each of the memory cell transistors MT0 to MT(N-1) contained in the associated block BLK.

[0117] A "page" corresponds to a set of multiple memory cell transistors MT connected to a common word line WL within the same BLK. Depending on the number of bits stored by each memory cell transistor MT, this set of multiple memory cell transistors MT connected to a common word line WL within the same BLK can have a storage capacity of more than two pages of data.

[0118] Alternatively, the circuit configuration of the memory cell array 10 can also be other circuit configurations. For example, multiple select gate lines (SGDs) that can be independently controlled can be provided in each BLK. In this case, each BLK is configured to be able to select multiple cell units that correspond to the multiple select gate lines (SGDs).

[0119] Hereinafter, the memory device 1 of the first embodiment will be described using the case where each NAND string NS has 10 memory cell transistors MT0 to MT9 connected to 10 word lines WL0 to WL9 respectively (that is, the case where N=10).

[0120] <1-1-3> Structure of memory device 1

[0121] The structure of the memory device 1 according to the first embodiment will be described below.

[0122] In the accompanying figures with reference below, a 3D orthogonal coordinate system is used. The X direction corresponds, for example, to the extension direction of the word line WL. The Y direction corresponds, for example, to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction of the memory device 1 relative to the substrate. "Up" and "down" are defined based on the direction along the Z direction. "Up" corresponds to the direction away from the configuration (e.g., source line SL) set as a reference. "Down" corresponds to the direction closer to the configuration (e.g., source line SL) set as a reference. The XY plane (section) corresponds to a plane (section) parallel to the X and Y directions, respectively. The YZ section corresponds to a section parallel to the Y and Z directions, respectively. The XZ section corresponds to a section parallel to the X and Z directions, respectively. "XY section area" corresponds to the section area in the XY section of the object.

[0123] In memory device 1, memory cell array 10 includes multiple wiring layers (e.g., word lines WL0 to WL9 and select gate lines SGD and SGS) stacked separately in the Z direction. Hereinafter, the multiple wiring layers (conductor layers) stacked separately in the Z direction will also be referred to as "stacked wiring". As a method for forming stacked wiring, a method is known of forming a structure corresponding to each wiring layer using sacrificial components, removing the sacrificial components to form gaps, and embedding the gaps with a conductive material. Hereinafter, this method of forming stacked wiring by replacing (replacing) sacrificial components with conductive material will be referred to as "WL replacement".

[0124] (1: Planar layout of storage cell array 10)

[0125] Figure 3 This is a top view showing an example of the planar layout of the memory cell array 10 included in the memory device 1 of the first embodiment. For example... Figure 3As shown, the memory cell array 10 includes, for example, multiple components SLT. Furthermore, the memory cell array 10 includes a memory region MA and a contact region CA arranged in the X direction.

[0126] Each component SLT has a portion extending along the X direction. Each component SLT traverses the memory region MA and the contact region CA along the X direction. Multiple component SLTs are arranged in the Y direction. Each component SLT divides the stacked wiring according to each block BLK. That is, in the memory cell array 10, each region divided by the component SLT along the Y direction corresponds to one block BLK. Each component SLT, for example, has a conductive component LI and a spacer SP. The spacer SP is an insulator disposed on the side of the conductive component LI, separating the conductive component LI from the stacked wiring. The conductive component LI is insulated from the stacked wiring by the spacer SP and functions as part of the source line SL. Alternatively, each component SLT may also be constructed of an insulator.

[0127] The memory region MA is used to store data and includes multiple memory pillars MP and multiple contact plugs CV. Each memory pillar MP is, for example, a generally cylindrical component that functions as a NAND string NS. The multiple memory pillars MP are configured in a grid-like arrangement per block BLK, for example. At least one bit line BL is arranged overlapping each memory pillar MP. Moreover, one bit line BL is electrically connected to each memory pillar MP via a contact plug CV. Each contact plug CV contains a generally cylindrical conductor extending in the Z direction. The multiple bit lines BL each have a portion extending in the Y direction and are arranged in the X direction. In this example, two bit lines BL are arranged to overlap with one memory pillar MP.

[0128] The contact area CA is used to connect the stacked wiring configured for each block BLK to the line decoder module 16. In the contact area CA, each wiring layer (conductor layer) included in the stacked wiring has a plateau portion TP. The plateau portion TP corresponds to the portion of the wiring layer that does not overlap with the wiring layer above it. In the contact area CA, for example, multiple plateau portions TP corresponding to the select gate line SGD, word lines WL9 to WL0, and select gate line SGS are sequentially arranged from the memory region MA toward the end in the X direction (right side of the paper). Thus, the plateau portions TP of the multiple wiring layers included in the stacked wiring can be arranged in a single-column stepped configuration. Alternatively, the plateau portions TP of each wiring layer included in the stacked wiring can also be arranged in two or more columns of stepped configuration. Furthermore, two adjacent plateau portions TP viewed from above may not necessarily correspond to two adjacent wiring layers in the Z direction.

[0129] Furthermore, the contact area CA comprises multiple contact plugs CC and multiple support posts HR for each BLK block. Each contact plug CC contains a generally cylindrical conductor extending in the Z direction. Each contact plug CC is electrically connected to the platform portion TP of any one of the wiring layers in the multilayer wiring, but not to other wiring layers. The multiple contact plugs CC of each BLK are arranged in a row in the X direction, for example, within the contact area CA. Each support post HR contains a generally cylindrical insulator extending in the Z direction. In WL replacement, each support post HR serves as a pillar supporting the multilayer structure with gaps. Each support post HR is appropriately positioned within the contact area CA in a portion that does not overlap with the contact plugs CC.

[0130] Furthermore, the number and arrangement of memory columns MP can be arbitrarily designed in the memory cell array 10. The associated memory columns MP and bit lines BL can be connected via two or more contact plugs. The number and arrangement of contact plugs CC for each BLK can be arbitrarily designed. Only one or more contact plugs CC need to be connected to the platform portion TP of each wiring layer. Multiple contact plugs CC for each BLK can also be configured in a grid shape within the contact area CA. The number and arrangement of support columns HR for each BLK can be arbitrarily designed. The memory cell array 10 can also have two contact areas CA arranged to sandwich a memory area MA in the X direction. The contact areas CA can also be arranged to divide the memory area MA in the X direction.

[0131] (2: Cross-sectional structure of memory region MA)

[0132] Figure 4 This is a cross-sectional view showing an example of the cross-sectional structure of the memory region MA of the memory cell array 10 provided in the memory device 1 of the first embodiment. Figure 4 The YZ cross-section of the memory region MA of the memory cell array 10, which includes two memory pillars MP and one component SLT, is shown. Figure 4 As shown, the memory cell array 10 includes, for example, a substrate 20, semiconductor layers 21-23, conductor layers 24 and 25, and insulating layers 30-35.

[0133] The substrate 20 is, for example, a silicon substrate. An insulating layer 31 is disposed on the substrate 20. The insulating layer 31 includes, for example, silicon oxide. In the area where the insulating layer 31 is disposed, circuits such as the line decoder module 16 or the sense amplifier module 17 may also be disposed. In addition, if the memory device 1 is a structure in which a chip on which the memory cell array 10 is disposed is bonded together with a chip on which circuits other than the memory cell array 10 are disposed, the substrate 20 disposed under the insulating layer 31 may be discarded.

[0134] Semiconductor layers 21, 22, and 23 are sequentially deposited on insulating layer 31. The group of semiconductor layers 21, 22, and 23 functions as source lines SL. Each of semiconductor layers 21, 22, and 23 contains, for example, silicon. Furthermore, each of semiconductor layers 21, 22, and 23 contains, for example, phosphorus (P) as an impurity for the n-type semiconductor. Semiconductor layer 22 is formed, for example, by replacing a sacrificial component disposed between semiconductor layers 21 and 23 with a semiconductor material. Hereinafter, this method of forming semiconductor layer 22 by replacing a sacrificial component with a semiconductor material will be referred to as "SL replacement." Additionally, although not illustrated, semiconductor layers 21 and 23 are disposed from memory region MA to contact region CA. Moreover, in this example, semiconductor layer 22 is disposed in memory region MA, but not in contact region CA. Depending on the configuration of memory cell array 10, semiconductor layer 22 may also be disposed in contact region CA.

[0135] An insulating layer 31 is disposed on the semiconductor layer 23. The insulating layer 31 may contain silicon oxide, for example. On the insulating layer 31, for example, 12 conductive layers 24 (wiring layers) and 12 insulating layers 32 are alternately deposited layer by layer. The conductive layers 24 are formed, for example, in a plate shape extending along the XY plane. The conductive layers 24 may contain a titanium nitride (TiN) / tungsten (W) laminate as the conductive material. In this case, the titanium nitride is formed to cover the tungsten. The titanium nitride contained in the conductive layer 24 may, for example, function as a barrier layer to suppress the oxidation of tungsten or as a bonding layer to improve the adhesion of tungsten when tungsten is deposited by CVD (Chemical Vapor Deposition). In addition, the conductive layer 24 may contain a high dielectric constant material such as aluminum oxide. In this case, the high dielectric constant material is formed to cover the conductive material of the conductive layer 24. For example, in the conductor layer 24, a high dielectric constant material is disposed in contact with the insulating layers 31 or 32 disposed above and below the conductor layer 24, and the side of the memory pillar MP. Furthermore, in the conductor layer 24, for example, titanium nitride is disposed in contact with the high dielectric constant material, and tungsten is disposed in contact with the titanium nitride and embedded within the conductor layer 24.

[0136] An insulating layer 33 is disposed on the uppermost insulating layer 32. An insulating layer 34 is disposed on the insulating layer 33. Each of the insulating layers 33 and 34 contains, for example, silicon oxide. A conductive layer 25 is disposed on the insulating layer 34. The conductive layer 25 functions as a bit line BL. The conductive layer 25 has, for example, a portion extending in the Y direction. Although not shown in the figure, multiple conductive layers 25 are arranged in the X direction. The conductive layer 25 contains, for example, copper (Cu). An insulating layer 35 is disposed on the conductive layer 25. The insulating layer 35 contains, for example, silicon oxide.

[0137] The component SLT has a portion that expands along the XZ plane. The component SLT, for example, has a tapered shape where the width in the Y direction at the upper end is greater than the width in the Y direction at the lower end. The component SLT separates the semiconductor layer 23, the insulating layer 31, the alternatingly stacked conductive layers 24 and insulating layers 32, and the insulating layer 33. In other words, the component SLT separates the semiconductor layer 23, the insulating layer 31, the alternatingly stacked conductive layers 24 and insulating layers 32, and the insulating layer 33 disposed in adjacent blocks BLK. The lower end of the component SLT reaches the semiconductor layer 22. In the component SLT, each of the conductive component LI and the spacer SP has a portion that expands along the XZ plane. Each of the conductive component LI and the spacer SP is disposed continuously within the component SLT. The conductive component LI has a portion that separates the spacer SP in the Y direction from each of the plurality of conductive layers 24. The lower end of the conductive component LI is electrically connected to the semiconductor layer 22 (source line SL). The conductive component LI, for example, comprises tungsten and titanium nitride, or silicon. Spacers SP may contain silicon oxide, for example.

[0138] Each memory pillar MP extends along the Z-direction, penetrating (through) the semiconductor layer 23, the insulating layer 31, and the alternately stacked conductive layers 24 and insulating layers 32. For example, the lower part of each memory pillar MP is covered by semiconductor layers 21, 22, and 23. Each memory pillar MP includes, for example, a core component 40, a semiconductor film 41, and a stacked film 42. The core component 40 is a generally cylindrical insulator extending along the Z-direction. The upper end of the core component 40 is located above the uppermost conductive layer 24. The lower end of the core component 40 is, for example, located in the same layer as the semiconductor layer 21. The semiconductor film 41 extends along the Z-direction, covering the periphery of the core component 40. The semiconductor film 41 has a portion that connects to the semiconductor layer 22 (source line SL) via a portion of the side surface of the memory pillar MP. The stacked film 42 covers the side surface and bottom surface of the semiconductor film 41, except for the portion that connects the semiconductor film 41 to the semiconductor layer 22. The semiconductor film 41 and the dielectric stacked film 42 are oriented in a planar direction (e.g., the Y direction) to each of the plurality of conductive layers 24 arranged in the Z direction.

[0139] Contact plugs CV are disposed on the semiconductor film 41 of each memory column MP. The contact plugs CV penetrate (pass through) the insulating layers 33 and 34. The semiconductor film 41 (memory column MP) and the conductive layer 25 (bit line BL) are electrically connected via the contact plugs CV.

[0140] Furthermore, the number of conductor layers 24 corresponds to the number of wiring layers included in the stacked wiring (conductor layers 24 arranged in the Z direction). In this example, the 12 conductor layers 24 are used sequentially from the source line SL side as the select gate line SGS, word lines WL0 to WL9, and select gate line SGD. The portion of the conductor layer 24 used as the select gate line SGS that intersects with the memory pillar MP functions as the select transistor STS. The portion of the conductor layer 24 used as the word line WL that intersects with the memory pillar MP functions as the memory cell transistor MT. The portion of the conductor layer 24 used as the select gate line SGD that intersects with the memory pillar MP functions as the select transistor STD. The semiconductor film 41 of each memory pillar MP serves as the channel (current path) for the memory cell transistors MT0 to MT9 and the select transistors STD and STS included in the NAND string NS. When the conductor layer 24 contains aluminum oxide as a high dielectric constant material, the memory cell transistor MT is also called a MANOS (Metal-Aluminum-Nitride-Oxide-Silicon) type memory cell.

[0141] (3: Hierarchical structure of storage cell array 10)

[0142] Next, refer to Figure 4 The hierarchical structure of the memory cell array 10 will be described. The memory cell array 10 has stacked wiring formed in two tiers.

[0143] In the first embodiment, the lower-level layer in the two-layer stacked wiring is referred to as "lower-level layer T". LCA The upper-level layer in a two-tier stacked cabling system is called the "upper-level layer T". UCA "The lower level T" LCA With the higher level T UCA The boundary is called the "boundary BD". Multiple conductive layers 24 and multiple insulating layers 32 extend to the lower-level layer T. LCA and the higher level T UCA And the configuration. In the first embodiment, the lower level T is configured. LCA The included conductive layer 24 and insulating layer 32 are referred to as conductive layer 24a and insulating layer 32a, respectively. The upper layer T... UCA The included conductive layer 24 and insulating layer 32 are referred to as conductive layer 24b and insulating layer 32b, respectively. In this example, the boundary BD is located between conductive layer 24a, which functions as word line WL4, and conductive layer 24b, which functions as word line WL5. In other words, the boundary BD is located between the uppermost conductive layer 24a and the lowermost conductive layer 24b.

[0144] Furthermore, in the first embodiment, the space between the uppermost conductive layer 24a and the lowermost conductive layer 24b, that is, the lower-level layer T... LCA With the higher level T UCA The insulating layer 32 (32a) corresponding to the boundary BD is called "insulator layer 32j". In the first embodiment, the thickness of the insulating layer 32j in the Z direction is thicker than that of the other insulating layers 32. Therefore, the spacing in the Z direction between the conductive layers 24a and 24b adjacent to the dielectric boundary BD is wider than the spacing in the Z direction between the two conductive layers 24 adjacent to the non-dielectric boundary BD. In other words, the spacing in the Z direction between the uppermost conductive layer 24a and the lowermost conductive layer 24b is wider than the spacing between two adjacent conductive layers 24a or 24b in the Z direction among the plurality of conductive layers 24a or 24b. In addition, the insulating layer 32j may also be composed of multiple insulating layers.

[0145] In the first embodiment, each memory column MP is formed in two layers. Specifically, each memory column MP includes a lower-level memory column LMP and an upper-level memory column UMP connected in the Z direction. The lower-level memory column LMP and the upper-level memory column UMP are respectively contained in the lower-level layer T. LCA and the higher level T UCA The boundary between the lower-level memory cylinder (LMP) and the upper-level memory cylinder (UMP) is substantially the same as the boundary BD. The upper-level memory cylinder (UMP), for example, extends through six conductive layers 24b (word lines WL5-WL9, select gate line SGD) and six insulating layers 32b, with its bottom connected to the upper end of the lower-level memory cylinder (LMP). The lower-level memory cylinder (LMP), for example, extends through six conductive layers 24a (select gate line SGS, word lines WL0-WL4), five insulating layers 32a, insulating layers 31 and 32j, and semiconductor layers 22 and 23, with its bottom located within semiconductor layer 21.

[0146] Furthermore, each of the core component 40, the semiconductor film 41, and the multilayer film 42 is continuously disposed within the lower-level memory pillar LMP and the upper-level memory pillar UMP. Each of the lower-level memory pillar LMP and the upper-level memory pillar UMP has, for example, a conical shape (positive cone shape) in which the upper diameter (XY cross-sectional area) is larger than the lower diameter (XY cross-sectional area). In other words, each of the lower-level memory pillar LMP and the upper-level memory pillar UMP has, for example, a frustum-shaped structure in which the lower part is smaller than the upper part. Therefore, the boundary BD can be identified by observing the cross-sectional shape of the memory pillar MP. Each of the lower-level memory pillar LMP and the upper-level memory pillar UMP can be referred to as a sub-pillar of the memory pillar MP. The lower-level memory pillar LMP may also have a shape in which the width widens in the portion intersecting with the insulating layer 32j.

[0147] In the first embodiment, it will be related to the lower level TLCA The stacked structure comprising the six conductive layers 24a, five insulating layers 32a, and insulating layer 32j is referred to as the "lower-level stacked structure." This is in contrast to the higher-level layer T. UCA The stacked structure corresponding to the 6 conductive layers 24b and 6 insulating layers 32b is called the "upper stack".

[0148] (4: Cross-sectional structure of memory cylinder MP)

[0149] Figure 5 This is an example of the cross-sectional structure of the memory cylinder MP provided in the memory device 1 of the first embodiment. Figure 4 A cross-sectional view of the VV line. Figure 5 The XY cross-section showing the memory pillar MP and conductor layer 24 is shown. Figure 5 As shown, the multilayer film 42 includes, for example, a tunnel insulating film 43, a charge storage film 44, and a barrier insulating film 45. The tunnel insulating film 43 surrounds the sides of the semiconductor film 41. The charge storage film 44 surrounds the sides of the tunnel insulating film 43. The barrier insulating film 45 surrounds the sides of the charge storage film 44. The conductive layer 24 surrounds the sides of the barrier insulating film 45. The core component 40 includes, for example, an insulator such as silicon oxide. The semiconductor film 41 includes, for example, silicon. Each of the tunnel insulating film 43 and the barrier insulating film 45 includes, for example, silicon oxide. The charge storage film 44 functions as a charge storage layer for the memory cell transistor MT and includes, for example, silicon nitride.

[0150] (5: Cross-sectional structure of the contact area CA)

[0151] Figure 6 and Figure 7 These are cross-sectional views showing an example of the cross-sectional structure of the contact area CA of the memory cell array 10 provided in the memory device 1 of the first embodiment. Figure 6 An XZ cross-section of the contact region CA containing the memory cell array 10 is shown. Figure 7 The YZ cross-section of the platform portion TP, including word line WL3, is shown in the contact region CA of memory cell array 10. (See diagram below.) Figure 6 As shown, the memory cell array 10 includes, for example, insulating layers 36, 37, and 38, and insulating films 50 and 51 in the contact area CA. Furthermore, the memory cell array 10 includes multiple contact plugs CC, with each block BLK comprising multiple contact plugs CCa and multiple contact plugs CCb.

[0152] An insulating layer 36 is disposed in the contact region CA between semiconductor layers 21 and 23. The insulating layer 36 in the contact region CA remains after replacement of SL and is not removed. The insulating layer 36 may contain, for example, silicon oxide.

[0153] Insulator layer 37 is embedded in contact area CA by the lower layer T. LCA The insulating layer 37 is configured such that it comprises multiple platform portions TP forming a stepped portion. In other words, the insulating layer 37 is configured in the contact region CA such that the stepped portion formed by the multiple platform portions TP of the lower-level stack is embedded therein. Through the insulating layer 37, the step difference corresponding to the stepped portion of the lower-level stack can be flattened from the memory region MA throughout the contact region CA. The insulating layer 37 comprises, for example, silicon oxide.

[0154] Insulator layer 38 is embedded in contact area CA by the upper layer T. UCA The insulating layer 38 is configured such that it comprises multiple platform portions TP forming a stepped portion. In other words, the insulating layer 38 is configured in the contact region CA such that the stepped portion formed by the multiple platform portions TP of the upper-level stack is embedded therein. Through the insulating layer 38, the step difference corresponding to the stepped portion of the upper-level stack can be flattened from the memory region MA throughout the contact region CA. The insulating layer 38, for example, comprises silicon oxide.

[0155] Insulating film 50 to the lower layer T LCA The multiple conductive layers 24a contained herein are arranged such that multiple platform portions TP are covered. In other words, the insulating film 50 is arranged along the lower layer T. LCA The multiple conductive layers 24a are arranged in a stepped shape, forming multiple platform portions TP. An insulating film 50 is located below the boundary BD. The insulating film 50 is continuously disposed between two adjacent platform portions TP. The insulating film 50 comprises, for example, silicon oxide.

[0156] An insulating film 51 is disposed on the insulating film 50. In the Z direction, the insulating film 51 is adjacent to the lower layer T. LCA The multiple conductive layers 24a contained herein have multiple overlapping platform portions TP. Furthermore, an insulating film 51 is continuously disposed between two adjacent platform portions TP. The upper surface of the insulating film 51 has a shape extending along the lower layers T. LCA The multiple platform portions TP of the included conductive layers 24a form a stepped shape with a step difference. The insulating film 51 has a structure that replaces a component used as a stop film when machining holes corresponding to contact plugs CC with an insulator. The insulating film 51 contains, for example, silicon oxide.

[0157] Multiple contact plugs CCa are electrically connected to the lower level T. LCA The included conductive layers 24a have multiple platform portions TP. Each contact plug CCa extends along the Z direction. Each contact plug CCa penetrates (throughs) insulating layers 33, 37, and 38 and insulating films 50 and 51, and its bottom is connected to the platform portion TP that forms the corresponding conductive layer 24a. The contact plug CCa may contain, for example, tungsten or copper.

[0158] Multiple contact plugs CCb are electrically connected to the upper level T. UCA The included conductive layers 24b have multiple platform portions TP. Each contact plug CCb extends along the Z direction. Each contact plug CCb penetrates (throughs) insulating layers 33 and 38, and its bottom is connected to the platform portion TP that forms the corresponding conductive layer 24b. The contact plug CCb may contain, for example, tungsten or copper.

[0159] In the first embodiment, each contact plug CCa is formed in two layers. Specifically, each contact plug CCa includes a lower-level contact plug LCC and an upper-level contact plug UCC connected in the Z direction. The lower-level contact plug LCC and the upper-level contact plug UCC are respectively included in the lower-level layer T. LCA and the higher level T UCA The boundary between the lower-level contact plug LCC and the upper-level contact plug UCC is substantially the same as the boundary BD. The upper-level contact plug UCC penetrates through insulating layers 33 and 38, and its bottom is connected to the upper end of the lower-level contact plug LCC. The lower-level contact plug LCC penetrates through insulating layers 37 and insulating films 50 and 51, and its bottom is connected to the platform portion TP where the corresponding conductive layer 24a is established. The lower-level contact plug LCC may also have a shape with an increased width near the boundary BD.

[0160] Each support pillar HR penetrates (throughs) insulating layers 31, 32a, 32b, 32j, 33, and 36, semiconductor layer 23, and at least one conductive layer 24 (24a and 24b) overlapped in top view. The upper end of each support pillar HR is located above the uppermost conductive layer 24b. The lower end of each support pillar HR is, for example, located in the same layer as semiconductor layer 21. The support pillar HR may, for example, contain silicon oxide. Additionally, each support pillar HR may also have a structure formed in multiple tiers. Referenced in this specification Figure 8 For the sake of simplicity, the illustrations of the support pillars HR will be omitted from the following figures. In the manufacturing method of the memory device 1 described later, each support pillar HR only needs to be formed before the SL replacement and WL replacement.

[0161] like Figure 7As shown, in this layer, two conductive layers 24a are respectively disposed between two adjacent blocks BLK (e.g., BLK0 and BLK1), and are isolated and insulated by a component SLT disposed between them. Thus, the voltage of each of the multiple conductive layers 24a can be controlled for each BLK by establishing corresponding contact plugs CCa. Similarly, although not shown in the figure, in this layer, two conductive layers 24b are respectively disposed between two adjacent blocks BLK, and are isolated and insulated by a component SLT disposed between them. Thus, the voltage of each of the multiple conductive layers 24b can be controlled for each BLK by establishing corresponding contact plugs CCb. Furthermore, the side surfaces of each component SLT are in contact with insulating films 50 and 51.

[0162] (6: Detailed cross-sectional structure of the contact area CA)

[0163] Figure 8 This is a cross-sectional view showing an example of the detailed cross-sectional structure of the contact area CA of the memory cell array 10 provided in the memory device 1 of the first embodiment. For example... Figure 8 As shown, the insulating film 51 includes, for example, a high-dielectric film 52 and an insulating component 53. The conductive layer 24a includes, for example, a high-dielectric film 54, a barrier metal 55, and a conductive component 56. The contact plug CCa includes, for example, a barrier metal 57 and a conductive component 58. Furthermore, although not shown in the figure, the structure within the conductive layer 24b is the same as that within the conductive layer 24a, and the structure within the contact plug CCb is the same as that within the contact plug CCa.

[0164] A high-dielectric film 52 is disposed on the outer periphery of the insulating film 51. Specifically, the high-dielectric film 52 is disposed on the portion of the insulating film 51 where the insulating layer 37 is in contact with the insulating film 51, and on the portion of the insulating film 50 in contact with the insulating film 51. The high-dielectric film 52 may contain, for example, aluminum oxide. The insulating member 53 is disposed such that it is embedded in the insulating film 51 on the inner side of the high-dielectric film 52 (e.g., the portion sandwiched by the high-dielectric film 52 in the Z direction). The insulating member 53 may have a portion in the insulating film 51 that is not sandwiched by the high-dielectric film 52 in the Z direction near the portion through which the contact plug CCa passes in the insulating film 51. The insulating member 53 may contain, for example, silicon oxide. The thickness of the insulating film 51 in the Z direction is greater than the thickness of the conductive layer 24 in the Z direction. In other words, the thickness of the portion of the insulating film 51 disposed above the platform portion TP of the conductive layer 24a in the Z direction is greater than the thickness of the platform portion TP of the conductive layer 24a in the Z direction.

[0165] A high-dielectric film 54 is disposed on the outer periphery of the conductive layer 24a. Specifically, the high-dielectric film 54 is disposed on the portions of each of the two adjacent insulating layers 32a in the Z direction that are in contact with the conductive layer 24a, and on the portions of the insulating film 50 that are in contact with the conductive layer 24a. The high-dielectric film 54 is made of the same material as the high-dielectric film 52, for example, containing aluminum oxide. The film thickness of the high-dielectric film 54 is approximately equal to that of the high-dielectric film 52. A barrier metal 55 is disposed inside the high-dielectric film 54. Furthermore, the barrier metal 55 has a portion disposed in such a way that it covers the lower part of the contact plug CCa connected to the conductive layer 24a. The barrier metal 55 contains, for example, titanium nitride. A conductive member 56 is disposed in such a way that it is embedded inside the barrier metal 55 within the conductive layer 24a. The conductive member 56 contains, for example, tungsten.

[0166] Each of the barrier metal 57 and the conductive component 58 is continuously disposed between the lower-level contact plug LCC and the upper-level contact plug UCC. The barrier metal 57 is disposed on the outer peripheral portion of the contact plug CCa, excluding the upper surface. The barrier metal 57 may contain, for example, titanium nitride. The conductive component 58 is disposed such that it is embedded inside the barrier metal 57 in the contact plug CCa. The conductive component 58 may contain, for example, tungsten. Hereinafter, the portion near the boundary BD in the lower-level contact plug LCC of the contact plug CCa will be referred to as the "joint portion JT". The portion in the contact plug CCa that intersects with the insulating film 51 will be referred to as the "intersection portion CP".

[0167] The diameter (XY cross-sectional area) of the connector portion JT of the lower-level contact plug CCa (LCC), that is, the diameter (XY cross-sectional area) of the end on the boundary BD side of the lower-level contact plug LCC, is larger than the diameter (XY cross-sectional area) of the end on the boundary BD side of the upper-level contact plug UCC. By forming the connector portion JT, the difficulty of aligning the lower-level contact plug LCC and the upper-level contact plug UCC in the manufacturing process of memory device 1 can be reduced.

[0168] The diameter (XY cross-sectional area) of the cross portion CP of the contact plug CCa (lower-level contact plug LCC) is larger than the diameter (XY cross-sectional area) of the portion of the lower-level contact plug LCC that penetrates (passes through) the insulating layer 37 and the end of the cross portion CP side. Furthermore, the diameter (XY cross-sectional area) of the cross portion CP of the contact plug CCa (lower-level contact plug LCC) is larger than the diameter (XY cross-sectional area) of the portion of the lower-level contact plug LCC that penetrates (passes through) the insulating film 50.

[0169] The barrier metal 57 of the contact plug CCa has portions that expand in the planar direction (e.g., the X direction) along the insulating member 53 on the upper and lower sides of the intersection portion CP. Furthermore, the barrier metal 57 of the contact plug CCa also has portions that expand in the planar direction (e.g., the X direction) along the barrier metal 55 of the conductive layer 24a at the intersection with the high-dielectric film 54. Hereinafter, the portion of the barrier metal 57 disposed on the upper side of the intersection portion CP is referred to as "part 1", the portion disposed on the lower side of the intersection portion CP is referred to as "part 2", the portion between part 1 and part 2 is referred to as "part 3", and the portion expanding in the planar direction along the barrier metal 55 is referred to as "part 4". Part 1 and part 2 of the barrier metal 57 sandwich a portion of the conductive member 58 and a portion of the insulating member 53 in the Z direction. A portion of part 4 of the barrier metal 57 is sandwiched in the Z direction by the insulating film 50 and the barrier metal 55 of the conductive layer 24a. The XY cross-sectional area of ​​the fourth part of the contact plug CCa containing barrier metal 57 is greater than the XY cross-sectional area of ​​the bottom of the contact plug CCa.

[0170] (7: Cross-sectional structure of the contact plug CCa)

[0171] Figure 9 , Figure 10 and Figure 11 These are cross-sectional views showing an example of the cross-sectional structure of the contact plug CCa provided in the memory device 1 of the first embodiment. Figure 9 Show along Figure 8 The cross-section along the IX-IX line shows the third portion of the barrier metal 57 containing the contact plug CCa, and the XY cross-section of the insulating component 53 within the insulating film 51. Figure 10 Show along Figure 8 The XY cross-section of the XX line shows the first portion of the barrier metal 57 containing the contact plug CCa, and the high dielectric film 52 within the insulating film 51. Figure 11 Show along Figure 8 The cross-section along the XI-XI line shows the fourth portion of the barrier metal 57 containing the contact plug CCa, and the XY cross-section of the high dielectric film 54 within the conductor layer 24a.

[0172] like Figure 9 As shown, in the XY cross-section of the third portion of the barrier metal 57 containing the contact plug CCa, the conductive member 58 is disposed at the center portion of the contact plug CCa. The barrier metal 57 surrounds the sides of the conductive member 58. In the XY cross-section containing the contact plug CCa and the insulating member 53 within the insulating film 51, the sides of the barrier metal 57 are surrounded by the insulating member 53. Figure 10As shown, in the XY cross-section of the first portion of the barrier metal 57 containing the contact plug CCa, the sides of the barrier metal 57 are surrounded by a high-dielectric film 52. In the XY cross-section of the barrier metal 57, the film thickness of the first portion is thicker than that of the third portion. Similarly, although not shown in the figure, in the XY cross-section of the barrier metal 57, the film thickness of the second portion is thicker than that of the third portion. Figure 11 As shown, in the XY cross-section of the fourth portion of the barrier metal 57 containing the contact plug CCa, the sidewalls of the barrier metal 57 are surrounded by a high-dielectric film 54. In the XY cross-section of the barrier metal 57, the film thickness of the fourth portion is thicker than that of the third portion. Thus, the barrier metal 57 of the contact plug CCa has a fin shape in each of the first, second, and fourth portions.

[0173] <1-2> Manufacturing Method

[0174] Next, as a method for manufacturing the memory device 1 according to the first embodiment, appropriate reference will be made. Figure 12 The method for forming the stacked wiring and contact plugs CC corresponding to the memory cell array 10 is explained. Figure 12 This is a flowchart illustrating an example of a method for manufacturing the memory device 1 according to the first embodiment. Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 and Figure 26 These are cross-sectional views showing an example of the cross-sectional structure of the memory device 1 in the manufacturing process of the first embodiment. Figures 13-26 The regions forming the memory pillar MP and component SLT, and a portion of the contact region CA are shown respectively.

[0175] first, Figure 13 The structure shown is formed by sequentially executing steps ST101 and ST102.

[0176] In step ST101, a source line portion is formed. The source line portion is a structure for forming semiconductor layers 21-23 that function as source lines SL within the memory region MA. Specifically, firstly, an insulating layer 60 and a sacrificial member 61 are sequentially deposited on the semiconductor layer 21. The insulating layer 60 includes, for example, silicon oxide. The sacrificial member 61 includes, for example, silicon nitride. Then, the sacrificial member 61 within the contact region CA is removed. Next, an insulating layer 36 is formed, and the upper surface of the insulating layer 36 is planarized. Hereinafter, the portion of the planarized insulating layer 36 encompassing the memory region MA is referred to as insulating layer 36a. Subsequently, the semiconductor layer 23 and the insulating layer 31 are formed on the insulating layers 36 and 36a.

[0177] In step ST102, a lower-level stack is formed. Specifically, as the lower-level stack, multiple sacrificial members 62a corresponding to multiple conductive layers 24a and multiple insulating layers 32a are alternately stacked on insulating layer 31. The sacrificial members 62a, for example, contain silicon nitride. Furthermore, an insulating layer 32j is formed on the uppermost sacrificial member 62a. Additionally, components that will serve as a hard mask (protective film) in subsequent step processing may be provided on insulating layer 32j.

[0178] Next, as Figure 14 As shown, execute the lower level T LCA The stepped processing (step ST103). Through the processing in step ST103, a process is formed from the lower level T. LCA The stepped structure is formed by multiple platform portions TP of multiple sacrificial components 62a. The platform portion TP of the sacrificial component 62a corresponds to the portion of the sacrificial component 62a that does not overlap with the upper sacrificial component 62a. The stepped processing in this specification includes a group of photolithography and etching processes.

[0179] Next, as Figure 15 As shown, this forms the lower-level hierarchy T. LCA The stop part (step ST104). Lower level T LCA The stop portion includes a stop film used in the formation process of multiple holes for forming the lower-level contact plug LCC, which will be described later. Specifically, firstly, the insulating film 50 and the sacrificial member 63 are sequentially formed. Then, to cover the lower-level layer T LCA The insulating film 50 and the sacrificial component 63 are processed (removed) in a manner that leaves the multiple platform portions TP of the multiple sacrificial components 62a. At this time, the insulating film 50 and the sacrificial component 63 formed on the memory region MA are removed, and the insulating film 50 and the sacrificial component 63 on the insulating layer 32j are removed. The shape of the sacrificial component 63 corresponds to Figures 6-8The shape of the insulating film 51 is shown. The sacrificial member 63 can be used as a stop film. The sacrificial member 63 is made of, for example, the same material as the sacrificial member 62a, but a different material from the insulating layers 37 and 38, and is formed to be thicker than the sacrificial member 62a. The sacrificial member 63 may contain, for example, silicon nitride.

[0180] Next, as Figure 16 As shown, execute the lower level T LCA The step embedding and flattening (step ST105). Specifically, to embed the lower level T LCA The insulating layer 37 is formed using a stepped structure. Furthermore, a portion of the insulating layer 37 is removed, for example, by CMP (Chemical Mechanical Polishing). This aligns (planarizes) the upper surface of the insulating layer 32j with the upper surface of the insulating layer 37. If a component serving as a hard mask is provided in step ST102, this component (hard mask) is removed in step ST105.

[0181] Next, as Figure 17 As shown, LMP processing and sacrificial component embedding are performed (step ST106). Specifically, firstly, a plurality of holes corresponding to the lower-level memory pillar LMP are formed such that they penetrate sacrificial components 61 and 62a, and insulating layers 31, 32a, 32j, 36a and 60, with their bottoms reaching the semiconductor layer 21. Then, sacrificial components 64 are embedded in the plurality of holes corresponding to the lower-level memory pillar LMP. The sacrificial component 64 may be made of, for example, any of carbon, silicon, or metal materials. In addition, in the various hole formation processes described in this specification, anisotropic etching processes such as RIE (Reactive Ion Etching) are used.

[0182] Next, as Figure 18 As shown, LCC machining and sacrificial component embedding are performed (step ST107). Through this process, the sacrificial component 65 forms a structure corresponding to multiple lower-level contact plugs LCC of the multiple contact plugs CCa. More details of this process will be described later.

[0183] Next, as Figure 19 As shown, an upper-level stack is formed (step ST108). Specifically, as the upper-level stack, multiple sacrificial components 62b corresponding to multiple conductive layers 24b and multiple insulating layers 32b are alternately stacked on the lower-level stack. The sacrificial components 62b are made of the same material as the sacrificial components 62a, for example, containing silicon nitride. Alternatively, a component that will serve as a hard mask (protective film) in the subsequent step processing may be provided on the uppermost insulating layer 32b.

[0184] Next, as Figure 20 As shown, execute the parent level T UCA The stepped processing (step ST109). Through the processing in step ST109, a process is formed from the upper level T. UCA The multiple sacrificial components 62b form a stepped structure consisting of multiple platform portions TP. The platform portions TP of the sacrificial components 62b correspond to the portions of the sacrificial components 62b that do not overlap with the upper sacrificial components 62b. Furthermore, through this process, the upper surface of the insulating layer 37 and the upper surfaces of the multiple sacrificial components 65 are exposed.

[0185] Next, as Figure 21 As shown, execute the parent level T UCA The step embedding and flattening (step ST110). Specifically, firstly, the upper level T is embedded. UCA An insulating layer 38 is formed using a stepped structure. Then, for example, a portion of the insulating layer 38 is removed by CMP processing. Thus, for example, the upper surface of the uppermost insulating layer 32b is aligned with the upper surface of the insulating layer 38 (planarized). If a component used as a hard mask is formed in step ST108, the component (hard mask) is removed by step ST110.

[0186] Next, as Figure 22 As shown, UMP processing and MP formation are performed (step ST111). Specifically, firstly, multiple holes corresponding to the upper memory pillar UMP are formed such that the sacrificial component 62b and the insulating layer 32b are penetrated, and their bottoms reach the sacrificial component 64 formed in the corresponding lower memory pillar LMP. Then, the sacrificial components 64 formed in each hole corresponding to the lower memory pillar LMP are removed through the multiple holes corresponding to the upper memory pillar UMP. Then, a multilayer film 42, a semiconductor film 41, and a core component 40 are formed in each hole corresponding to the group of upper memory pillar UMP and lower memory pillar LMP (i.e., memory pillar MP). Subsequently, an insulating layer 33 is formed on the uppermost insulating layer 32b and insulating layer 38.

[0187] Next, by sequentially executing steps ST112, ST113, and ST114, a process is formed. Figure 23 The structure shown.

[0188] In step ST112, SLT processing is performed. Specifically, the slit corresponding to the component SLT is formed in such a way that it passes through the sacrificial components 62a, 62b and 63, the semiconductor layer 23, the insulating layers 31, 32a, 32b, 32j, 33 and 36a, and the insulating film 50, and its bottom reaches the sacrificial component 61.

[0189] In step ST113, SL replacement and WL replacement are performed. Specifically, firstly, by SL replacement, the insulating layers 60 and 36a and the sacrificial component 61 of the memory region MA are replaced with the semiconductor layer 22. Then, by WL replacement, the sacrificial components 62a and 62b of the memory region MA and the contact region CA are replaced with the conductive layers 24a and 24b, respectively.

[0190] In the SL replacement, firstly, an insulating film is formed on the side of the slit of the opening, and the insulating film at the bottom of the slit is removed. Then, the sacrificial component 61 is removed through the slit corresponding to the component SLT by wet etching. Next, the insulating layers 60 and 36a are removed through the slit corresponding to the component SLT by wet etching. At this time, the stacked film 42 located on the same layer as the sacrificial component 61 is also removed in each memory pillar MP. Then, the semiconductor layer 22 is buried in the area (space) where the insulating layers 60 and 36a and the sacrificial component 61 have been removed. Subsequently, the remaining semiconductor layer 22 is removed on the side of the slit corresponding to the component SLT and above the insulating layer 33.

[0191] In the WL replacement, firstly, the insulating film on the sides of the slit is removed. Then, sacrificial components 62a, 62b, and 63 are removed via wet etching through the slit corresponding to component SLT. Next, a conductive layer 24 is embedded in the area (space) where sacrificial components 62a and 62b have been removed. Materials corresponding to the conductive layer 24 are also formed in the area where sacrificial component 63 has been removed. Subsequently, the remaining conductive layer 24 is removed from the sides and bottom of the slit corresponding to component SLT, and above the insulating layer 33. At this time, the conductive material of the conductive layer 24 formed in the area where sacrificial component 63 has been removed is also removed. Then, an insulating component 53 is embedded in the space where sacrificial component 63 has been removed. Thus, a structure corresponding to the insulating film 51 is formed. More detailed descriptions of this process will follow.

[0192] In step ST114, the SLT component embedding is performed. Specifically, first, an insulating film corresponding to the spacer SP is formed. Then, the insulating film corresponding to the bottom of the slits of the component SLT is removed. Then, the conductive component LI is formed by filling each slit. Subsequently, the remaining conductive component LI is removed above the insulating layer 33.

[0193] Next, perform UCC machining and LCC sacrificial part removal (step ST115). Specifically, first, as... Figure 24As shown, multiple contact holes CHa and CHb are formed. The multiple contact holes CHa correspond to the upper-level contact plug UCC of the contact plug CCa, and are formed by penetrating insulating layers 33 and 38. The bottom of each contact hole CHa reaches the upper part of the sacrificial member 65, which corresponds to the lower-level contact plug LCC of the contact plug CCa. The multiple contact holes CHb correspond to the contact plug CCb, and are formed by penetrating insulating layers 33 and 38. The bottom of each contact hole CHb reaches the platform portion TP of the conductive layer 24b, which corresponds to the contact plug CCb. Then, as... Figure 25 As shown, the sacrificial component 65 corresponding to the lower-level contact plug LCC is removed via multiple contact holes CHa. More details of this process will be described later.

[0194] Next, as Figure 26 As shown, the CC conductive component is embedded (step ST116). Specifically, the conductive component is formed by embedding multiple contact holes CHa and multiple contact holes CHb respectively. Furthermore, the remaining conductive component is removed outside the contact holes CHa and CHb. Thus, a structure corresponding to multiple contact plugs CCa and a structure corresponding to multiple contact plugs CCb are formed.

[0195] By following the steps outlined above, the usage will be complete. Figures 3 to 11 The construction of the storage cell array 10 is described.

[0196] (1: Details of step ST107)

[0197] The details of step ST107 are explained below. Figure 27 , Figure 28 , Figure 29 , Figure 30 and Figure 31 These are cross-sectional views illustrating an example of the cross-sectional construction of the memory device 1 in step ST107. Figures 27-31 Show respectively with Figure 8 The area shown corresponds to the area. Hereinafter, the hole used to form the lower-level contact plug LCC will be referred to as the "contact hole LH".

[0198] In the processing of step ST107, firstly, as Figure 27 As shown, multiple contact holes LH are formed by anisotropic etching processes such as RIE, penetrating the insulating layer 37 and reaching the sacrificial member 63 at their bottom. Here, the sacrificial member 63 serves as a stop film. Next, as... Figure 28 As shown, for example, a portion of the sacrificial member 63 is selectively removed via each contact hole LH using a wet etching process with phosphoric acid, etc. This forms a space corresponding to the intersection portion CP of the contact plug CCa. Next, as... Figure 29As shown, the bottom of each contact hole LH is machined through anisotropic etching processes such as RIE, penetrating the insulating film 50 and reaching the sacrificial component 62a. Next, as... Figure 30 As shown, the sacrificial film 66 is formed within each contact hole LH in a manner that the contact holes LH are not completely buried. The sacrificial film 66 comprises, for example, silicon oxide. Then, as... Figure 31 As shown, a space corresponding to the connector portion JT is formed in the upper part of each contact hole LH, and a sacrificial member 67 is embedded within the contact hole LH. The shape corresponding to the connector portion JT is formed, for example, by expanding the upper part of the contact hole LH using wet etching after a portion of the sacrificial member 67 is embedded into the contact hole LH. Subsequently, the remaining portion of the sacrificial member 67 is embedded within the contact hole LH. The sacrificial member 67 comprises, for example, amorphous silicon.

[0199] (2: Details of step ST113)

[0200] The details of step ST113 are explained below. Figure 32 , Figure 33 , Figure 34 and Figure 35 These are cross-sectional views illustrating an example of the cross-sectional construction of the memory device 1 during step ST113. Figures 32-35 Show respectively with Figure 8 The area shown corresponds to the region.

[0201] In the WL replacement in step ST113, when sacrificial components 62a, 62b, and 63 are removed via the slits corresponding to component SLT, a process is formed. Figure 32 The structure is shown. In the space where the sacrificial component 63 has been removed, the sides of the sacrificial film 66 within each contact hole LH are exposed. Next, the conductive layer 24 is embedded in the region (space) where the sacrificial components 62a and 62b have been removed. At this time, in the region where the sacrificial component 63, which is thicker than the sacrificial components 62a and 62b, has been removed, in the wide space formed by removing the sacrificial component 63, as shown... Figure 33 As shown, the high-dielectric film 54, the barrier metal 55, and the conductive component 56 are sequentially formed in a manner that does not completely embed them. The high-dielectric film 54 formed in the space where the sacrificial component 63 has been removed corresponds to... Figure 8 The high-dielectric film 52 is shown. Subsequently, when the remaining conductive layer 24 is removed from the side of the slit corresponding to the component SLT, as shown... Figure 34 As shown, the barrier metal 55 and conductive component 56 formed in the space where the sacrificial component 63 has been removed are removed via a slit corresponding to component SLT. Subsequently, as... Figure 35 As shown, an insulating component 53 is embedded inside the high-dielectric film 52 in the region where the sacrificial component 63 has been removed, thus completing the connection with... Figure 8 The structure corresponding to the insulating film 51 shown.

[0202] (3: Details of step ST115)

[0203] The details of step ST115 are explained below. Figure 36 and Figure 37 These are cross-sectional views illustrating an example of the cross-sectional construction of the memory device 1 during step ST115. Figure 36 and Figure 37 Show respectively with Figure 8 The area shown corresponds to the region.

[0204] In the processing of step ST115, firstly, as Figure 36 As shown, multiple contact holes CHa are formed in such a way that they penetrate the insulating layer 38 and their bottoms reach the sacrificial member 67 within the corresponding contact hole LH. Next, as... Figure 37 As shown, the sacrificial film 66 and sacrificial component 67 within the multiple contact holes CCa are selectively removed. At the same time, a portion of the high-dielectric film 52 within the insulating film 51 and a portion of the high-dielectric film 54 within the conductive layer 24a are also removed via the multiple contact holes LH. Consequently, the barrier metal 55 within the conductive layer 24a is exposed at the bottom of each contact hole LH. Furthermore, the high-dielectric film 52 within the insulating film 51 and the high-dielectric film 54 within the conductive layer 24a are recessed in the planar direction via the multiple contact holes LH. As a result, spaces corresponding to the first, second, and fourth portions of the barrier metal 57 of the contact plug CCa are formed within each contact hole LH.

[0205] <1-3> Effects of the first embodiment

[0206] Next, the effects of the memory device 1 in the first embodiment will be explained.

[0207] In 3D stacked NAND flash memory, the difficulty of etching processes used to form memory pillars (MP), component layers (SLT), support pillars (HR), and contact plugs (CC) increases with the number of word lines (WL). Furthermore, in the machining of contact holes for forming contact plugs (CC), there is a height difference corresponding to the position of the wiring layer at the connection destination. As the number of word lines (WL) increases and the height difference in contact hole machining increases, there are concerns about the penetration of contact holes corresponding to the wiring layer positions.

[0208] In contrast, the memory device 1 of the first embodiment has a contact plug CC divided into two levels (lower level T). LCA and the higher level T UCAThe structure is formed by dividing the contact plug CC into two layers, reducing the maximum height of the contact hole processing in each layer and decreasing the height difference of the contact hole processing. This improves the controllability of the contact hole processing in each layer and suppresses contact hole penetration. As a result, it reduces the occurrence of defects where contact hole penetration is the main cause, improving the yield of the memory device 1. Therefore, the memory device 1 of the first embodiment can reduce the manufacturing cost of the memory device 1. Furthermore, in the fifth embodiment, the lower layer T... LCA The advantages of the stop structure will be described in detail.

[0209] <1-4> Examples of variations of the first embodiment

[0210] The memory device 1 of the first embodiment can be modified in various ways. Hereinafter, the first, second, third and fourth modifications of the first embodiment will be described in sequence.

[0211] (First variation of the first embodiment)

[0212] Figure 38 This is a cross-sectional view showing an example of the cross-sectional structure of the contact region CA of the memory cell array 10a in the first variation of the first embodiment. For example... Figure 38 As shown, the conductive layer 24a of the memory cell array 10a has a configuration in which the barrier metal 55 of the conductive layer 24a is omitted, and the conductive member 56 is replaced by a conductive member 59. The conductive member 59 is disposed inside the high-dielectric film 54. The conductive member 59 has a portion that is in contact with the high-dielectric film 54 and a portion that is in contact with the barrier metal 57 of the contact plug CCa. The conductive member 59 contains, for example, molybdenum (Mo). As in the first variation of the first embodiment, a conductive layer 24a without the barrier metal 55 may also be used as a multilayer wiring.

[0213] (Second variation of the first embodiment)

[0214] Figure 39 and Figure 40 These are cross-sectional views showing an example of the cross-sectional structure of the manufacturing process of the memory device 1 in the second variation of the first embodiment. Figure 41 This is a cross-sectional view showing an example of the cross-sectional structure of the contact region CA of the memory cell array 10b in the second variation of the first embodiment. In the second variation of the first embodiment, the processing of step ST107 is different. In the second variation of the first embodiment, in the processing of step ST107, anisotropic etching is used when removing the sacrificial member 63 at the bottom of each contact hole LH.

[0215] Specifically, in step ST107 of the second variation of the first embodiment, firstly, multiple contact holes LH are formed by anisotropic etching such as RIE, penetrating the insulating layer 37 and reaching the sacrificial member 63 at their bottom. Then, as... Figure 39 As shown, sacrificial parts 63 at the bottom of each contact hole LH are selectively removed through anisotropic etching processes such as RIE. Then, as... Figure 40 As shown, similar to the first embodiment, the bottom of each contact hole LH is processed by anisotropic etching such as RIE to penetrate the insulating film 50 and reach the sacrificial member 62a. Therefore, in the second variation of the first embodiment, the side of the portion penetrating (through) the insulating layer 37, the side of the portion penetrating (through) the sacrificial member 63 (intersection CP), and the side of the portion penetrating (through) the insulating film 50 in the contact hole LH are substantially the same.

[0216] Subsequently, when steps ST108 to ST116 are performed in the same manner as in the first embodiment, a process is formed. Figure 41 The structure shown is as follows. In the second variation of the first embodiment, the diameter (XY cross-sectional area) of the intersection portion CP of the contact plug CCa is smaller than that of the first embodiment. Furthermore, the barrier metal 57 of the contact plug CCa of the memory cell array 10b is the same as that of the first embodiment, and can have a first portion, a second portion, and a fourth portion that are enlarged in the planar direction.

[0217] (Third variation of the first embodiment)

[0218] Figure 42 and Figure 43 These are cross-sectional views showing an example of the cross-sectional structure of the manufacturing process of the memory device 1 in the third variation of the first embodiment. Figure 44 This is a cross-sectional view showing an example of the cross-sectional structure of the contact region CA of the memory cell array 10c in the third variation of the first embodiment. In the third variation of the first embodiment, the processing content of step ST107 is different. In the third variation of the first embodiment, an insulating film is embedded in the portion recessed within the contact hole LH by a wet etching process of the same direction.

[0219] Specifically, in step ST107 of the second variation of the first embodiment, firstly, a plurality of contact holes LH are formed by anisotropic etching such as RIE, penetrating the insulating layer 37 and reaching the sacrificial member 63 at their bottom. Next, similar to the first embodiment, a portion of the sacrificial member 63 is selectively removed via each contact hole LH using a wet etching process with phosphoric acid or the like. Then, as in the second variation... Figure 42As shown, an insulating film 68 is formed within each contact hole LH. At this time, the insulating film 68 is formed in a manner where each contact hole LH is not completely embedded. The insulating film 68 is, for example, silicon oxide. Next, as... Figure 43 As shown, the insulating film 68 provided on the side of the contact hole LH is removed. Thus, in the intersection portion CP of each contact hole LH, the insulating film 68 is left in the portion that expands in the planar direction (the space of the sacrificial member 63 is removed). Subsequently, similar to the first embodiment, the bottom of each contact hole LH is processed by anisotropic etching such as RIE, so as to penetrate the insulating film 50 and reach the sacrificial member 62a. Therefore, in the third variation of the first embodiment, the side of the portion penetrating the insulating layer 37, the side of the portion penetrating the insulating film 68 (intersection portion CP), and the side of the portion penetrating the insulating film 50 are substantially the same in the contact hole LH.

[0220] Subsequently, when steps ST108 to ST116 are performed in the same manner as in the first embodiment, a process is formed. Figure 44 The structure shown is as follows. In the third variation of the first embodiment, the diameter (XY cross-sectional area) of the intersection portion CP of the contact plug CCa is smaller than that of the first embodiment. Furthermore, the barrier metal 57 of the contact plug CCa of the memory cell array 10c, like in the first embodiment, has a fourth portion that expands in the planar direction. On the other hand, the barrier metal 57 of the contact plug CCa of the memory cell array 10c differs from that of the first embodiment, and does not have the first and second portions that expand in the planar direction.

[0221] (Fourth variation of the first embodiment)

[0222] Figure 45 This is a cross-sectional view showing an example of the cross-sectional structure of the contact region CA of the memory cell array 10d in the fourth variation of the first embodiment. For example... Figure 45 As shown, in the memory cell array 10d, the contact region CA has the same configuration as the source line SL in the memory region MA, and contact plugs CCs are connected to the semiconductor layer 23. The contact plugs CCs have the same configuration as the contact plug CCa. Furthermore, the bottom of the contact plugs CCs is connected to the semiconductor layer 23, for example. Therefore, the memory device 1 can control the voltage of the source line SL via the contact plugs CCs. In the fourth variation of the first embodiment, the memory device 1 can control the voltage of the source line SL via the contact plugs CCs in the contact region CA. In this case, the conductive components LI within each component SLT can be omitted.

[0223] <2> Second Implementation Method

[0224] The second embodiment relates to a case where the multilayer wiring in the first embodiment is arranged in three layers. Hereinafter, details of the second embodiment will be explained, primarily focusing on the differences from the first embodiment.

[0225] <2-1> Composition

[0226] First, the configuration of the memory device 1 in the second embodiment will be described.

[0227] <2-1-1> Cross-sectional construction of memory region MA

[0228] Figure 46 This is a cross-sectional view showing an example of the cross-sectional structure of the memory region MA of the memory cell array 10A provided in the memory device 1 of the second embodiment. For example... Figure 46 As shown, the memory cell array 10A has stacked wiring formed in three layers.

[0229] In the second embodiment, the lower-level layer in the three-layer stacked wiring is referred to as "lower-level layer T". LCA The upper-level layer in the three-layer stacked cabling is called the "upper-level layer T". UCA "The lower level T in the three-level stacked wiring..." LCA With the higher level T UCA The levels between them are called "intermediate levels T". MCA "The lower level T" LCA With intermediate level T MCA The boundary is called "boundary BD1". The intermediate level T... MCA With the higher level T UCA The boundary is called "Boundary BD2".

[0230] In the memory cell array 10A, the stacked wiring (multiple conductor layers 24) extends to the lower-level layers T. LCA Intermediate level T MCA and the higher level T UCA And configuration.

[0231] In the second embodiment, the lower level T LCA The included conductive layer 24 and insulating layer 32 are referred to as conductive layer 24a and insulating layer 32a, respectively. The intermediate layer T... MCA The included conductive layer 24 and insulating layer 32 are referred to as conductive layer 24b and insulating layer 32b, respectively. The upper layer T... UCAThe included conductive layer 24 and insulating layer 32 are referred to as conductive layer 24c and insulating layer 32c, respectively. In this example, boundary BD1 is located between conductive layer 24a, which functions as word line WL2, and conductive layer 24b, which functions as word line WL3. In other words, boundary BD1 is located between the uppermost conductive layer 24a and the lowermost conductive layer 24b. Boundary BD2 is located between conductive layer 24b, which functions as word line WL6, and conductive layer 24c, which functions as word line WL7. In other words, boundary BD2 is located between the uppermost conductive layer 24b and the lowermost conductive layer 24c.

[0232] Furthermore, in the second embodiment, the space between the uppermost conductive layer 24a and the lowermost conductive layer 24b, that is, the lower-level layer T... LCA With intermediate level T MCA The insulating layer 32 (32a) corresponding to the boundary BD1 is called "insulator layer 32j1". The space between the uppermost conductive layer 24b and the lowermost conductive layer 24c, that is, the intermediate layer T... MCA With the higher level T UCA The insulating layer 32 (32b) corresponding to the boundary BD2 is called "insulator layer 32j2". The thickness of insulating layers 32j1 and 32j2 in the Z direction is thicker than the other insulating layers 32 (32a, 32b, 32c). That is, the Z-direction spacing of the conductive layers 24a and 24b adjacent to the dielectric boundary BD1 is wider than the Z-direction spacing of the two conductive layers 24 (24a, 24b, 24c) adjacent to the non-dielectric boundaries BD1 or BD2. The Z-direction spacing of the conductive layers 24b and 24c adjacent to the dielectric boundary BD2 is wider than the Z-direction spacing of the two conductive layers 24 (24a, 24b, 24c) adjacent to the non-dielectric boundaries BD1 or BD2. Furthermore, insulating layers 32j1 and 32j2 may each be composed of multiple insulating layers.

[0233] In the second embodiment, each memory column MP is formed in three layers. Specifically, each memory column MP includes a lower-level memory column LMP, an intermediate-level memory column MMP, and a higher-level memory column UMP connected in the Z direction. The lower-level memory column LMP, the intermediate-level memory column MMP, and the higher-level memory column UMP are each contained in the lower-level layer T. LCA Intermediate level T MCA and the higher level T UCAThe boundary between the lower-level memory cylinder LMP and the intermediate-level memory cylinder MMP is substantially the same as boundary BD1. The boundary between the intermediate-level memory cylinder MMP and the upper-level memory cylinder UMP is substantially the same as boundary BD2. The upper-level memory cylinder UMP, for example, extends through four conductive layers 24c (word lines WL7-WL9 and select gate line SGD) and four insulating layers 32c, and its bottom is connected to the upper end of the intermediate-level memory cylinder MMP. The intermediate-level memory cylinder MMP, for example, extends through four conductive layers 24b (word lines WL3-WL6), three insulating layers 32b, and insulating layer 32j2, and its bottom is connected to the upper end of the lower-level memory cylinder LMP. The lower-level memory pillar (LMP) passes through, for example, four conductive layers 24a (select gate line SGS and word lines WL0 to WL2), three insulating layers 32a, insulating layers 31 and 32j1, and semiconductor layers 22 and 23, with its bottom located within semiconductor layer 21.

[0234] Furthermore, each of the core component 40, the semiconductor film 41, and the multilayer film 42 is continuously disposed within the lower-level memory column LMP, the intermediate-level memory column MMP, and the upper-level memory column UMP. Each of the lower-level memory column LMP, the intermediate-level memory column MMP, and the upper-level memory column UMP has, for example, a conical shape (a positive conical shape) in which the upper diameter (XY cross-sectional area) is larger than the lower diameter (XY cross-sectional area). Therefore, the boundaries BD1 and BD2 can be identified respectively by observing the cross-sectional shape of the memory column MP. Each of the lower-level memory column LMP, the intermediate-level memory column MMP, and the upper-level memory column UMP can be referred to as a sub-column of the memory column MP. The lower-level memory column LMP may also have a shape in which the width increases in the portion intersecting with the insulating layer 32j1. The intermediate-level memory column MMP may also have a shape in which the width increases in the portion intersecting with the insulating layer 32j2.

[0235] In the second embodiment, it will be related to the lower level T LCA The stacked structure comprising four conductive layers 24a, three insulating layers 32a, and insulating layer 32j1 is referred to as the "lower-level stacked structure." This is related to the intermediate layer T. MCA The stacked structure comprising four conductive layers 24b, three insulating layers 32b, and insulating layer 32j2 is referred to as an "intermediate stacked structure." This is related to the higher-level layer T. UCA The stacked structure corresponding to the four conductive layers 24c and four insulating layers 32c is called the "upper stack".

[0236] <2-1-2> Cross-sectional structure of the contact region CA

[0237] Figure 47This is a cross-sectional view showing an example of the cross-sectional structure of the contact area CA of the memory cell array 10A provided in the memory device 1 of the second embodiment. Figure 47 The XZ cross-section of the contact region CA, which includes the memory cell array 10A, is shown. (Example) Figure 47 As shown, the memory cell array 10A includes, for example, insulating layers 37a, 37b, and 38, and insulating films 50a, 50b, 51a, and 51b in the contact area CA. Furthermore, the memory cell array 10A includes multiple contact plugs CC, with each block BLK comprising multiple contact plugs CCa1, multiple contact plugs CCa2, and multiple contact plugs CCb.

[0238] Insulator layer 37a is embedded in contact region CA by the lower layer T. LCA The structure is arranged in a stepped manner, comprising multiple platform sections TP. The insulating layer 37b is embedded in the contact region CA, formed by the intermediate layer T. MCA The structure is arranged in a stepped manner, comprising multiple platform sections TP. The insulating layer 38 is embedded in the contact area CA, formed by the upper layer T. UCA The multiple platform portions TP are arranged in a stepped manner. Each of the insulating layers 37a, 37b and 38 contains, for example, silicon oxide.

[0239] Insulating film 50a with its upper surface along the lower layer T LCA The multiple conductive layers 24a are arranged in a stepped shape with a stepped arrangement formed by multiple platform portions TP. The insulating film 50a is located below the boundary BD1. The insulating film 50b has its upper surface along the intermediate layer T. MCA The multiple conductive layers 24b are arranged in a stepped shape with a stepped difference, forming multiple platform portions TP. An insulating film 50b is located between boundaries BD1 and BD2. Insulating films 50a and 50b, for example, contain silicon oxide.

[0240] Insulating film 51a is on insulating film 50a, and is adjacent to the lower layer T. LCA The multiple platform portions TP of the included multiple conductive layers 24a are arranged in an overlapping manner in the Z direction. The upper surface of the insulating film 51a has a shape along the lower layer T. LCA The multiple platform portions TP of the included conductive layers 24a form a stepped shape with distinct differences. The insulating film 51a is located below the boundary BD1. The insulating film 51b is on top of the insulating film 50b, with intermediate layer T. MCA The multiple platform portions TP of the included multiple conductive layers 24b are arranged in an overlapping manner in the Z direction. The upper surface of the insulating film 51b has a shape along the intermediate layer T. MCAThe plurality of conductive layers 24b comprise a stepped shape formed by multiple platform portions TP. An insulating film 51b is located between boundaries BD1 and BD2. Each of the insulating films 51a and 51b has a structure that replaces a component used as a stop film during hole machining corresponding to the contact plug CC with an insulator. Insulating films 51a and 51b, for example, comprise silicon oxide. The thickness of each of the insulating films 51a and 51b is thicker than that of the conductive layer 24.

[0241] In the second embodiment, multiple contact plugs CCa1 are electrically connected to the lower level T. LCA The included multiple conductive layers 24a have multiple platform portions TP. Furthermore, each contact plug CCa1 is formed in three layers. Specifically, each contact plug CCa1 includes a lower-level contact plug LCC, an intermediate-level contact plug MCC, and an upper-level contact plug UCC connected in the Z direction. The lower-level contact plug LCC, intermediate-level contact plug MCC, and upper-level contact plug UCC are each contained within the lower-level layer T. LCA Intermediate level T MCA and the higher level T UCA The boundary between the lower-level contact plug LCC and the intermediate-level contact plug MCC is substantially the same as boundary BD1. The boundary between the intermediate-level contact plug MCC and the upper-level contact plug UCC is substantially the same as boundary BD2. In contact plug CCa1, the upper-level contact plug UCC penetrates through insulating layers 33 and 38, and its bottom is connected to the upper end of the intermediate-level contact plug MCC. In contact plug CCa1, the intermediate-level contact plug MCC penetrates through insulating layer 37b, and its bottom is connected to the upper end of the lower-level contact plug LCC. In contact plug CCa1, the lower-level contact plug LCC penetrates through insulating layers 37a and insulating films 50a and 51a, and its bottom is connected to the platform portion TP where the corresponding conductive layer 24a is established.

[0242] In the second embodiment, multiple contact plugs CCa2 are respectively connected to the intermediate level T. MCA The contact plugs comprise multiple platform portions TP of the multiple conductive layers 24b. Furthermore, each contact plug CCa2 is formed in two layers. Specifically, each contact plug CCa2 includes an intermediate contact plug MCC and an upper contact plug UCC connected in the Z direction. In the contact plug CCa2, the upper contact plug UCC penetrates through insulating layers 33 and 38, and its bottom is connected to the upper end of the intermediate contact plug MCC. In the contact plug CCa2, the intermediate contact plug MCC penetrates through insulating layers 37b and insulating films 50b and 51b, and its bottom is connected to the platform portion TP where the corresponding conductive layer 24b is formed. In the contact plug CCa2, the intermediate contact plug MCC can be referred to as the lower contact plug.

[0243] In the second embodiment, multiple contact plugs CCb are respectively connected to the upper-level layer T. UCA The multiple conductive layers 24c include multiple platform portions TP. Specifically, the contact plug CCb penetrates (through) the insulating layers 33 and 38, and its bottom is connected to the platform portion TP that forms the corresponding conductive layer 24c.

[0244] The other configurations of the memory device 1 in the second embodiment are the same as those in the first embodiment.

[0245] <2-2> Manufacturing Method

[0246] Next, as a method for manufacturing the memory device 1 according to the second embodiment, appropriate reference will be made. Figure 48 The method for forming the stacked wiring and contact plugs CC corresponding to the memory cell array 10A is explained. Figure 48 This is a flowchart illustrating an example of a method for manufacturing the memory device 1 according to the second embodiment. Figure 49 , Figure 50 , Figure 51 , Figure 52 , Figure 53 , Figure 54 , Figure 55 and Figure 56 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the memory device 1 according to the second embodiment. Figures 49-56 The regions forming the memory pillar MP and component SLT, and a portion of the contact region CA are shown respectively.

[0247] First, similar to the first embodiment, a source line portion is formed (step ST101), a lower-level stack is formed (step ST102), and the lower-level layer T is executed. LCA The stepped processing (step ST103) forms the lower level T. LCA The stop section (step ST104) executes the next level T. LCA Step embedding and flattening (step ST105), LMP machining and sacrificial part embedding (step ST106), LCC machining and sacrificial part embedding (step ST107). Thus, a... Figure 49 The structure shown. In addition, in the processing of steps ST101 to ST107 in the second embodiment, the insulating layers 32j and 37, the insulating film 50, and the sacrificial components 63, 64 and 65 in the first embodiment are respectively referred to as insulating layers 32j1 and 37a, insulating film 50a, and sacrificial components 63a, 64a and 65a.

[0248] Next, by sequentially executing steps ST201, ST202, ST203, and ST204, a process is formed. Figure 50 The structure shown.

[0249] In step ST201, an intermediate stack is formed. Specifically, as the intermediate stack, multiple sacrificial members 62b corresponding to multiple conductive layers 24b and multiple insulating layers 32b are alternately stacked on insulating layer 32j1. The sacrificial members 62b, for example, contain silicon nitride. Furthermore, an insulating layer 32j2 is formed on the uppermost sacrificial member 62b. Additionally, components that will serve as a hard mask (protective film) in subsequent step processing may be provided on insulating layer 32j2.

[0250] In the processing of step ST202, the intermediate level T is executed. MCA The stepped processing. Through the processing in step ST202, a process is formed consisting of intermediate level T. MCA The stepped structure is formed by multiple platform portions TP of multiple sacrificial components 62b. The platform portions TP of the sacrificial component 62b correspond to the parts of the sacrificial component 62b that do not overlap with the upper sacrificial component 62b.

[0251] In step ST203, an intermediate level T is formed. MCA The stop section. Intermediate level T MCA The stop portion includes a stop film used in the formation process of multiple holes for forming the intermediate contact plug MCC described later. Specifically, firstly, the insulating film 50b and the sacrificial member 63b are sequentially formed. Then, to cover the intermediate layer T MCA The insulating film 50b and the sacrificial component 63b are processed (removed) in a manner that leaves the multiple platform portions TP of the multiple sacrificial components 62b. At this time, the insulating film 50b and the sacrificial component 63b formed on the memory region MA are removed, as are the insulating film 50b and the sacrificial component 63b on the insulating layer 37a and the insulating film 50b and the sacrificial component 63b on the insulating layer 32j2. The shape of the sacrificial component 63b corresponds to Figure 47 The shape of the insulating film 51b is shown. The sacrificial member 63b can be used as a stop film. The sacrificial member 63b is made of, for example, the same material as the sacrificial member 62b, but a different material from the insulating layers 37b and 38, and is formed to be thicker than the sacrificial member 62b. The sacrificial member 63b contains, for example, silicon nitride.

[0252] In the processing of step ST204, the intermediate level T is executed. MCA The step embedding and flattening. Specifically, taking the embedding of intermediate level T... MCAThe insulating layer 37b is formed using a stepped structure. Furthermore, a portion of the insulating layer 37b is removed, for example, by a CMP (Chemical Mechanical Polishing) process. This aligns (planarizes) the upper surface of the insulating layer 32j2 with the upper surface of the insulating layer 37b. If a component serving as a hard mask is provided in step ST201, this component (hard mask) is removed in step ST204.

[0253] Next, by sequentially executing steps ST205 and ST206, a process is formed. Figure 51 The structure shown.

[0254] In step ST205, MMP fabrication and sacrificial component embedding are performed. Specifically, firstly, multiple holes corresponding to the intermediate memory pillar MMP are formed such that they penetrate the sacrificial component 62b, and the insulating layers 32b and 32j2, with their bottoms reaching the sacrificial components 64a corresponding to the multiple lower memory pillars LMP. Then, the sacrificial component 64b is embedded in the multiple holes corresponding to the intermediate memory pillar MMP. The sacrificial component 64b may be made of, for example, any of carbon, silicon, or a metallic material.

[0255] In step ST206, MCC machining and sacrificial component embedding are performed. Through this process, a structure corresponding to the plurality of intermediate contact plug MCCs is formed from the sacrificial component 65b. The details of this process are the same as step ST107 of the first embodiment. Briefly, a plurality of holes corresponding to the intermediate contact plug MCCs of contact plug CCa1 and the intermediate contact plug MCCs of contact plug CCa2 are formed, and sacrificial components 65b are embedded in these holes. The bottoms of the plurality of sacrificial components 65b corresponding to the intermediate contact plug MCCs of contact plug CCa1 are respectively connected to a plurality of sacrificial components 65a corresponding to the lower-level contact plug LCCs of contact plug CCa1. The bottoms of the plurality of sacrificial components 65b corresponding to the intermediate contact plug MCCs of contact plug CCa2 are respectively connected to a plurality of platform portions TP of the plurality of sacrificial components 62b.

[0256] Next, the same steps ST108, ST109, and ST110 as in the first embodiment are executed sequentially. That is, a higher-level stack is formed (step ST108), and the higher-level layer T is executed. UCA The stepped processing (step ST109) executes the upper-level T. UCA The step embedding and flattening (step ST110). In addition, in the processing of steps ST108 to ST110 in the second embodiment, the insulating layer 32b and the sacrificial member 62b in the first embodiment are respectively referred to as the insulating layer 32c and the sacrificial member 62c.

[0257] Next, as Figure 52 As shown, UMP processing and MP formation are performed (step ST207). Specifically, firstly, multiple holes corresponding to the upper memory pillar UMP are formed to penetrate the sacrificial component 62c and the insulating layer 32c, with their bottoms reaching the sacrificial component 64b formed in the corresponding intermediate memory pillar MMP. Then, sacrificial components 64a formed in each hole corresponding to the lower memory pillar LMP and sacrificial components 64b formed in each hole corresponding to the intermediate memory pillar MMP are removed through the multiple holes corresponding to the upper memory pillar UMP. Then, a multilayer film 42, a semiconductor film 41, and a core component 40 are formed in each hole corresponding to the group of upper memory pillar UMP, intermediate memory pillar MMP, and lower memory pillar LMP (i.e., memory pillar MP). Subsequently, an insulating layer 33 is formed on the uppermost insulating layer 32c and insulating layer 38.

[0258] Next, by sequentially executing steps ST208, ST209, and ST114, the following process is formed: Figure 53 The structure shown.

[0259] In step ST208, SLT processing is performed. Specifically, the slits corresponding to the component SLT are formed in such a way that they pass through the sacrificial components 62a, 62b, 62c, 63a and 63b, the semiconductor layer 23, the insulating layers 31, 32a, 32b, 32c, 32j1, 32j2, 33 and 36a, and the insulating films 50a and 50b, and their bottoms reach the sacrificial component 61.

[0260] In step ST209, SL replacement and WL replacement are performed. Specifically, firstly, by SL replacement, the insulating layers 60 and 36a and the sacrificial component 61 of the memory region MA are replaced with the semiconductor layer 22. Then, by WL replacement, the sacrificial components 62a, 62b, and 62c of the memory region MA and the contact region CA are replaced with conductive layers 24a, 24b, and 24c, respectively. The details of the SL replacement are the same as in the first embodiment.

[0261] In the WL replacement, firstly, the insulating film on the sides of the slit is removed. Then, sacrificial components 62a, 62b, 62c, 63a, and 63b are removed via wet etching through the slits corresponding to component SLT. Next, a conductive layer 24 is embedded in the regions (spaces) where sacrificial components 62a, 62b, and 62c have been removed. Materials corresponding to the conductive layer 24 are also formed in the regions where sacrificial components 63a and 63b have been removed. Subsequently, the remaining conductive layer 24 is removed from the sides and bottom of the slits corresponding to component SLT, and above the insulating layer 33. At this time, the conductive material of the conductive layer 24 formed in the regions where sacrificial components 63a and 63b have been removed is also removed. Then, insulating components 53 are embedded in the regions where sacrificial components 63a and 63b have been removed. Thus, a structure corresponding to insulating films 51a and 51b is formed. Subsequently, the process of step ST114 is performed, and in the same manner as in the first embodiment, spacers SP and conductive components LI are formed in each slit corresponding to component SLT.

[0262] Next, perform UCC machining and remove sacrificial parts for MCC and LCC (step ST210). Specifically, first, as... Figure 54 As shown, multiple contact holes CHa1, CHa2, and CHb are formed, for example, by penetrating insulating layers 33 and 38. Contact hole CHa1 corresponds to the upper contact plug UCC of contact plug CCa1. The bottoms of the multiple contact holes CHa1 respectively reach multiple sacrificial components 65b corresponding to the intermediate contact plug MCC of contact plug CCa1. Contact hole CHa2 corresponds to the upper contact plug UCC of contact plug CCa2. The bottoms of the multiple contact holes CHa2 respectively reach multiple sacrificial components 65b corresponding to the intermediate contact plug MCC of contact plug CCa2. The bottoms of the multiple contact holes CHb respectively reach multiple platform portions TP of multiple conductive layers 24c. Then, as... Figure 55 As shown, multiple sacrificial components 65a and 65b corresponding to the lower-level contact plug LCC and the intermediate-level contact plug MCC of contact plug CCa1 are removed via multiple contact holes CCa1 or CCa2, and multiple sacrificial components 65b corresponding to the intermediate-level contact plug MCC of contact plug CCa2 are removed. The details of this process are the same as step ST115 of the first embodiment.

[0263] Next, as Figure 56As shown, similar to the first embodiment, the CC conductive component is embedded (step ST116). Specifically, firstly, a conductive component is formed by embedding multiple contact holes CCa1, multiple contact holes CCa2, and multiple contact holes CHb respectively. Then, the remaining conductive component is removed outside the contact holes CCa1, CCa2, and CHb. Thus, a structure corresponding to multiple contact plugs CCa1, a structure corresponding to multiple contact plugs CCa2, and a structure corresponding to multiple contact plugs CCb are formed.

[0264] By following the steps outlined above, the usage will be complete. Figure 46 and Figure 47 The construction of the storage cell array 10A is described.

[0265] <2-3> Effects of the second implementation method

[0266] As described in the second embodiment, the contact plug CC can also be formed in three layers. By increasing the number of layers of the contact plug CC according to the layer of the wiring layer of the connection destination, similar to the first embodiment, the maximum height of the contact hole processing in each layer becomes lower, and the height difference of the contact hole processing becomes smaller. Therefore, in the second embodiment, similar to the first embodiment, the occurrence of defects caused by contact hole penetration is suppressed, and the yield of memory device 1 is improved. Therefore, the memory device 1 of the second embodiment, like the first embodiment, can reduce the manufacturing cost of memory device 1.

[0267] <3> Third Implementation Method

[0268] The third embodiment addresses a case where the number of layers of the contact plug CCa differs from the number of layers of the stacked wiring in the memory cell array 10A described in the second embodiment. Hereinafter, details of the third embodiment will be provided, primarily focusing on the differences from the second embodiment.

[0269] <3-1> Composition

[0270] First, the configuration of the memory device 1 in the third embodiment will be described.

[0271] Figure 57 This is a cross-sectional view showing an example of the cross-sectional structure of the contact region CA of the memory cell array 10B provided in the memory device 1 of the third embodiment. For example... Figure 57 As shown, the storage cell array 10B has multiple contact plugs CC, each of which includes multiple contact plugs CCa, multiple contact plugs CCb1 and multiple contact plugs CCb2 per block BLK.

[0272] In the third embodiment, multiple contact plugs CCa are electrically connected to the lower level T. LCAThe included multiple conductive layers 24a have multiple platform portions TP. Furthermore, each contact plug CCa has three layers (lower layer T) throughout the multilayer wiring. LCA Intermediate level T MCA and the higher level T UCA The configuration, on the other hand, is structured in two layers. Specifically, each contact plug CCa contains a lower-level contact plug LCC and an upper-level contact plug UCC connected in the Z direction. Within each contact plug CCa, the lower-level contact plug LCC is contained within the lower-level layer T... LCA The upper-level contact plug UCC is contained in the intermediate level T. MCA and the higher level T UCA In each contact plug CCa, the boundary between the lower-level contact plug LCC and the upper-level contact plug UCC is substantially the same as boundary BD1. In each contact plug CCa, the upper-level contact plug UCC penetrates (passes through) insulating layers 33, 37b, and 38, and its bottom is connected to the upper end of the lower-level contact plug LCC. In each contact plug CCa, the lower-level contact plug LCC penetrates (passes through) insulating layer 37a and insulating films 50a and 51a, and its bottom is connected to the platform portion TP where the corresponding conductive layer 24a is established.

[0273] In the third embodiment, the plurality of contact plugs CCb1 are electrically connected to the intermediate level T. MCA The included multiple conductive layers 24b have multiple platform portions TP. Furthermore, multiple contact plugs CCb1 have coverage across two layers (intermediate layer T). MCA and the higher level T UCA The configuration, on the other hand, is a structure formed in a 1-level configuration. Specifically, each contact plug CCb1 is contained in the intermediate level T. MCA and the higher level T UCA Each contact plug CCb1 penetrates through insulating layers 33, 37b and 38, and its bottom is connected to the platform portion TP where the corresponding conductive layer 24b is formed.

[0274] In the third embodiment, multiple contact plugs CCb2 are electrically connected to the upper-level layer T. UCA The multiple conductive layers 24c comprise multiple platform portions TP. Each contact plug CCb2 is formed in a single layer, contained within the upper layer T. UCA Each contact plug CCb2 penetrates through insulating layers 33 and 38, and its bottom is connected to the platform portion TP where the corresponding conductive layer 24c is established.

[0275] The other configurations of the memory device 1 in the third embodiment are the same as those in the second embodiment.

[0276] <3-2> Manufacturing Method

[0277] Next, as a method for manufacturing the memory device 1 according to the third embodiment, appropriate reference will be made. Figure 58 The method for forming the stacked wiring and contact plugs CC corresponding to the memory cell array 10B is explained. Figure 58 This is a flowchart illustrating an example of a method for manufacturing the memory device 1 according to the third embodiment. Figure 59 , Figure 60 , Figure 61 and Figure 62 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the memory device 1 according to the third embodiment.

[0278] First, similar to the second embodiment, a source line portion is formed (step ST101), a lower-level stack is formed (step ST102), and the lower-level layer T is executed. LCA The stepped processing (step ST103) forms the lower level T. LCA The stop section (step ST104) executes the next level T. LCA Step embedding and flattening (step ST105), LMP machining and sacrificial part embedding (step ST106), LCC machining and sacrificial part embedding (step ST107).

[0279] Next, similar to the second embodiment, an intermediate stack is formed (step ST201), and the intermediate layer T is executed. MCA Step-by-step machining (step ST202), performing intermediate level T MCA The step embedding and flattening (step ST204) are performed, followed by MMP processing and sacrificial part embedding (step ST205). Thus, in the third embodiment, step ST203 is omitted. Therefore, the intermediate level T is not formed. MCA The stop section.

[0280] Next, similar to the second embodiment, a higher-level stack is formed (step ST108), and the higher-level layer T is executed. UCA The stepped processing (step ST109) executes the upper-level T. UCA The step embedding and flattening (step ST110) are performed, followed by UMP processing and MP formation (step ST207). This results in the formation of... Figure 59 The structure shown.

[0281] Next, as in the second embodiment, SLT machining is performed (step ST208), followed by SL replacement and WL replacement (step ST209). The SLT machining and WL replacement in the third embodiment are the same as those in the second embodiment after omitting the processing related to the sacrificial component 63b. Subsequently, as in the second embodiment, SLT component embedding is performed (step ST114). Thus, a [structure / component] is formed. Figure 60 The structure shown.

[0282] Next, perform UCC machining and LCC sacrificial part removal (step ST301). Specifically, first, as... Figure 61 As shown, multiple contact holes CHa, CHb1, and CHb2 are formed. The multiple contact holes CHa correspond to the upper-level contact plug UCC of the contact plug CCa and are formed by penetrating insulating layers 33, 37b, and 38. The bottoms of the multiple contact holes CHa reach multiple sacrificial components 65a corresponding to the lower-level contact plug LCC of the contact plug CCa. The multiple contact holes CHb1 correspond to the contact plug CCb1 and are formed by penetrating insulating layers 33, 37b, and 38. The bottoms of the multiple contact holes CHb1 reach multiple platform portions TP of multiple conductive layers 24b. The multiple contact holes CHb2 correspond to the contact plug CCb2 and are formed by penetrating insulating layers 33 and 38. The bottoms of the multiple contact holes CHb2 reach multiple platform portions TP of multiple conductive layers 24c. Subsequently, the multiple sacrificial components 65a corresponding to the lower-level contact plug LCC of the contact plug CCa are removed via the multiple contact holes CHa. The details of this process are the same as those of step ST115 in the first embodiment.

[0283] Next, as Figure 62 As shown, similar to the first embodiment, the CC conductive component is embedded (step ST116). Specifically, firstly, a conductive component is formed by embedding multiple contact holes CHa, multiple contact holes CHb1, and multiple contact holes CHb2 respectively. Then, the remaining conductive component is removed outside the contact holes CHa, CHb1, and CHb2. Thus, a structure corresponding to the multiple contact plugs CCa, a structure corresponding to the multiple contact plugs CCb1, and a structure corresponding to the multiple contact plugs CCb2 are formed.

[0284] By following the steps outlined above, the usage will be complete. Figure 57 The construction of the storage cell array 10B is described.

[0285] <3-3> Effects of the third implementation method

[0286] As described in the third embodiment, the maximum number of layers of the contact plug CC can be different from the number of layers of the stacked wiring, and the number of divisions of the contact plug CC can be reduced according to the ease of processing the contact holes. Therefore, the memory device 1 of the third embodiment can suppress the occurrence of defects where contact hole penetration is the main cause, and can reduce the number of processes used to form the contact plug CC. As a result, the memory device 1 of the third embodiment reduces the manufacturing cost of the memory device 1 more than that of the second embodiment.

[0287] <4> Fourth Implementation Method

[0288] In the fourth embodiment, the insulating films 50 and 51 in the first embodiment are provided in a manner that does not cover at least one of the plurality of conductive layers 24a from the boundary BD side. Hereinafter, the differences between the fourth embodiment and the first embodiment will be mainly described in detail.

[0289] <4-1> Composition

[0290] First, the configuration of the memory device 1 in the fourth embodiment will be described.

[0291] Figure 63 This is a cross-sectional view showing an example of the cross-sectional structure of the contact area CA of the memory cell array 10C provided by the memory device 1 of the fourth embodiment. Figure 63 The XZ cross-section of the contact region CA, which includes the memory cell array 10C, is shown. (Example) Figure 63 As shown, the memory cell array 10C includes insulating films 50c and 51c instead of insulating films 50 and 51 in the contact area CA, for example. Furthermore, the memory cell array 10C includes multiple contact plugs CC, at least one contact plug CCb1, and multiple contact plugs CCb2 per block BLK.

[0292] Insulating film 50c to the lower layer T LCA The plurality of conductive layers 24a included are arranged such that multiple platform portions TP of the multiple conductive layers 24a, except for at least one conductive layer 24a from the boundary BD side, are covered. In other words, the insulating film 50c has the structure described in the first embodiment, in which the insulating film 50 is arranged in a manner that does not cover the platform portion TP of at least one conductive layer 24a from the boundary BD side. Further, in other words, the lower layer T LCA The included multiple conductive layers 24a include those disposed in the lower layer T LCA With the higher level T UCA At least one intermediate conductive layer near the boundary BD. Furthermore, the insulating film 50c is used to connect the lower layer T. LCAThe multiple platform portions TP of the multiple conductive layers 24a, excluding the intermediate conductive layer, are covered in a manner that allows for coverage.

[0293] An insulating film 51c is disposed on an insulating film 50c. Furthermore, in the Z direction, the insulating film 51c is adjacent to the lower layer T. LCA The multiple platform portions TP of the multiple conductive layers 24a, excluding the intermediate conductive layer, overlap. In other words, the insulating film 51c has the structure described in the first embodiment, in which the insulating film 51 is disposed in a manner that does not overlap with the platform portion TP of the intermediate conductive layer in the Z direction. The thickness of the insulating film 51c is thicker than that of the conductive layers 24.

[0294] In the fourth embodiment, multiple contact plugs CCa are electrically connected to the lower level T. LCA The plurality of conductive layers 24a included are covered by insulating films 50c and 51c, and each conductive layer 24a has multiple platform portions TP. Furthermore, each contact plug CCa, like in the first embodiment, is formed in two layers. In each contact plug CCa, the upper-level contact plug UCC penetrates through insulating layers 33 and 38, and its bottom is connected to the upper end of the lower-level contact plug LCC. In each contact plug CCa, the lower-level contact plug LCC penetrates through insulating layer 37 and insulating films 50c and 51c, and its bottom is connected to the platform portion TP where the corresponding conductive layer 24a is formed.

[0295] In the fourth embodiment, at least one contact plug CCb1 is electrically connected to the lower level T. LCA The platform portion TP of at least one conductive layer 24a (intermediate conductive layer) that is not covered by insulating films 50c and 51c among the multiple conductive layers 24a included. Furthermore, each contact plug CCb1 has two layers (lower layer T) covering the multilayer wiring. LCA and the higher level T UCA The configuration, on the other hand, is a structure formed in a hierarchical manner. Specifically, each contact plug CCb1 is contained in the lower-level hierarchy T. LCA and the higher level T UCA Each contact plug CCb1 penetrates through insulating layers 33, 37 and 38, and its bottom is connected to the platform portion TP where the corresponding conductive layer 24a is formed.

[0296] In the fourth embodiment, multiple contact plugs CCb2 are electrically connected to the upper-level layer T. UCA The multiple conductive layers 24b comprise multiple platform portions TP. Each contact plug CCb2 is formed in a single layer, contained within the upper layer T. UCAEach contact plug CCb2 penetrates through insulating layers 33 and 38, and its bottom is connected to the platform portion TP where the corresponding conductive layer 24b is formed.

[0297] The other configurations of the memory device 1 in the fourth embodiment are the same as those in the first embodiment.

[0298] <4-2> Manufacturing Method

[0299] Next, as a method for manufacturing the memory device 1 according to the fourth embodiment, appropriate reference will be made. Figure 64 The method for forming the stacked wiring and contact plugs CC corresponding to the memory cell array 10C is explained. Figure 64 This is a flowchart illustrating an example of a method for manufacturing the memory device 1 according to the fourth embodiment. Figure 65 , Figure 66 , Figure 67 , Figure 68 , Figure 69 , Figure 70 , Figure 71 and Figure 72 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the memory device according to the fourth embodiment. Figures 65-72 The regions forming the memory pillar MP and component SLT, and a portion of the contact region CA are shown respectively.

[0300] First, similar to the first embodiment, a source line portion is formed (step ST101), a lower-level stack is formed (step ST102), and the lower-level layer T is executed. LCA Stepped machining (step ST103).

[0301] Next, the lower level T is formed. LCA The stop portion (step ST401). Specifically, firstly, the insulating film 50c and the sacrificial component 63c are sequentially formed. Then, as... Figure 65 As shown, to cover the lower level T LCA The insulating film 50c and the sacrificial component 63c are processed (removed) in a manner that leaves only a portion of the stepped structure (multiple platform portions TP) of the multiple sacrificial components 62a, excluding the sacrificial component 62a corresponding to the intermediate conductor layer. At this time, the insulating film 50c and the sacrificial component 63c formed on the memory region MA are removed, and the insulating film 50c and the sacrificial component 63c on the insulating layer 32j are also removed.

[0302] Next, similar to the first embodiment, the lower level T is executed. LCA Step embedding and flattening (step ST105). Thus, as... Figure 66 As shown, an insulating layer 37 is formed.

[0303] Next, similar to the first embodiment, LMP machining and sacrificial component embedding are performed (step ST106), and LCC machining and sacrificial component embedding are performed (step ST107). Thus, as... Figure 67 As shown, sacrificial components 64 are embedded in multiple holes corresponding to the lower-level memory cylinder LMP, and sacrificial components 65 are embedded in multiple holes corresponding to the lower-level contact plug LCC. Furthermore, in step ST106 of the fourth embodiment, sacrificial components 65 are not formed on the platform portion TP of at least one sacrificial component 62a that is not covered by the insulating film 50c and the sacrificial component 63c.

[0304] Next, similar to the first embodiment, a higher-level stack is formed (step ST108), and the higher-level layer T is executed. UCA The stepped processing (step ST109) executes the upper-level T. UCA Step embedding and flattening (step ST110). Thus, as... Figure 68 As shown, multiple platform portions TP forming multiple sacrificial components 62b form an insulating layer 38.

[0305] Next, as in the first embodiment, UMP processing and MP formation are performed (step ST111). Thus, as... Figure 69 As shown, a memory column MP is formed.

[0306] Next, similar to the first embodiment, SLT machining is performed (step ST112), SL replacement and WL replacement are performed (step ST113), and SLT component embedding is performed (step ST114). Thus, as... Figure 70 As shown, semiconductor layer 22 is connected to semiconductor film 41 of memory pillar MP to form multilayer wiring (multiple conductive layers 24a and 24b), forming insulating film 51c, and forming component SLT.

[0307] Next, perform UCC machining and LCC sacrificial part removal (step ST402). Specifically, first, as... Figure 71 As shown, multiple contact holes CHa, CHb1, and CHb2 are formed. The multiple contact holes CHa correspond to the upper-level contact plug UCC of the contact plug CCa, and are formed by penetrating insulating layers 33 and 38. The bottoms of the multiple contact holes CHa respectively reach multiple sacrificial components 65 that correspond to the lower-level contact plug LCC of the contact plug CCa. The multiple contact holes CHb1 correspond to the contact plug CCb1, and are formed by penetrating insulating layers 33, 37, and 38. The bottom of each contact hole CHb1 reaches the lower-level layer T. LCAThe platform portion TP of the conductive layer 24a (intermediate conductive layer) is not covered by the insulating films 50c and 51c. Multiple contact holes CHb2 are formed corresponding to contact plugs CCb2, penetrating the insulating layers 33 and 38. The bottoms of the multiple contact holes CHb2 reach the multiple platform portions TP of the multiple conductive layers 24b. Subsequently, multiple sacrificial components 65 corresponding to the lower-level contact plug LCC of the contact plug CCa are removed via the multiple contact holes CHa. The details of this process are the same as step ST115 of the first embodiment.

[0308] Next, as Figure 72 As shown, the CC conductive component is embedded (step ST116). Specifically, firstly, conductive components are formed by embedding multiple contact holes CHa, multiple contact holes CHb1, and multiple contact holes CHb2 respectively. Then, the remaining conductive components are removed outside the contact holes CHa, CHb1, and CHb2. Thus, a structure corresponding to the multiple contact plugs CCa, a structure corresponding to the multiple contact plugs CCb1, and a structure corresponding to the multiple contact plugs CCb2 are formed.

[0309] By following the steps outlined above, the usage will be complete. Figure 63 The construction of the memory cell array 10C is described.

[0310] <4-3> Effects of the fourth embodiment

[0311] Next, the effects of the memory device 1 of the fourth embodiment will be explained using the first comparative example. The first comparative example corresponds to the case where the thickness of the insulating layer 32j in the memory device 1 of the first embodiment is TH1. Figure 73 This is a cross-sectional view showing an example of the cross-sectional structure near the boundary BD of the stack during the manufacturing process of the memory device 1 of the first comparative example. In this project, the sacrificial component 62a, which is included in the lower-level stack and has 3 layers from top, is referred to as sacrificial component 62a-1, 62a-2, and 62a-3 in sequence from top to bottom.

[0312] In the first comparative example, such as Figure 73 As shown in (A), when executing the lower level T LCA The timing of the step difference embedding, the lower level T LCA The platform portions TP of the upper sacrificial components 62a-1, 62a-2, and 62a-3 are each covered by the insulating film 50 and the sacrificial component 63. Subsequently, when the lower-level T is executed... LCA During planarization (CMP treatment), recesses may occur in portions of the insulating layer 37. Then, when the CMP treatment reaches the surface of the target insulating layer 32j, as... Figure 73As shown in (B), there is a case where a portion of the sacrificial member 63 above the platform portion TP of the sacrificial member 62a-1 is cut off by recessing.

[0313] Thus, in a multi-layered, stepped structure, the lower level T LCA The shape of the upper sacrificial member 63 cannot be maintained due to manufacturing processes. When the film thickness of the sacrificial member 63 becomes thinner, during the formation process of the contact hole LH, the bottom of the contact hole LH may penetrate the sacrificial member 62a-1 and reach the sacrificial member 62a-2, potentially becoming a major cause of short circuits in the adjacent conductive layer 24. To suppress the effect of the recess on the sacrificial member 63, it is considered to increase the film thickness of the insulating layer 32j. However, increasing the film thickness of the insulating layer 32j becomes a major cause of the increase in the channel resistance of the memory cylinder MP. Therefore, the film thickness of the insulating layer 32j is preferably formed as thin as possible.

[0314] In contrast, in the memory device 1 of the fourth embodiment, the sacrificial member 63, which serves as a stop, is disposed without covering the lower level T. LCA The upper part is arranged in such a way that at least one layer of sacrificial component 62a is provided. Figure 74 This is a cross-sectional view showing an example of the cross-sectional structure near the boundary BD of the stack during the manufacturing process of the memory device 1 of the fourth embodiment.

[0315] In the fourth embodiment, when executing the lower level T LCA The timing of the step difference embedding, for example, forming Figure 74 The structure shown in (A) is as follows. In this example, the insulating film 50 and the sacrificial member 63 are arranged such that they cover the sacrificial member 62a-3 but do not cover the sacrificial members 62a-1 and 62a-2. Therefore, in the fourth embodiment, the distance between the upper end of the sacrificial member 63 and the upper end of the insulating layer 32j is increased. When the lower layer T is performed in this state... LCA During planarization (CMP treatment), even if the CMP treatment reaches the surface of the target insulating layer 32j, such as Figure 74 As shown in (B), the effect of the concavity will not reach the sacrificial part 63.

[0316] Thus, in the memory device 1 of the fourth embodiment, by changing the lower-level layer T LCA The range of the sacrificial component 63 formed in the middle can suppress the film thickness of the sacrificial component 63 in the lower layer T. LCA It thins during flattening. Furthermore, for the lower level T... LCA The processing of contact holes in sacrificial components 62a (e.g., sacrificial components 62a-1 and 62a-2) that are not covered by insulating film 50 and sacrificial components 63, and the processing of contact holes in the upper layer T. UCAThe contact hole machining of the included sacrificial component 62b is performed together.

[0317] As a result, the memory device 1 of the fourth embodiment, like the one of the first embodiment, forms contact plugs CCa in multiple layers, and the film thickness TH2 of the insulating layer 32j is thinner than TH1. As a result, in addition to the same effects as the one of the first embodiment, the memory device 1 of the fourth embodiment can also reduce the channel resistance of the memory pillar MP and improve the operating characteristics of the memory device 1.

[0318] Furthermore, in the memory device 1 of the fourth embodiment, because the distance between the upper end of the sacrificial member 63 and the upper end of the insulating layer 32j can be increased, the sacrificial member 63 can be formed to be thicker than in the first embodiment. As a result, the memory device 1 of the fourth embodiment can improve the lower-level layer T. LCA The tolerance of the stop membrane in the middle can reduce the T in the lower layer. LCA The difficulty of machining contact holes in the process.

[0319] Furthermore, in the memory device 1 of the fourth embodiment, the target of the multiple contact holes CHb1 and CHb2 in the UCC processing of step ST402 is metal (the platform portion TP of the conductor layer 24a or 24b). Therefore, the UCC processing can increase the etch selectivity between the insulating layers 33, 38, and 37 and the conductor layers 24a and 24b. For example, in the UCC processing, the bottom of the contact hole CHb2 corresponding to the uppermost conductor layer 24b reaches the target conductor layer 24b first, but by increasing the etch selectivity, penetration of the uppermost conductor layer 24b (over-etching) can be suppressed. In addition, in the UCC processing, since the bottom of the contact hole CHb1 reaches the target intermediate conductor layer last, over-etching can be suppressed. Thus, the UCC processing of the fourth embodiment, performed after WL replacement, can achieve the same results even without using the layer T formed at the lower level. LCA The stop portion, such as the sacrificial component 63, can also suppress excessive etching of multiple contact holes CHb1 and CHb2. Therefore, the memory device 1 of the fourth embodiment can reduce the upper-level layer T. UCA The ease of machining the contact holes in the process. Thus, the advantages of performing contact hole machining after WL replacement can also be applied to other implementation methods.

[0320] Furthermore, in the memory device 1 of the fourth embodiment, in the lower level T of step ST401 LCAWhen forming the stop portion, an insulating film 51c, which is made of a material different from any of the sacrificial components 62a and 62b and the insulating layer 37, may be formed to replace the sacrificial component 63c. In this example, the insulating film 51c is not replaced or removed by WL, but remains in the memory cell array 10C. Moreover, in this example, the insulating film 51c does not contain the high-dielectric film 52 and is made of a material having an etch selectivity different from that of the insulating layer 37. In this example, the insulating film 51c may not be formed thicker than the conductive layer 62a. In this case, the memory device 1 of the fourth embodiment can also obtain the same effect as the fourth embodiment described above.

[0321] <5> Fifth Implementation Method

[0322] The fifth embodiment relates to a case where the multilayer wiring in the first embodiment is arranged in a single layer, and two memory regions MA are configured such that a contact region CA is sandwiched between them in the X direction. Hereinafter, details of the fifth embodiment will be provided, primarily focusing on the differences from the first embodiment.

[0323] <5-1> Composition

[0324] First, the configuration of the memory device 1 in the fifth embodiment will be described.

[0325] <5-1-1> Planar Layout of 10D Memory Cell Array

[0326] Figure 75 This is a top view showing an example of the planar layout of the memory cell array 10D provided in the memory device 1 of the fifth embodiment. For example... Figure 75 As shown, the memory cell array 10D includes memory regions MA1 and MA2, and a contact region CA. The contact region CA of the memory cell array 10D is sandwiched between memory regions MA1 and MA2 in the X direction. Furthermore, the contact region CA of the memory cell array 10D includes a sub-contact region CAe and a bridging region BRe in even-numbered blocks BLK (BLK0, BLK2, ...), and a sub-contact region CAo and a bridging region BRo in odd-numbered blocks BLK (BLK1, BLK3, ...).

[0327] In each even-numbered BLK block, the sub-contact regions CAe and bridging regions BRe are arranged in the Y direction. Within the sub-contact regions CAe, settings are configured as follows: Figure 3 or Figure 6 The stepped structure of the multilayer wiring is described, with multiple contact plugs CC. In each even-numbered block BLK, the multilayer wiring provided in memory region MA1 and the multilayer wiring provided in memory region MA2 are connected to each other via bridging regions BRe, with the wiring layers (conductor layers 24) on the same layer being continuously connected.

[0328] In each odd-numbered block BLK, the sub-contact region CAo and the bridging region BRo are arranged in the Y direction. Within the sub-contact region CAo, settings are configured as follows: Figure 3 or Figure 6 The stepped structure of the multilayer wiring is described, with multiple contact plugs CC. In each odd-numbered block BLK, the multilayer wiring provided in memory region MA1 and the multilayer wiring provided in memory region MA2 are connected to each other via bridging region BRo, with the wiring layers (conductor layers 24) on the same layer being continuously arranged.

[0329] In adjacent even-numbered and odd-numbered blocks of BLK in the Y direction, the sub-contact regions CAe and CAo, or the bridging regions BRe and BRo, are adjacent to the dielectric separator SLT. The multilayer wiring in the sub-contact regions CAe and CAo adjacent to the dielectric separator SLT has, for example, a structure that is symmetrically arranged with reference to the separator SLT between adjacent sub-contact regions CAe and CAo. In addition, in the memory cell array 10D, the conductive layer 24 used as the select gate line SGD can also be separated between the memory regions MA1 and MA2.

[0330] <5-1-2> Cross-sectional structure of memory region MA

[0331] Figure 76 This is a cross-sectional view showing an example of the cross-sectional structure of the memory region MA1 of the memory cell array 10D provided in the memory device 1 of the fifth embodiment. For example... Figure 76 As shown, the memory cell array 10D has stacked wiring formed in one layer.

[0332] Specifically, the memory cell array 10D has the following characteristics: Figure 4 In the illustrated memory cell array 10, conductive layers 24a and 24b are replaced with a conductive layer 24, and insulating layers 32a, 32b, and 32j are replaced with an insulating layer 32. Thus, because the stacked wiring of the memory cell array 10D is constructed with a single-layer stacked structure, the memory cell array 10D does not have the same characteristics as... Figure 4 The insulating layer 32j corresponding to the boundary BD of the layer shown and the boundary BD of the adjacent layer are also shown. Furthermore, in the memory cell array 10D, the memory pillars MP are formed in one layer, similar to the stacked wiring. In the fifth embodiment, the stacked structure corresponding to the plurality of conductive layers 24 and the plurality of insulating layers 32 is referred to as a "stacked structure".

[0333] <5-1-3> Cross-sectional structure of the contact area CA

[0334] Figure 77 This is a cross-sectional view showing an example of the cross-sectional structure of the contact area CA of the memory cell array 10D provided in the memory device 1 of the fifth embodiment. Figure 77The diagram shows a YZ cross-section of blocks BLK0 and BLK1 within the contact region CA of the memory cell array 10D, and including the platform portion TP of the conductor layer 24 corresponding to the word line WL3. (See diagram for reference.) Figure 77 As shown, pseudo-step structures, which are secondary formations during the step processing of the multilayer wiring, are provided between the sub-contact region CAe and the bridging region BRe, and between the sub-contact region CAo and the bridging region BRo. Furthermore, insulating films 50 and 51 are provided together with the step structure of the multilayer wiring (the step structure formed by multiple platform portions TP of multiple conductive layers 24) to cover the pseudo-step structures.

[0335] In addition, Figure 77 In the example shown, insulating films 50 and 51 are configured to cover the stepped structure of the plurality of conductive layers 24, excluding the single conductive layer 24 from the top, as in the fourth embodiment. However, this is not a limitation; in the fifth embodiment, insulating films 50 and 51 can be configured to cover the platform portions TP of all conductive layers 24, or they can be configured to cover the platform portions TP of the plurality of conductive layers 24, excluding the platform portions TP of two or more conductive layers 24 from the top.

[0336] The other configurations of the memory device 1 in the fifth embodiment are the same as those in the first embodiment.

[0337] <5-2> Manufacturing Method

[0338] Next, as a method for manufacturing the memory device 1 according to the fifth embodiment, appropriate reference will be made. Figure 78 The method for forming the stacked wiring and contact plugs CC corresponding to the memory cell array 10D is explained. Figure 78 This is a flowchart illustrating an example of a method for manufacturing the memory device 1 according to the fifth embodiment. Figure 79 , Figure 80 , Figure 81 , Figure 82 and Figure 83 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the memory device 1 according to the fifth embodiment. Figures 79-83 Show respectively with Figure 77 The area shown corresponds to the region.

[0339] First, similar to the first embodiment, a source line portion is formed (step ST101). Then, a laminate is formed (step ST501), and a stepped processing of the laminate is performed (step ST502). The processing of steps ST501 and ST502 is the same as that in steps ST102 and ST103 of the first embodiment, where the lower-level laminate is renamed as a laminate, the insulating layers 32a and 32j are renamed as insulating layer 32, and the sacrificial member 62a is renamed as sacrificial member 62. Through the processing of step ST502, a stepped structure composed of multiple platform portions TP of multiple sacrificial members 62 is formed in the sub-contact regions CAe and CAo, and a pseudo-stepped structure is also formed.

[0340] Next, the stop portion is formed (step ST503). Specifically, first, the insulating film 50 and the sacrificial member 63 are formed sequentially. Then, through photolithography, such as... Figure 79 As shown, a photoresist REG is formed. The photoresist REG is set in such a way that it covers the sub-contact regions CAe and CAo. Then, through an etching process, as shown... Figure 80 As shown, the insulating film 50 and sacrificial component 63 not covered by the resist REG are removed. Subsequently, the resist REG is removed.

[0341] Next, step embedding and planarization are performed (step ST504). Specifically, the insulating layer 37 is formed by embedding the stepped structure created in step ST502. Moreover, for example, a portion of the insulating layer 37 is removed by CMP processing. As a result, the upper surface of the uppermost insulating layer 32 is aligned with the upper surface of the insulating layer 37 (planarization).

[0342] Next, MP processing and MP formation are performed (step ST505). Specifically, firstly, a plurality of holes corresponding to the memory pillar MP are formed in such a way that they penetrate sacrificial components 61 and 62, semiconductor layer 23, and insulating layers 31, 32, 36a, and 60, and their bottoms reach semiconductor layer 21. Then, a stacked film 42, a semiconductor film 41, and a core component 40 are formed in each hole corresponding to the memory pillar MP. Subsequently, an insulating layer 33 is formed on top of the uppermost insulating layer 32 and insulating layer 37.

[0343] Next, perform CC machining and sacrificial part embedding (step ST506). Specifically, first, as... Figure 81 As shown, a plurality of contact holes CH are formed using sacrificial member 63 as a stop film. Subsequently, similar to step ST107 of the first embodiment, a structure corresponding to the intersection portion CP of the contact plug CC is formed, and the bottom of the contact hole CH is machined in such a way that it penetrates the insulating film 50 and reaches the sacrificial member 62. Then, the sacrificial member 65 is embedded in the plurality of contact holes CH.

[0344] Next, SLT processing is performed (step ST507). Specifically, the slit TR corresponding to the component SLT is formed in such a way that it passes through the sacrificial components 62 and 63, the semiconductor layer 23, the insulating layers 31, 32, 33 and 36a, and the insulating film 50, and its bottom reaches the sacrificial component 61.

[0345] Next, perform SL replacement and WL replacement (step ST508). Specifically, first, as... Figure 82 As shown, by SL replacement, the insulating layers 60 and 36a and the sacrificial component 61 of the memory region MA are replaced with the semiconductor layer 22. Then, by WL replacement, each sacrificial component 62 is replaced with the conductive layer 24. Specifically, in WL replacement, the insulating film on the side of the slit TR is first removed. Then, as... Figure 83 As shown, sacrificial components 62 and 63 are removed via wet etching through the slit TR corresponding to component SLT. Then, conductive layer 24 is embedded in the area (space) where sacrificial component 62 has been removed. Materials corresponding to conductive layer 24 are also formed in the area where sacrificial component 63 has been removed. Subsequently, the remaining conductive layer 24 is removed from the sides and bottom of the slit TR, and above the insulating layer 33. At this time, the conductive material of the conductive layer 24 formed in the area where sacrificial component 63 has been removed is also removed. Then, insulating component 53 is embedded in the area where sacrificial component 63 has been removed. Thus, a structure corresponding to insulating film 51 is formed.

[0346] Next, as in the first embodiment, the SLT component embedding is performed (step ST114). Specifically, firstly, an insulating film corresponding to the spacer SP is formed. Then, the insulating film at the bottom of the slits TR corresponding to the component SLT is removed. Then, conductive components LI are formed by filling each slit TR. Subsequently, the remaining conductive components LI are removed above the insulating layer 33.

[0347] Next, CC sacrificial component removal is performed (step ST509). Specifically, multiple sacrificial components 65 within multiple contact holes CH are selectively removed, for example, by wet etching.

[0348] Next, similar to the first embodiment, the CC conductive component is embedded (step ST116). That is, the conductive component is formed by embedding multiple contact holes CH, and the remaining conductive component is removed outside the contact holes CH. Thus, a structure corresponding to multiple contact plugs CC is formed.

[0349] By following the steps outlined above, the usage will be complete. Figures 75-77 The construction of the storage cell array 10D is described.

[0350] <5-3> Effects of the fifth embodiment

[0351] Hereinafter, the effects of the fifth embodiment will be explained using Comparative Example 2. The second comparative example differs from the fifth embodiment in that it has a structure in which the component corresponding to the stop film during the processing of the contact hole CH is not in contact with the component SLT, and the processing of the contact hole CH is performed after WL is replaced. Figure 84 , Figure 85 , Figure 86 , Figure 87 , Figure 88 and Figure 89 These are cross-sectional views illustrating an example of the cross-sectional structure of the memory device 1 of the second comparative example during its manufacturing process.

[0352] In the second comparative example, when forming the stop portion, firstly as follows: Figure 84 The resist REGa is formed as shown. The resist REGa is provided such that it covers the sub-contact regions CAe and CAo, and has an opening in the area near the component SLT between the sub-contact regions CAe and CAo. Then, it is etched, as shown... Figure 85 As shown, the portion of the insulating film 50 not covered by the resist REGa and the sacrificial component 63 are removed, and the sacrificial component 63 between the sub-contact regions CAe and CAo is also removed. Thus, the sacrificial component 63 is divided into sacrificial component 63-1 within the sub-contact region CAe and sacrificial component 63-2 within the sub-contact region CAo. After removing the resist REGa, as... Figure 86 As shown, an insulating layer 37 is embedded in the sub-contact regions CAe and CAo. Subsequently, in the SLT processing of the second comparative example, as... Figure 87 As shown, the slit TR is formed in a manner that does not connect with the sacrificial parts 63-1 and 63-2. Therefore, in the SL and WL substitutions of the second comparative example, as Figure 88 As shown, during the process of removing sacrificial component 62, sacrificial components 63-1 and 63-2 are not removed and remain. Then, when WL replacement and SLT component embedding are performed, a process is formed. Figure 88 The structure is shown. Subsequently, sacrificial components 63-1 and 63-2 are used as stop membranes to perform contact hole machining. Then, a structure corresponding to the contact plug is formed in the contact hole.

[0353] In this second comparative example, if the aspect ratio of the region opening near the component SLT in the REGa resist increases with the increase in the number of layers in the multilayer wiring, the pattern of the REGa resist may collapse. Furthermore, the dimensional control of the REGa resist is difficult, and a highly tapered pseudo-step structure is required to position the ends of sacrificial components 63-1 and 63-2 between the component SLT and the contact plug CC.

[0354] In contrast, in the fifth embodiment, the resist REG used when processing the sacrificial component 63 is continuously formed between adjacent sub-contact regions CAe and CAo. As a result, the sacrificial component 63 is not interrupted between adjacent sub-contact regions CAe and CAo. Furthermore, before performing WL replacement, the sacrificial component 63 is used as a stop film to process the contact hole CH corresponding to the contact plug CC as described in step ST107 of the first embodiment. Moreover, after embedding the sacrificial component 65 into the formed contact hole CH, SLT processing is performed. In the fifth embodiment, the sacrificial component 63 is exposed on the side of the slit TR formed by SLT processing. On the other hand, in the fifth embodiment, because the sacrificial component 63 is formed to be thicker than the sacrificial component 62, the space where the sacrificial component 63 is removed cannot be completely embedded by the conductive component after performing WL replacement. Therefore, in the fifth embodiment, the conductive component can be removed from the space where the sacrificial component 63 is removed, and the insulating component 53 can be embedded in the space. As a result, short circuits of multiple contact plugs CC caused by the structure of the stop portion are avoided.

[0355] As explained above, in the memory device 1 of the fifth embodiment, the dimensional control of the resist REGa, as in the second comparative example, is not required when forming the resist REG. As a result, the memory device 1 of the fifth embodiment can reduce the ease of processing the sacrificial component 63 and improve the yield rate. Therefore, the memory device 1 of the fifth embodiment can reduce the manufacturing cost of the memory device 1. In addition, the effects described in the fifth embodiment are also achieved in the first to fourth embodiments.

[0356] <5-4> Examples of variations in the fifth embodiment

[0357] The memory device 1 of the fifth embodiment can be modified in various ways. For example, in the memory cell array 10D of the fifth embodiment, the insulating films 50 and 51 may also be arranged to cover the multilayer wiring in the memory region MA.

[0358] Figure 90 This is a cross-sectional view illustrating an example of the cross-sectional structure of the memory region MA of the memory cell array 10E provided in the memory device 1 according to a variation of the fifth embodiment. For example... Figure 90 As shown, in the memory cell array 10E, insulating films 50 and 51 are disposed, for example, between the uppermost insulating layer 32 and the insulating layer 33. In this case, the contact plug CV has a portion that extends through the insulating films 50 and 51. Although not shown in the figure, the insulating films 50 and 51 may also be disposed in a manner that covers the bridging regions BRe and BRo.

[0359] <6> Others

[0360] The memory device 1 described above can be modified in various ways.

[0361] In the above embodiments, the circuit configuration, planar layout, and cross-sectional structure of the memory device 1 can be appropriately modified. Multiple conductive layers 24, which function as select gate lines (SGS) or SGD, can also be provided. The number of wiring layers or contact plugs provided in the memory device 1 can be appropriately changed according to the circuit design. The XY cross-sectional structure of each of the memory pillar MP, support pillar HR, and contact plug CC can be approximately circular or approximately elliptical. In the above embodiments, an example is shown where the semiconductor film 41 of the memory pillar MP and the source line SL (semiconductor layer 22) are connected via the side of the memory pillar MP, but this is not a limitation. The semiconductor film 41 of the memory pillar MP and the source line SL (semiconductor layer 22) can also be electrically connected via the bottom of the memory pillar MP. The memory device 1 can also be a structure in which a chip with a memory cell array 10 is mounted, and a chip with circuitry other than the memory cell array 10 are bonded together.

[0362] In the described embodiment, the case where each of the lower-level memory column LMP, intermediate-level memory column MMP, and upper-level memory column UMP has a positive conical shape with an upper diameter (XY cross-sectional area) larger than its lower diameter (XY cross-sectional area) is described, but the shape of each sub-column of the memory column MP is not limited to this. For example, each sub-column may be a straight cylindrical shape with a substantially constant diameter, an inverted conical shape with a lower diameter (XY cross-sectional area) larger than its upper diameter (XY cross-sectional area), or an arc shape with the diameter (XY cross-sectional area) of the middle portion in the Z direction being the largest. Similarly, for each sub-contact plug of the contact plug CCa, it may be a straight cylindrical shape, an inverted conical shape, or an arc shape, similar to the memory column MP. Furthermore, the shape of the intersection portion CP of the contact plug CCa may also be a positive conical shape with an upper diameter (XY cross-sectional area) larger than its lower diameter (XY cross-sectional area).

[0363] In the embodiments described above, examples are shown using 2-level and 3-level stepped machining, but each embodiment can also be applied to stepped machining with 4 or more levels. The memory column MP can also have a structure with 4 or more levels. That is, the memory column MP can be machined by dividing it into 4 or more sections. The component SLT can also have a structure with 2 or more levels. That is, the component SLT can be machined by dividing it into 2 or more sections. The support column HR can also have a structure with 2 or more levels. That is, the support column HR can be machined by dividing it into 2 or more sections. As long as the contact plug CCa has a multi-level structure and multi-level stepped machining is used, the ideas described in embodiments 1 to 4 can be applied. The ideas described in embodiment 5 can be applied to any of embodiments 1 to 4.

[0364] Figure 91This is a cross-sectional view representing an example of a cross-sectional structure containing memory cylinders MP and near the boundary BD. Figure 91 Extract and display the lower level T LCA and the higher level T UCA Near the boundary BD. For example... Figure 91 As shown, for example in the YZ section, the upper end of the lower-level memory cylinder LMP may not be angular, but rather rounded. In this case, it cannot be said that the XY cross-sectional area of ​​the upper end of the lower-level memory cylinder LMP is significantly larger than the XY cross-sectional area of ​​the lower end of the upper-level memory cylinder UMP. However, the side profile shape of the memory cylinder MP is discontinuous in both the lower-level memory cylinder LMP and the upper-level memory cylinder UMP. Specifically, for example in the YZ section, the side profile SLMP of the lower-level memory cylinder LMP deviates from... Figure 91 The extension line of the side SUMP of the upper-level memory cylinder UMP is represented by a dashed line. The offset of the two side SLMPs and SUMPs may occur in any cross-section including the Z direction, such as the XZ section. In this specification, the boundary portion of the memory cylinder MP in two adjacent layers in the Z direction can be defined based on the discontinuous portions in the side shape of the memory cylinder MP. Even when the memory cylinder MP has a structure connecting three or more sub-cylinders, it can still have [discontinuities / discretions] in the boundary portion of adjacent layers. Figure 91 The structure shown. For the support column HR and component SLT, similar to the memory column MP, it is also possible to specify the boundary portion in two adjacent layers in the Z direction.

[0365] Figure 92 This is a cross-sectional view showing an example of a cross-sectional structure containing the contact plug CCa and near the boundary BD. Figure 92 Extract and display the lower level T LCA and the higher level T UCA Near the boundary BD. For example... Figure 92 As shown, the connector portion JT can be omitted from the contact plug CCa. In this case, the diameter (XY cross-sectional area) of the upper end of the lower-level contact plug LCC is larger than the diameter (XY cross-sectional area) of the lower end of the upper-level contact plug UCC. Even without the connector portion JT, by designing a larger diameter at the upper end of the lower-level contact plug LCC, the ease of overlap between the lower-level contact plug LCC and the upper-level contact plug UCC can be reduced. When the contact plug CCa has a structure with two or more layers and does not have the connector portion JT, the boundary portion of the contact plug CCa in two adjacent layers in the Z direction, like the memory column MP, can be specified based on the discontinuous portion in the side shape.

[0366] The manufacturing process described in this embodiment is only one example. If the same structure as the memory device 1 described in this embodiment can be formed, the order of processing can be changed. For example, the order of processing and component embedding of the lower-level memory column LMP and the order of processing and component embedding of the lower-level contact plug LCC can also be changed. Furthermore, in the manufacturing process described in this embodiment, the manufacturing process of the support column HR is omitted, but the process of forming the hole for forming the support column HR can be combined with other processes. For example, the process of forming the hole for forming the support column HR can also be integrated with the process of forming the hole for forming the memory column MP.

[0367] In this specification, "high-dielectric film" is also referred to as High-k (high dielectric constant film). High-dielectric films have a dielectric constant higher than that of silicon oxide. High-dielectric films are thinner than silicon oxide films, achieving equivalent insulation performance. Hafnium (Hf)-based oxides or zirconium (Zr)-based oxides may also be used as each of the high-dielectric films 52 and 54. "Barrier metal" may also be referred to as "barrier film" or "metal film".

[0368] In this specification, "connection" means electrical connection, which may include, for example, the presence of another element between them. "Electrical connection" may also include an insulator, provided it can function in the same way as an electrical connection. "Region" can also be considered as a configuration contained within a substrate. For example, if substrate 20 (semiconductor substrate) is specified to contain a memory region MA and a contact region CA, the memory region MA and the contact region CA are respectively associated with different regions above substrate 20. "Height" corresponds, for example, to the distance between the configuration of the object being measured and substrate 20 in the Z direction. Configurations other than substrate 20 may also be used as a reference for "height." "Upper surface (plane) observation" corresponds, for example, to viewing the surface of substrate 20 from a vertical direction. "Diameter" refers to the inner diameter of a hole or the outer diameter of a pillar in a cross-section (XY cross-section) parallel to the surface of substrate 20. "Thickness" corresponds, for example, to the thickness of the object being measured along the Z direction.

[0369] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, with various omissions, substitutions, and modifications possible without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, as well as within the scope of the invention as described in the claims and its equivalents.

[0370] [Explanation of Symbols]

[0371] 1. Memory devices

[0372] 2. Memory controller

[0373] 10, 10a, 10b, 10c, 10d, 10A, 10B, 10C, 10D, 10E Memory Cell Array

[0374] 11 Input / Output Circuit

[0375] 12 Logic Controller

[0376] 13 Register Circuit

[0377] 14 Sequence Generator

[0378] 15 Driver Circuit

[0379] 16-line decoder module

[0380] 17. Sensing Amplifier Module

[0381] 20 substrates

[0382] Semiconductor layers 21-23

[0383] 24, 24a, 24b, 24c, 25 Conductor layers

[0384] 30~32, 32a, 32b, 32c, 32j, 32j1, 32j2, 33~36, 36a, 37, 37a, 37b, 38, 60 Insulator Layer 40 Core Component

[0385] 41 Semiconductor film

[0386] 42. Laminated film

[0387] 43 Tunnel insulation film

[0388] 44 Charge storage membrane

[0389] 45 Barrier Insulating Film

[0390] 50, 50a, 50b, 50c, 51, 51a, 51b, 51c, 68 Insulating film

[0391] 52,54 high dielectric film

[0392] 53 Insulating components

[0393] 55,57 Barrier metals

[0394] 56, 58, 59 Conductive components

[0395] 61,62,62a,62a-1,62a-2,62a-3,62b,62c,63,63-1,63-2,63a,63b,63c,64,64a,64b,65,65a,65b,67 Sacrificial parts

[0396] 66 Sacrificial membrane

[0397] Boundaries of BD, BD1, BD2

[0398] MA, MA1, MA2 memory regions

[0399] CA contact area

[0400] CAe,CAo sub-contact areas

[0401] BR bridging area

[0402] BLK block

[0403] BL bitline

[0404] WL lettering

[0405] SL source line

[0406] MT memory cell transistor

[0407] STD,STS Select Transistor

[0408] SGD, SGS gate line selection

[0409] RD line decoder

[0410] SAU Sensing Amplifier Unit

[0411] CC,CCa1,CCa2,CCb1,CCb2 Contact plugs

[0412] LH,CHa,CHa1,CHa2,CHb,CHb1,CHb2 contact holes

[0413] TR slit

[0414] TH1, TH2 film thickness.

Claims

1. A memory device comprising: Multiple conductive layers are arranged in a first region and a second region in a first direction, and are disposed apart from each other in a second direction that intersects the first direction. They are also arranged across multiple layers including a first layer and a second layer above the first layer. Each conductive layer has a platform portion in the second region that does not overlap with a conductive layer disposed on the upper layer in the same layer of the multiple conductive layers and a first high dielectric film. A memory column is disposed in the first region and in the second direction through the plurality of conductive layers, and the portion intersecting with the plurality of conductive layers functions as a memory cell. An insulating film having a stepped shape along a stepped shape formed by multiple platform portions of multiple first conductive layers included in the first layer of the plurality of conductive layers, and being thicker than the plurality of first conductive layers, and including a second high dielectric film of the same material as the first high dielectric film. and Multiple contact plugs, in the second region, are respectively connected to multiple platform portions of the multiple conductive layers; and The plurality of contact plugs includes: a plurality of first contact plugs respectively connected to the plurality of first conductive layers, and each including a first sub-contact plug having a portion containing the insulating film within the first layer and passing through the first layer, and a second sub-contact plug having a portion passing through the second layer.

2. The memory device according to claim 1, wherein The thickness of the first high-dielectric film is approximately equal to that of the second high-dielectric film.

3. The memory device according to claim 1, wherein... The insulating film includes a first insulating component having a portion surrounded by the second high-dielectric film; and The first sub-contact plug has a portion in the second direction that sandwiches the first insulating member at the intersection with the insulating film.

4. The memory device according to claim 1, wherein The first sub-contact plug has a portion in the connection portion of the first conductor layer corresponding to the plurality of first conductor layers that extends along the first direction with a thickness approximately the same as that of the first high dielectric film.

5. The memory device according to claim 1, wherein The plurality of conductive layers further include a metal film disposed inside the first high-dielectric film, and a conductive component disposed inside the metal film and different from the metal film; and The conductive component contains tungsten.

6. The memory device according to claim 1, wherein Each of the plurality of conductive layers further includes a conductive component disposed inside the first high-dielectric film; and The conductive component contains molybdenum.

7. The memory device according to claim 1, wherein The insulating film includes a first insulating component having a portion surrounded by the second high-dielectric film; and In a cross-section along a direction orthogonal to the second direction, the cross-sectional area of ​​the portion of the first sub-contact plug that intersects with the first insulating member is greater than the cross-sectional area of ​​the portion of the first sub-contact plug that intersects with the portion of the plurality of first conductor layers that connects the first sub-contact plug.

8. The memory device according to claim 1, wherein The insulating film includes a first insulating component having a portion surrounded by the second high-dielectric film; and In a cross-section along a direction orthogonal to the second direction, the cross-sectional area of ​​the portion of the first sub-contact plug that intersects with the first insulating member is approximately equal to the cross-sectional area of ​​the portion of the first sub-contact plug that intersects with the portion of the plurality of first conductor layers that connects the first sub-contact plug.

9. The memory device according to claim 1, further comprising: The second insulating component is disposed between the first sub-contact plug and the second high-dielectric film.

10. The memory device according to claim 1, wherein At the boundary between the first layer and the second layer, the side shapes of the plurality of first contact plugs are discontinuous.

11. The memory device of claim 10, wherein The plurality of layers also includes a third layer above the second layer; and The plurality of conductive layers further include a plurality of second conductive layers contained in the second layer and a plurality of third conductive layers contained in the third layer; The plurality of contact plugs each have portions passing through the second layer and the third layer, and further include a plurality of second contact plugs respectively connected to the plurality of second conductor layers; The second sub-contact plug of the plurality of first contact plugs has a portion that also passes through the third layer; In the boundary between the second layer and the third layer, the side shapes of the plurality of second contact plugs are continuous, and the side shapes of the second sub-contact plugs are continuous.

12. The memory device according to claim 1, wherein In a cross-section along a direction orthogonal to the second direction, the cross-sectional area of ​​the end portion of the first sub-contact plug at the boundary between the first and second layers is greater than the cross-sectional area of ​​the end portion of the second sub-contact plug at the boundary.

13. A memory device comprising: Multiple conductive layers are arranged in a first region and a second region in a first direction, and are disposed apart from each other in a second direction that intersects the first direction. They are also arranged across multiple layers including a first layer and a second layer above the first layer. Each layer has a platform portion in the second region that does not overlap with a conductive layer disposed on the upper layer in the same layer of the multiple conductive layers. The multiple conductive layers included in the first layer and at least one intermediate conductive layer included in the first layer and disposed closer to the boundary between the first layer and the second layer than the multiple conductive layers. A memory column is disposed in the first region and in the second direction through the plurality of conductive layers, and the portion intersecting with the plurality of conductive layers functions as a memory cell. The insulating film is arranged such that its upper surface has a stepped shape along a stepped shape formed by multiple platform portions of the plurality of first conductor layers; and Multiple contact plugs, in the second region, are respectively connected to multiple platform portions of the multiple conductive layers; and The plurality of contact plugs includes a plurality of first contact plugs respectively connected to the plurality of first conductor layers, and at least one second contact plug respectively connected to the intermediate conductor layer of the at least one layer; Each of the plurality of first contact plugs includes a first sub-contact plug having a portion containing the insulating film within the first layer and passing through the first layer, and a second sub-contact plug having a portion passing through the second layer; The at least one second contact plug has a portion passing through the first layer and the second layer, and is disposed away from the insulating film.

14. The memory device of claim 13, wherein At the boundary between the first layer and the second layer, the side shapes of the plurality of first contact plugs are discontinuous, while the side shapes of the second contact plugs are continuous.

15. The memory device of claim 13, further comprising: The first insulating layer is provided in such a way that the step difference formed by the multiple platform portions of the multiple first conductive layers and the platform portion of the intermediate conductive layer is embedded therein, and the material is different from that of the insulating film.

16. The memory device of claim 15, further comprising: The second insulating layer is provided in such a way that it is embedded in a step formed by multiple platform portions of the multiple second conductive layers included in the second layer of the plurality of conductive layers; and Between the plurality of platform portions of the plurality of second conductive layers and the plurality of second insulating layers, no insulating film of a material different from that of the second insulating layers is provided.

17. A memory device comprising: Multiple conductive layers are multiple conductive layers arranged in a first region and a second region in a first direction, and disposed apart from each other in a second direction that intersects the first direction. Each conductive layer has a platform portion in the second region that does not overlap with the conductive layer disposed on the upper layer of the multiple conductive layers and a first high dielectric film. A memory column is disposed in the first region and in the second direction through the plurality of conductive layers, and the portion intersecting with the plurality of conductive layers functions as a memory cell. An insulating film having a stepped shape along a stepped shape formed by a plurality of platform portions of the plurality of conductive layers on its upper surface and being thicker than the plurality of conductive layers, and comprising a second high dielectric film of the same material as the first high dielectric film. and Multiple contact plugs are connected to multiple platform portions of the multiple conductive layers respectively through the insulating film in the second region.

18. The memory device of claim 17, wherein The thickness of the first high-dielectric film is approximately equal to that of the second high-dielectric film.

19. The memory device of claim 17, wherein The insulating film includes a first insulating component having a portion surrounded by the second high-dielectric film; and The plurality of contact plugs passing through the insulating film each have a portion in the second direction that sandwiches the first insulating member at the intersection with the insulating film.

20. The memory device of claim 17, wherein The plurality of contact plugs through the insulating film each have a portion extending along the first direction with a thickness approximately the same as that of the first high-dielectric film in the connection portion of the corresponding conductive layer in the plurality of conductive layers.

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