Memory device and method of manufacturing the same

Abstract

The present application relates to memory devices and methods of manufacturing the same. A memory device includes a plurality of insulating interlayers stacked in alternation with a plurality of gate lines on a first structure and at least one cell plug extending through the insulating interlayers and the gate lines. A barrier layer of the cell plug manufactured according to an embodiment includes a first barrier layer covering surfaces of the insulating pattern and the gate lines and a second barrier pattern formed on the first barrier layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, including but not limited to a three-dimensional memory device and a method for manufacturing a three-dimensional memory device. Background Technology

[0002] Memory devices can be volatile memory devices that lose stored data when power is interrupted. Non-volatile memory devices retain stored data when power is interrupted.

[0003] Non-volatile memory devices include NAND flash memory, NOR flash memory, resistive random access memory (ReRAM), phase change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT RAM), etc.

[0004] Among these memory devices, the non-volatile memory device, formed as a three-dimensional structure, includes cell plugs formed through multiple insulating layers alternately stacked with multiple gate lines. Each gate line includes a gate electrode and a gate barrier layer configured to surround the gate electrode. Summary of the Invention

[0005] According to an embodiment, a memory device may include: a plurality of insulating interlayers that are alternately stacked with a plurality of gate lines in a first structure; and cell plugs that extend through the insulating interlayers and the gate lines.

[0006] In one embodiment, the cell plug may include a plurality of insulating patterns, a first barrier layer, a second barrier pattern, a charge trapping pattern, a tunnel insulating layer, a channel layer, and a core post. The insulating patterns may protrude from the interlayer insulating layer toward the center of the cell plug. The first barrier layer may be formed to cover the surface of the gate line and the insulating patterns. The second barrier pattern may be disposed on a segment of the first barrier layer adjacent to the gate line. The charge trapping pattern may contact the second barrier pattern between the insulating patterns. The tunnel insulating layer may contact the charge trapping pattern and may be disposed in a first direction perpendicular to the first structure. The channel layer may contact the tunnel insulating layer in the first direction. The core post may be surrounded by the channel layer and may be disposed in the first direction.

[0007] According to an embodiment, a method of manufacturing a memory device includes the following steps: alternately stacking an insulating interlayer with a first sacrificial layer on a first structure; forming a first hole extending through the insulating interlayer and the first sacrificial layer in a first direction; forming an insulating pattern on the insulating interlayer exposed through the first hole; forming a first barrier layer covering the exposed first surface of the first structure, the surface of the insulating pattern, and the surface of the first sacrificial layer; and forming a second barrier pattern on the first barrier layer, the second barrier pattern including spaced-apart portions and disposed on a segment of the first barrier layer adjacent to a gate line. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure;

[0009] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A circuit diagram of a memory block in a memory device;

[0010] Figures 3 to 5 This illustrates an embodiment according to the present disclosure. Figure 1 Cross-sectional views of various examples of memory devices;

[0011] Figures 6A to 6M This is a cross-sectional view of a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure;

[0012] Figures 7A to 7G A cross-sectional view of a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure; and

[0013] Figures 8A to 8G This is a cross-sectional view of a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0014] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification. For clarity, the dimensions and relative sizes of layers and regions in the figures may be exaggerated. Crosshairs running through the figures indicate corresponding or similar areas between figures, and do not indicate material associated with those areas.

[0015] Terms such as “vertical,” “top,” “bottom,” “above,” “overlapping,” “on,” “side,” “up,” “down,” “low,” “column,” “row,” “height,” and other terms that suggest relative spatial relationships or orientations are used for ease of description or reference to the accompanying drawings only and are not intended to be limiting.

[0016] Terms such as “first” and “second” are used to distinguish between various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be referred to as the second element, and in another example, the second element may be referred to as the first element.

[0017] When one element is identified as "connected" to another element, the elements can be directly connected or connected through at least one intermediate element between the elements. When two elements are identified as "directly connected," one element is directly connected to the other element, and there is no intermediate element between the two elements.

[0018] When an improperly sized gate barrier is formed, smog degradation due to fluorine (F) contained in the gate electrode may occur. To form a gate barrier of appropriate volume, sufficient space is provided between the cell plugs on which gate lines are formed. One or more embodiments may include a memory device and a method of manufacturing the memory device, wherein sufficient space for the gate is provided between the cell plugs. One or more embodiments include a memory device having improved memory cell characteristics and a method of manufacturing the memory device.

[0019] According to the implementation, a barrier layer can be formed without partially oxidizing the sacrificial layer of the laminated structure. Therefore, the diameter of the cell plug does not increase. Preventing an increase in the diameter of the cell plug allows sufficient space to form a gate barrier of appropriate volume, thereby improving cell properties. While preventing an increase in the diameter of the cell plug, sufficient space is provided for the charge trapping patterns to be formed between vertically adjacent insulating patterns, thereby improving cell characteristics.

[0020] Figure 1 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0021] Reference Figure 1 The memory device 100 includes a memory cell array 110, peripheral circuitry 170, and control circuitry 180.

[0022] The memory cell array 110 includes first memory blocks BLK1 to j-th memory blocks BLKj, where j is an integer greater than 1. For example, the first memory blocks BLK1 to j-th memory blocks BLKj can be formed in a three-dimensional structure. Each of the first memory blocks BLK1 to j-th memory blocks BLKj may include a plurality of memory cells vertically stacked above a substrate.

[0023] Depending on the programming method, a memory cell can store one bit, two bits, or more of data. For example, one bit of data stored in a single memory cell is called a single-level cell, two bits of data stored in a single memory cell can be called a multi-level cell, three bits of data stored in a single memory cell is called a three-level cell, four bits of data stored in a single memory cell is called a four-level cell, and five bits of data can be stored in a single memory cell.

[0024] Peripheral circuitry 170 is configured to perform programming operations that store data in memory cell array 110, reading operations that output data stored in memory cell array 110, and erasing operations that erase data stored in memory cell array 110. For example, peripheral circuitry 170 includes voltage generator 120, row decoder 130, page buffer set 140, column decoder 150, and input / output circuitry 160.

[0025] Voltage generator 120 generates various operating voltages Vop for programming, reading, and erasing operations in response to the opcode OPCD. For example, voltage generator 120 generates programming voltage, through voltage, turn-on voltage, turn-off voltage, ground voltage, negative voltage, source voltage, verification voltage, read voltage, erase voltage, and precharge voltage in response to or based on the opcode OPCD.

[0026] Programming voltage is the voltage applied to the selected word line among multiple word lines (WL) during a programming operation. The programming voltage increases the threshold voltage of the memory cell connected to the selected word line. Through voltage is the voltage applied to the unselected word line among the word lines (WL) during a programming or read operation. The through voltage is used to turn on the memory cell connected to the unselected word line.

[0027] The on-state voltage is the voltage applied to the drain-select line DSL or the source-select line SSL. The on-state voltage is used to turn on the drain-select transistor or the source-select transistor. The off-state voltage is the voltage applied to the drain-select line DSL or the source-select line SSL. The off-state voltage is used to turn off the drain-select transistor or the source-select transistor.

[0028] Ground voltage is approximately 0V. Negative voltage is any voltage below 0V. Source voltage is the voltage applied to the source line SL. Source voltage can be negative, ground, or positive. Verification voltage is the voltage used to determine the threshold voltage for the selected memory cell during a programming or erasing operation. Verification voltage is applied to the selected word line or to all word lines connected to the selected memory block.

[0029] The read voltage is the voltage applied to the selected word line during a read operation. The read voltage is used to determine the data stored in the memory cell. The erase voltage is the voltage applied to the source line SL during an erase operation. The erase voltage is used to lower the threshold voltage of the memory cell. The precharge voltage is a positive voltage applied to the source line SL during a verification or read operation to precharge the channel of the unselected string.

[0030] The row decoder 130 is connected to the voltage generator 120 via at least one global line. The row decoder is connected to the first memory block BLK1 through the j-th memory block BLKj via the drain select line DSL, word line WL, source select line SSL, and source line SL. The row decoder 130 is configured to send the operating voltage Vop to the drain select line DSL, word line WL, source select line SSL, and source line SL connected to the selected memory block according to the row address RADD.

[0031] Page buffer group 140 includes at least one page buffer (not shown) that is commonly connected to first memory blocks BLK1 through j-th memory blocks BLKj. For example, each page buffer is connected to the first memory blocks BLK1 through j-th memory blocks BLKj via multiple bit lines BL. The page buffer senses current or voltage on the bit lines BL in response to a page buffer control signal PBSIG.

[0032] Column decoder 150 is configured to transfer data between page buffer group 140 and input / output circuitry 160 in response to column address CADD. For example, column decoder 150 is connected to page buffer group 140 via at least one column line CL. Column decoder 150 is connected to input / output circuitry 160 via at least one data line DL.

[0033] Input / output circuitry 160 is configured to receive or output commands (CMD), addresses (ADD), or data via input / output line I / O. For example, input / output circuitry 160 may transmit commands (CMD) and addresses (ADD) received from an external controller to control circuitry 180 via input / output line I / O. Input / output circuitry 160 may also transmit data received from an external controller to column decoder 150 via input / output line I / O. Alternatively, input / output circuitry 160 may output data received from column decoder 150 to an external controller via input / output line I / O.

[0034] Control circuit 180 responds to command CMD and address ADD by outputting opcode OPCD, row address RADD, page buffer control signal PBSIG, and column address CADD. For example, when the command CMD input to control circuit 180 corresponds to a programming operation, control circuit 180 controls peripheral circuit 170 to perform a programming operation on the selected memory block according to address ADD. When the command CMD input to control circuit 180 corresponds to a read operation, control circuit 180 controls peripheral circuit 170 to perform a read operation on the selected memory block according to the address and output the read data. When the command CMD input to control circuit 180 corresponds to an erase operation, control circuit 180 controls peripheral circuit 170 to perform an erase operation on the selected memory block.

[0035] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A circuit diagram of a memory block in a memory device. Because Figure 1 The configurations of storage blocks BLK1 to BLKj shown are similar, so Figure 2 The j-th storage block BLKj among storage blocks BLK1 to BLKj is shown and described as an example.

[0036] Reference Figure 2 The j-th storage block BLKj includes multiple strings ST connected between bit lines BL1 to BLn and the source line SL. Because bit lines BL1 to BLn extend along the Y direction and are spaced apart from each other along the X direction, the strings ST extending in the Z direction are spaced apart in both the X and Y directions.

[0037] Referring to the example of a string ST connected to the nth bit line BLn, the string ST includes a source selection transistor SST, first memory cells MC1 to IMi, and a drain selection transistor DST, where i is an integer greater than 1. Because Figure 2 The j-th memory block BLKj shown is illustrated in the memory block connection configuration, so the number of source selection transistors SST, first memory cells MC1 to i-th memory cells MCI, and drain selection transistors DST in the string ST can vary depending on the memory device.

[0038] The gates of the source select transistors SST in different strings ST are connected to the source select line SSL. The gates of memory cells MC1 to MCi are connected to word lines WL1 to WLi. The gate of the drain select transistor DST is connected to the drain select line DSL.

[0039] Among memory cells MC1 to MCi, memory cells formed in the same layer are connected to the same word line. For example, the first memory cell MC1, which is included in different strings ST, is connected to the first word line WL1, and the second memory cell MC2, which is included in different strings ST, is connected to the second word line WL2. A group of memory cells in different strings ST and connected to the same word line is a page PG. Programming and reading operations can be performed based on the page PG, and erasing operations can be performed based on the memory block.

[0040] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 1 A cross-sectional view of an example memory device.

[0041] Reference Figure 3 The memory device 10A of the embodiment includes a lower structure 1, a plurality of insulating interlayers 2, a plurality of gate lines 3 and cell plugs CP1.

[0042] Multiple insulating interlayers 2 are alternately stacked with multiple gate lines above the lower structure 1.

[0043] Cell plug CP1 is formed to extend vertically through interlayer insulating layer 2 and gate line 3. Cell plug CP1 includes multiple insulating patterns 4, barrier layer B1, multiple charge trapping patterns 7p, tunnel insulating layer 8, channel layer 9, and core pillar P. For example, barrier layer B1 includes a first barrier layer 5 and a second barrier layer 6a located on the first barrier layer 5.

[0044] For example, the insulating interlayer 2 has different thicknesses. Therefore, the insulating pattern 4 formed on the insulating interlayer 2 has different thicknesses.

[0045] For example, the lower structure 1 includes a substrate or source lines. Alternatively, the lower structure 1 includes a peripheral circuit structure or a stacked structure including an insulating interlayer 2 and multiple gate lines 3. The insulating interlayer 2, the insulating pattern 4, and the tunnel insulating layer 8 may include insulating materials such as oxide materials. The gate lines 3 include conductive materials. For example, the gate lines 3 include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polysilicon (poly-Si), and may include various other conductive materials.

[0046] The charge trapping pattern 7p may include, but is not limited to, examples of nitride materials. The channel layer 9 may include a conductive material such as doped silicon. The core pillar P may include an insulating or conductive material.

[0047] As described, the barrier layer B1 of the embodiment includes a first barrier layer 5 and a second barrier layer 6a located on the first barrier layer 5. The first barrier layer 5 is continuously formed along a section of the upper surface of the lower structure 1 and the surface of the insulating pattern 4. The second barrier layer 6a is discontinuously formed in a direction perpendicular to the surface of the lower structure 1 (e.g., the Z direction). The second barrier layer 6a is located on the gate line 3 between the insulating patterns 4 in the X direction. Therefore, the number of second barrier layers 6a is the same as the number of gate lines 3. Each of the second barrier patterns 6a to 6c is disposed on a section of the first barrier layer 5 adjacent to the gate line 3. A portion of the first barrier layer 5 is located between the second barrier patterns 6a to 6c and the gate line 3. The second barrier patterns 6a to 6c cover the portion of the first barrier layer 5 adjacent to the gate line.

[0048] The first barrier layer 5 and the second barrier layer 6a each comprise an insulating material such as an oxide material. The first barrier layer 5 is formed to cover a section of the upper surface of the lower structure 1, the surface of the insulating pattern 4, and the surface of the gate line 3. The second barrier layer 6a has a "C" shape and its open end faces the tunnel insulating layer 8. For example, the second barrier layer 6a covers three of the four surfaces of the charge trapping pattern 7p, excluding the surface that contacts the tunnel insulating layer 8.

[0049] In this embodiment, the thickness of the barrier layer B1 may be less than 200 Å, but is not limited to this example. The thickness of each of the first barrier layer 5 and the second barrier layer 6a may be less than 100 Å, but is not limited to this example.

[0050] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 1 A cross-sectional view of an example memory device. Figure 4 Descriptions of similar structures to memory devices are included in Figure 3 In the description.

[0051] Reference Figure 4 The memory device 10B of the embodiment includes a lower structure 1, multiple insulating interlayers 2, multiple gate lines 3, and cell plugs CP2.

[0052] Multiple insulating interlayers 2 are alternately stacked with multiple gate lines 3 on the lower structure 1.

[0053] Cell plug CP2 extends vertically through interlayer insulating 2 and gate line 3. Cell plug CP2 includes multiple insulating patterns 4, barrier layer B2, charge trapping pattern 7p, tunnel insulating layer 8, channel layer 9 and core P.

[0054] The barrier layer B2 in this embodiment includes a first barrier layer 5 and a second barrier pattern 6b on the first barrier layer 5. The first barrier layer 5 is continuously formed along a section of the upper surface of the lower structure 1 and the surface of the insulating pattern 4. The second barrier pattern 6b is discontinuously formed in a direction perpendicular to the upper surface of the lower structure 1 (e.g., the Z direction). For example, the second barrier pattern 6b is located in the same plane as the gate line 3 in the X direction and between the insulating patterns 4 in the Z direction. Therefore, the number of second barrier patterns 6b is the same as the number of gate lines 3.

[0055] The first barrier layer 5 may include an insulating material such as an oxide material. The second barrier pattern 6b may include an insulating material such as an oxide material. The first barrier layer 5 is formed to cover a section of the upper surface of the lower structure 1, the surface of the insulating pattern 4, and the side surface of the gate line 3. The second barrier pattern 6b is formed between the first barrier layer 5 and the charge trapping pattern 7p located on the gate line 3. The second barrier pattern 6b may have a vertical bar or a rectangular shape. Therefore, Figure 4 One side of the charge trapping pattern 7p of the memory device 10B contacts the tunnel insulating layer 8. The opposite side of the charge trapping pattern 7p contacts the second barrier pattern 6b. The upper surface of the charge trapping pattern 7p may contact the first barrier layer 5.

[0056] Figure 5 This illustrates an embodiment according to the present disclosure. Figure 1 A cross-sectional view of an example memory device. Figure 5Descriptions of similar structures to memory devices are included in Figure 3 In the description.

[0057] Reference Figure 5 The memory device 10C of the embodiment includes a lower structure 1, a plurality of insulating interlayers 2, a plurality of gate lines 3 and cell plugs CP3.

[0058] Multiple insulating interlayers 2 are alternately stacked with multiple gate lines above the lower structure 1.

[0059] Cell plug CP1 extends vertically through the interlayer insulating layer 2 and the gate line 3. Cell plug CP3 includes multiple insulating patterns 4, a barrier layer B3, a charge trapping pattern 7p, a tunnel insulating layer 8, a channel layer 9, and a core post P.

[0060] The barrier layer B3 in this embodiment includes a first barrier layer 5 and a second barrier pattern 6c on the first barrier layer 5. The first barrier layer 5 is continuously formed along a section of the upper surface of the lower structure 1 and the surface of the insulating pattern 4. The second barrier pattern 6c is discontinuously formed in a direction perpendicular to the surface of the lower structure 1 (e.g., the Z direction). For example, each of the second barrier patterns 6c is located in the same plane as the gate line 3 in the X direction and is located between the insulating patterns 4 in the Z direction. Therefore, the number of second barrier patterns 6c is the same as the number of gate lines 3.

[0061] The first barrier layer 5 may include an insulating material such as an oxide material. The second barrier pattern 6c may include an insulating material such as an oxide material. The first barrier layer 5 is formed to cover a section of the upper surface of the lower structure 1, the surface of the insulating pattern 4, and the surface of the gate line 3. The second barrier pattern 6c is formed between the first barrier layer 5 and the charge trapping pattern 7p located at the height or plane of the gate line 3. For example, the second barrier pattern 6c may have a vertical bar or a rectangular shape. Therefore, Figure 5 One side of the charge trapping pattern 7p of the memory device 10C contacts the tunnel insulating layer 8. The opposite side of the charge trapping pattern 7p contacts the second barrier pattern 6c. The upper surface of the charge trapping pattern 7p contacts the first barrier layer 5.

[0062] Figures 6A to 6M This is a cross-sectional view of a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure.

[0063] Reference Figure 6AA stacked structure SS1 is formed above the lower structure 1. Multiple insulating interlayers 2 are alternately stacked with multiple sacrificial layers S in a direction perpendicular to the upper surface of the lower structure 1, thereby forming the stacked structure SS1. The lower structure 1 may include a substrate or source lines, and may include peripheral circuit structures formed on the substrate. The insulating interlayers 2 may include insulating materials such as oxide materials. The sacrificial layers S are removed in subsequent processes. The sacrificial layers S include materials with different etching selectivity than the insulating interlayers 2. For example, the sacrificial layers S may include nitride materials.

[0064] For example, the insulating interlayer 2 can be formed with different thicknesses. Therefore, in subsequent processes, the insulating interlayer 2 is formed... Figure 3 The insulating pattern 4 can also have different thicknesses. The sacrificial layer S can be formed with different thicknesses. Therefore, it can replace the sacrificial layer S in subsequent processes. Figure 3 The gate line 3 can also have different thicknesses.

[0065] Figure 6A The stacked structure SS2 shown is a part of the stacked structure SS1 and is used to simplify the description of subsequent processes. The processes described for SS2 are applicable to the stacked structure SS1.

[0066] Reference Figure 6B , perpendicularly through Figure 6A The stacked structure SS2 forms a vertical via VH. For example, the vertical via VH can be formed by etching portions of the interlayer insulating layer 2 and the sacrificial layer S until the upper surface of the lower structure 1 is exposed. Thus, within the vertical via VH, a portion of the surface of the lower structure 1, the side surface of the interlayer insulating layer 2, and the side surface of the sacrificial layer S are exposed.

[0067] A plurality of first sacrificial layers S1 are formed on the surface of the sacrificial layer S exposed through the vertical hole VH. For example, the first sacrificial layers S1 can be formed from the surface of the sacrificial layer S via a growth method. The first sacrificial layers S1 may comprise an oxide material. For example, the thickness of the first sacrificial layers S1 may be thicker than the thickness of the sacrificial layer S, but is not limited to this example. For example, the thickness of the first sacrificial layers S1 may vary such that each first sacrificial layer S1 does not contact a vertically continuous first sacrificial layer S1.

[0068] Reference Figure 6C A second sacrificial layer S2 is formed to cover the surface of the first sacrificial layer S1, the insulating interlayer 2, and the upper surface of the lower structure 1, which are exposed through the vertical hole VH. Although Figures 6B to 6L The holes in the holes have different shapes and / or sizes, but for simplicity, these holes are simply referred to as "vertical holes". In this example, the second sacrificial layer S2 is formed such that the second sacrificial layer S2 does not fill the vertical hole VH, but rather covers the inner surface adjacent to the vertical hole VH. The second sacrificial layer S2 may include a silicon-containing material.

[0069] Reference Figure 6D The second sacrificial layer S2 is etched to expose the upper surface of the lower structure 1 and the vertically oriented surface of the first sacrificial layer S1, and a second sacrificial pattern S2p is formed between the first sacrificial layers S1. For example, the second sacrificial layer S2 can be etched by a dry etching process and a wet etching process.

[0070] Reference Figure 6E Perform an etching process to remove Figure 6D The first sacrificial layer S1 is shown. The etching process may include a dry etching process or a dry etching process.

[0071] Reference Figure 6F An oxidation process is performed to oxidize the second sacrificial pattern S2p. As described, because the second sacrificial pattern S2p comprises silicon or a silicon-containing material, the oxidation process causes each second sacrificial pattern S2p to become silicon oxide. Therefore, the second sacrificial pattern S2p is processed or transformed into a plurality of insulating patterns 4 corresponding to the insulating interlayer 2.

[0072] Reference Figure 6G A first barrier layer 5 is formed along the upper surface of the lower structure 1 exposed through the vertical aperture VH, the surface of the insulating pattern 4, and the surface of the sacrificial layer S. The first barrier layer 5 may comprise an oxide material. The insulating pattern 4 has a shape protruding from the interlayer insulating 2 toward the center of the vertical aperture VH. The first barrier layer 5 is formed with an irregular shape along the surfaces of the insulating pattern 4 and the sacrificial layer S. The first barrier layer 5 on the insulating pattern 4 has a convex shape facing the center of the vertical aperture VH, and the first barrier layer 5 on the sacrificial layer S has a concave shape facing the center of the vertical aperture VH. For example, the first barrier layer 5 may be formed with a thickness of less than 100 Å, but is not limited to this example.

[0073] Reference Figure 6H The first barrier layer 5 can be partially etched to adjust its thickness to a target thickness. For example, the first barrier layer 5 can be etched using a dry etching process or a wet etching process. For example, the etching process can be performed until the thickness of the first barrier layer 5 on the sacrificial layer S becomes less than 60 Å, but is not limited to this example.

[0074] Reference Figure 6I A second barrier layer 6a is formed on the first barrier layer 5. For example, the second barrier layer 6a covers the outer surface of the first barrier layer 5. Therefore, similar to the first barrier layer 5, the second barrier layer 6a includes convex portions alternating with concave portions. The second barrier layer 6a may comprise an oxide material. For example, the second barrier layer 6a may be formed with a thickness of less than 50 Å, but is not limited to this example.

[0075] Reference Figure 6JA charge trapping layer 7 is formed to cover the second barrier layer 6a exposed through the vertical aperture VH. The charge trapping layer 7 is formed to fill the depressions of the second barrier layer 6a. The charge trapping layer 7 does not fill the interior space of the vertical aperture VH. The surface of the charge trapping layer 7 exposed through the vertical aperture VH may have alternating uneven shapes. The charge trapping layer 7 may include nitrides. For example, the charge trapping layer 7 may be formed with a thickness of about 150 Å to about 200 Å, but is not limited to this example.

[0076] Reference Figure 6K The charge trapping layer 7 is partially etched to expose the second barrier layer 6a and form a plurality of charge trapping patterns 7p. The charge trapping layer 7 can be etched by a dry etching process or a wet etching process. For example, the etching process is performed until the charge trapping layer 7 on the lower structure 1 and the charge trapping layer 7 on the second barrier layer 6a are removed. Thus, the charge trapping patterns 7p are formed in the Z direction between the insulating patterns 4. For example, the charge trapping patterns 7p may have a thickness of about 30 Å to about 80 Å, but are not limited to this example.

[0077] Reference Figure 6L An oxide trimming process is performed to remove portions of the first barrier layer 5 and the second barrier layer 6a. For example, hydrofluoric acid (HF) can be used to perform the oxide trimming process. After removing portions of the first barrier layer 5 and the second barrier layer 6a, the remaining surfaces of the charge trapping pattern 7p (e.g., top, bottom, and side surfaces) except for the surface exposed through the vertical hole VH are covered by the second barrier layer 6a. After removing portions of the second barrier layer 6a, the second barrier pattern 6a remains. In other words, the insulating pattern 4, comprising insulating material, the first barrier layer 5, and the second barrier pattern 6a are located between vertically continuous charge trapping patterns 7p, such that the charge trapping patterns 7p are electrically isolated from each other.

[0078] Reference Figure 6M A tunnel insulating layer 8, a channel layer 9, and a core pillar P are sequentially formed along the inner surface adjacent to the vertical hole VH where the charge trapping pattern 7p is formed. The tunnel insulating layer 8 may comprise an oxide material. The channel layer 9 may comprise a doped silicon material. The core pillar P may be formed of an insulating or conductive material. The tunnel insulating layer 8 may be formed in a cylindrical shape along the surface of the charge trapping pattern 7p and the first barrier layer 5 and the second barrier pattern 6a. The channel layer 9 may be formed in a cylindrical shape along the inner surface of the tunnel insulating layer 8. The core pillar P may be formed in the form of a pillar surrounded by the channel layer 9.

[0079] Additional processes can be performed to form Figure 3 The structure shown.

[0080] For example, such as Figure 6AAs shown, an etching process can be performed to remove the sacrificial layer S from the stacked structure SS2. The etching process may include a dry etching process or a wet etching process. As the sacrificial layer S is removed, a recessed region can be formed between the insulating interlayers 2, and the surfaces of the insulating interlayers 2 and the first barrier layer 5 can be exposed through the recessed region.

[0081] A gate barrier layer (not shown) may be formed on the surfaces of the first barrier layer 5 and the insulating interlayer 2 exposed through the recessed region. The gate barrier layer may include titanium (Ti), titanium nitride (TiN), molybdenum nitride (MoN), or a combination thereof. For example, the gate barrier layer may be formed to cover the surfaces of the insulating interlayer 2 and the first barrier layer 5.

[0082] A conductive material layer, such as a gate electrode, can be formed on the gate barrier layer within the recessed region. For example, the conductive material layer can fill the recessed region. The conductive material layer may include at least one conductive material selected from tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polysilicon (poly-Si), and may include a variety of other conductive materials.

[0083] Figures 7A to 7G This is a cross-sectional view of a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure. Figures 7A to 7G It utilizes the implementation method and reference. Figures 6G to 6I Cross-sectional views of memory devices formed by different methods of forming a barrier layer are described. Figure 7A The process performed and referenced in the cross-sectional view shown Figures 6A to 6F The described processes are similar.

[0084] Reference Figures 7A to 7G The method for forming a barrier layer according to an embodiment is described, and descriptions of similar structures are included. Figures 6G to 6I In the description.

[0085] Reference Figure 7A A first barrier layer 5, comprising oxide material, is formed along the upper surface of the lower structure 1 exposed through the vertical hole VH, the surface of the insulating pattern 4, and the surface of the sacrificial layer S. Although Figures 7B to 7F The holes in the structure have different shapes and / or sizes, but for simplicity, these holes are simply referred to as "vertical holes". The first barrier layer 5 is formed with an irregular shape along the surfaces of the insulating pattern 4 and the sacrificial layer S. The first barrier layer 5 along the surface of the insulating pattern 4 has a convex shape facing the center of the vertical hole VH, and the first barrier layer 5 on the sacrificial layer S has a concave shape facing the center of the vertical hole VH. For example, the first barrier layer 5 may be formed with a thickness of less than 60 Å, but is not limited to this example.

[0086] Reference Figure 7BA third sacrificial layer S3 is formed on the first barrier layer 5. For example, the third sacrificial layer S3 covers the surface of the first barrier layer 5. Therefore, the third sacrificial layer S3 has an alternating uneven shape similar to that of the first barrier layer 5. The third sacrificial layer S3 may include a nitride material. For example, the third sacrificial layer S3 may be formed with a thickness of about 50 Å to about 150 Å, but is not limited to this example.

[0087] Reference Figure 7C An etching process is performed to remove the third sacrificial layer S3. The etching process may include a dry etching process or a wet etching process. For example, the etching process is performed until the third sacrificial layer S3 remains on the first barrier layer 5 adjacent to the sacrificial layer S. Therefore, the third sacrificial layer S3 is located on the bottom surface of the recessed portion of the first barrier layer 5 in the X-axis direction. The portions of the third sacrificial layer S3 are spaced apart in the vertical direction (Z-direction) and may have a vertical stripe shape. For example, the thickness of the third sacrificial layer S3 including the vertical stripe shape in the X-axis direction may be from about 30 Å to about 80 Å, but is not limited to this example.

[0088] An oxidation process is performed to oxidize the third sacrificial layer S3 on the bottom surface of the recessed portion of the first barrier layer 5 in the X-axis direction. For example, the oxidation process can be performed by an annealing process using O2 gas, but is not limited to this example. Upon completion of the oxidation process, the third sacrificial layer S3 is processed into a second barrier pattern 6b. The second barrier pattern 6b may include a nitride material.

[0089] Reference Figure 7D A charge trapping layer 7 is formed to cover the surfaces of the first barrier layer 5 and the second barrier pattern 6b exposed through the vertical aperture VH. In this example, the charge trapping layer 7 is formed to fill the depressions of the first barrier layer 5. The charge trapping layer 7 may comprise a nitride material.

[0090] Reference Figure 7E An etching process is performed to partially remove the charge trapping layer 7. The etching process may include a dry etching process or a wet etching process. For example, the etching process is performed until the charge trapping layer 7 disposed on the first barrier layer 5 on the lower structure 1 and on the inner portion of the first barrier layer 5 are removed. In this example, the etching process is performed until the outer surface of the charge trapping layer 7 that can fill the recesses of the first barrier layer 5 is removed, but this example is not limited to this one.

[0091] Reference Figure 7FAn oxide trimming process is performed to remove a section of the first barrier layer 5. A section of the charge trapping layer 7 and a section of the first barrier layer 5 are removed to form a plurality of vertically spaced charge trapping patterns 7p. For example, one side of each charge trapping pattern 7p is exposed through a vertical aperture VH, the opposite sides of each charge trapping pattern 7p contact the second barrier pattern 6b, and the remaining surfaces, such as the top and bottom surfaces, contact the first barrier layer 5. Because the isolation pattern 4 and the first barrier layer 5 are located between vertically continuous charge trapping patterns 7p, portions of the charge trapping patterns 7p are electrically isolated from each other.

[0092] Reference Figure 7G A tunnel insulation layer 8, a channel layer 9, and a core pillar P are sequentially formed along the inner surface adjacent to the vertical hole VH on which the charge trapping pattern 7p is formed.

[0093] Perform various processes to form Figure 4 The structure shown. For example, performing an etching process to extract from... Figure 6A The sacrificial layer S is removed from the stacked structure SS2. As the sacrificial layer S is removed, a recess is formed between the insulating interlayers 2, and the recess exposes the surface of the insulating interlayer 2 and the surface of the first barrier layer 5.

[0094] The gate line 3 is formed by sequentially forming a gate barrier layer and a conductive material layer on the surface of the insulating interlayer 2 exposed through the recess and on the surface of the first barrier layer 5.

[0095] Figures 8A to 8G This is a cross-sectional view of a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure. Figures 8A to 8G It utilizes the implementation method and reference. Figures 6G to 6I and Figures 7A to 7G Cross-sectional views of memory devices formed by different methods of forming a barrier layer are described. Figure 8A The process performed and referenced in the cross-sectional view shown Figures 6A to 6F The described processes are similar.

[0096] Reference Figures 8A to 8G The method for forming a barrier layer according to an embodiment is described, and descriptions of similar structures are included. Figures 6G to 6I and Figures 7A to 7G In the description.

[0097] Reference Figure 8A A first barrier layer 5, comprising oxide material, is formed along the upper surface of the lower structure 1 exposed through the vertical hole VH, the surface of the insulating pattern 4, and the surface of the sacrificial layer S. Although Figures 8A to 8FThe holes in the structure have different shapes and / or sizes, but for simplicity, these holes are simply referred to as "vertical holes". The first barrier layer 5 is formed with an irregular shape along the surfaces of the insulating pattern 4 and the sacrificial layer S. The first barrier layer 5 on the insulating pattern 4 has a convex shape facing the center of the vertical hole VH, and the first barrier layer 5 on the sacrificial layer S has a concave shape facing the center of the vertical hole VH. For example, the first barrier layer 5 may be formed with a thickness of less than 60 Å, but is not limited to this example.

[0098] Reference Figure 8B A fourth sacrificial layer S4 is formed on the first barrier layer 5. For example, the fourth sacrificial layer S4 covers the surface of the first barrier layer 5. Therefore, the fourth sacrificial layer S4 has an alternating bumpy shape similar to that of the first barrier layer 5. The fourth sacrificial layer S4 may include a silicon-containing material. For example, the fourth sacrificial layer S4 may be formed with a thickness of about 50 Å to about 150 Å, but is not limited to this example.

[0099] Reference Figure 8C An etching process is performed to remove the fourth sacrificial layer S4. The etching process may include a dry etching process or a wet etching process. For example, the etching process is performed such that the fourth sacrificial layer S4 remains on the first barrier layer 5 adjacent to the sacrificial layer S. Therefore, the fourth sacrificial layer S4 is located on the bottom surface of the recessed portion of the first barrier layer 5 in the X-axis direction. The portions of the fourth sacrificial layer S4 are spaced apart in the vertical direction and may have a vertical stripe shape.

[0100] An oxidation process is performed to oxidize the fourth sacrificial layer S4, which is retained on the bottom surface of the recessed portion of the first barrier layer 5, in the X-axis direction. For example, the oxidation process is performed using an annealing method with O2 gas, but is not limited to this example. Upon completion of the oxidation process, the fourth sacrificial layer S4 is processed into a second barrier pattern 6c. The second barrier pattern 6c may comprise a silicon oxide material or a silicon-containing oxide.

[0101] Reference Figure 8D A charge trapping layer 7 is formed to cover the surfaces of the first barrier layer 5 and the second barrier pattern 6c exposed through the vertical aperture VH. In this example, the charge trapping layer 7 is formed to fill the depressions of the first barrier layer 5. The charge trapping layer 7 may comprise a nitride material.

[0102] Reference Figure 8E An etching process is performed to partially remove the charge trapping layer 7. The etching process may include a dry etching process or a wet etching process. For example, the etching process is performed until the charge trapping layer 7 disposed on the first barrier layer 5 on the lower structure 1 and the charge trapping layer 7 on the first barrier layer 5 are removed. In this example, the etching process is performed until the upper surface of the charge trapping layer 7 filling the recess of the first barrier layer 5 is removed, but this example is not limited to this one.

[0103] Reference Figure 8F An oxide trimming process is performed to remove segments of the first barrier layer 5. A segment of the charge trapping layer 7 and a segment of the first barrier layer 5 are removed to form a plurality of vertically spaced charge trapping patterns 7p. For example, one side of each charge trapping pattern 7p is exposed through a vertical aperture VH, the opposite sides of each charge trapping pattern 7p contact the second barrier pattern 6c, and the remaining surfaces of the charge trapping patterns 7p (e.g., top and bottom surfaces) contact the first barrier layer 5. Because the isolation pattern 4 and the first barrier layer 5 can be located between vertically continuous charge trapping patterns 7p, the charge trapping patterns 7p can be electrically isolated from each other.

[0104] Reference Figure 8G A tunnel insulation layer 8, a channel layer 9, and a core pillar P are sequentially formed along the inner surface adjacent to the vertical hole VH on which the charge trapping pattern 7p is formed.

[0105] Perform various processes to form Figure 5 The structure shown. For example, performing an etching process to extract from... Figure 6A The sacrificial layer S is removed from the stacked structure SS2. As the sacrificial layer S is removed, a recess is formed between the insulating interlayers 2, and the recess exposes the surface of the insulating interlayer 2 and the surface of the first barrier layer 5.

[0106] The gate line 3 is formed by sequentially forming a gate barrier layer and a conductive material layer on the surface of the insulating interlayer 2 exposed through the recess and on the surface of the first barrier layer 5.

[0107] Therefore, according to the implementation method Figures 3 to 5 The barrier layers B1, B2, and B3 can be formed without partially oxidizing the sacrificial layer S of the laminated structure SS1, thus preventing... Figures 3 to 5 The diameters of the unit plugs CP1, CP2 and CP3 are increased.

[0108] In this implementation, by preventing the diameter of the cell plug from increasing, sufficient space is available for the formation of charge trapping patterns between vertically adjacent insulating patterns, which improves cell characteristics.

[0109] The concepts are disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions can be made without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered illustrative rather than restrictive. Therefore, the scope of this disclosure is not limited to these descriptions. All changes within the meaning of the claims and their equivalents are included within its scope.

[0110] Cross-references to related applications

[0111] This application claims priority to Korean Application No. 10-2025-0035271, filed with the Korean Intellectual Property Office on March 19, 2025, the entirety of which is incorporated herein by reference.

Claims

1. A memory device comprising: Multiple insulating interlayers are alternately stacked with multiple gate lines in a first structure; as well as A cell plug that extends through the insulating interlayer and the gate line; The unit plug includes: Multiple insulating patterns protrude from the insulating interlayer toward the center of the unit plug; A first barrier layer covers the surface of the gate line and the insulating pattern; A second barrier pattern is disposed on a section of the first barrier layer adjacent to the gate line; A charge trapping pattern that contacts the second blocking pattern between the insulating patterns; A tunnel insulation layer that contacts the charge trapping pattern and is disposed in a first direction perpendicular to the first structure; A trench layer that contacts the tunnel insulation layer in the first direction; and A core post, which is surrounded by the channel layer and positioned in the first direction.

2. The memory device according to claim 1, wherein, The charge trapping pattern includes a first side that contacts the tunnel insulation layer, a second side that is opposite to the first side, and a first surface and a second surface that are adjacent to the insulation pattern.

3. The memory device according to claim 2, wherein, The second blocking pattern contacts the second side of the charge trapping pattern and the first and second surfaces of the charge trapping pattern.

4. The memory device according to claim 3, wherein, The second blocking pattern comprises an oxide material.

5. The memory device according to claim 2, wherein, The second blocking pattern contacts the second side of the charge-capturing pattern.

6. The memory device according to claim 5, wherein, The second blocking pattern includes at least one silicon oxide material and a silicon oxynitride material.

7. A method for manufacturing a memory device, the method comprising the following steps: An insulating interlayer is alternately laminated with a sacrificial layer in the first structure; A first hole is formed extending through the insulating interlayer and the sacrificial layer in a first direction; An insulating pattern is formed on the insulating interlayer exposed through the first hole; A first barrier layer is formed covering the exposed first surface of the first structure, the surface of the insulating pattern, and the surface of the sacrificial layer; as well as A second barrier pattern is formed on the first barrier layer, the second barrier pattern including spaced portions disposed on a segment of the first barrier layer adjacent to the gate line.

8. The method according to claim 7, wherein, The steps for forming the second blocking pattern include the following: An oxide layer is formed covering the surface of the first barrier layer; and An etching process is used to remove a portion of the oxide layer and a portion of the first barrier layer to form a second barrier pattern that contacts the inner wall of a recess in the first barrier layer, wherein each of the recesses is formed at a height corresponding to one of the plurality of gate lines.

9. The method according to claim 8, wherein, The steps for forming the first barrier layer include the following: An oxide layer is formed covering the first surface of the first structure, the surface of the insulating pattern, and the exposed surface of the sacrificial layer, the oxide layer having a first thickness; and The oxide layer is removed by an etching process to form a first barrier layer having a second thickness less than the first thickness.

10. The method of claim 8, further comprising the step of: A charge trapping layer is formed on the exposed surface of the oxide layer to fill the depressions in the oxide layer; as well as A portion of the charge trapping layer is removed by an etching process to form a charge trapping pattern within the depression of the oxide layer.

11. The method of claim 10, further comprising the step of: A tunnel insulation layer is formed in a direction perpendicular to the first structure and along the surface of the insulation pattern, the surface of the first barrier layer and the second barrier pattern, and the exposed surface of the charge trapping pattern; A trench layer is formed along the surface of the tunnel insulation layer; as well as A core pillar is formed, surrounded by the channel layer.

12. The method of claim 11, further comprising the step of: Remove the sacrificial layer to form a depression; and A gate barrier layer and a gate line are sequentially formed in the recess using at least one layer of conductive material.

13. The method according to claim 8, wherein, The steps for forming the second blocking pattern include the following: A barrier material layer is formed covering the surface of the first barrier layer; A portion of the barrier material layer is removed using an etching process to form a barrier material pattern on the bottom surface of the first barrier layer adjacent to one of the recesses; and The blocking material pattern on the bottom surface of the first blocking layer is oxidized using an oxidation process to form the second blocking pattern.

14. The method according to claim 13, wherein, The barrier material layer includes at least one of nitride material, silicon material, and silicon-containing insulating material.

15. The method of claim 13, further comprising the step of: A charge trapping layer is formed on the exposed surface of the oxide layer to fill the depressions in the oxide layer; as well as A portion of the charge trapping layer is removed by an etching process to form the charge trapping pattern that fills the depression in the oxide layer.

16. The method according to claim 15, wherein, The method also includes the following steps: A tunnel insulation layer is formed along the surface of the insulation pattern, the surface of the first barrier layer, and the exposed surface of the charge trapping pattern in a direction perpendicular to the first structure; A trench layer is formed along the surface of the tunnel insulation layer; and A core pillar is formed, surrounded by the channel layer.

17. The method of claim 16, further comprising the step of: Remove the sacrificial layer to form a depression; and A gate barrier layer and a conductive material layer are sequentially formed in the recess to form a gate line.

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