A semiconductor structure, a method for manufacturing a semiconductor structure, and a semiconductor device

Abstract

This disclosure provides a semiconductor structure, a method for fabricating the semiconductor structure, and a semiconductor device, applicable to the field of semiconductor technology. The semiconductor structure includes a channel layer, a charge trapping layer, and a barrier layer stacked together. The charge trapping layer includes a charge storage layer and a first ferroelectric material layer stacked together. The barrier layer includes a charge blocking layer and a second ferroelectric material layer stacked together. At least one charge blocking layer is disposed between the first ferroelectric material layer and the second ferroelectric material layer. The operating voltage of the semiconductor structure is reduced by introducing the ferroelectric material layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for fabricating a semiconductor structure, and a semiconductor device. Background Technology

[0002] Semiconductor devices, such as NAND semiconductor devices, are facing increasing capacity demands and layer counts, but excessively high operating voltages are creating a bottleneck for their further development. Summary of the Invention

[0003] The embodiments of this disclosure provide a semiconductor structure, a method for fabricating the semiconductor structure, and a semiconductor device.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor structure including a channel layer, a charge trapping layer, and a barrier layer stacked together. The charge trapping layer includes a charge storage layer and a first ferroelectric material layer stacked together. The barrier layer includes a charge blocking layer and a second ferroelectric material layer stacked together. At least one charge blocking layer is disposed between the first ferroelectric material layer and the second ferroelectric material layer.

[0005] In some possible implementations, the peripheral circuitry is specifically configured to: after programming a target memory cell among multiple memory cells to a first programming state among multiple programming states, perform an erase operation on the target memory cell when the threshold voltage of the target memory cell is greater than a first verification voltage of the first programming state. The first verification voltage falls within the threshold voltage distribution range corresponding to the first programming state.

[0006] In some possible implementations, the charge trapping layer includes a charge storage layer and a first ferroelectric material layer. The first ferroelectric material layer is located on the side of the charge storage layer away from the channel layer.

[0007] In some possible implementations, the barrier layer comprises a charge barrier layer and a second ferroelectric material layer. The second ferroelectric material layer is located on the side of the charge barrier layer away from the channel layer.

[0008] In some possible implementations, the charge trapping layer comprises multiple charge storage layers and multiple first ferroelectric material layers. The charge storage layers and the first ferroelectric material layers are alternately arranged.

[0009] In some possible implementations, at least two of the first ferroelectric material layers are made of different ferroelectric materials.

[0010] In some possible implementations, the barrier layer comprises multiple charge-blocking layers and multiple layers of second ferroelectric material. The charge-blocking layers and second ferroelectric material layers are alternately arranged.

[0011] In some possible implementations, at least two of the layers in the multilayer second ferroelectric material layer are made of different ferroelectric materials.

[0012] In some possible implementations, the first ferroelectric material layer includes multiple ferroelectric material sublayers stacked together, wherein adjacent ferroelectric material sublayers are different.

[0013] In some possible implementations, the second ferroelectric material layer comprises multiple ferroelectric material sublayers stacked together, wherein adjacent ferroelectric material sublayers are different.

[0014] In some possible implementations, both the first ferroelectric material layer and the second ferroelectric material layer include at least one of the following: hafnium zirconium oxide, hafnium silicon oxide, lead zirconate titanate, strontium barium titanate, strontium bismuth tantalate, lanthanum lead zirconate titanate, hafnium aluminum oxide, hafnium yttrium oxide, LiNbO3, BaMgF, BaMnF, BaFeF, BaCoF, BaNiF, BaZnF, or SrAlF5.

[0015] In some possible implementations, the charge storage layer is made of silicon nitride. The charge blocking layer is made of silicon oxide.

[0016] In some possible implementations, the memory cell also includes a tunneling layer located between the channel layer and the charge trapping layer.

[0017] Secondly, embodiments of this disclosure provide a semiconductor structure, including a stacked structure and a channel structure penetrating the stacked structure. The channel structure includes a channel layer, a charge trapping layer, and a barrier layer stacked along a predetermined direction. The predetermined direction is the radial direction of the channel structure. The charge trapping layer includes a charge storage layer and a first ferroelectric material layer stacked along the predetermined direction. The barrier layer includes a charge blocking layer and a second ferroelectric material layer stacked along the predetermined direction. At least one charge blocking layer is disposed between the first ferroelectric material layer and the second ferroelectric material layer.

[0018] In some possible implementations, the charge trapping layer includes a charge storage layer and a first ferroelectric material layer. The first ferroelectric material layer is located on the side of the charge storage layer away from the channel layer.

[0019] In some possible implementations, the barrier layer comprises a charge barrier layer and a second ferroelectric material layer. The second ferroelectric material layer is located on the side of the charge barrier layer away from the channel layer.

[0020] In some possible implementations, the charge trapping layer comprises multiple charge storage layers and multiple first ferroelectric material layers. The charge storage layers and the first ferroelectric material layers are alternately arranged.

[0021] In some possible implementations, at least two of the first ferroelectric material layers are made of different ferroelectric materials.

[0022] In some possible implementations, the barrier layer comprises multiple charge-blocking layers and multiple layers of second ferroelectric material. The charge-blocking layers and second ferroelectric material layers are alternately arranged.

[0023] In some possible implementations, at least two of the layers in the multilayer second ferroelectric material layer are made of different ferroelectric materials.

[0024] In some possible implementations, the first ferroelectric material layer includes multiple ferroelectric material sublayers stacked along a predetermined direction, wherein adjacent ferroelectric material sublayers are different.

[0025] In some possible implementations, the second ferroelectric material layer includes multiple ferroelectric material sublayers stacked along a predetermined direction, wherein adjacent ferroelectric material sublayers are different.

[0026] In some possible implementations, the stacked structure includes alternating layers of dielectric and gate layers.

[0027] Thirdly, embodiments of this disclosure provide a semiconductor structure, including: a stacked structure and a channel structure penetrating the stacked structure. The channel structure includes a channel layer, a first material layer, and a second material layer stacked along a predetermined direction. The predetermined direction is the radial direction of the channel structure. The first material layer includes a first sub-material layer and a first ferroelectric material layer stacked along the predetermined direction. The second material layer includes a second sub-material layer and a second ferroelectric material layer stacked along the predetermined direction. At least one second sub-material layer is disposed between the first ferroelectric material layer and the second ferroelectric material layer. The defect concentration of the first sub-material layer is greater than the defect concentration of the second sub-material layer.

[0028] In some possible implementations, the first material layer includes a first sub-material layer and a first ferroelectric material layer. The first ferroelectric material layer is located on the side of the first material layer away from the channel layer.

[0029] In some possible implementations, the second material layer includes a second sub-material layer and a second ferroelectric material layer. The second ferroelectric material layer is located on the side of the second material layer away from the channel layer.

[0030] In some possible implementations, the first material layer includes multiple first sub-material layers and multiple first ferroelectric material layers. The first sub-material layers and the first ferroelectric material layers are alternately arranged.

[0031] In some possible implementations, the second material layer comprises multiple second sub-material layers and multiple second ferroelectric material layers. The second ferroelectric material layers and the second ferroelectric material layers are alternately arranged.

[0032] In some possible implementations, the material of the first sub-material layer comprises silicon nitride. The material of the second sub-material layer comprises silicon oxide.

[0033] Fourthly, embodiments of this disclosure provide a method for fabricating a semiconductor structure, comprising: forming a channel layer, a charge trapping layer, and a barrier layer stacked together. The charge trapping layer includes a charge storage layer and a first ferroelectric material layer stacked together. The barrier layer includes a charge blocking layer and a second ferroelectric material layer stacked together. At least one charge blocking layer is disposed between the first ferroelectric material layer and the second ferroelectric material layer.

[0034] In some possible implementations, forming a channel layer, a charge trapping layer, and a barrier layer stacked together includes: forming a stacked structure; forming a channel structure penetrating the stacked structure, the channel structure including the channel layer, the charge trapping layer, and the barrier layer stacked along a predetermined direction. The predetermined direction is the radial direction of the channel structure. The charge trapping layer includes a charge storage layer and a first ferroelectric material layer stacked along the predetermined direction. The barrier layer includes a charge blocking layer and a second ferroelectric material layer stacked along the predetermined direction.

[0035] In some possible implementations, a charge storage layer and a first ferroelectric material layer are formed between the barrier layer and the channel layer. The first ferroelectric material layer is located on the side of the charge storage layer away from the channel layer.

[0036] In some possible implementations, a charge blocking layer and a second ferroelectric material layer are formed on the charge trapping layer. The second ferroelectric material layer is located on the side of the charge blocking layer away from the channel layer.

[0037] In some possible implementations, multiple charge storage layers and multiple first ferroelectric material layers are formed between the barrier layer and the channel layer. The charge storage layers and the first ferroelectric material layers are alternately arranged.

[0038] In some possible implementations, at least two of the first ferroelectric material layers are made of different ferroelectric materials.

[0039] In some possible implementations, multiple charge-blocking layers and multiple second ferroelectric material layers are formed on the charge-trapping layer. The charge-blocking layers and second ferroelectric material layers are alternately arranged.

[0040] In some possible implementations, at least two of the layers in the multilayer second ferroelectric material layer are made of different ferroelectric materials.

[0041] In some possible implementations, the first ferroelectric material layer or the second ferroelectric material layer includes: forming multiple ferroelectric material sublayers stacked along a preset direction, wherein adjacent ferroelectric material sublayers in the multiple ferroelectric material sublayers are different.

[0042] Fifthly, embodiments of this disclosure provide a semiconductor device, including: a semiconductor structure and peripheral circuitry as described in any of the first aspects. The peripheral circuitry is coupled to the semiconductor structure.

[0043] In a sixth aspect, embodiments of this disclosure provide a storage system including: a controller and a semiconductor device as described in any of the fifth aspects, wherein the controller is coupled to the semiconductor device.

[0044] In a seventh aspect, embodiments of this disclosure provide an electronic device, including: a host and a storage system as described in any of the sixth aspects. The host and the storage system are coupled.

[0045] Eighthly, embodiments of this disclosure provide a computer storage medium, the computer-readable storage medium including instructions. When the instructions are executed on a processor, they cause the processor to perform a method for manufacturing any semiconductor structure according to the fourth aspect. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0047] Figure 1 A schematic diagram of the structure of a semiconductor device according to some embodiments of the present disclosure is shown. Figure 1 ;

[0048] Figure 2 A schematic diagram of the structure of a semiconductor device according to some embodiments of the present disclosure is shown. Figure 2 ;

[0049] Figure 3 A schematic diagram of a channel structure according to some embodiments of the present disclosure is shown;

[0050] Figure 4 A schematic diagram of the structure of a storage cell according to some embodiments of the present disclosure is shown;

[0051] Figure 5 A schematic diagram of the structure of a semiconductor device according to some embodiments of the present disclosure is shown. Figure 3 ;

[0052] Figure 6 A schematic diagram showing the relationship between the polarization intensity of a ferroelectric material and an applied electric field according to some embodiments of the present disclosure is shown;

[0053] Figure 7 A schematic cross-sectional view of a memory cell structure formed using a ferroelectric material according to some embodiments of the present disclosure is shown. Figure 1 ;

[0054] Figure 8A A schematic diagram of a programming operation according to some embodiments of the present disclosure is shown;

[0055] Figure 8B A schematic diagram of a data reading operation according to some embodiments of the present disclosure is shown;

[0056] Figure 8C A schematic diagram of voltage pulses applied during programming and erasing operations and charge distribution in a ferroelectric material is shown, according to some embodiments of the present disclosure.

[0057] Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B Schematic cross-sectional views of a memory cell structure formed using a ferroelectric material according to some embodiments of the present disclosure are shown respectively. Figure 2 ;

[0058] Figure 12A , Figure 12B , Figure 13A and Figure 13B Schematic cross-sectional views of a memory cell structure formed using a ferroelectric material according to some embodiments of the present disclosure are shown respectively. Figure 3 ;

[0059] Figure 14 A flowchart is shown illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure;

[0060] Figure 15 for Figure 14 A structural diagram of a semiconductor structure corresponding to step S1 in the flowchart of the semiconductor structure fabrication method;

[0061] Figure 16 for Figure 14 A structural diagram of a semiconductor structure corresponding to step S21 in the flowchart of the semiconductor structure fabrication method;

[0062] Figure 17 for Figure 14 The flowchart of the semiconductor structure fabrication method is shown in the schematic diagram of a semiconductor structure corresponding to steps S22 and S25.

[0063] Figure 18 for Figure 14 A schematic diagram of a semiconductor structure corresponding to step S3 in the flowchart of the semiconductor structure fabrication method;

[0064] Figure 19 A schematic diagram of the structure of an electronic device according to some embodiments of the present disclosure is shown;

[0065] Figure 20 A schematic diagram of the structure of a memory card according to some embodiments of the present disclosure is shown;

[0066] Figure 21 A schematic diagram of the structure of a solid-state drive according to some embodiments of the present disclosure is shown. Detailed Implementation

[0067] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0068] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0069] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0070] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0071] In describing some embodiments, the terms "coupled," "connected," and "linked," and their derivatives, may be used. For example, the term "linked" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0072] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0073] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0074] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0075] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0076] This disclosure is not limited to three-dimensional (3D) NAND semiconductor devices, although 3D NAND semiconductor devices may be used in some examples for illustration. For example, the techniques disclosed herein can be applied to planar two-dimensional (2D) NAND semiconductor devices and NOR semiconductor devices, etc.

[0077] Figure 1 A schematic diagram of the structure of a semiconductor device according to some embodiments of the present disclosure is shown. The semiconductor device 100 may include a semiconductor structure 1000 and peripheral circuitry 2000 coupled to the semiconductor structure 1000.

[0078] The semiconductor structure 1000 may be a NAND memory cell array, wherein the memory cells 1001 are provided in the form of an array of NAND memory strings 1002 that are all vertically extended above a substrate (not shown).

[0079] In some implementations, each NAND memory string 1002 includes a plurality of memory cells 1001 that are series-coupled and vertically stacked. Each memory cell 1001 is capable of holding a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the region of the memory cell 1001. Each memory cell 1001 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0080] In some embodiments, each storage cell 1001 is a single-level cell (SLC) having two possible storage states (levels) and thus being capable of storing one bit of data. Specifically, each storage cell 1001 may be configured to store two... N One of the storage states (levels) stores N bits of data, where N is a natural number greater than 0. This 2 N The storage states include erase state and 2. N -1 programming state.

[0081] In some embodiments, each storage cell 1001 may be a single-level cell (SLC) having two possible storage states and thus being able to store one bit of data. For example, an SLC may have a first storage state "1" and a second storage state "0", where the threshold voltage (V) of the first storage state "1" is... th The voltage distribution of the second storage state "0" can correspond to the first voltage range, and the voltage distribution of the second storage state "0" can correspond to the second voltage range. The first storage state is the erase state, and the second storage state is the programming state.

[0082] In some implementations, each storage cell 1001 is a multi-level cell (xLC) capable of storing more than one bit of data in four or more storage states (levels). For example, an xLC can store two bits per cell (multi-level cell, MLC), three bits per cell (triple-level cell, TLC), or four bits per cell (quad-level cell, QLC). Each xLC can be programmed to take a voltage range of possible threshold voltage distributions.

[0083] In one example, if each MLC stores two bits of data, the MLC can have a first storage state "11", a second storage state "10", a third storage state "01", and a fourth storage state "00". Here, the threshold voltage distributions for the first, second, third, and fourth storage states correspond to the first, second, third, and fourth voltage ranges, respectively. The first storage state is the erase state, and the second, third, and fourth storage states are all programming states. Similarly, a TLC can have 8 storage states, including an erase state and 7 programming states; a QLC can have 16 storage states, including an erase state and 15 programming states.

[0084] For semiconductor devices, the storage window is the difference between the highest and lowest threshold voltages corresponding to a storage cell. For example, for a charge-trapping storage cell, the highest threshold voltage can be the threshold voltage at which the storage cell stores the most charge, and the lowest threshold voltage can be the threshold voltage at which the storage cell stores the least charge.

[0085] The width of the storage window determines the number of storage states that a storage cell can reliably distinguish, which is especially crucial in multi-level storage (MLC / TLC / QLC). The larger the storage window, the more storage states can be distinguished.

[0086] like Figure 1As shown, each NAND flash memory string 1002 may further include a source select gate (SSG) transistor 1003 at its source end and a drain select gate (DSG) transistor 1004 at its drain end. The SSG transistor 1003 and DSG transistor 1004 can be configured to activate the selected NAND flash memory string 1002 (column of the array) during read and program operations. In some embodiments, the sources of the NAND flash memory strings 1002 in the same block 1009 are coupled via a common source line (CSL) 1005. In other words, according to some embodiments, all NAND flash memory strings 1002 in the same block 1009 have an array common source (ACS). According to some embodiments, the drain of each NAND flash memory string 1002 is coupled to a corresponding bit line (BL) 1006, enabling data to be read from or written to the corresponding bit line 1006 via an output bus (not shown).

[0087] In some implementations, each NAND memory string 1002 is configured to be selected or deselected by applying a selection voltage or deselection voltage to the gate of the corresponding DSG transistor 1004 via one or more DSG lines 1007 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the DSG transistor 1004) or a deselection voltage (e.g., 0V) to the gate of the corresponding SSG transistor 1003 via one or more SSG lines 1008 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the SSG transistor 1003) or a deselection voltage (e.g., 0V) to the corresponding SSG transistor 1003 via one or more SSG lines 1008.

[0088] like Figure 1As shown, NAND flash memory strings 1002 can be organized into multiple memory blocks 1009, each of which may have a common source line 1005 coupled to, for example, an ACS. In some implementations, each memory block 1009 is the basic data unit for an erase operation, i.e., all memory cells 1001 on the same memory block 1009 are erased simultaneously. To erase memory cells 1001 in a selected memory block 1009, the source lines 1005 coupled to the selected memory block 1009 and unselected memory blocks 1009 in the same plane as the selected memory block 1009 can be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or higher). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The storage cells 1001 of adjacent NAND storage strings 1002 can be coupled through word lines (WL) 1010. The word line 1010 selects which row of storage cells 1001 to use, which is affected by read and program operations.

[0089] like Figure 1 As shown, the semiconductor structure 1000 may include an array of memory cells in multiple rows and columns in each memory block 1009.

[0090] According to some implementations, a column of storage cells corresponds to a NAND storage string 1002. Multiple rows of storage cells 1001 can be coupled to word lines 1010, and multiple columns of storage cells 1001 can be coupled to bit lines 1006.

[0091] Semiconductor device 100 can be a three-dimensional semiconductor device, such as a 3D NAND semiconductor device, like Figure 2 As shown, a schematic diagram of the structure of a semiconductor device according to some embodiments of the present disclosure is illustrated.

[0092] like Figure 2 As shown, the semiconductor device 100 includes a semiconductor structure 1000, a peripheral circuit 2000, and a semiconductor material layer 3000. The semiconductor material layer 3000 is disposed on the side of the semiconductor structure 1000 away from the peripheral circuit 2000 and can serve as a common source electrode CSL.

[0093] In some embodiments, the semiconductor material layer 3000 may be a material such as silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), germanium (Ge), or silicon germanium (SiGe).

[0094] Please continue reading. Figure 2 The semiconductor structure 1000 includes a stacked structure 1100 and a channel structure 1200. The channel structure 1200 extends through the stacked structure 1100.

[0095] The stacked structure 1100 includes multiple gate layers 1110 and dielectric layers 1120. The gate layers 1110 and dielectric layers 1120 are stacked alternately along a first direction Z. For ease of explanation of the embodiments of this disclosure, a first direction Z is introduced, which is the thickness direction of the semiconductor structure 1000.

[0096] For example, for the stacked structure 1100, different numbers of stacking layers correspond to different stacking heights. For example, the stacked structure 1100 can have 8, 32, 64, or 128 layers. The more layers the stacked structure 1100 has, the higher the integration and the more storage units it forms. The number of stacking layers and the stacking height of the stacked structure 1100 can be designed according to actual storage requirements. This disclosure does not make any specific limitations in this regard.

[0097] It should be noted that, Figure 2 The illustration only uses a semiconductor structure 1000 with two channel structures 1200 as an example. In actual fabrication, multiple channel structures 1200 penetrating the stacked structure 1100 can be formed. The number and arrangement of the channel structures 1200 can be fabricated according to actual storage requirements. The region corresponding to the channel structure 1200 can be referred to as the storage region of the semiconductor structure 1000, and the storage region can be used to realize the storage function of the semiconductor structure 1000.

[0098] like Figure 3 As shown, a schematic diagram of a channel structure according to some embodiments of the present disclosure is illustrated. Figure 3 for Figure 2 Enlarged view of region AA outlined by the dashed line. The channel structure 1200 includes a channel layer 1210, a tunneling layer 1220, a charge trapping layer 1230, and a barrier layer 1240 stacked radially along the channel structure 1200.

[0099] For example, the channel layer 1210 may include polycrystalline silicon. Alternatively, the channel layer 1210 may also include amorphous silicon.

[0100] The barrier layer 1240 is located between the gate layer 1110 and the charge trapping layer 1230, which can reduce the tunneling of charge between the charge trapping layer 1230 and the gate layer 1110, that is, reduce the leakage of charge from the charge trapping layer 1230 to the gate layer 1110, thereby reducing the programming / erasing voltage and giving the semiconductor structure 1000 better fatigue resistance.

[0101] For example, the barrier layer 1240 may include one or more film layers, which may include one or more materials. For instance, the barrier layer 1240 may include a silicon oxide layer.

[0102] For example, the tunneling layer 1220 may include one or more film layers, which may include one or more materials. For example, the tunneling layer 1220 may be a silicon oxide layer.

[0103] For example, the charge trapping layer 1230 is used to store charge, and typically employs an insulating material film layer with a certain trap density to trap and store charge. For instance, the charge trapping layer 1230 may include a silicon nitride (such as Si3N4) layer.

[0104] It is understood that when the barrier layer 1240 includes a silicon oxide (such as SiO2) layer, the charge trapping layer 1230 includes a silicon nitride layer, and the tunneling layer 1220 includes a silicon oxide layer, an oxide-nitride-oxide (ONO) structure is formed by the barrier layer 1240, the charge trapping layer 1230, and the tunneling layer 1220.

[0105] Figure 4 A schematic diagram of the structure of a storage cell according to some embodiments of the present disclosure is shown. For example... Figure 4 As shown, the memory cell includes a channel layer 1210, a tunneling layer 1220, a charge trapping layer 1230, a barrier layer 1240 and a gate layer 1110 stacked along the thickness direction of the channel layer 1210, and also includes a source electrode S and a drain electrode D.

[0106] Return to reference Figure 1 The peripheral circuitry 2000 can be coupled to the semiconductor structure 1000 via bit line 1006, word line 1010, source line 1005, SSG line 1008, and DSG line 1007. The peripheral circuitry 2000 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the semiconductor structure 1000 by applying and sensing voltage and / or current signals to and from each target memory cell 1001 via bit line 1006, word line 1010, source line 1005, SSG line 1008, and DSG line 1007. The peripheral circuitry 2000 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0107] For example, Figure 5 A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown, including peripheral circuitry 2000. Peripheral circuitry 2000 includes a page buffer / sensor amplifier 2001, a column decoder / bit line driver 2002, a row decoder / word line driver 2003, a voltage generator 2004, a control logic unit 2005, a register 2006, an interface (I / F) circuit 2007, and a data bus 2008. It should be understood that it may also include... Figure 5Additional peripheral circuitry not shown.

[0108] Page buffer / sensor amplifier 2001 can be configured to read and program (write) data from and to semiconductor structure 1000 according to control signals from control logic unit 2005. In one example, page buffer / sensor amplifier 2001 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 1001 coupled to selected word line 2001010. In yet another example, page buffer / sensor amplifier 2001 can also sense a low-power signal representing a data bit stored in memory cell 1001 from bit line 1006 during a read operation and amplify a small voltage swing to a recognizable logic level. As detailed below and consistent with the scope of this disclosure, during a programming operation, page buffer / sensor amplifier 2001 may include a memory module (e.g., latch, cache, register, etc.) for temporarily storing a segment of N-bit data received from data bus 2008 and using 2 N -2 N In each programming pass of the multi-pass programming operation, the N-bit data segment is provided to the corresponding target storage unit 1001 via the corresponding bit line 1006.

[0109] The column decoder / bit line driver 2002 can be configured to be controlled by the control logic unit 2005 and to select one or more NAND memory strings 1002 by applying a bit line voltage generated by the voltage generator 2004.

[0110] The row decoder / word line driver 2003 can be configured to be controlled by the control logic unit 2005 and to select / deselect memory block 1009 of semiconductor structure 1000 and word line 2001010 of memory block 1009. The row decoder / word line driver 2003 can also be configured to drive word line 2001010 using word line voltages generated by voltage generator 2004. In some embodiments, the row decoder / word line driver 2003 can also select / deselect and drive SSG line 1008 and DSG line 1007. The voltage generator 2004 can be configured to be controlled by the control logic unit 2005 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and verification voltage), bit line voltages, and source line voltages to be provided to semiconductor structure 1000.

[0111] Control logic unit 2005 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 2006 can be coupled to control logic unit 2005 and includes a status register, a command register, and an address register for storing status information, command operation code (OP), and command address for controlling the operation of each peripheral circuit. Interface circuit 2007 can be coupled to control logic unit 2005 and acts as a control buffer to buffer control commands received from the host (not shown) and forward them to control logic unit 2005, and to buffer status information received from control logic unit 2005 and forward it to the host. Interface circuit 2007 can also be coupled to column decoder / bit line driver 2002 via data bus 2008 and acts as a data input / output (I / O) interface and data buffer to buffer and forward data to and from semiconductor structure 1000.

[0112] In semiconductor devices, such as NAND flash memory devices, memory cells can be programmed for data storage based on charge trapping technology. The stored information in a memory cell depends on the amount of charge trapped in the storage layer. Although NAND flash memory devices can be high-density and cost-effective, they suffer from low write speeds and high power consumption at the system level.

[0113] For NAND semiconductor devices with memory cell structures using silicon-based materials (such as SiO2 barrier layers and Si3N4 charge trapping layers), on the one hand, a strong electric field is required to inject / erase charges through the tunneling oxide layer, and the higher operating voltage leads to high power consumption and easy damage and degradation of the oxide layer; on the other hand, charge injection / extraction depends on the tunneling mechanism, which limits the electron migration speed; furthermore, the trap density of the charge trapping layer (Si3N4) is limited, resulting in insufficient stored charge and a narrow storage window.

[0114] In view of this, in order to solve one or more of the above problems, embodiments of this application provide a semiconductor structure that can form a ferroelectric NAND semiconductor device by introducing ferroelectric materials into the NAND semiconductor device.

[0115] Ferroelectricity is a property observed in non-centrosymmetric dielectric crystals exhibiting spontaneous polarization, where the polarization direction can be altered by an externally applied electric field. In ferroelectric materials, due to the distribution of charge, some atoms in the unit cell are displaced to generate permanent electric dipoles. The macroscopic manifestation of charge separation is the surface charge of the ferroelectric material, described by the polarization P.

[0116] Typical ferroelectric materials, such as lead zirconate titanate (PZT), strontium bismuth tantalate (SrBi₂Ta₂O₉ or SBT), barium titanate (BaTiO₃), and PbTiO₃, have a perovskite-type crystal structure in which the cation at the center of the unit cell has two positions, both of which are stable low-energy states. These two low-energy states correspond to two opposite directions of the electric dipole. Under an external electric field, the cation can move in the direction of the field. Therefore, by applying an external electric field to the crystal, the cation in the unit cell can move from one low-energy position to another, and if the applied electric field is high enough, the direction of the electric dipole can be reversed. As a result, the electric polarization P in the ferroelectric material can be aligned with the direction of the external electric field.

[0117] The following will combine Figure 6 and Figure 7 The properties of ferroelectric materials are explained. Figure 6 A schematic diagram showing the relationship between the polarization intensity of a ferroelectric material and an applied electric field according to some embodiments of the present disclosure is shown; Figure 7 A schematic cross-sectional view of a memory cell structure formed using a ferroelectric material according to some embodiments of the present disclosure is shown.

[0118] Figure 6 An exemplary polarization P of a ferroelectric material as a function of an applied electric field E is shown, wherein the remanent polarization Pr (or reverse remanent polarization -Pr) of the ferroelectric material can be measured at zero external electric field. Figure 6 As shown, the polarization P changes with the applied electric field following a hysteresis loop. When a positive electric field is applied to a ferroelectric material, the ferroelectric material is positively polarized until its polarization P changes linearly with the applied electric field E.

[0119] When the external electric field is removed, the polarization (also referred to as polarization in this disclosure) in the ferroelectric material does not disappear. When the external electric field is removed after the ferroelectric material has been fully polarized, the residual polarization in the ferroelectric material is the residual polarization Pr.

[0120] Applying a reverse electric field does not depolarize the ferroelectric material until it reaches a reverse coercive field -Ec. Here, the negative sign indicates the reversal of the electric field, and the magnitude is denoted by Ec, where the polarization P reaches zero to the left of the lap. By continuously increasing the magnitude of the negative electric field, the ferroelectric material can become fully polarized in the negative direction. When the negative electric field is removed, the ferroelectric material has a reverse remanent polarization -Pr in the negative direction.

[0121] From that point onward, when a positive electric field is applied and a coercive field Ec is transmitted in the positive direction, the polarization in the ferroelectric material can be flipped back to the positive direction until it is fully polarized to linearly follow the electric field. The hysteresis loop can be repeated multiple times to change the polarization direction of the ferroelectric material, typically more than 10. 16 One cycle, depending on the material.

[0122] Ferropolarization is non-volatile because once polarization is generated, an external electric field cannot change the polarization direction until the magnitude of the electric field reaches a threshold (i.e., the coercive field Ec or the reverse coercive field -Ec). Ferroelectric field-effect transistor random access memory (FeFET RAM) can form memory cells using FeFETs, where the stored information depends on the polarization direction of the ferroelectric material in the memory layer, and digital bits "0" and "1" are stored according to the direction of spontaneous polarization.

[0123] like Figure 7 As shown, the memory cell 10000 formed by FeFET may include a channel layer 11000, a ferroelectric material layer 12000, a gate layer 13000, and a source electrode S / drain electrode D stacked together.

[0124] In some embodiments, the channel layer 11000 may comprise amorphous silicon, polycrystalline silicon, monocrystalline silicon, and / or any combination thereof. The channel layer 11000 may be formed using any suitable thin-film deposition technique, such as ALD, CVD, sputtering, etc.

[0125] In some embodiments, the source electrode S / drain electrode D may be a metal layer formed on the channel layer 11000.

[0126] Storage unit 10000 can also be configured to perform data write (programming), data erase, and data read operations. (See reference) Figure 8A , Figure 8B and Figure 8C Please provide an explanation.

[0127] Figure 8A A schematic diagram of a programming operation according to some embodiments of the present disclosure is shown; Figure 8B A schematic diagram of a data reading operation according to some embodiments of the present disclosure is shown; Figure 8C A schematic diagram of voltage pulses applied during programming and erasing operations and charge distribution in a ferroelectric material is shown according to some embodiments of the present disclosure.

[0128] like Figure 8A As shown, during the execution of programming operations, by sending data to the target storage unit (such as...) Figure 8A A programming voltage pulse V is applied to the gate of the memory cell (coupled to word line WL1 and bit line BL1). PRG (e.g., +3V), the polarization direction of the ferroelectric material layer is forcibly reversed to a predetermined direction (e.g., upward) by an electric field, and programming voltage pulses V of different amplitudes are generated. PRG(e.g., 2.5V / 3V / 4.0V) can achieve gradual reversal of ferroelectric polarization. The channel carrier concentration changes, forming a conductive channel (conduction state). Simultaneously, the gradient of charge distribution can be controlled by utilizing the synergistic effect of pulse duration (e.g., 100μs) and voltage amplitude. Furthermore, the negative differential capacitance generated in the polarization reversal transient of the ferroelectric material can reduce the effective operating voltage.

[0129] like Figure 8B As shown, during the data read operation, data is read from the target storage unit (such as...) Figure 8A A small read voltage V is applied to the gate of the memory cell (coupled to word line WL1 and bit line BL1). READ (e.g., +1V, below the coercive voltage, and low read voltage to avoid false polarization reversal). The ferropolar polarization direction affects the channel surface potential. The polarization state is determined by the difference in current measured from the bit line BL or common source line CSL of the memory string where the target memory cell is located.

[0130] During the data erasure operation, a reverse voltage pulse V is applied. ERS (e.g., -3V) or a short pulse sequence, the ferropolarization direction reverses, the negative capacitance effect accelerates the reversal process, the channel carriers are depleted, and the conductive channel is blocked (off state).

[0131] like Figure 8C As shown, taking a 2-bit Fe-NAND semiconductor device, i.e., a single memory cell 10000, as an example, four memory states (00 / 01 / 10 / 11) are distinguished by the polarization state of the ferroelectric material layer 12000. Programming voltage pulses V of different amplitudes... PRG (e.g., 2.5V / 3V / 4.0V) can achieve a gradual reversal of ferroelectric polarization, and the gradient of charge distribution can be controlled by the synergistic effect of pulse duration (e.g., 100μs) and voltage amplitude.

[0132] In some examples, a first voltage pulse (e.g., -3V, with a duration of 100μs) is applied to reset the polarization state of the ferroelectric material layer to a reference threshold voltage (e.g., "00"); a second voltage pulse is applied to cause the polarization of the ferroelectric material layer to reverse, forming a first storage state (e.g., "01"); a third voltage pulse is applied to drive the polarization of the ferroelectric material layer to reverse, forming a second storage state (e.g., "10"); and a fourth voltage pulse is applied to drive the polarization of the ferroelectric material layer to reverse, forming a second storage state (e.g., "11").

[0133] The amplitudes of the second voltage pulse (e.g., 2.5V), the third voltage pulse (e.g., 3V), and the fourth voltage pulse (e.g., 4V) increase sequentially, and the pulse durations can be the same (e.g., 100μs). Within a certain amplitude range, the larger the amplitude of the voltage pulse applied to the gate of the memory cell, the deeper the polarization reversal of the ferroelectric material layer.

[0134] As described above, by applying a suitable voltage pulse to the gate layer 13000, the polarization direction of the ferroelectric material layer 12000 can be switched, and the threshold voltage of the memory cell can be changed. This affects the conductivity of the channel layer 11000 and the on / off state of the memory cell. The storage state (or stored data) of the memory cell can be determined accordingly.

[0135] FeFET RAM, which introduces FeFET memory cells, improves the operating speed of semiconductor devices based on the negative capacitance characteristics of ferroelectric materials during ferroelectric polarization and polarization reversal. It has become a high-performance, low-power non-volatile memory that can provide low-voltage and low-power operation, fast writing, non-volatility and high cycle endurance.

[0136] Next, we will combine Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B The ferroelectric semiconductor device provided in this embodiment will be described. The ferroelectric semiconductor device includes a semiconductor structure and peripheral circuitry coupled to the semiconductor structure. The semiconductor structure includes multiple memory cells.

[0137] Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B Schematic cross-sectional views of a memory cell structure formed using ferroelectric materials according to some embodiments of the present disclosure are shown.

[0138] In some possible implementations, such as Figure 9A As shown, the storage cell 10000 includes a channel layer 11000, a first material layer 14000, and a second material layer 15000 stacked along a preset direction. It may also include a third material layer 16000 and a fourth material layer 17000. The third material layer 16000 is located between the channel layer 11000 and the first material layer 14000, and the fourth material layer 17000 is located on the side of the second material layer 15000 away from the channel layer 11000.

[0139] The first material layer 14000 includes a first sub-material layer 14100 and a first ferroelectric material layer 14200 stacked along a predetermined direction. The first ferroelectric material layer 14200 may be located on the side of the first sub-material layer 14100 away from the channel layer 11000. The defect concentration of the first sub-material layer 14100 is greater than that of the second material layer 15000. Furthermore, the defect concentration of the first sub-material layer 14100 is also greater than that of the third material layer 16000. The material of the fourth material layer 17000 can be conductive, such as being a metal.

[0140] Defect concentration refers to the density or number of defects (such as vacancies, impurities, lattice distortions, etc.) present in a material. In the first submaterial layer 14100, these defects can be trap states in the material, such as dangling bonds or impurity atoms in silicon nitride. The high defect concentration enables the first submaterial layer 14100 to effectively trap and store electrons or holes.

[0141] In some implementations, taking a ferroelectric NAND semiconductor structure as an example, such as Figure 9B As shown, the first material layer 14000 can be used as a charge trapping layer 1230, wherein the first sub-material layer 14100 serves as a charge storage layer 1231 for storing charge from the channel layer 11000. The second material layer 15000 can be used as a barrier layer 1240 for preventing the charge stored in the first sub-material layer 14100 from leaking out of the second material layer 15000, such as preventing the charge stored in the first sub-material layer 14100 from entering the fourth material layer 17000 from the second material layer 15000. The third material layer 16000 can be used as a tunneling layer 1220, and the fourth material layer 17000 can be used as a gate layer 1110. The channel layer 11000 can be an embodiment of the channel layer 1210 in the above embodiment.

[0142] In some examples, for 2D ferroelectric semiconductor devices, the preset direction is the thickness direction of the channel layer.

[0143] In other examples, for 3D ferroelectric semiconductor devices, the semiconductor structure in the 3D ferroelectric semiconductor device includes a stacked structure and a channel structure through the stacked structure.

[0144] In one example, the channel structure may include, for example, Figure 9A The storage cell structure shown, namely the channel structure, includes a channel layer 11000, a first material layer 14000 and a second material layer 15000 stacked along a preset direction, which can be the radial direction of the channel structure.

[0145] In another example, the channel structure may include, for example, Figure 9BThe memory cell structure shown, i.e., the channel structure, includes a channel layer 11000, a charge trapping layer 1230, and a barrier layer 1240 stacked along a predetermined direction. The predetermined direction is the radial direction of the channel structure.

[0146] exist Figure 9A and Figure 9B The storage cell structure provided by the illustrated embodiment benefits from the non-volatile ferroelectric polarization of the ferroelectric material. This means that, in the absence of an external electric field, the centers of positive and negative charges within the ferroelectric material do not coincide, forming an electric dipole moment. When an external electric field is applied, the polarization state of the ferroelectric material can reverse, a characteristic that can be used to store information. By introducing ferroelectric material into the first material layer 14000 or the charge trapping layer 1230, the threshold voltage of the storage cell can be adjusted by controlling the polarization state of the ferroelectric material. Because the polarization state of the ferroelectric material is stable and can be reversed, the storage cell can maintain a stable storage state over a long period, thus significantly improving the storage window.

[0147] On the other hand, such as Figure 9A As shown, the first ferroelectric material layer 14200 can be located on the side of the first sub-material layer 14100 away from the channel layer 11000. Figure 9B As shown, the first ferroelectric material layer 14200 can be located on the side of the charge storage layer 1231 away from the channel layer 11000.

[0148] by Figure 9B Taking the shown memory cell structure as an example, the charge storage layer 1231 is closer to the channel layer 11000 than the first ferroelectric material layer 14200. Because the charge storage layer 1231 is closer to the channel layer 11000, the charge in the channel is more easily captured into the charge storage layer 1231. This design reduces charge loss during the transmission process and improves charge capture efficiency.

[0149] Because the charge transport path between the charge storage layer 1231 and the channel layer 11000 is shorter, the required operating voltage is correspondingly reduced. This helps reduce the power consumption of the memory and improve energy efficiency.

[0150] A shorter charge transport path means faster read and write speeds. The proximity of the charge storage layer 1231 to the channel layer 11000 allows for faster charge transfer between the channel and the charge storage layer 1231, thereby improving the memory's response speed.

[0151] The charge storage layer 1231, located near the channel layer 11000, can better utilize the charge in the channel for storage and release operations, reducing memory failures caused by poor or lost charge transfer. This helps improve the reliability and lifespan of the memory.

[0152] In other possible implementations, such as Figure 10A As shown, similar to Figure 9A The illustrated memory cell structure includes a channel layer 11000, a first material layer 14000, and a second material layer 15000 stacked along a predetermined direction. It may also include a third material layer 16000 and a fourth material layer 17000, with the third material layer 16000 located between the channel layer 11000 and the first material layer 14000, and the fourth material layer 17000 located on the side of the second material layer 15000 away from the channel layer 11000.

[0153] and Figure 9A The difference in the shown memory cell structure is that, Figure 10A The second material layer 15000 in the illustrated memory cell structure includes a second sub-material layer 15100 and a second ferroelectric material layer 15200 stacked along a predetermined direction. The second ferroelectric material layer 15200 is located on the side of the second sub-material layer 15100 away from the channel layer 11000. At least one second sub-material layer 15100 is disposed between the first ferroelectric material layer 14200 and the second ferroelectric material layer 15200. The defect concentration of the first material layer 14000 is greater than that of the second sub-material layer 15100, and furthermore, the defect concentration of the first material layer 14000 is also greater than that of the third material layer 16000.

[0154] Regarding the selection of the preset direction and Figure 9A and Figure 9B The selection of the preset direction is similar in the embodiments shown, and will not be repeated here.

[0155] In some implementations, such as Figure 10B As shown, Figure 10A In the illustrated memory cell structure, the first material layer 14000 can be used as a charge trapping layer 1230 to store charge from the channel layer 11000. The second material layer 15000 can be used as a barrier layer 1240, wherein the second sub-material layer 15100 serves as a charge barrier layer 1241 to prevent the charge stored in the first sub-material layer 14100 from leaking out of the second material layer 15000, such as preventing the charge stored in the first material layer 14000 from entering the fourth material layer 17000 from the second material layer 15000. The third material layer 16000 can be used as a tunneling layer 1220, and the fourth material layer 17000 can be used as a gate layer 1110.

[0156] exist Figure 10A and Figure 10BThe memory cell structure provided in the illustrated embodiment replaces a portion of the second material layer 15000 or the barrier layer 1240 with a ferroelectric material. Since the negative capacitance effect of the ferroelectric material can amplify the gate electric field when connected in series with the conventional dielectric layer, the transistor can achieve the same channel conduction current at a lower operating voltage (equivalent to reducing the threshold voltage). Therefore, by increasing the dielectric constant of the barrier layer 1240 through the ferroelectric material, the negative capacitance effect of the ferroelectric material can amplify the voltage, thereby reducing the operating voltage and improving the response speed.

[0157] Specifically, with Figure 10B Taking the illustrated memory cell structure as an example, the main function of the barrier layer 1240 is to prevent charge leakage, and the dielectric constant is an important parameter for measuring the dielectric properties of a material. Ferroelectric materials typically have high dielectric constants, so introducing them into the barrier layer 1240 can significantly improve its dielectric properties. A higher dielectric constant means that the barrier layer 1240 has a stronger ability to bind charges, which helps reduce the risk of charge leakage and improves the data retention capability of the memory. Furthermore, an increased dielectric constant can also reduce the thickness of the barrier layer 1240, thereby reducing the size of the memory cell and increasing the integration density and storage capacity of the memory.

[0158] Ferroelectric materials also exhibit a negative capacitance effect under the influence of an electric field. That is, when the direction of the applied electric field changes, the polarization direction of the ferroelectric material reverses, leading to a change in capacitance. The negative capacitance of the ferroelectric material is connected in series with the positive capacitance of the high-dielectric-constant dielectric layer, increasing the overall capacitance. This enhances the gate's control over the channel, reducing the operating voltage. This effect can be used to amplify the voltage, thereby lowering the operating voltage. Simultaneously, it helps reduce power consumption and improve the energy efficiency ratio of the memory.

[0159] On the other hand, such as Figure 10A As shown, the second ferroelectric material layer 15200 can be located on the side of the first sub-material layer 14100 away from the channel layer 11000. Figure 10B As shown, the second ferroelectric material layer 15200 can be located on the side of the charge blocking layer 1241 away from the channel layer 11000. Figure 10B Taking the structure of the shown memory cell as an example, the main function of the charge blocking layer 1241 is to prevent illegal migration or leakage of charge. Placing it closer to the channel layer 11000 than the second ferroelectric material layer 15200 can more effectively isolate the charge in the charge trapping layer 1230 from unintended interactions between the ferroelectric material layer or other regions, thereby improving the charge isolation effect and the data retention capability of the memory.

[0160] In some other possible implementations, combined with Figure 9A and Figure 10A Two implementation methods, such as Figure 11AAs shown, the storage cell includes a channel layer 11000, a first material layer 14000, and a second material layer 15000 stacked along a preset direction. It may also include a third material layer 16000 and a fourth material layer 17000. The third material layer 16000 is located between the channel layer 11000 and the first material layer 14000, and the fourth material layer 17000 is located on the side of the second material layer 15000 away from the channel layer 11000.

[0161] The first material layer 14000 includes a first sub-material layer 14100 and a first ferroelectric material layer 14200 stacked along a predetermined direction. The second material layer 15000 includes a second sub-material layer 15100 and a second ferroelectric material layer 15200 stacked along a predetermined direction. At least one second sub-material layer 15100 is disposed between the first ferroelectric material layer 14200 and the second ferroelectric material layer 15200. The defect concentration of the first sub-material layer 14100 is greater than that of the second sub-material layer 15100. Furthermore, the defect concentration of the first sub-material layer 14100 is also greater than that of the third material layer 16000. The fourth material layer 17000 is made of a conductive material, such as a metal.

[0162] Regarding the selection of the preset direction and Figure 9A and Figure 9B The selection of the preset direction is similar in the embodiments shown, and will not be repeated here.

[0163] In some implementations, combined Figure 9B and Figure 10B Two implementation methods, such as Figure 11B As shown, the first material layer 14000 can be used as a charge trapping layer 1230, wherein the first sub-material layer 14100 is used to store charge from the channel layer 11000. The second material layer 15000 can be used as a barrier layer 1240, and the second sub-material layer 15100 is used to prevent the charge stored in the first sub-material layer 14100 from leaking out of the second sub-material layer 15100, such as preventing the charge stored in the first sub-material layer 14100 from entering the fourth material layer 17000 through the second sub-material layer 15100. The third material layer 16000 can be used as a tunneling layer 1220, and the fourth material layer 17000 can be used as a gate layer 1110.

[0164] exist Figure 11A and Figure 11BThe storage cell structure provided by the embodiment shown applies ferroelectric material (FE) to both the first material layer 14000 (or charge trapping layer 1230) and the second material layer 15000 (or barrier layer 1240). This fully utilizes the unique properties of ferroelectric material, such as its ferroelectric polarization characteristics, high dielectric constant, and negative capacitance effect, thereby improving the storage window, data retention capability, operating voltage, and response speed of the memory.

[0165] In other embodiments, the first ferroelectric material layer 14200 includes multiple ferroelectric material sublayers stacked together, wherein adjacent ferroelectric material sublayers are different, such as having different materials or compositions.

[0166] In some other embodiments, the second ferroelectric material layer 15200 includes multiple ferroelectric material sublayers stacked together, wherein adjacent ferroelectric material sublayers are different, such as having different materials or compositions.

[0167] For example, both the first ferroelectric material layer and the second ferroelectric material layer include at least one of the following: hafnium zirconium oxide, hafnium silicon oxide, lead zirconate titanate, strontium barium titanate, strontium bismuth tantalate, lanthanum lead zirconate titanate, hafnium aluminum oxide, hafnium yttrium oxide, LiNbO3, BaMgF, BaMnF, BaFeF, BaCoF, BaNiF, BaZnF, or SrAlF5.

[0168] By configuring the first ferroelectric material layer 14200 or the second ferroelectric material layer 15200 as a stacked multilayer of ferroelectric material sublayers, on the one hand, since different ferroelectric materials respond differently to voltage, the different components of the ferroelectric material layers in the multilayer structure can achieve more precise voltage control. This flexibility helps optimize the operating voltage and power consumption of the memory, while improving the response speed of the memory cell.

[0169] On the other hand, by combining different ferroelectric materials, the advantages of each material, such as high thermal stability or fatigue resistance, can be utilized to improve the thermal stability and fatigue resistance of the entire memory cell, thereby enhancing the long-term stability and reliability of the memory.

[0170] On the other hand, the introduction of multi-component ferroelectric material layers allows memory to be customized and optimized according to different application requirements. For example, in applications requiring high storage density and read / write speeds, a combination of ferroelectric materials with excellent electrical properties can be selected. In applications requiring high stability and reliability, a combination of ferroelectric materials with high thermal stability and fatigue resistance can be selected.

[0171] by Figure 11A and Figure 11B Based on the storage cell structure shown, this embodiment also provides some implementation methods, which can be found in the references. Figure 12A , Figure 12B, Figure 13A and Figure 13B Please provide an explanation.

[0172] Figure 12A , Figure 12B , Figure 13A and Figure 13B Schematic cross-sectional views of a memory cell structure formed using ferroelectric materials according to some embodiments of the present disclosure are shown.

[0173] In some implementations, such as Figure 12A As shown, the first material layer 14000 includes multiple first sub-material layers 14100 and multiple first ferroelectric material layers 14200, with the first sub-material layers 14100 and the first ferroelectric material layers 14200 being alternately arranged.

[0174] In other implementations, such as Figure 12B As shown, the charge trapping layer 1230 includes multiple charge storage layers 1231 and multiple first ferroelectric material layers 14200, with the charge storage layers 1231 and the first ferroelectric material layers 14200 being alternately arranged.

[0175] In some implementations, such as Figure 13A As shown, the second material layer 15000 includes multiple second sub-material layers 15100 and multiple second ferroelectric material layers 15200. The second ferroelectric material layers 15200 and the second ferroelectric material layers 15200 are alternately arranged.

[0176] In other implementations, such as Figure 13B As shown, the barrier layer 1240 includes multiple charge barrier layers 1241 and multiple second ferroelectric material layers 15200. The charge barrier layers 1241 and the second ferroelectric material layers 15200 are alternately arranged.

[0177] In some examples, such as Figure 12A , Figure 12B , Figure 13A and Figure 13B In the storage cell structure shown, the first ferroelectric material layer 14200 includes multiple ferroelectric material sublayers, and adjacent ferroelectric material sublayers in the second ferroelectric material layer 15200 are also different. For example, one ferroelectric material can be hafnium silicon oxide, and the adjacent ferroelectric material can be hafnium aluminum oxide.

[0178] exist Figure 12A , Figure 12B , Figure 13A and Figure 13BThe storage cell structure provided by the illustrated embodiment, on the one hand, can further increase the charge storage capacity by setting up multiple charge storage layers 1231, and on the other hand, the multi-layer structure also helps to optimize the charge storage and release process. The alternating arrangement of multiple first ferroelectric material layers 14200 and multiple second ferroelectric material layers 15200 can more effectively control the capture and release of charge, and improve the response speed and stability of the storage cell.

[0179] Alternating charge storage layers 1231 and ferroelectric material layers enable the formation of more complex charge trapping and releasing mechanisms, thereby improving the storage performance and reliability of the memory cell. The multilayer structure helps reduce charge loss during storage, extending the memory's lifespan.

[0180] The alternating arrangement of the multilayer second ferroelectric material layer 15200 within the charge blocking layer 1241 can superimpose a negative capacitance effect, thereby more effectively amplifying the voltage applied to the memory cell and further reducing the operating voltage. By reducing the operating voltage, the power consumption of the memory can be significantly reduced, improving the energy efficiency ratio.

[0181] Multilayer structures enable memory cells to respond to external signals more quickly, improving the memory's response speed. The introduction of multiple ferroelectric material layers enhances the stability of memory cells and reduces performance fluctuations caused by changes in the external environment.

[0182] On the other hand, since ferroelectric materials of different compositions respond differently to voltage, the different ferroelectric material layers in a multilayer structure can achieve more precise voltage control. This flexibility helps optimize the operating voltage and power consumption of the memory, while improving the response speed of the memory cells.

[0183] By combining different ferroelectric materials, the advantages of each material, such as high thermal stability or fatigue resistance, can be utilized to improve the thermal stability and fatigue resistance of the entire memory cell, thereby enhancing the long-term stability and reliability of the memory.

[0184] The introduction of different ferroelectric material layers allows memory to be customized and optimized for various application requirements. For example, in applications requiring high storage density and read / write speeds, a combination of ferroelectric materials with excellent electrical properties can be selected. In applications requiring high stability and reliability, a combination of ferroelectric materials with high thermal stability and fatigue resistance can be chosen.

[0185] The fabrication method of the above semiconductor structure is described below.

[0186] like Figure 14 As shown, Figure 14 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments. It is understood that... Figure 14The method for fabricating the semiconductor structure shown is not exclusive and can also be used in... Figure 14 Other steps are performed before, after, or between any step in the method of fabricating the semiconductor structure shown.

[0187] The method for fabricating a semiconductor structure includes the following steps S1 to S3.

[0188] S1, forming the initial stacked structure.

[0189] like Figure 15 As shown, Figure 15 for Figure 14 The flowchart of the semiconductor structure fabrication method is shown in the diagram. Step S1 corresponds to a semiconductor structure. In step S1, an initial stacked structure 1100A can be formed on a substrate 4000.

[0190] For example, the initial stacked structure 1100A can be formed by a deposition process. For example, the deposition process can be chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or metal-organic chemical vapor deposition (MOCVD), etc.

[0191] Please continue reading. Figure 15 The initial stacked structure 1100A includes a sacrificial layer 1130 and a dielectric layer 1120 that are alternately stacked along the first direction Z.

[0192] The aforementioned "alternating stacking" refers to the arrangement of multiple dielectric layers 1120 and sacrificial layers 1130 in an alternating manner along the first direction Z. For example, along the first direction Z, a dielectric layer 1120 is first set, then a sacrificial layer 1130 is set on the dielectric layer 1120, and then another dielectric layer 1120 is set on the sacrificial layer 1130, and so on, alternatingly, to form the initial stacking structure 1100A.

[0193] It should be noted that, Figure 15 The number of dielectric layer 1120 and sacrificial layer 1130 is merely illustrative, and the embodiments of this disclosure do not impose any limitation on the number of dielectric layer 1120 and sacrificial layer 1130.

[0194] For example, the material used to form the dielectric layer 1120 can be an oxide, such as silicon oxide. The material used to form the sacrificial layer 1130 can be a nitride, such as silicon nitride, specifically Si3N4.

[0195] After forming the initial stacked structure 1100A, the method for fabricating the semiconductor structure in this embodiment further includes:

[0196] S2, forming a channel structure that runs through the initial stacked structure.

[0197] The trench structure 1200 includes a barrier layer 1240, a charge trapping layer 1230, a tunneling layer 1220, and a trench layer 1210, which are stacked radially along the trench structure 1200.

[0198] The following provides a detailed explanation of step S2.

[0199] Please continue reading. Figure 14 and combined Figures 16-18 , Figure 16 for Figure 14 The flowchart of the semiconductor structure fabrication method shows a schematic diagram of a semiconductor structure corresponding to step S21. Figure 17 for Figure 14 The flowchart of the semiconductor structure fabrication method shows a schematic diagram of a semiconductor structure corresponding to steps S22 and S25. It should be noted that, for ease of explanation of the channel structure 1200, Figure 17 for Figure 16 The structural diagram of the CC region after the formation of the channel structure at 1200°.

[0200] Step S2 in the method for fabricating a semiconductor structure includes:

[0201] S21, such as Figure 16 As shown, a channel hole is formed that penetrates the initial stacked structure.

[0202] For example, a plasma etching process can be used to form the channel hole CH.

[0203] After forming the channel hole CH that penetrates the initial stacked structure 1100A, step S2 in this embodiment further includes:

[0204] S22. A barrier layer is formed inside the channel hole, and the barrier layer covers the sidewall of the channel hole.

[0205] In some embodiments, such as Figure 17 As shown, the barrier layer 1240 is a composite film structure, that is, it includes at least one second ferroelectric material layer 15200 and at least one charge barrier layer 1241. The step S22 of forming the barrier layer 1240 includes S221 and S222.

[0206] S221. A second ferroelectric material layer is formed using the first deposition process.

[0207] For example, the first deposition process described above can be atomic layer deposition (ALD). The feed gas forms a second ferroelectric material layer 15200 through the atomic layer deposition process.

[0208] For example, the aforementioned raw material gas refers to a gaseous raw material. For instance, the raw material gas may include a gas obtained by vaporizing a raw material that is liquid at room temperature and pressure, and a gas that is gaseous at room temperature and pressure.

[0209] S222. A second deposition process is used to form a charge blocking layer. The second ferroelectric material layer and the charge blocking layer are stacked radially along the channel structure.

[0210] For example, the second deposition process described above can be atomic layer deposition (ALD). The feed gas forms a charge barrier layer 1241 through the atomic layer deposition process.

[0211] For example, the process for forming the barrier layer 1240 includes, but is not limited to, chemical vapor deposition, physical vapor deposition and atomic layer deposition.

[0212] It should be noted that, Figure 17 The method of fabricating the barrier layer 1240 is illustrated by taking an example where the barrier layer 1240 includes a second ferroelectric material layer 15200 and at least one charge barrier layer 1241, with the second ferroelectric material layer 15200 located on the side of the charge barrier layer 1241 away from the channel layer 1210. However, the embodiments disclosed herein are not limited to this.

[0213] In one example, the barrier layer 1240 may further include multiple charge barrier layers 1241 and multiple second ferroelectric material layers 15200, with the charge barrier layers 1241 and the second ferroelectric material layers 15200 alternately arranged. At least two of the multiple second ferroelectric material layers 15200 may contain different ferroelectric materials.

[0214] In another example, the second ferroelectric material layer 15200 may include multiple ferroelectric material sublayers, wherein adjacent ferroelectric material sublayers are different.

[0215] After forming the barrier layer 1240, step S2 in this embodiment further includes:

[0216] S23. A charge trapping layer is formed inside the channel hole, and the charge trapping layer covers the surface of the barrier layer.

[0217] In some embodiments, please continue reading Figure 17The charge trapping layer 1230 is a composite film structure, namely, it includes at least one first ferroelectric material layer 14200 and at least one charge storage layer 1231. The step S23 of forming the charge trapping layer 1230 includes S231 and S232:

[0218] S231. The first ferroelectric material layer is formed by using the third deposition process.

[0219] For example, the third deposition process described above can be atomic layer deposition (ALD). The feed gas forms a first ferroelectric material layer 14200 through the atomic layer deposition process.

[0220] For example, the aforementioned raw material gas refers to a gaseous raw material. For instance, the raw material gas may include a gas obtained by vaporizing a raw material that is liquid at room temperature and pressure, and a gas that is gaseous at room temperature and pressure.

[0221] S232. A charge storage layer is formed using a fourth deposition process, wherein the first ferroelectric material layer and the charge storage layer are stacked radially along the channel structure.

[0222] For example, the fourth deposition process described above can be atomic layer deposition (ALD). The feed gas forms a charge storage layer 1231 through the atomic layer deposition process.

[0223] For example, the process for forming the charge storage layer 1231 includes, but is not limited to, chemical vapor deposition, physical vapor deposition, and atomic layer deposition (ALD).

[0224] It should be noted that, Figure 17 The method of fabricating the charge trapping layer 1230 is illustrated by taking an example where the charge trapping layer 1230 includes a first ferroelectric material layer 14200 and at least one charge storage layer 1231, and the first ferroelectric material layer 14200 is located on the side of the charge storage layer 1231 away from the channel layer 1210. However, the embodiments disclosed herein are not limited to this.

[0225] In one example, the charge trapping layer 1230 may further include multiple charge storage layers 1231 and multiple first ferroelectric material layers 14200, with the charge storage layers 1231 and the first ferroelectric material layers 14200 alternating. At least two of the multiple first ferroelectric material layers 14200 may contain different ferroelectric materials.

[0226] In another example, the first ferroelectric material layer 14200 may include multiple ferroelectric material sublayers, wherein adjacent ferroelectric material sublayers are different.

[0227] After forming the charge trapping layer 1230, step S2 in this embodiment further includes:

[0228] S24. A tunneling layer is formed inside the channel hole, and the tunneling layer covers the surface of the charge trapping layer.

[0229] For example, the process for forming the tunnel layer 1220 includes, but is not limited to, chemical vapor deposition, physical vapor deposition, and atomic layer deposition (ALD).

[0230] After the tunneling layer 1220 is formed, step S2 in this embodiment further includes:

[0231] S25. A channel layer forming a channel structure within the channel hole.

[0232] After forming the channel structure 1200 that runs through the initial stacked structure 1100A, please refer again. Figure 17 and combined Figure 18 , Figure 18 for Figure 14 The flowchart of the semiconductor structure fabrication method shows a structural diagram of a semiconductor structure corresponding to step S3. The semiconductor structure fabrication method also includes:

[0233] S3. Remove the sacrificial layer in the initial stacked structure and form a gate layer in the cavity formed after removing the sacrificial layer.

[0234] like Figure 18 As shown, the sacrificial layer 1130 in the initial stacked structure 1100A is removed, and a gate layer 1110 is formed in the cavity formed after the sacrificial layer 1130 is removed, resulting in a stacked structure 1100 and a semiconductor structure 1000.

[0235] This application provides a semiconductor structure, a method for fabricating the semiconductor structure, and a semiconductor device. Ferroelectric materials (FE) are introduced into the charge trapping layer and barrier layer of the semiconductor device, such as changing from Si3N4 to a multilayer structure of Si3N4 and ferroelectric materials, and changing the barrier layer from SiO2 to a multilayer structure of SiO2 and ferroelectric materials. Based on the non-volatile ferroelectric polarization and negative capacitance characteristics during polarization reversal of ferroelectric materials, the operating speed of the semiconductor device is improved, and the memory wall problem is mitigated. Simultaneously, the operating voltage, such as the maximum programming voltage, is reduced, the programming voltage is improved, and the memory window and tolerance characteristics are increased, resulting in an overall reduction in power consumption.

[0236] Embodiments of this disclosure also provide an electronic device, such as Figure 19The diagram illustrates a structural schematic of an electronic device according to some embodiments of the present disclosure. The electronic device 1 can be a mobile phone (e.g., a cell phone), desktop computer, tablet computer, laptop computer, server, in-vehicle device, game console, printer, positioning device, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, power bank, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0237] like Figure 19 As shown, electronic device 1 includes a storage system 10 and a host 20. The storage system 10 includes a controller 200 and one or more semiconductor devices 100 as described in some of the embodiments above, with the controller 200 coupled to the semiconductor devices 100. The controller 200 may be a controller.

[0238] The host 20 can be the processor of the electronic device 1. For example, the processor can be a chip, specifically a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), an application processor (AP), or other integrated chips.

[0239] According to some embodiments, controller 200 is coupled to semiconductor device 100 and host 20 and is configured to control semiconductor device 100. Controller 200 can manage data stored in semiconductor device 100 and communicate with host 20. In some embodiments, controller 200 is designed to operate in a low duty cycle environment, such as secure digital (SD) cards, compact flash cards (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, controller 200 is designed to operate in a high duty cycle environment, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage devices for mobile electronic devices such as smartphones, tablets, personal computers, etc., and for enterprise storage arrays.

[0240] The controller 200 can be configured to manage data stored in the semiconductor device 100 and communicate with external devices (e.g., host 20). It controls the semiconductor device 100 to perform corresponding operations, such as data reading, data erasure, and programming operations. Exemplarily, the controller 200 can also be configured to manage various functions related to data stored or to be stored in the semiconductor device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and redundant array of independent disks (RAID).

[0241] In some implementations, the controller 200 is also configured to process error correction codes (ECCs) relating to data read from or written to the semiconductor device 100.

[0242] Controller 200 can also perform any other suitable functions, such as formatting semiconductor device 100. Controller 200 can communicate with external devices (e.g., host 20) according to a specific communication protocol. For example, controller 200 can communicate with external devices through at least one of various interface protocols, such as USB, Multimedia Card (MMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0243] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0244] The controller 200 and one or more semiconductor devices 100 can be integrated into various types of storage systems 10, for example, included in the same package, such as an embedded multimedia card (eMMC), universal flash storage (UFS) package, embedded multichip package (eMCP) package, or UFS-based multichip package (uMCP) package. eMMC uses a unified MMC standard interface, encapsulating high-density NAND and the MMC controller in a ball grid array (BGA) package chip. UFS is an advanced version of eMMC, also an array-type storage module composed of multiple flash memory chips and a controller. UFS overcomes the limitation of eMMC, which only supports half-duplex operation (read and write must be performed separately), enabling full-duplex operation and thus doubling performance. eMCP is a package that incorporates volatile memory, such as static random-access memory (SRAM) or dynamic random-access memory (DRAM), on an eMMC.

[0245] In a practical implementation, the DRAM can be low-power double-data-rate synchronous dynamic random-access memory (LPDDR). uMCP is a packaged form of UFS with volatile memory (such as SRAM or DRAM) mounted on it, offering high performance and large capacity. In a practical implementation, the DRAM can be LPDDR. That is to say, the storage system 10 can be implemented and packaged into different types of end electronic devices.

[0246] In such Figure 20 In one example shown, controller 200 and a single semiconductor device 100 can be integrated into memory card 30. Memory card 30 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 30 may also include a connection between memory card 30 and a host (e.g., Figure 19 The host 20) is coupled to the memory card connector T1.

[0247] In such Figure 21In another example shown, controller 200 and multiple semiconductor devices 100 can be integrated into SSD 40. SSD 40 may also include interfaces for connecting SSD 40 to a host (e.g.,...). Figure 19 The host 20 is coupled to the SSD connector T2. In some implementations, the storage capacity and / or operating speed of the SSD 40 is higher than that of the memory card 30.

[0248] This application also provides a computer-readable storage medium including instructions. When the instructions are executed on the electronic device or storage system described in the above embodiments, the electronic device or storage system performs the preparation method described in the above embodiments.

[0249] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A stacked channel layer, charge trapping layer, and barrier layer; The charge trapping layer includes a charge storage layer and a first ferroelectric material layer stacked together. The barrier layer includes a charge barrier layer and a second ferroelectric material layer stacked together. At least one charge blocking layer is disposed between the first ferroelectric material layer and the second ferroelectric material layer.

2. The semiconductor structure according to claim 1, characterized in that, The charge trapping layer includes a charge storage layer and a first ferroelectric material layer; The first ferroelectric material layer is located on the side of the charge storage layer away from the channel layer.

3. The semiconductor structure according to claim 1, characterized in that, The barrier layer includes a charge barrier layer and a second ferroelectric material layer; The second ferroelectric material layer is located on the side of the charge blocking layer away from the channel layer.

4. The semiconductor structure according to claim 1, characterized in that, The charge trapping layer includes multiple charge storage layers and multiple first ferroelectric material layers; The charge storage layer and the first ferroelectric material layer are alternately arranged.

5. The semiconductor structure according to claim 4, characterized in that, At least two of the first ferroelectric material layers in the multilayer structure are made of different ferroelectric materials.

6. The semiconductor structure according to claim 1, characterized in that, The barrier layer comprises multiple charge barrier layers and multiple second ferroelectric material layers; The charge blocking layer and the second ferroelectric material layer are alternately arranged.

7. The semiconductor structure according to claim 6, characterized in that, At least two of the multilayer second ferroelectric material layers are made of different ferroelectric materials.

8. The semiconductor structure according to any one of claims 1-7, characterized in that, The first ferroelectric material layer includes multiple layers of ferroelectric material sublayers stacked together, wherein adjacent ferroelectric material sublayers are different.

9. The semiconductor structure according to any one of claims 1-7, characterized in that, The second ferroelectric material layer includes multiple layers of ferroelectric material sublayers stacked together, wherein adjacent ferroelectric material sublayers are different.

10. The semiconductor structure according to any one of claims 1-7, characterized in that, Both the first ferroelectric material layer and the second ferroelectric material layer include at least one of the following: hafnium zirconium oxide, hafnium silicon oxide, lead zirconate titanate, strontium barium titanate, strontium bismuth tantalate, lanthanum lead zirconate titanate, hafnium aluminum oxide, hafnium yttrium oxide, LiNbO3, BaMgF, BaMnF, BaFeF, BaCoF, BaNiF, BaZnF, or SrAlF5.

11. The semiconductor structure according to any one of claims 1-7, characterized in that, The material of the charge storage layer includes silicon nitride; the material of the charge blocking layer includes silicon oxide.

12. The semiconductor structure according to claim 1, characterized in that, The storage unit also includes a tunneling layer. The tunneling layer is located between the channel layer and the charge trapping layer.

13. A semiconductor structure, characterized in that, include: Stacked structure; A channel structure, penetrating the stacked structure, includes a channel layer, a charge trapping layer, and a blocking layer stacked along a predetermined direction; the predetermined direction is the radial direction of the channel structure. The charge trapping layer includes a charge storage layer and a first ferroelectric material layer stacked along the preset direction; the blocking layer includes a charge blocking layer and a second ferroelectric material layer stacked along the preset direction; at least one charge blocking layer is disposed between the first ferroelectric material layer and the second ferroelectric material layer.

14. The semiconductor structure according to claim 13, characterized in that, The charge trapping layer includes a charge storage layer and a first ferroelectric material layer; The first ferroelectric material layer is located on the side of the charge storage layer away from the channel layer.

15. The semiconductor structure according to claim 13, characterized in that, The barrier layer includes a charge barrier layer and a second ferroelectric material layer; The second ferroelectric material layer is located on the side of the charge blocking layer away from the channel layer.

16. The semiconductor structure according to claim 13, characterized in that, The charge trapping layer includes multiple charge storage layers and multiple first ferroelectric material layers; The charge storage layer and the first ferroelectric material layer are alternately arranged.

17. The semiconductor structure according to claim 16, characterized in that, At least two of the first ferroelectric material layers in the multilayer structure are made of different ferroelectric materials.

18. The semiconductor structure according to claim 13, characterized in that, The barrier layer comprises multiple charge barrier layers and multiple second ferroelectric material layers; The charge blocking layer and the second ferroelectric material layer are alternately arranged.

19. The semiconductor structure according to claim 18, characterized in that, At least two of the multilayer second ferroelectric material layers are made of different ferroelectric materials.

20. The semiconductor structure according to any one of claims 13-19, characterized in that, The first ferroelectric material layer includes multiple ferroelectric material sublayers stacked along the preset direction, wherein adjacent ferroelectric material sublayers are different.

21. The semiconductor structure according to any one of claims 13-19, characterized in that, The second ferroelectric material layer includes multiple ferroelectric material sublayers stacked along the preset direction, wherein adjacent ferroelectric material sublayers are different.

22. The semiconductor structure according to any one of claims 13-19, characterized in that, The stacked structure includes alternating layers of dielectric and gate layers.

23. A semiconductor structure, characterized in that, include: Stacked structure; The channel structure extends through the stacked structure and includes a channel layer, a first material layer, and a second material layer stacked along a preset direction. The preset direction is the radial direction of the channel structure; The first material layer includes a first sub-material layer and a first ferroelectric material layer stacked along the preset direction; the second material layer includes a second sub-material layer and a second ferroelectric material layer stacked along the preset direction; at least one second sub-material layer is disposed between the first ferroelectric material layer and the second ferroelectric material layer; the defect concentration of the first sub-material layer is greater than the defect concentration of the second sub-material layer.

24. The semiconductor structure according to claim 23, characterized in that, The first material layer includes a first sub-material layer and a first ferroelectric material layer; The first ferroelectric material layer is located on the side of the first material layer away from the channel layer.

25. The semiconductor structure according to claim 23, characterized in that, The second material layer includes a second sub-material layer and a second ferroelectric material layer; The second ferroelectric material layer is located on the side of the second material layer away from the channel layer.

26. The semiconductor structure according to claim 23, characterized in that, The first material layer includes multiple first sub-material layers and multiple first ferroelectric material layers; The first sub-material layer and the first ferroelectric material layer are alternately arranged.

27. The semiconductor structure according to claim 23, characterized in that, The second material layer includes multiple layers of the second sub-material layer and multiple layers of the second ferroelectric material layer; The second ferroelectric material layer and the second ferroelectric material layer are alternately arranged.

28. The semiconductor structure according to any one of claims 23-27, characterized in that, The material of the first sub-material layer includes silicon nitride; the material of the second sub-material layer includes silicon oxide.

29. A method for fabricating a semiconductor structure, characterized in that, include: A channel layer, a charge trapping layer, and a barrier layer are stacked together; The charge trapping layer includes a charge storage layer and a first ferroelectric material layer stacked together. The barrier layer includes a charge barrier layer and a second ferroelectric material layer stacked together. At least one charge blocking layer is disposed between the first ferroelectric material layer and the second ferroelectric material layer.

30. The method for fabricating a semiconductor structure according to claim 29, characterized in that, The channel layer, charge trapping layer, and barrier layer formed by the stacking include: Forming a stacked structure; A channel structure is formed that runs through the stacked structure. The channel structure includes a channel layer, a charge trapping layer, and a blocking layer stacked along a predetermined direction; the predetermined direction is the radial direction of the channel structure. The charge trapping layer includes a charge storage layer and a first ferroelectric material layer stacked along the preset direction; the blocking layer includes a charge blocking layer and a second ferroelectric material layer stacked along the preset direction.

31. The method for fabricating a semiconductor structure according to claim 29 or 30, characterized in that, A charge storage layer and a first ferroelectric material layer are formed between the barrier layer and the channel layer; The first ferroelectric material layer is located on the side of the charge storage layer away from the channel layer.

32. The method for fabricating a semiconductor structure according to claim 29 or 30, characterized in that, A charge blocking layer and a second ferroelectric material layer are formed on the charge trapping layer; The second ferroelectric material layer is located on the side of the charge blocking layer away from the channel layer.

33. The method for fabricating a semiconductor structure according to claim 30, characterized in that, A multilayer charge storage layer and a multilayer first ferroelectric material layer are formed between the barrier layer and the channel layer; The charge storage layer and the first ferroelectric material layer are alternately arranged.

34. The method for fabricating a semiconductor structure according to claim 33, characterized in that, At least two of the first ferroelectric material layers in the multilayer structure are made of different ferroelectric materials.

35. The method for fabricating a semiconductor structure according to claim 30, characterized in that, Multiple charge blocking layers and multiple second ferroelectric material layers are formed on the charge trapping layer; The charge blocking layer and the second ferroelectric material layer are alternately arranged.

36. The method for fabricating a semiconductor structure according to claim 35, characterized in that, At least two of the multilayer second ferroelectric material layers are made of different ferroelectric materials.

37. The method for fabricating a semiconductor structure according to any one of claims 30 or 33-36, characterized in that, The first ferroelectric material layer or the second ferroelectric material layer includes: Along the preset direction, multiple layers of ferroelectric material sublayers are formed, wherein adjacent ferroelectric material sublayers are different.

38. A semiconductor device, characterized in that, include: The semiconductor structure as described in any one of claims 1-28; The peripheral circuit is coupled to the semiconductor structure.

39. A storage system, characterized in that, include: The semiconductor device as described in claim 38; The controller is coupled to the semiconductor device.

40. An electronic device, characterized in that, include: The host and the storage system as described in claim 39 are coupled together.

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