Semiconductor memory device

Abstract

This invention provides a semiconductor memory device capable of suppressing substrate mining. One embodiment of the semiconductor memory device includes a first stack, a second stack, memory pillars, a first contact, a first break, a second contact, and a second break. The first stack includes a plurality of first wiring layers and a plurality of first insulating layers disposed on the same layer as the plurality of first wiring layers. The second stack includes a plurality of second wiring layers and a plurality of second insulating layers disposed on the same layer as the plurality of second wiring layers, and is disposed above the first stack. The memory pillar penetrates through the plurality of first and second wiring layers. The first contact penetrates through the second stack and is connected to a third wiring layer among the plurality of first wiring layers. The first break divides the plurality of first wiring layers. The second contact is connected to a fourth wiring layer among the plurality of second wiring layers. The second break divides the plurality of second wiring layers. The second break does not overlap with the first break.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0002] NAND flash memory is a known semiconductor storage device capable of non-volatile data storage. Summary of the Invention

[0003] One embodiment of the present invention provides a semiconductor memory device capable of suppressing substrate mining.

[0004] The semiconductor memory device of the embodiment includes a first stack, a second stack, a memory pillar, a first contact, a first break portion, a second contact, and a second break portion. The first stack includes a plurality of first wiring layers spaced apart from each other in a first direction, and a plurality of first insulating layers disposed on the same layer as the plurality of first wiring layers. The second stack includes a plurality of second wiring layers spaced apart from each other in the first direction, and a plurality of second insulating layers disposed on the same layer as the plurality of second wiring layers, and is disposed above the first stack. The memory pillar extends through the plurality of first wiring layers and the plurality of second wiring layers in the first direction. The first contact extends along the first direction and through the second stack, connects to a third wiring layer among the plurality of first wiring layers, and at least a portion of its side surface is covered by a first insulator. The first break portion extends along the first direction and a second direction intersecting the first direction, breaking the plurality of first wiring layers in a third direction intersecting the first and second directions. The second contact extends along the first direction, connects to the fourth wiring layer among a plurality of second wiring layers, and at least a portion of its side surface is covered by the second insulator. The second break extends along both the first and second directions, breaking the plurality of second wiring layers in the third direction. The second break does not overlap with the first break in the first direction. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system including the semiconductor memory device of the first embodiment.

[0006] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the semiconductor memory device of the first embodiment.

[0007] Figure 3 This is a perspective view showing the outline of the bonding structure of the semiconductor memory device according to the first embodiment.

[0008] Figure 4 This is a top view showing an example of the planar layout of the semiconductor memory device according to the first embodiment.

[0009] Figure 5This is a top view showing an example of the planar layout of the memory cell array in the core region of the semiconductor memory device according to the first embodiment.

[0010] Figure 6 This is an example of a cross-sectional structure along the storage region of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 5 A sectional view along line VI-VI.

[0011] Figure 7 This is an example of the cross-sectional structure of the memory pillars included in the semiconductor memory device of the first embodiment, along... Figure 6 A sectional view along line VII-VII.

[0012] Figure 8 This is an example of a cross-sectional structure in the contact region of the memory cell array included in the semiconductor memory device of the first embodiment, along... Figure 5 A cross-sectional view of line VIII-VIII.

[0013] Figure 9 This is an example of a cross-sectional structure in the contact region of the memory cell array included in the semiconductor memory device of the first embodiment, along... Figure 5 A cross-sectional view of the IX-IX line.

[0014] Figure 10 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0015] Figure 11 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0016] Figure 12 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0017] Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0018] Figure 14 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0019] Figure 15 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0020] Figure 16 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0021] Figure 17 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0022] Figure 18 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0023] Figure 19 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0024] Figure 20 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0025] Figure 21 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0026] Figure 22 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0027] Figure 23 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0028] Figure 24 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0029] Figure 25 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0030] Figure 26 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0031] Figure 27 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0032] Figure 28 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0033] Figure 29 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0034] Figure 30This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0035] Figure 31 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0036] Figure 32 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0037] Figure 33 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0038] Figure 34 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0039] Figure 35 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0040] Figure 36 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0041] Figure 37 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the first embodiment.

[0042] Figure 38 This is an example of the cross-sectional structure of the contact region of the memory cell array included in the semiconductor memory device of the first variation of the first embodiment, along... Figure 5 A cross-sectional view of line VIII-VIII.

[0043] Figure 39 This is an example of the cross-sectional structure of the contact region of the memory cell array included in the semiconductor memory device of the first variation of the first embodiment, along... Figure 5 A cross-sectional view of the IX-IX line.

[0044] Figure 40 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0045] Figure 41 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0046] Figure 42This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0047] Figure 43 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0048] Figure 44 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0049] Figure 45 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0050] Figure 46 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0051] Figure 47 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0052] Figure 48 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0053] Figure 49 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0054] Figure 50 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0055] Figure 51 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0056] Figure 52 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0057] Figure 53 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0058] Figure 54 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0059] Figure 55 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a first variation of the first embodiment.

[0060] Figure 56 This is a top view showing an example of the planar layout of the memory cell array in the core region of the semiconductor memory device of the second variation of the first embodiment.

[0061] Figure 57 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a second variation of the first embodiment.

[0062] Figure 58 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a second variation of the first embodiment.

[0063] Figure 59 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a second variation of the first embodiment.

[0064] Figure 60 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a second variation of the first embodiment.

[0065] Figure 61 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a second variation of the first embodiment.

[0066] Figure 62 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a second variation of the first embodiment.

[0067] Figure 63 This is a top view showing an example of the planar structure of a semiconductor memory device during the manufacturing process of a second variation of the first embodiment.

[0068] Figure 64 This is a top view showing an example of the planar layout of the memory cell array in the core region of the semiconductor memory device according to the second embodiment.

[0069] Figure 65 This is an example of a cross-sectional structure in the storage region of the memory cell array included in the semiconductor memory device of the second embodiment, along... Figure 64 A sectional view of line S1-S1.

[0070] Figure 66 This is an example of a cross-sectional structure in the contact region of the memory cell array included in the semiconductor memory device of the second embodiment, along... Figure 64 A cross-sectional view of line S2-S2.

[0071] Figure 67 This is an example of a cross-sectional structure in the contact region of the memory cell array included in the semiconductor memory device of the second embodiment, along... Figure 64 A sectional view of line S3-S3.

[0072] Figure 68 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0073] Figure 69 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0074] Figure 70 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0075] Figure 71 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0076] Figure 72 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0077] Figure 73 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0078] Figure 74 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0079] Figure 75 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0080] Figure 76 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0081] Figure 77 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0082] Figure 78 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0083] Figure 79This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0084] Figure 80 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0085] Figure 81 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0086] Figure 82 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0087] Figure 83 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0088] Figure 84 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0089] Figure 85 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0090] Figure 86 This is a top view showing an example of the planar structure of the semiconductor memory device during manufacturing according to the second embodiment.

[0091] Figure 87 This is an example of the cross-sectional structure of the contact region of the memory cell array included in the semiconductor memory device, which represents a variation of the second embodiment. (The text abruptly ends here, likely due to an incomplete sentence or missing information.) Figure 64 A cross-sectional view of line S2-S2.

[0092] Figure 88 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a variation of the second embodiment.

[0093] Figure 89 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a variation of the second embodiment.

[0094] Figure 90 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a variation of the second embodiment.

[0095] Figure 91 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device during the manufacturing process of a variation of the second embodiment. Detailed Implementation

[0096] The embodiments will now be described with reference to the accompanying drawings.

[0097] The dimensions and scale of the accompanying drawings are not necessarily the same as the actual objects. Illustrations of the composition may be omitted as appropriate. Furthermore, in the following description, constituent elements with substantially the same function and structure are labeled with the same symbols. Where elements with the same composition are specifically distinguished from each other, sometimes different characters or numbers are appended to the end of the same symbol.

[0098] 1. First Implementation Method

[0099] 1.1 Composition

[0100] 1.1.1 Memory System Composition

[0101] use Figure 1 The configuration of a memory system including the semiconductor memory device of the first embodiment will be described. Figure 1 This is a block diagram illustrating an example of the configuration of a memory system including the semiconductor memory device of the first embodiment. The memory system 1 is a memory device configured to connect to an external host machine (not shown). The memory system 1 is, for example, a memory card such as an SDTM card, UFS (universal flash storage), or SSD (solid state drive). Figure 1 As shown, the memory system 1 includes a memory controller 2 and a semiconductor memory device 3.

[0102] The memory controller 2 is, for example, an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on requests from the host machine. For example, the memory controller 2 writes data requested by the host machine to the semiconductor memory device 3. Additionally, the memory controller 2 reads data requested by the host machine from the semiconductor memory device 3 and sends it to the host machine.

[0103] Semiconductor memory device 3 is a memory that stores data non-volatilely. Semiconductor memory device 3 is, for example, NAND flash memory. Hereinafter, NAND flash memory will be used as an example of semiconductor memory device 3 for explanation.

[0104] 1.1.2 Structure of Semiconductor Memory Devices

[0105] Next, refer to Figure 1 The configuration of semiconductor memory device 3 will be explained. For example... Figure 1 As shown, the semiconductor memory device 3 includes an array chip 100 and a circuit chip 200.

[0106] The array chip 100 includes, for example, a memory cell array 10.

[0107] The memory cell array 10 includes multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors capable of non-volatilely storing data. Block BLK is used, for example, as a data erasure unit. Additionally, the memory cell array 10 includes multiple bit lines and multiple word lines. Each memory cell transistor is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described below.

[0108] The circuit chip 200 includes, for example, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a line decoder module 15, and a sense amplifier module 16.

[0109] Instruction register 11 is a circuit that stores instructions (CMD) received by semiconductor memory device 3 from memory controller 2. Instructions (CMD) may include commands that cause sequencer 13 to perform read, write, and erase operations.

[0110] Address register 12 is a circuit that stores the address ADD received by the semiconductor memory device 3 from the memory controller 2. The address ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, page address PAd, and column address CAd are used for the selection of the block BLK, word line, and bit line, respectively.

[0111] The sequencer 13 is a circuit that controls the operation of other circuits according to a predetermined program. The sequencer 13 controls the operation of the entire semiconductor memory device 3. For example, the sequencer 13 controls the driver module 14, the line decoder module 15, and the sense amplifier module 16 based on the instruction CMD stored in the instruction register 11. For example, the sequencer 13 performs read operations, write operations, and erase operations.

[0112] Driver module 14 is a circuit that generates the voltages used in read, write, and erase operations. For example, driver module 14 applies the generated voltages to the signal lines corresponding to the select word lines based on the page address PAd stored in address register 12.

[0113] The line decoder module 15 is a circuit that selects a block BLK within the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. For example, the line decoder module 15 transmits the voltage applied to the signal line corresponding to the selection word line to the selection word line within the selected block BLK.

[0114] The sense amplifier module 16 is a circuit that selects a bit line based on the column address CAd stored in the address register 12. For example, during a write operation, the sense amplifier module 16 applies a voltage based on the write data DAT received from the memory controller 2 to the selected bit line. Additionally, during a read operation, the sense amplifier module 16 determines the data stored in the memory cell transistor based on the voltage of the selected bit line. The sense amplifier module 16 then transmits the determination result as read data DAT to the memory controller 2.

[0115] 1.1.3 Circuit configuration of memory cell array

[0116] use Figure 2 The circuit configuration of the memory cell array 10 will be described. Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 10 included in the semiconductor memory device 3 of the first embodiment. Figure 2 The image shows one of the multiple block BLKs included in the storage cell array 10. The other block BLKs also have similar characteristics. Figure 2 Same composition. For example... Figure 2 As shown, a block BLK may contain, for example, five string components SU0 to SU4. String component SU is a set of NAND strings NS, which will be described later. For example, during a write or read operation, the NAND strings NS within the string component SU are selected together.

[0117] Each string component SU contains multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MT0 to MT10, and select transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage layer, and stores data non-volatilely. Select transistors ST1 and ST2 are used to select the string component SU for various operations.

[0118] In each NAND string NS, memory cell transistors MT0 to MT10 are connected in series. The drain of select transistor ST1 is connected to the bit line BL that establishes the association. The source of select transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT10. The drain of select transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT10. The source of select transistor ST2 is connected to the source line SL.

[0119] Within the same block BLK, the control gates of memory cell transistors MT0 to MT10 are connected to word lines WL0 to WL10, respectively. The gates of select transistors ST1 within serial assemblies SU0 to SU4 are connected to select gate lines SGD0 to SGD4, respectively. The gate of select transistor ST2 within serial assemblies SU0 to SU4 is connected to select gate line SGS.

[0120] Each bit line BL0 to BLm is assigned a different column address CAd. Each bit line BL is shared by NAND strings NS that are assigned the same column address CAd across multiple blocks BLK. Word lines WL0 to WL10 are set in each block BLK. The source line SL is shared, for example, across multiple blocks BLK.

[0121] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string component SU is, for example, called a cell component CU. For instance, the storage capacity of a cell component CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell component CU can have a storage capacity of 2 pages or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0122] Furthermore, the circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, the number of string components SU contained in each BLK can be designed to be arbitrary. The number of memory cell transistors MT, and selection transistors ST1 and ST2 contained in each NAND string NS can each be designed to be arbitrary.

[0123] 1.1.4 Structure of Semiconductor Memory Devices

[0124] 1.1.4.1 Bonding Structure of Semiconductor Memory Devices

[0125] use Figure 3 A summary of the bonding structure of the semiconductor memory device 3 is provided. Figure 3 This is a perspective view showing the outline of the bonding structure of the semiconductor memory device 3 according to the first embodiment. Figure 3 As shown, the semiconductor memory device 3 has a structure (bonding structure) in which an array chip 100 is bonded to a circuit chip 200. The array chip 100 and the circuit chip 200 each include a plurality of bonding pads BP disposed on opposing surfaces. In the bonding structure, a bonding pad BP of the array chip 100 and a bonding pad BP of the circuit chip 200 are bonded together to form one bonding pad BP. In other words, a bonding pad BP is formed by bonding an electrode (conductor) constituting a bonding pad BP disposed on the array chip 100 to an electrode (conductor) constituting a bonding pad BP disposed on the circuit chip 200.

[0126] Hereinafter, the surfaces where the array chip 100 and the circuit chip 200 are bonded (bonding surfaces) are designated as the XY plane. The directions orthogonal to each other on the XY plane are designated as the X direction and the Y direction. The X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. Furthermore, the direction approximately perpendicular to the XY plane and extending from the circuit chip 200 toward the array chip 100 is designated as the Z1 direction. The direction approximately perpendicular to the XY plane and extending from the array chip 100 toward the circuit chip 200 is designated as the Z2 direction. Without specifying either the Z1 or Z2 direction, it is denoted as the Z direction.

[0127] 1.1.4.2 Planar Layout of Semiconductor Memory Devices

[0128] use Figure 4 The planar layout of the semiconductor memory device 3 will be described. Figure 4 This is a top view showing an example of the planar layout of the semiconductor memory device 3 according to the first embodiment. For example... Figure 4 As shown, the semiconductor memory device 3 (array chip 100 and circuit chip 200 each) includes, for example, a core region CR, a peripheral region PR, a wall region WR, and a notch region KR.

[0129] The core region CR is, for example, a rectangular area located near the center of the semiconductor substrate (not shown) of the semiconductor memory device 3. The core region CR may contain, for example, a memory cell array 10, an instruction register 11, an address register 12, a row decoder module 15, and a sense amplifier module 16.

[0130] The peripheral region PR is a square annular region that surrounds the core region CR. For example, a sequencer 13 and a driver module 14 are configured in the peripheral region PR. Additionally, contacts are configured in the peripheral region PR to connect external devices of the semiconductor memory device 3 to circuitry within the circuit chip 200.

[0131] The wall region WR is a square annular region that surrounds the outer perimeter of the outer region PR. At least one sealing part (not shown) is configured in the wall region WR to surround the outer perimeter of the outer region PR.

[0132] The notch region KR is a square annular region that surrounds the outer periphery of the wall region WR. The notch region KR is adjacent to the outermost periphery of the semiconductor memory device 3. Alignment marks used during the manufacturing of the semiconductor memory device 3 are, for example, placed in the notch region KR.

[0133] 1.1.4.3 Planar Layout of Storage Cell Array

[0134] use Figure 5 The planar layout of the storage cell array 10 is described. Figure 5 This is a top view showing an example of the planar layout of the memory cell array 10 in the core region CR of the semiconductor memory device 3 according to the first embodiment. Figure 5 The area corresponding to one block BLK contained in the storage cell array 10 is shown. For example... Figure 5 As shown, the memory cell array 10 includes, for example, two components SLT, multiple components SHE, component SLTv_L, component SLTv_M, and component SLTv_U. Additionally, the memory cell array 10 includes, for example, a memory region MA and a contact region CA arranged in the X direction. Furthermore, the interlayer insulating film is omitted.

[0135] Each component SLT has a portion extending along the X direction and is configured to span the memory region MA and the contact region CA. Two component SLTs are arranged in the Y direction. The end of each component SLT opposite to the memory region MA in the X direction is connected to component SLTv_U. Each component SLT breaks the stacked wiring (the select gate line SGS, word lines WL0 to WL10, and select gate line SGD, which are spaced apart from each other in the Z direction) that is adjacent to the component SLT. In each component SLT, a conductor LI with an insulating spacer SP on its sidewall is disposed in a manner that is insulated from these stacked wirings. In addition, each component SLT may also have a structure in which an insulator is embedded. In the memory cell array 10, the regions separated by component SLTs correspond to one block BLK.

[0136] In addition, each component SLT includes an upper component SLT_U, a middle component SLT_M, and a lower component SLT_L. The upper component SLT_U is positioned above the middle component SLT_M. The lower end of the upper component SLT_U connects to the upper end of the middle component SLT_M. The middle component SLT_M is positioned above the lower component SLT_L. The lower end of the middle component SLT_M connects to the upper end of the lower component SLT_L. The upper component SLT_U, middle component SLT_M, and lower component SLT_L span the storage region MA and the contact region CA. The end of the upper component SLT_U in the X direction opposite to the storage region MA connects to component SLTv_U. The end of the middle component SLT_M in the X direction opposite to the storage region MA connects to component SLTv_M. The lower component SLT_L is connected to component SLTv_L at the end opposite to the storage area MA in the X direction.

[0137] Each component SHE has a portion extending along the X direction and is configured to span the memory region MA and the contact region CA. Multiple component SHEs are arranged in the Y direction. The end of each component SHE opposite to the memory region MA in the X direction is connected to component SLTv_U. In this example, four component SHEs are arranged between each of two adjacent component SLTs in the Y direction. Each component SHE is separated by an adjacent wiring (at least the select gate line SGD). Each component SHE, for example, has a structure with embedded insulators. In the memory cell array 10, the regions separated by component SLTs and SHEs each correspond to one string assembly SU.

[0138] Components SLTv_L, SLTv_M, and SLTv_U are configured in contact area CA. Starting from the storage area MA side, components SLTv_L, SLTv_M, and SLTv_U are configured in the following order: SLTv_L, SLTv_M, and SLTv_U. Component SLTv_U is positioned above component SLTv_M. Component SLTv_M is positioned above component SLTv_L.

[0139] Component SLTv_L has a portion extending along the Y direction. Component SLTv_L is connected to the lower component SLT_L of each component SLT on the storage region MA side. Component SLTv_L divides adjacent blocks BLK in the Y direction. Component SLTv_L has, for example, a structure with embedded insulators.

[0140] Component SLTv_M has a portion extending along the Y direction. Component SLTv_M is connected to the middle component SLT_M of each component SLT on the storage region MA side. Component SLTv_M divides adjacent blocks BLK in the Y direction. Component SLTv_M, for example, has a structure with embedded insulators.

[0141] Component SLTv_U has a portion extending along the Y direction. Component SLTv_U is connected to the upper component SLT_U of each component SLT and to each component SHE on the storage region MA side. That is, the ends of component SLTv_U and each component SLT opposite to the storage region MA in the X direction, and the ends of each component SHE opposite to the storage region MA in the X direction, are connected to each other. Component SLTv_U divides adjacent blocks BLK in the Y direction. Component SLTv_U, for example, has a structure with embedded insulators.

[0142] Hereinafter, without distinguishing between components SLTv_L, SLTv_M, and SLTv_U, they will be abbreviated as "component SLTv". Alternatively, components SLTv_L, SLTv_M, and SLTv_U can be abbreviated as "segment DP_L", "segment DP_M", and "segment DP_U", respectively.

[0143] In addition, other block BLKs also have the same Figure 5 The same construction. In the case where the storage cell array 10 contains multiple block BLKs, for example, it is repeatedly configured in the Y direction. Figure 5 The structure shown.

[0144] The planar layout of the memory cell array 10 included in the semiconductor memory device 3 can also be other layouts. For example, the number of components SHEs arranged between two adjacent components SLTs can be designed to be arbitrary. The number of string components SUs included in each BLK can be varied based on the number of components SHEs arranged between two adjacent components SLTs. The number of components SLTv only needs to be two or more and can be varied according to the construction of the memory cell array 10.

[0145] 1.1.4.4 Planar Layout of Storage Areas

[0146] Next, refer to Figure 5 The planar layout of the storage region MA is described. For example... Figure 5 As shown, the semiconductor memory device 3 includes, for example, multiple memory pillars MP, multiple contacts CV, and multiple bit lines BL in the memory region MA.

[0147] Each memory column (MP) functions as a NAND string (NS). Multiple memory columns (MP) are arranged in a staggered 24-column configuration in the area between two adjacent components (SLT). For example, the 5th, 10th, 15th, and 20th memory columns (MP) from the side of the paper are each arranged in an overlapping configuration of one component (SHE).

[0148] Each bit line BL has a portion extending along the Y direction. Multiple bit lines BL are arranged in the X direction. Each bit line BL in each string assembly SU is configured to overlap with at least one memory column MP. In this example, two bit lines BL are overlapped with one memory column MP. The memory column MP is electrically connected to one of the overlapping bit lines BL via a contact CV. Furthermore, the contact CV between the memory column MP and the bit line BL, which is connected to two different select gate lines SGD, can be omitted.

[0149] Furthermore, the planar layout of the memory region MA in the memory cell array 10 included in the semiconductor memory device 3 can also be other layouts. For example, the number and arrangement of memory pillars MP, components SHE, etc., arranged between two adjacent components SLT can be appropriately changed. The number of bit lines BL overlapping each memory pillar MP can be designed to be arbitrary.

[0150] 1.1.4.5 Planar layout of the contact area

[0151] Next, refer to Figure 5 The planar layout of the contact area CA is described. For example... Figure 5 As shown, the storage cell array 10 includes, for example, multiple contacts CC and multiple support pillars HR in the contact area CA.

[0152] The contact CC electrically connects the select gate line SGS, word lines WL0 to WL10, and select gate line SGD to the wiring disposed above the memory cell array 10. The contact CC has, for example, a circular cross-sectional shape in the XY plane.

[0153] Contacts CC are configured in the contact area CA, excluding components SLT, SHE, and SLTv. In this example, five contacts CC are arranged in the Y direction near the memory area MA. These five contacts CC are respectively configured between components SLT and SHE and between two components SHE, that is, in the areas corresponding to string components SU0 to SU4. These five contacts CC are connected, for example, to the select gate line SGD.

[0154] In the area corresponding to string component SU1, six additional contacts CC are configured besides the contacts CC near storage region MA. Between the contacts CC near storage region MA and component SLTv_L, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to word line WL0 and word line WL2, for example, starting from the storage region MA side. Between component SLTv_L and component SLTv_M, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to word line WL4 and word line WL6, for example, starting from the storage region MA side. Between component SLTv_M and component SLTv_U, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to word line WL8 and word line WL10, for example, starting from the storage region MA side.

[0155] In the region corresponding to string component SU3, six additional contacts CC are configured besides the contacts CC near memory region MA. Between the contacts CC near memory region MA and component SLTv_L, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to select gate line SGS and word line WL1, for example, starting from the memory region MA side. Between component SLTv_L and component SLTv_M, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to word line WL3 and word line WL5, for example, starting from the memory region MA side. Between component SLTv_M and component SLTv_U, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to word line WL7 and word line WL9, for example, starting from the memory region MA side.

[0156] Additionally, the contact CC includes a conductor 50 and an insulator 51. The conductor 50 is connected to any one of the select gate line SGS, word lines WL0 to WL10, and select gate line SGD. The conductor 50 contains, for example, tungsten. The insulator 51 covers the side of the conductor 50. The insulator 51 contains, for example, silicon oxide.

[0157] The support pillars HR are insulators that penetrate the laminated wiring. For example, during the manufacturing process, the support pillars HR function as pillars supporting the interlayer insulating film when gaps are formed in areas corresponding to the laminated wiring. The support pillars HR have, for example, a circular cross-sectional shape in the XY plane. The support pillars HR are appropriately positioned in the contact area CA, excluding components SLT, SHE, and SLTv, and the area of ​​contact CC. In this example, nine support pillars HR are positioned in the area corresponding to string assembly SU0. Three support pillars HR are arranged in the X direction between contact CC near storage area MA and component SLTv_L. Three support pillars HR are arranged in the X direction between component SLTv_L and component SLTv_M. Three support pillars HR are arranged in the X direction between component SLTv_M and component SLTv_U. Nine support pillars HR are also positioned in the areas corresponding to string assembly SU2 and string assembly SU4. The support pillars HR contain, for example, silicon oxide.

[0158] Furthermore, the planar layout of the contact area CA of the memory cell array 10 included in the semiconductor memory device 3 can also be other layouts. For example, the number and configuration of the contacts CC and the support pillars HR can be appropriately changed.

[0159] 1.1.4.6 Cross-sectional structure of the storage area

[0160] use Figure 6 The cross-sectional structure of the storage region MA is described. Figure 6 This is an example of a cross-sectional structure along the memory region MA of the memory cell array 10 included in the semiconductor memory device 3 of the first embodiment. Figure 5 A sectional view along line VI-VI. (See example...) Figure 6 As shown, the memory cell array 10 also includes wiring layers 20-28, insulating layers 40-43, 43' and 44-48, and multiple contacts CV, V1 and V2 in the memory region MA. In the following description, the Z2 direction is defined as upward and the Z1 direction as downward.

[0161] The memory cell array 10 includes a lower stack L_SB, a middle stack M_SB, and an upper stack U_SB. The lower stack L_SB includes a wiring layer 22 corresponding to the select gate line SGS and multiple wiring layers 23 corresponding to word lines WL0 to WL2. The middle stack M_SB is positioned above the lower stack L_SB and includes multiple wiring layers 20 corresponding to word lines WL3 to WL6. The upper stack U_SB is positioned above the middle stack M_SB and includes multiple wiring layers 24 corresponding to word lines WL7 to WL10 and a wiring layer 25 corresponding to the select gate line SGD.

[0162] A wiring layer 21 is disposed above a semiconductor substrate W2 (not shown). The wiring layer 21 is formed, for example, as a plate extending in the X direction in the XY plane. The wiring layer 21 is used as a source line SL. The wiring layer 21 contains, for example, phosphorus-doped silicon.

[0163] An insulating layer 41 and a wiring layer 22 are sequentially stacked on top of the wiring layer 21. The insulating layer 41 contains, for example, silicon oxide (SiO2). The wiring layer 22 is formed, for example, as a plate extending in the X direction in the XY plane. The wiring layer 22 is used as the select gate line (SGS). The wiring layer 22 contains, for example, tungsten.

[0164] Insulating layers 42 and 23 are alternately stacked on top of wiring layer 22. Insulating layer 42 contains, for example, silicon oxide. Wiring layer 23 is formed, for example, as a plate extending in the X direction in the XY plane. Wiring layer 23 is used as word lines WL0 to WL2 sequentially from the wiring layer 22 side. Wiring layer 23 contains, for example, tungsten.

[0165] An insulating layer 43 is disposed above the uppermost insulating layer 42. The insulating layer 43 may contain, for example, TEOS (Tetraethoxysilane). Wiring layers 20 and insulating layers 40 are alternately layered on the insulating layer 43. The wiring layers 20 are, for example, formed as a plate extending in the X direction in the XY plane. The wiring layers 20, starting from the insulating layer 43 side, are sequentially used as word lines WL3 to WL6. The wiring layers 20 may contain, for example, tungsten. The insulating layer 40 may contain, for example, silicon oxide.

[0166] An insulating layer 43' is disposed above the uppermost insulating layer 40. The insulating layer 43' may contain, for example, TEOS. Above the insulating layer 43', wiring layers 24 and insulating layers 44 are alternately stacked. The wiring layers 24 are, for example, formed as a plate extending in the X direction in the XY plane. The wiring layers 24, starting from the insulating layer 43' side, are sequentially used as word lines WL7 to WL10. The wiring layers 24 may contain, for example, tungsten. The insulating layers 44 may contain, for example, silicon oxide.

[0167] Above the top insulating layer 44, a wiring layer 25, an insulating layer 45, and an insulating layer 46 are stacked sequentially. The wiring layer 25 is, for example, formed as a plate extending in the X direction in the XY plane. The wiring layer 25 is used as the select gate line (SGD). The wiring layer 25 contains, for example, tungsten. The insulating layers 45 and 46 contain, for example, silicon oxide.

[0168] A wiring layer 26 is disposed on the insulating layer 46. The wiring layer 26 is formed, for example, as a line extending in the Y direction. The wiring layer 26 is used as a bit line BL. In areas not shown, multiple wiring layers 26 are arranged along the X direction. The wiring layer 26 contains, for example, copper.

[0169] A wiring layer 27 is disposed above wiring layer 26. Wiring layer 27 is the wiring connecting the relay bit line BL to the sense amplifier module 16. Wiring layer 26 and wiring layer 27 are connected via contact V1. A wiring layer 28 is disposed above wiring layer 27. Wiring layer 28 corresponds to the bonding pad BP for bonding. Wiring layer 27 and wiring layer 28 are connected via contact V2. The sides of wiring layer 27, and contacts V1 and V2, are each covered by an insulating layer 47. The insulating layer 47 may be composed of multiple insulating films. The sides of wiring layer 28 are covered by an insulating layer 48. The memory cell array 10 may include multiple wiring layers 27 and multiple wiring layers 28. Wiring layers 27 and 28, for example, contain copper.

[0170] The memory pillars MP extend along the Z-direction and are, for example, cylindrical in shape. Each memory pillar MP includes a lower pillar MP_L, a middle pillar MP_M, and an upper pillar MP_U. The lower pillar MP_L extends through wiring layer 22 and multiple wiring layers 23 in the Z-direction. The middle pillar MP_M extends through multiple wiring layers 20 in the Z-direction. The upper pillar MP_U extends through multiple wiring layers 24 and wiring layers 25 in the Z-direction. The upper end of the lower pillar MP_L and the lower end of the middle pillar MP_M are connected at the boundary surface of insulating layer 42 and insulating layer 43. The upper end of the middle pillar MP_M and the lower end of the upper pillar MP_U are connected at the boundary surface of insulating layer 40 and insulating layer 43'. For example, the cross-sectional area (XY cross-sectional area) of each of the lower pillar MP_L, middle pillar MP_M, and upper pillar MP_U along the XY plane increases from bottom to top. At the junction of the lower pillar MP_L and the middle pillar MP_M, the side surface of the lower pillar MP_L is offset from the side surface of the middle pillar MP_M. At the junction of the middle pillar MP_M and the upper pillar MP_U, the side surface of the middle pillar MP_M is offset from the side surface of the upper pillar MP_U. Alternatively, the side surface of the lower pillar MP_L and the side surface of the middle pillar MP_M may not be offset from each other. The side surface of the middle pillar MP_M and the side surface of the upper pillar MP_U may also not be offset from each other.

[0171] Additionally, the memory column MP includes, for example, a core film 30, a semiconductor film 31, and a laminated film 32. The core film 30 extends along the Z direction. For example, the upper end of the core film 30 is located within the insulating layer 46, and the lower end of the core film 30 is located within the wiring layer 21. The core film 30 contains, for example, an insulator such as silicon oxide. The semiconductor film 31 covers, for example, the area surrounding the core film 30. At the lower end of the memory column MP, a portion of the semiconductor film 31 contacts the wiring layer 21. The semiconductor film 31 contains, for example, silicon. The laminated film 32 covers the side and bottom surfaces of the semiconductor film 31, except for the portion where the semiconductor film 31 contacts the wiring layer 21.

[0172] exist Figure 6 In the structure of the memory pillar MP shown, the portion where the memory pillar MP intersects with wiring layer 22 functions as selection transistor ST2. The portions where the memory pillar MP intersects with wiring layers 23, 20, and 24 function as memory cell transistors MT0 to MT10, respectively. The portion where the memory pillar MP intersects with wiring layer 25 functions as selection transistor ST1.

[0173] A columnar contact CV is formed on the upper surface of the semiconductor film 31 within the memory column MP. Figure 6 The area shown illustrates two contacts CV corresponding to two of the six memory pillars MP. For memory pillars MP that do not overlap with component SHE in this area and are not connected to contact CV, other contact CVs are connected in an area not shown.

[0174] One wiring layer 26, i.e., one bit line BL, contacts the upper surface of each contact CV. Within one wiring layer 26, one contact CV is connected in each space separated by components SLT and SHE. That is, within each wiring layer 26, for example, one memory column MP in each region between adjacent components SLT and SHE is electrically connected to one memory column MP in each region between two adjacent components SHE.

[0175] Component SLT is formed, for example, to extend along the XZ plane. Lower component SLT_L extends along the Z and X directions and divides wiring layer 22 and multiple wiring layers 23 in the Y direction. Middle component SLT_M extends along the Z and X directions and divides multiple wiring layers 20 in the Y direction. Upper component SLT_U extends along the Z and X directions and divides multiple wiring layers 24 and wiring layers 25 in the Y direction. The upper end of lower component SLT_L and the lower end of middle component SLT_M are connected at the boundary surface of insulating layer 42 and insulating layer 43. The upper end of middle component SLT_M and the lower end of upper component SLT_U are connected at the boundary surface of insulating layer 40 and insulating layer 43'. For example, the cross-sectional area (XY cross-sectional area) of each of the lower component SLT_L, middle component SLT_M, and upper component SLT_U along the XY plane increases from bottom to top. At the junction of the lower component SLT_L and the middle component SLT_M, the side surface of the lower component SLT_L is offset from the side surface of the middle component SLT_M. At the junction of the middle component SLT_M and the upper component SLT_U, the side surface of the middle component SLT_M is offset from the side surface of the upper component SLT_U.

[0176] Within component SLT, contacts LI are configured to extend along the XZ plane, and spacers SP are disposed between contacts LI and wiring layers 20 and 22-25. The upper end of contacts LI is located, for example, within insulating layer 46. The lower end of contacts LI is located, for example, within wiring layer 21. Spacers SP contain, for example, silicon oxide. Contacts LI contain, for example, tungsten. Alternatively, contacts LI may be omitted depending on the configuration of the memory cell array 10.

[0177] The component SHE is formed, for example, as a plate extending along the XZ plane, and the wiring layer 25 is divided in the Y direction. The upper end of the component SHE is located within the insulating layer 46. The lower end of the component SHE is located, for example, within the uppermost insulating layer 44. The component SHE contains, for example, an insulator such as silicon oxide. Furthermore, the upper end of the component SHE may or may not be aligned with the upper end of the component SLT. Additionally, the upper end of the component SHE may or may not be aligned with the upper end of the memory cylinder MP.

[0178] 1.1.4.7 Cross-sectional structure of memory cylinders

[0179] use Figure 7 The cross-sectional structure of the memory cylinder MP is described. Figure 7 This is an example of the cross-sectional structure of the memory pillar MP included in the semiconductor memory device 3 of the first embodiment, along... Figure 6 A sectional view along line VII-VII. More specifically, Figure 7 This indicates the cross-sectional structure of the memory pillar MP in the layer containing wiring layer 23. For example... Figure 7As shown, the laminated film 32 includes, for example, a tunnel insulating film 33, an insulating film 34, and a barrier insulating film 35. The tunnel insulating film 33 surrounds the sides of the semiconductor film 31. The insulating film 34 surrounds the sides of the tunnel insulating film 33. The barrier insulating film 35 surrounds the sides of the insulating film 34. The wiring layer 23 surrounds the sides of the barrier insulating film 35. The tunnel insulating film 33 and the barrier insulating film 35, for example, each contain silicon oxide. The insulating film 34 is used as a charge storage layer for the memory cell transistor MT. The insulating film 34, for example, contains silicon nitride (SiN).

[0180] 1.1.4.8 Cross-sectional structure of the contact area

[0181] use Figure 8 and Figure 9 The cross-sectional structure of the contact area CA is described. Figure 8 This is an example of the cross-sectional structure of the contact region CA of the memory cell array 10 included in the semiconductor memory device 3 of the first embodiment, along... Figure 5 A cross-sectional view of line VIII-VIII. Figure 8 The cross-sectional structure of the storage region MA near the contact area CA is also shown. The cross-sectional structure of the storage region MA is similar to... Figure 6 Same. For example... Figure 8 As shown, the memory cell array 10 also includes wiring layers 20-28, insulating layers 40-43, 43', 44-48 and 60-64, and multiple contacts VY, V1 and V2 in the contact area CA. In the following description, the Z2 direction is defined as upward and the Z1 direction as downward.

[0182] The lower laminate L_SB further includes an insulating layer 61 and multiple insulating layers 62 disposed on the same layer as wiring layer 22 and multiple wiring layers 23. The middle laminate M_SB further includes multiple insulating layers 60 disposed on the same layer as multiple wiring layers 20. The upper laminate U_SB further includes multiple insulating layers 63 and multiple insulating layers 64 disposed on the same layer as multiple wiring layers 24 and wiring layers 25.

[0183] The contacts CC extend along the Z direction and are, for example, cylindrical in shape. Multiple contacts CC are respectively disposed on the select gate line SGS, word lines WL0 to WL10, and select gate line SGD.

[0184] First, the contacts CC (hereinafter referred to as "lower layer wiring contacts CC") located on the select gate line SGS and word lines WL0 to WL2 will be explained. The lower layer wiring contacts CC include the lower contact CC_L, the middle contact CC_M, and the upper contact CC_U.

[0185] The lower contact CC_L extends along the Z-direction and connects to any one of the wiring layers 22 and multiple wiring layers 23. In other words, the lower contact CC_L penetrates the wiring layer 23 and the insulating layer 42 above the wiring layer (select gate line SGS and word lines WL0 to WL2) to which the contact CC is connected. The lower contact CC_L includes a conductor 50 and an insulator 51 covering at least a portion of the side surface of the conductor 50. The middle contact CC_M is disposed above the lower contact CC_L and penetrates multiple wiring layers 20 and insulating layers 43 and multiple insulating layers 40 in the Z-direction. The upper end of the lower contact CC_L and the lower end of the middle contact CC_M are connected at the boundary surface of the insulating layer 42 and the insulating layer 43. The middle contact CC_M includes a conductor 50 and an insulator 51 covering the side surface of the conductor 50. The upper contact CC_U is disposed above the middle contact CC_M and extends through multiple wiring layers 24 and 25, and through insulating layers 43', 44, and 45 in the Z direction. The upper end of the middle contact CC_M and the lower end of the upper contact CC_U are connected at the boundary surface of insulating layers 40 and 43'. The upper contact CC_U includes a conductor 50 and an insulator 51 covering at least a portion of the side surface of the conductor 50.

[0186] The upper end of conductor 50 is located within insulating layer 46, and the lower end of conductor 50 is connected to the wiring layer to which conductor 50 is connected. The upper end of insulator 51 is located within insulating layer 46 at a lower position than the upper end of conductor 50, and the lower end of insulator 51 is connected to insulating layer 42 above the wiring layer to which conductor 50 is connected. In other words, insulator 51 covers the side surface of conductor 50 except for the upper and lower parts of conductor 50.

[0187] As described above, the lower wiring contact CC extends along the Z direction and penetrates the middle stack M_SB (multiple wiring layers 20) and the upper stack U_SB (multiple wiring layers 24 and wiring layer 25), connects to any of the wiring layers 22 and multiple wiring layers 23, and at least a portion of its side surface is covered by an insulator 51.

[0188] Next, the contacts CC (hereinafter referred to as "middle layer wiring contacts CC") installed on each of the word lines WL3 to WL6 will be explained. The middle layer wiring contacts CC include the middle contact CC_M and the upper contact CC_U.

[0189] The middle contact CC_M extends along the Z-direction and connects to any one of the multiple wiring layers 20. In other words, the middle contact CC_M penetrates the wiring layer 20 above the wiring layer (word lines WL3 to WL6) to which the contact CC is connected, and the insulating layer 40. The middle contact CC_M includes a conductor 50 and an insulator 51 covering at least a portion of the side surface of the conductor 50. The upper contact CC_U is disposed above the middle contact CC_M and penetrates the multiple wiring layers 24 and 25, and the insulating layer 43', multiple insulating layers 44 and 45 in the Z-direction. The upper end of the middle contact CC_M and the lower end of the upper contact CC_U are connected at the boundary surface of the insulating layer 40 and the insulating layer 43'. The upper contact CC_U includes a conductor 50 and an insulator 51 covering at least a portion of the side surface of the conductor 50.

[0190] The upper end of conductor 50 is located within insulating layer 46, and the lower end of conductor 50 is connected to the wiring layer to which conductor 50 is connected. The upper end of insulator 51 is located within insulating layer 46 at a lower position than the upper end of conductor 50, and the lower end of insulator 51 is connected to insulating layer 40 above the wiring layer to which conductor 50 is connected. In other words, insulator 51 covers the side surface of conductor 50 except for the upper and lower parts of conductor 50.

[0191] As described above, the middle layer wiring contact CC extends along the Z direction and penetrates the upper stack U_SB (multiple wiring layers 24 and wiring layers 25), is connected to any of the multiple wiring layers 20, and at least a portion of its side is covered by an insulator 51.

[0192] Next, the contacts CC (hereinafter referred to as "upper layer wiring contacts CC") located on word lines WL7 to WL10 and select gate line SGD will be described. The upper layer wiring contacts CC each include the upper contact CC_U.

[0193] The upper contact CC_U extends along the Z direction and is connected to any one of the multiple wiring layers 24 and 25. In other words, the upper contact CC_U corresponding to word lines WL7 to WL10 passes through wiring layers 24 and 25 above the wiring layer to which contact CC is connected, and insulating layers 44 and 45. The upper contact CC_U corresponding to the select gate line SGD passes through the insulating layer 45 above the select gate line SGD. The upper contact CC_U includes a conductor 50 and an insulator 51 covering at least a portion of the side surface of the conductor 50.

[0194] The upper end of conductor 50 is located within insulating layer 46, and the lower end of conductor 50 is connected to the wiring layer to which conductor 50 is connected. The upper end of insulator 51 is located within insulating layer 46 at a lower position than the upper end of conductor 50, and the lower end of insulator 51 is connected to insulating layer 44 or 45 above the wiring layer to which conductor 50 is connected. In other words, insulator 51 covers the side surface of conductor 50 except for the upper and lower parts of conductor 50.

[0195] As described above, the upper wiring contact CC extends along the Z direction and is connected to any of the multiple wiring layers 24 and 25, and at least a portion of its side is covered by an insulator 51.

[0196] For example, the cross-sectional area (XY cross-sectional area) of the lower contact CC_L and the middle contact CC_M along the XY plane increases from bottom to top. Similarly, the portion of the upper contact CC_U located lower than the portion of the upper conductor 50 not covered by the insulator 51 also increases from bottom to top along the XY plane. The portion of the upper conductor 50 in the upper contact CC_U not covered by the insulator 51 also increases from bottom to top along the XY plane. At the junction of the lower contact CC_L and the middle contact CC_M, the side surface of the lower contact CC_L is offset from the side surface of the middle contact CC_M. At the junction of the middle contact CC_M and the upper contact CC_U, the side surface of the middle contact CC_M is offset from the side surface of the upper contact CC_U.

[0197] Components SLTv_L (splitting section DP_L), SLTv_M (splitting section DP_M), and SLTv_U (splitting section DP_U) are, for example, formed to extend along the YZ plane. Component SLTv_L extends along the Z and Y directions and splits wiring layer 22 and multiple wiring layers 23 in the X direction. The upper end of component SLTv_L is, for example, at the same position as the boundary surface of insulating layer 42 and insulating layer 43. The lower end of component SLTv_L is, for example, located within wiring layer 21. Component SLTv_M extends along the Z and Y directions and splits multiple wiring layers 20 in the X direction. The upper end of component SLTv_M is, for example, at the same position as the boundary surface of insulating layer 40 and insulating layer 43'. The lower end of component SLTv_M is, for example, at the same position as the boundary surface of insulating layer 42 and insulating layer 43. Component SLTv_U extends along the Z and Y directions and divides multiple wiring layers 24 and 25 in the X direction. The upper end of component SLTv_U is located, for example, within insulating layer 46. The lower end of component SLTv_U is located, for example, at the same position as the boundary surface of insulating layers 40 and 43'. For example, the cross-sectional area (XY cross-sectional area) of components SLTv_L, SLTv_M, and SLTv_U along the XY plane increases from bottom to top. Components SLTv_L, SLTv_M, and SLTv_U, for example, each contain silicon oxide.

[0198] Component SLTv_L is positioned closer to memory cylinder MP than component SLTv_M. Component SLTv_M is positioned closer to memory cylinder MP than component SLTv_U. In other words, component SLTv_U does not overlap with components SLTv_L and SLTv_M in the Z direction, and component SLTv_M does not overlap with component SLTv_L in the Z direction.

[0199] The lower-layer wiring contact CC and the upper-layer wiring contact CC connected to the select gate line SGD are configured in the region between the memory cylinder MP and component SLTv_L. The middle-layer wiring contact CC is configured in the region between component SLTv_L and component SLTv_M. All upper-layer wiring contacts CC except those connected to the select gate line SGD are configured in the region between component SLTv_M and component SLTv_U.

[0200] Insulator layer 61 and multiple insulating layers 62 are disposed at a position further away from memory cylinder MP than component SLTv_L. In other words, component SLTv_L is disposed closer to memory cylinder MP than insulating layer 61 and multiple insulating layers 62. In the region further away from memory cylinder MP than component SLTv_L, insulating layer 41 and insulating layer 61 are sequentially stacked on wiring layer 21. Insulator layer 61 and wiring layer 22 are disposed on the same layer. Insulator layer 42 and insulating layer 62 are alternately stacked on insulating layer 61. Each of multiple insulating layers 62 is disposed on the same layer as each of multiple wiring layers 23. Insulator layer 61 and multiple insulating layers 62 are respectively connected to wiring layer 22 and multiple wiring layers 23 at a position further away from memory cylinder MP than component SLTv_L. In other words, in a region further away from the memory cylinder MP than component SLTv_L, the lower stack L_SB includes wiring layer 22 and multiple wiring layers 23, as well as insulating layer 61 and multiple insulating layers 62. Insulating layers 61 and 62 contain, for example, silicon nitride.

[0201] Multiple insulating layers 60 are disposed at a location further away from the memory cylinder MP than component SLTv_M. In other words, component SLTv_M is disposed closer to the memory cylinder MP than the multiple insulating layers 60. Furthermore, component SLTv_M is disposed above insulating layer 61 and multiple insulating layers 62. In a region further away from the memory cylinder MP than component SLTv_M, insulating layer 43 is stacked on top of the uppermost insulating layer 42. Insulating layers 60 and 40 are alternately stacked on insulating layer 43. Each of the multiple insulating layers 60 is disposed on the same layer as each of the multiple wiring layers 20. The multiple insulating layers 60 are respectively connected to each of the multiple wiring layers 20 at a location further away from the memory cylinder MP than component SLTv_M. In other words, in a region further away from the memory cylinder MP than component SLTv_M, the middle stack M_SB includes multiple wiring layers 20 and multiple insulating layers 60. Insulating layer 60 contains, for example, silicon nitride.

[0202] Multiple insulating layers 63 and 64 are disposed further away from the memory cylinder MP than component SLTv_U. In other words, component SLTv_U is disposed closer to the memory cylinder MP than multiple insulating layers 63 and 64. Furthermore, component SLTv_U is disposed above multiple insulating layers 60. In the region further away from the memory cylinder MP than component SLTv_U, insulating layer 43' is stacked above the uppermost insulating layer 40. Insulating layers 63 and 44 are alternately stacked above insulating layer 43'. Each of the multiple insulating layers 63 and each of the multiple wiring layers 24 are disposed on the same layer. Above the uppermost insulating layer 44, insulating layers 64, 45, and 46 are stacked sequentially. Insulating layer 64 and wiring layer 25 are disposed on the same layer. Multiple insulating layers 63 and 64 are respectively connected to multiple wiring layers 24 and 25 at locations further away from the memory cylinder MP than component SLTv_U. In other words, in a region further away from the memory cylinder MP than component SLTv_U, the upper stack U_SB includes multiple wiring layers 24 and 25, and multiple insulating layers 63 and 64. Insulating layers 63 and 64, for example, contain silicon nitride.

[0203] A contact VY is provided above each of the multiple contacts CC (multiple conductors 50). That is, contact VY is connected to the upper end of each of the lower layer wiring contacts CC. Contact VY is connected to the upper end of each of the middle layer wiring contacts CC. Contact VY is connected to the upper end of each of the upper layer wiring contacts CC. A wiring layer 26 is provided above each of the multiple contacts VY. A contact V1 is provided on each wiring layer 26. Figure 8 The diagram shows only the contact V1 corresponding to the word line WL5 among multiple contacts V1. A wiring layer 27 is disposed above contact V1. A contact V2 is disposed above wiring layer 27. Wiring layers 26 and 27, along with contacts V1 and V2, are covered by an insulating layer 47. A wiring layer 28 is disposed above contact V2, penetrating the insulating layer 48.

[0204] Here, the distance from the upper end of the lower layer wiring contact CC to the lower end of the lower layer wiring contact CC connected to the wiring layer is defined as "distance DLla", and the distance from the lower end of the lower layer wiring contact CC to the memory cylinder MP is defined as "distance DLb". The distance from the upper end of the middle layer wiring contact CC to the lower end of the middle layer wiring contact CC connected to the wiring layer is defined as "distance DMa", and the distance from the lower end of the middle layer wiring contact CC to the memory cylinder MP is defined as "distance DMb". The distance from the upper end of the upper layer wiring contact CC to the lower end of the upper layer wiring contact CC connected to the wiring layer is defined as "distance DUa", and the distance from the lower end of the upper layer wiring contact CC to the memory cylinder MP is defined as "distance DUb". The sum of distance DLla and distance DLb, the sum of distance DMa and distance DMb, and the sum of distance DUa and distance DUb are averaged.

[0205] The wiring layers 26, 27, and 28 described above, along with the groups of contacts CC, VY, V1, and V2, correspond to the wiring and contacts used to connect any of the wiring layers 20 and 22-25 to the line decoder module 15. Although the illustrations are omitted, wiring layers 20 and 22-25, except for the word line WL5, are also connected to the line decoder module 15 via the wiring layers 26, 27, and 28 and the groups of contacts CC, VY, V1, and V2.

[0206] Figure 9 This is an example of the cross-sectional structure of the contact region CA of the memory cell array 10 included in the semiconductor memory device 3 of the first embodiment, along... Figure 5 A cross-sectional view of the IX-IX line. Figure 9 The diagram also shows the cross-sectional structure of the storage region MA near the contact area CA. (See diagram for example.) Figure 9 As shown, the cross-sectional structures of the regions in contact area CA that are farther from storage area MA than component SLTv_L, the regions that are farther from storage area MA than component SLTv_M, and the regions that are farther from storage area MA than component SLTv_U are shown in the figure. Figure 8 same.

[0207] In the contact area CA, in the region closer to the storage area MA than component SLTv, the lower component SLT_L is connected to component SLTv_L and passes through wiring layer 22 and multiple wiring layers 23. The upper end of the lower component SLT_L is, for example, at the same position as the upper end of component SLTv_L. The lower end of the lower component SLT_L is, for example, at the same position as the lower end of component SLTv_L. The middle component SLT_M is connected to component SLTv_M and passes through multiple wiring layers 20. The upper end of the middle component SLT_M is, for example, at the same position as the upper end of component SLTv_M. The lower end of the middle component SLT_M is, for example, at the same position as the lower end of component SLTv_M. The upper component SLT_U is connected to component SLTv_U and passes through multiple wiring layers 24 and wiring layer 25. The upper end of the upper component SLT_U is, for example, at the same position as the upper end of component SLTv_U. The lower end of the upper component SLT_U is located at the same position as the lower end of component SLTv_U. The cross-sectional structure in the storage region MA also has the same structure.

[0208] In addition, component SLTv_L can also be positioned directly below the middle layer wiring contact CC. Component SLTv_M can also be positioned directly below the upper layer wiring contact CC.

[0209] 1.2 Manufacturing method of semiconductor memory device

[0210] use Figures 10 to 37 The manufacturing method of the semiconductor memory device 3 according to the first embodiment will be described. Figures 10-15 , Figure 17 , Figure 18 , Figure 20 , Figure 21 , Figure 23 , Figure 24 , Figure 26 , Figure 27 , Figures 29-32 and Figures 34-36 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3 during manufacturing according to the first embodiment. Figures 10-14 , Figure 17 , Figure 20 , Figure 23 , Figure 26 , Figure 29 , Figure 31 and Figures 34-36 It corresponds to Figure 8 The cross-sectional structure. Figure 15 , Figure 18 , Figure 21 , Figure 24 , Figure 27 , Figure 30 and Figure 32 It corresponds to Figure 9 The cross-sectional structure. Figure 16 , Figure 19 , Figure 22 , Figure 25 , Figure 28 , Figure 33 and Figure 37 This is a top view showing an example of the planar structure of the semiconductor memory device 3 during manufacturing according to the first embodiment. Figure 16 , Figure 19 , Figure 22 , Figure 25 , Figure 28 , Figure 33 and Figure 37 The interlayer insulation film is omitted in the original text. The following description of the formation steps for the support column HR is also omitted.

[0211] In this embodiment, as a method for forming wiring layers 20 and 22-25 corresponding to each of the select gate line SGS, word lines WL0 to WL10, and select gate line SGD, the following method will be described: for example, after forming structures corresponding to each wiring layer 22, 23, 20, 24, and 25 from insulating layers 61, 62, 60, 63, and 64, respectively, the insulating layers 61, 62, 60, 63, and 64 are replaced with conductive materials to form each wiring layer 22, 23, 20, 24, and 25 (hereinafter referred to as "replacement"). Hereinafter, insulating layers 60 to 64 will also be referred to as "sacrificial components 60 to 64".

[0212] First, such as Figure 10 As shown, a wiring layer 21, an insulating layer 41, and a sacrificial member 61 are sequentially stacked on a semiconductor substrate W2. Next, four insulating layers 42 and three sacrificial member layers 62 are alternately stacked on the sacrificial member 61. The wiring layer 21 contains, for example, polysilicon. Insulating layers 41 and 42 contain, for example, silicon oxide. Sacrificial members 61 and 62 contain, for example, silicon nitride. Next, although not shown, a hole corresponding to the lower pillar MP_L is provided, in which the sacrificial member is embedded.

[0213] Next, as Figure 10 As shown, a hole CH_L corresponding to the lower contact CC_L is provided. For example, a mask with an opening in the area corresponding to the hole CH_L is formed by photolithography or the like, and the hole CH_L is formed by anisotropic etching of the mask. The lower end of the hole CH_L corresponding to the select gate line SGS reaches the upper surface of the lowermost insulating layer 42. The lower end of the hole CH_L corresponding to the word line WL1 reaches the upper surface of the next insulating layer 42 after the uppermost insulating layer 42.

[0214] Next, as Figure 11As shown, an insulator 101 is provided in the hole CH_L. Thus, the sides and bottom of the hole CH_L are covered by the insulator 101. The insulator 101 contains, for example, silicon oxide.

[0215] Next, as Figure 12 As shown, for example, the insulator 101 on the bottom surface of the hole CH_L is removed by anisotropic etching. At this time, the portion of the insulator layer 42 that is in contact with the bottom surface of the hole CH_L corresponding to the select gate line SGS, located below the removed insulator 101, is also removed. As a result, the insulator layer 61 is exposed in the hole CH_L corresponding to the select gate line SGS. Furthermore, the portion of the insulator layer 42 that is in contact with the bottom surface of the hole CH_L corresponding to the word line WL1, located below the removed insulator 101, is also removed. As a result, the next insulator layer 62 after the uppermost insulator layer 62 is exposed in the hole CH_L corresponding to the word line WL1. Hereinafter, this step will also be referred to as the "bottom removal step".

[0216] Next, as Figure 13 As shown, a sacrificial component 102 is embedded in the hole CH_L. The sacrificial component 102 contains, for example, polysilicon.

[0217] Next, as Figure 14 and Figure 15 As shown, a hole SHv_L corresponding to component SLTv_L and a hole SH_L corresponding to the lower component SLT_L are provided. For example, a mask with openings in the areas corresponding to holes SHv_L and SH_L is formed by photolithography or the like, and holes SHv_L and SH_L are formed by anisotropic etching using the mask. The lower ends of holes SHv_L and SH_L reach into wiring layer 21. The planar structure viewed from above the lower stack L_SB after forming holes SHv_L and SH_L is shown. Figure 16 As shown.

[0218] Next, as Figure 17 and Figure 18 As shown, sacrificial components 103 are embedded in holes SHv_L and SH_L. The planar structure of the lower laminate L_SB, viewed from above, after the sacrificial components 103 are embedded in holes SHv_L and SH_L, is as follows. Figure 19 As shown.

[0219] Next, as Figure 20 and Figure 21 As shown, an insulating layer 43 is disposed above the uppermost insulating layer 42. Then, four sacrificial member layers 60 and four insulating layers 40 are alternately stacked on top of the insulating layer 43. The insulating layer 43 contains, for example, TEOS. The insulating layer 40 contains, for example, silicon oxide. The sacrificial member 60 contains, for example, silicon nitride. Next, although not shown, a hole corresponding to the central pillar MP_M is provided, and the sacrificial member is embedded in this hole.

[0220] Next, as Figure 20 and Figure 21 As shown, the hole CH_M corresponding to the middle contact CC_M is provided in the same manner as the hole CH_L. The lower end of the hole CH_M corresponding to the select gate line SGS and the lower end of the hole CH_M corresponding to the word line WL1 reach the upper surface of the hole CH_L. The lower end of the hole CH_M corresponding to the word line WL3 reaches the upper surface of the bottom insulating layer 40. The lower end of the hole CH_M corresponding to the word line WL5 reaches the upper surface of the next insulating layer 40 after the top insulating layer 40. Next, similar to the hole CH_L, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_M, the sacrificial member 102 is embedded in the hole CH_M.

[0221] Next, as Figure 20 and Figure 21 As shown, similarly to holes SHv_L and SH_L, holes SHv_M corresponding to component SLTv_M and SH_M corresponding to the middle component SLT_M are provided. The lower ends of holes SHv_M and SH_M reach the boundary surfaces of insulating layer 42 and insulating layer 43. Then, similarly to holes SHv_L and SH_L, sacrificial components 103 are embedded in holes SHv_M and SH_M. The planar structures (first from the side of the paper) viewed from above the lower laminate L_SB and the planar structures (second from the side of the paper) viewed from above the middle laminate M_SB after embedding sacrificial components 103 in holes SHv_M and SH_M are as follows. Figure 22 As shown.

[0222] Next, as Figure 23 and Figure 24 As shown, an insulating layer 43' is provided above the uppermost insulating layer 40. Next, four sacrificial members 63 and four insulating layers 44 are alternately stacked on top of the insulating layer 43'. Then, sacrificial members 64, insulating layer 45, and insulating layer 46a are sequentially stacked on top of the uppermost insulating layer 44. Insulating layer 43' contains, for example, TEOS. Insulating layers 44, 45, and 46a contain, for example, silicon oxide. Sacrificial members 63 and 64 contain, for example, silicon nitride. Next, although not shown, a hole corresponding to the upper pillar MP_U is provided, similar to the hole MH_L. Next, after removing the sacrificial members from the holes corresponding to the lower pillar MP_L and the middle pillar MP_M, memory pillars MP are formed in the holes corresponding to the lower pillar MP_L, the middle pillar MP_M, and the upper pillar MP_U.

[0223] Next, as Figure 23 and Figure 24As shown, similar to the hole CH_L, a hole CH_U corresponding to the upper contact CC_U is provided. The lower ends of the hole CH_U corresponding to the select gate line SGS, the word line WL1, the word line WL3, and the word line WL5 reach the upper surface of the hole CH_M. The lower end of the hole CH_U corresponding to the word line WL7 reaches the upper surface of the bottom insulating layer 44. The lower end of the hole CH_U corresponding to the word line WL9 reaches the upper surface of the next insulating layer 44 after the top insulating layer 44. The lower end of the hole CH_U corresponding to the select gate line SGD reaches the upper surface of the insulating layer 45. Next, similar to the hole CH_L, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_U, a sacrificial member 102 is embedded in the hole CH_U.

[0224] Next, as Figure 23 and Figure 24 As shown, similarly to holes SHv_L and SH_L, holes SHv_U corresponding to component SLTv_U and SH_U corresponding to upper component SLT_U are provided. The lower ends of holes SHv_U and SH_U reach the boundary surfaces of insulating layer 40 and insulating layer 43'. The planar structures after forming holes SHv_U and SH_U, viewed from above the lower laminate L_SB (first from the side of the paper), the planar structures viewed from above the middle laminate M_SB (second from the side of the paper), and the planar structures viewed from above the upper laminate U_SB (third from the side of the paper) are as follows. Figure 25 As shown.

[0225] Next, as Figure 26 and Figure 27 As shown, for example, the sacrificial component 103 embedded in holes SHv_L, SHv_M, SH_L, and SH_M is removed by wet etching. The planar structures after removing the sacrificial component 103, viewed from above the lower laminate L_SB (first from the side of the paper), the planar structures viewed from above the middle laminate M_SB (second from the side of the paper), and the planar structures viewed from above the upper laminate U_SB (third from the side of the paper) are as follows: Figure 28 As shown.

[0226] then, Figure 29 and Figure 30As shown, for example, sacrificial components 60-64 are removed by wet etching with phosphoric acid. At this time, the etchant also reaches regions in the X direction that are farther from the memory cylinder MP than the holes SHv_L, SHv_M, and SHv_U. Therefore, in regions farther from the memory cylinder MP than the hole SHv_L, portions of sacrificial component 61 and each of the plurality of sacrificial components 62 are removed. More specifically, sacrificial components 61 and each of the plurality of sacrificial components 62 are removed until they are equidistant from the hole SHv_L. In regions farther from the memory cylinder MP than the hole SHv_M, portions of each of the plurality of sacrificial components 60 are removed. More specifically, each of the plurality of sacrificial components 60 is removed until it is equidistant from the hole SHv_M. In regions farther from the memory cylinder MP than the hole SHv_U, portions of each of the plurality of sacrificial components 63 and sacrificial components 64 are removed. More specifically, each of the plurality of sacrificial components 63 and sacrificial components 64 is removed until it is equidistant from the hole SHv_U. Therefore, in regions farther from the memory cylinder MP than the holes SHv_L, SHv_M, and SHv_U, regions are formed where sacrificial components 60-64 have been removed (gap) and regions where sacrificial components 60-64 have not been removed (sacrificial components 60-64 are retained). Then, wiring layers 20 and 22-25 are provided (replaced) in the regions (gap) where sacrificial components 60-64 have been removed. Wiring layers 20 and 22-25, for example, contain tungsten.

[0227] Next, as Figure 31 As shown, insulators 104 are embedded in each of the holes SHv_L, SHv_M, and SHv_U. This forms components SLTv_L, SLTv_M, and SLTv_U. The insulators 104, for example, contain silicon oxide.

[0228] Next, as Figure 32 As shown, spacers SP and conductors 105 (contacts LI) are embedded in holes SH_L, SH_M, and SH_U. This forms component SLT. The spacers SP, for example, contain silicon oxide. The conductors 105, for example, contain tungsten. The planar structures (first from the side of the paper) viewed from above the lower laminate L_SB, the second from the side of the paper viewed from above the middle laminate M_SB, and the third from the side of the paper viewed from above the upper laminate U_SB are shown below. Figure 33 As shown.

[0229] Next, as Figure 34As shown, after insulating layer 46b is formed on insulating layer 46a, hole EH corresponding to contact CC is formed. For example, a mask with an opening in the area corresponding to hole EH is formed by photolithography or the like, and hole EH is formed by anisotropic etching using the mask. The lower end of hole EH reaches the upper surface of hole CH_U. Insulating layer 46b contains, for example, silicon oxide. Insulating layers 46a and 46b correspond to insulating layer 46.

[0230] Next, as Figure 35 As shown, for example, sacrificial components 102 in holes CH_L, CH_M, and CH_U are removed by wet etching. As a result, holes CH_L, CH_M, and CH_U corresponding to the select gate line SGS are connected, and wiring layer 22 is exposed. Holes CH_L, CH_M, and CH_U corresponding to word line WL1 are connected, and wiring layer 23 is exposed. Holes CH_M and CH_U corresponding to word line WL3 are connected, and wiring layer 20 is exposed. Holes CH_M and CH_U corresponding to word line WL5 are connected, and wiring layer 20 is exposed. Wiring layer 24 corresponding to word line WL7 is exposed. Wiring layer 24 corresponding to word line WL9 is exposed. Wiring layer 25 corresponding to the select gate line SGD is exposed.

[0231] Next, as Figure 36 As shown, a conductor 106 is embedded in each of the holes CH_L, CH_M, CH_U, and EH. This forms a contact CC. The conductor 106 contains, for example, tungsten. The insulator 101 and conductor 106 included in each contact CC correspond to insulator 51 and conductor 50, respectively. The planar structures after forming the contact CC, viewed from above the lower laminate L_SB (first from the side of the paper), the planar structures viewed from above the middle laminate M_SB (second from the side of the paper), and the planar structures viewed from above the upper laminate U_SB (third from the side of the paper), are as follows: Figure 37 As shown.

[0232] 1.3 Effects of this implementation method

[0233] The array chip 100 is configured such that, in the contact area CA, the stacked wiring and the row decoder module are connected through contacts (hereinafter referred to as "through contacts") containing a conductor and an insulator covering the side of the conductor. In the array chip 100, for example, the stacked wiring is broken in each block BLK by means of a component SLT extending along the Z and Y directions and a component SLTv extending along the Z and X directions.

[0234] In the step of forming holes corresponding to components SLT and SLTv, the processing rate at the intersection of components SLT and SLTv is relatively high. Therefore, the amount of material removed from the semiconductor substrate W2 increases, and the semiconductor substrate W2 may be damaged. Furthermore, the more layers the laminated wiring has, the more material is removed from the semiconductor substrate W2.

[0235] In the bonding structure of array chip 100 and circuit chip 200, array chip 100 is processed from the back side (the side opposite to the bonding surface) after bonding. Therefore, the amount of excavation of semiconductor substrate W2 will hinder this processing.

[0236] In the semiconductor memory device 3 of this embodiment, holes corresponding to components SLT and SLTv are formed in the lower stack L_SB, the middle stack M_SB, and the upper stack U_SB, respectively. Therefore, compared to the case where holes corresponding to components SLT and SLTv are formed together in the lower stack L_SB, the middle stack M_SB, and the upper stack U_SB, the amount of substrate drilling required is reduced. Therefore, the semiconductor memory device 3 according to this embodiment can suppress the amount of substrate drilling.

[0237] In the semiconductor memory device 3 of this embodiment, holes SH_L corresponding to the lower component SLT_L and SHv_L corresponding to the component SLTv_L are formed simultaneously. Therefore, there are no areas of repeated processing when processing holes SH_L and SHv_L. Therefore, substrate breakdown can be suppressed. In addition, holes SH_M corresponding to the middle component SLT_M and SHv_M corresponding to the component SLTv_M are formed simultaneously. Holes SH_U corresponding to the upper component SLT_U and SHv_U corresponding to the component SLTv_U are formed simultaneously. Therefore, compared to the case where holes corresponding to components SLT and SLTv are formed separately in each of the lower stack L_SB, the middle stack M_SB, and the upper stack U_SB, the number of manufacturing steps can be reduced.

[0238] In the semiconductor memory device 3 of this embodiment, component SLTv_M is disposed above insulating layer 61 and multiple insulating layers 62. Component SLTv_U is disposed above multiple insulating layers 60. Therefore, compared to the case where the wiring layer is disposed below components SLTv_M and SLTv_U, the drilling amount can be disregarded when machining holes SHv_M and SHv_U.

[0239] In the semiconductor memory device 3 of this embodiment, the sum of distances DLa and DLb in the lower layer wiring contact CC, the sum of distances DMa and DMb in the middle layer wiring contact CC, and the sum of distances DUa and DUb in the upper layer wiring contact CC are averaged. Therefore, the RC delay time (the time from when a voltage is applied to the wiring until the voltage of the wiring rises or falls to the target value) can be mitigated.

[0240] 1.4 Example of the first variation

[0241] A first variation of the semiconductor memory device according to the first embodiment will be described. In this variation of the semiconductor memory device 3, the structure and manufacturing method of the lower stack L_SB, the middle stack M_SB, and the upper stack U_SB differ from those of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0242] 1.4.1 Cross-sectional structure of the contact area

[0243] use Figure 38 and Figure 39 The cross-sectional structure of the contact area CA is described. Figure 38 This is an example of the cross-sectional structure of the contact region CA of the memory cell array 10 included in the semiconductor memory device 3, which represents a first variation of the first embodiment. Figure 5 A cross-sectional view of line VIII-VIII. Figure 38 The cross-sectional structure of the storage region MA near the contact area CA is also shown. The cross-sectional structure of the storage region MA is similar to... Figure 6 Same. In the following description, the Z2 direction is set to upward, and the Z1 direction is set to downward.

[0244] like Figure 38 As shown, component SLTv_L is connected to wiring layer 22 and multiple wiring layers 23, and insulating layer 61 and multiple insulating layers 62. In other words, in the region farther from the memory cylinder MP than component SLTv_L, the lower stack L_SB includes insulating layer 61 and multiple insulating layers 62, but does not include wiring layer 22 and multiple wiring layers 23. Component SLTv_M is connected to multiple wiring layers 20 and multiple insulating layers 60. In other words, in the region farther from the memory cylinder MP than component SLTv_M, the middle stack M_SB includes multiple insulating layers 60, but does not include multiple wiring layers 20. Component SLTv_U is connected to multiple wiring layers 24 and wiring layers 25, and multiple insulating layers 63 and insulating layers 64. In other words, in the region further away from the memory cylinder MP than component SLTv_U, the upper stack U_SB contains multiple insulating layers 63 and 64, but does not contain multiple wiring layers 24 and 25.

[0245] The middle layer wiring contact CC is positioned above the insulation layer 61 and multiple insulation layers 62. The upper layer wiring contact CC is positioned above multiple insulation layers 60.

[0246] The construction and... Figure 8 same.

[0247] The cross-sectional structure above the insulating layer 46 and Figure 8 same.

[0248] Figure 39 This is an example of the cross-sectional structure of the contact region CA of the memory cell array 10 included in the semiconductor memory device 3, which represents a first variation of the first embodiment. Figure 5 A cross-sectional view of the IX-IX line. Figure 39 The cross-sectional structure of the storage region MA near the contact region CA is also shown. The cross-sectional structures of the regions in the contact region CA that are farther from the storage region MA than component SLTv_L, the regions that are farther from the storage region MA than component SLTv_M, and the regions that are farther from the storage region MA than component SLTv_U are also shown. Figure 38 The cross-sectional structures of the regions in contact area CA that are closer to memory area MA than component SLTv_L, closer to memory area MA than component SLTv_M, and closer to memory area MA than component SLTv_U are the same. Figure 9 The cross-sectional structure in the storage region MA is also the same. Figure 9 The cross-sectional structure above insulating layer 46 is the same. Figure 9 same.

[0249] 1.4.2 Manufacturing method of semiconductor memory device

[0250] use Figures 40-55 The manufacturing method of the semiconductor memory device 3 of the first variation of the first embodiment will be described. Figure 40 , Figure 42 , Figure 44 , Figure 46 , Figure 48 , Figure 50 , Figure 52 , Figure 54 and Figure 55 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3 during the manufacturing process of the first variation of the first embodiment. Figure 40 , Figure 44 , Figure 48 and Figure 54 Is with Figure 38 The corresponding cross-sectional structure. Figure 42 , Figure 46 , Figure 50 , Figure 52 and Figure 55 Is with Figure 39 The corresponding cross-sectional structure. Figure 41 , Figure 43 , Figure 45 , Figure 47 , Figure 49 , Figure 51 , Figure 53 This is a top view showing an example of the planar structure of the semiconductor memory device 3 during the manufacturing process of the first variation of the first embodiment. Figure 41 , Figure 43 , Figure 45 , Figure 47 , Figure 49 , Figure 51 , Figure 53 The interlayer insulating film is omitted. The following description of the formation steps of the memory pillars (MP) and support pillars (HR) is also omitted.

[0251] First, such as Figure 40 As shown, similar to the first embodiment, after the wiring layer 21, the insulating layer 41 and the sacrificial member 61 are stacked on the semiconductor substrate W2, four insulating layers 42 and three sacrificial member layers 62 are stacked alternately on the sacrificial member 61.

[0252] Next, as Figure 40 As shown, similarly to the first embodiment, a hole CH_L corresponding to the lower contact CC_L is provided. Next, similarly to the first embodiment, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_L, the sacrificial member 102 is embedded in the hole CH_L.

[0253] Next, as Figure 40 As shown, similarly to the first embodiment, a hole SHv_L corresponding to component SLTv_L is provided. The lower end of the hole SHv_L reaches into the wiring layer 21. Then, an insulator 104 is embedded in the hole SHv_L. Thus, component SLTv_L is formed. The insulator 104 contains, for example, silicon oxide. The planar structure viewed from above the lower laminate L_SB after embedding the insulator 104 in the hole SHv_L is as shown. Figure 41 As shown.

[0254] Next, as Figure 42 As shown, similarly to the first embodiment, a hole SH_L corresponding to the lower component SLT_L is provided. The lower end of the hole SH_L reaches into the wiring layer 21. Then, a sacrificial component 103 is embedded in the hole SH_L. The planar structure of the lower laminate L_SB after embedding the sacrificial component 103 in the hole SH_L is as shown. Figure 43 As shown.

[0255] Next, as Figure 44 As shown, similarly to the first embodiment, an insulating layer 43 is provided above the uppermost insulating layer 42. Next, similarly to the first embodiment, four sacrificial members 60 and four insulating layers 40 are alternately stacked on top of the insulating layer 43.

[0256] Next, as Figure 44 As shown, similar to the hole CH_L, a hole CH_M corresponding to the middle contact CC_M is provided. Next, similar to the hole CH_L, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_M, the sacrificial member 102 is embedded in the hole CH_M.

[0257] Next, as Figure 44 As shown, similarly to hole SHv_L, hole SHv_M corresponding to component SLTv_M is provided. The lower end of hole SHv_M reaches the boundary surface of insulating layer 42 and insulating layer 43. Then, similarly to hole SHv_L, insulator 104 is embedded in hole SHv_M. Thus, component SLTv_M is formed. The planar structure (first from the side of the paper) viewed from above the lower laminate L_SB after embedding insulator 104 in hole SHv_M, and the planar structure (second from the side of the paper) viewed from above the middle laminate M_SB, are shown below. Figure 45 As shown.

[0258] Next, as Figure 46 As shown, similar to hole SH_L, hole SH_M corresponding to the middle component SLT_M is provided. The lower end of hole SH_M reaches the boundary surface of insulating layer 42 and insulating layer 43. Then, similar to hole SH_L, sacrificial component 103 is embedded in hole SH_M. The planar structure (first from the side of the paper) viewed from above the lower laminate L_SB after embedding sacrificial component 103 in hole SH_M, and the planar structure (second from the side of the paper) viewed from above the middle laminate M_SB, are as follows. Figure 47 As shown.

[0259] Next, as Figure 48 As shown, similarly to the first embodiment, an insulating layer 43' is provided above the uppermost insulating layer 40. Next, similarly to the first embodiment, four sacrificial members 63 and four insulating layers 44 are alternately stacked on top of the insulating layer 43'. Next, similarly to the first embodiment, sacrificial members 64, insulating layers 45, and insulating layers 46a are sequentially stacked on top of the uppermost insulating layer 44.

[0260] Next, as Figure 48As shown, similar to the hole CH_L, a hole CH_U corresponding to the upper contact CC_U is provided. Next, similar to the hole CH_L, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_U, the sacrificial member 102 is embedded in the hole CH_U.

[0261] Next, as Figure 48 As shown, similarly to hole SHv_L, a hole SHv_U corresponding to component SLTv_U is provided. The lower end of hole SHv_U reaches the boundary surface of insulating layer 40 and insulating layer 43'. Then, similarly to hole SHv_L, insulator 104 is embedded in hole SHv_U. Thus, component SLTv_U is formed. The planar structure viewed from above the lower laminate L_SB (first from the side of the paper), the planar structure viewed from above the middle laminate M_SB (second from the side of the paper), and the planar structure viewed from above the upper laminate U_SB (third from the side of the paper) after embedding the insulator 104 in hole SHv_U are shown as follows. Figure 49 As shown.

[0262] Next, as Figure 50 As shown, similar to hole SH_L, hole SH_U corresponding to upper component SLT_U is provided. The lower end of hole SH_U reaches the boundary surface of insulating layer 40 and insulating layer 43'. The planar structures after forming hole SH_U, viewed from above the lower laminate L_SB (first from the side of the paper), the planar structures viewed from above the middle laminate M_SB (second from the side of the paper), and the planar structures viewed from above the upper laminate U_SB (third from the side of the paper) are as follows. Figure 51 As shown.

[0263] Next, as Figure 52 As shown, similarly to the first embodiment, the sacrificial member 103 embedded in the holes SH_L and SH_M is removed. The planar structures after removing the sacrificial member 103, viewed from above the lower laminate L_SB (first from the side of the paper), the planar structures viewed from above the middle laminate M_SB (second from the side of the paper), and the planar structures viewed from above the upper laminate U_SB (third from the side of the paper) are as follows: Figure 53 As shown.

[0264] Next, as Figure 54As shown, similarly to the first embodiment, sacrificial components 60 to 64 are removed. At this time, the etching solution does not reach the region in the X direction that is farther from the memory cylinder MP than components SLTv_L, SLTv_M, and SLTv_U. Therefore, in the region farther from the memory cylinder MP than component SLTv_L, sacrificial component 61 and the plurality of sacrificial components 62 are retained without removal. In the region farther from the memory cylinder MP than component SLTv_M, the plurality of sacrificial components 60 are retained without removal. In the region farther from the memory cylinder MP than component SLTv_U, the plurality of sacrificial components 63 and 64 are retained without removal. Then, similarly to the first embodiment, wiring layers 20 and 22 to 25 are provided (replaced) in the region (gap) where sacrificial components 60 to 64 have been removed.

[0265] Next, as Figure 55 As shown, similarly to the first embodiment, spacers SP and conductors 105 (contacts LI) are embedded in each of the holes SH_L, SH_M, and SH_U. This forms the component SLT. The planar structures (first from the paper side) viewed from above the lower laminate L_SB, the planar structures (second from the paper side) viewed from above the middle laminate M_SB, and the planar structures (third from the paper side) viewed from above the upper laminate U_SB after forming the component SLT are the same as those shown in the first embodiment. Figure 33 same.

[0266] The subsequent steps are the same as those shown in the first embodiment. Figures 34-37 same.

[0267] Alternatively, the formation of hole SH_L can be performed before the formation of hole SHv_L. The formation of hole SH_M can also be performed before the formation of hole SHv_M. The formation of hole SH_U can also be performed before the formation of hole SHv_U.

[0268] 1.4.3 Effects of this variation example

[0269] In the semiconductor memory device 3 of this variation, holes corresponding to components SLT and SLTv are formed in the lower stack L_SB, the middle stack M_SB, and the upper stack U_SB, respectively. Therefore, the semiconductor memory device 3 according to this variation can suppress substrate drilling in the same way as in the first embodiment.

[0270] Furthermore, in the semiconductor memory device 3 of this variation, a hole SHv_L corresponding to component SLTv_L is formed, and after the insulator 104 is embedded in the hole SHv_L, a hole SH_L corresponding to the lower component SLT_L is formed. Therefore, there are no areas of repeated processing when processing holes SH_L and SHv_L. Therefore, substrate breakdown can be suppressed.

[0271] In this variation of the semiconductor memory device 3, component SLTv_L is connected to wiring layer 22 and multiple wiring layers 23, and insulating layer 61 and multiple insulating layers 62. Component SLTv_M is connected to multiple wiring layers 20 and multiple insulating layers 60. Component SLTv_U is connected to multiple wiring layers 24 and 25, and multiple insulating layers 63 and insulating layers 64. In other words, wiring layers 20 and 22-25 are absent in the region farther from the memory cylinder MP than component SLTv. Therefore, the size of the region farther from the memory cylinder MP than component SLTv can be reduced. Therefore, the chip size of semiconductor memory device 3 can be reduced.

[0272] 1.5 Example of Variation 2

[0273] A second variation of the semiconductor memory device according to the first embodiment will be described. In this variation of the semiconductor memory device 3, the structure and manufacturing method of the lower component SLT_L and the split portion DP_L are different from those of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0274] 1.5.1 Planar layout of the contact area

[0275] Figure 56 This is a top view showing an example of the planar layout of the memory cell array 10 in the core region CR of the semiconductor memory device 3 of the second variation of the first embodiment. Figure 56 The diagram shows the planar structure including wiring layer 23 (word line WL2) and insulating layer 62, as viewed from above the lower laminate L_SB.

[0276] like Figure 56As shown, the lower component SLT_L extends along the Z and X directions and divides the wiring layer 22 and multiple wiring layers 23 in the Y direction. The lower component SLT_L has a first portion P1 containing contacts LI and spacers SP, and a second portion P2 containing insulator 52. The first portion P1 is located closer to the storage region MA than the second portion P2. The first portion P1 is connected to the second portion P2. The insulator 52 contains, for example, silicon oxide. The lower component SLT_L (second portion P2) extends through the boundary portion BD of each of the wiring layer 22 and multiple wiring layers 23 and each of the insulating layer 61 and multiple insulating layers 62 in the X direction. That is, the second portion P2 is connected to each of the wiring layer 22 and multiple wiring layers 23 and each of the insulating layer 61 and multiple insulating layers 62. The boundary portion BD extends along the Z and Y directions and includes a portion with an arc shape when viewed from above. The segment DP_L is formed by the boundary portion BD and the second portion P2 that penetrates the boundary portion BD in the X direction. That is, the segment DP_L includes the boundary portion BD and the second portion P2 (insulator 52). The segment DP_L segments the adjacent block BLK in the Y direction. The segment DP_L is positioned closer to the storage region MA than the segment DP_M. Furthermore, the segments DP_M and DP_U can also have similar characteristics to... Figure 56 The structure is the same as the segment DP_L shown.

[0277] 1.5.2 Manufacturing method of semiconductor memory device

[0278] The manufacturing method of the semiconductor memory device 3 in this variation example will be described. Figures 57-63 This is a top view showing an example of the planar structure of the semiconductor memory device 3 during manufacturing of the second variation of the first embodiment. Hereinafter, the description of the formation steps of the memory pillar MP and the support pillar HR will be omitted.

[0279] First, similar to the first embodiment, after stacking the wiring layer 21, the insulating layer 41 and the sacrificial member 61 on the semiconductor substrate W2, four insulating layers 42 and three sacrificial members 62 are stacked alternately on the sacrificial member 61.

[0280] Next, similarly to the first embodiment, a hole CH_L corresponding to the lower contact CC_L is provided. Then, similarly to the first embodiment, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_L, a sacrificial member 102 is embedded in the hole CH_L.

[0281] Next, as Figure 57 As shown, similar to the first embodiment, a hole SH_L corresponding to the lower component SLT_L is provided. The hole SH_L is formed, for example, such that its length in the X direction does not reach the position of the component SLTv_M.

[0282] Next, as Figure 58 As shown, the sacrificial component 103 is embedded in the region of hole SH_L corresponding to the first part P1. For example, the sacrificial component 103 is embedded in such a way that the length in the X direction of the region of hole SH_L corresponding to the second part P2 is longer than the length (distance) that the sacrificial component 61 and the plurality of sacrificial components 62 are etched away in the XY plane in the replacement step.

[0283] Next, as Figure 59 As shown, an insulator 107 is embedded in the region of hole SH_L corresponding to part P2 in section 2. The insulator 107 contains, for example, silicon oxide. The insulator 107 corresponds to insulator 52.

[0284] Next, similar to the first embodiment, after the insulating layer 43 is provided on the uppermost insulating layer 42, similar to the first embodiment, four sacrificial members 60 and four insulating layers 40 are alternately stacked on the insulating layer 43.

[0285] Next, similar to the hole CH_L, a hole CH_M corresponding to the middle contact CC_M is provided. Next, similar to the hole CH_L, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_M, the sacrificial member 102 is embedded in the hole CH_M.

[0286] Next, similarly to the first embodiment, after providing the hole SHv_M corresponding to the component SLTv_M and the hole SH_M corresponding to the middle component SLT_M, the sacrificial component 103 is embedded in the hole SHv_M and the hole SH_M, similarly to the first embodiment.

[0287] Next, similarly to the first embodiment, after the insulating layer 43' is provided on the uppermost insulating layer 40, four sacrificial members 63 and four insulating layers 44 are alternately stacked on the insulating layer 43'. Next, similarly to the first embodiment, the sacrificial members 64, the insulating layer 45 and the insulating layer 46a are stacked sequentially on the uppermost insulating layer 44.

[0288] Next, similar to the hole CH_L, a hole CH_U corresponding to the upper contact CC_U is provided. Next, similar to the hole CH_L, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_U, the sacrificial member 102 is embedded in the hole CH_U.

[0289] Next, similarly to holes SHv_M and SH_M, holes SHv_U corresponding to component SLTv_U and holes SH_U corresponding to upper component SLT_U are set.

[0290] Next, as Figure 60As shown, for example, the sacrificial component 103 embedded in each of the holes SHv_M, SH_L and SH_M is removed by wet etching.

[0291] Next, as Figure 61 As shown, for example, sacrificial components 60 to 64 are removed by wet etching with phosphoric acid. At this time, the etching solution reaches a position on the XY plane containing sacrificial component 61 and each of the multiple sacrificial components 62, equidistant from the end of the first portion P1 opposite to the storage region MA in the X direction. Therefore, sacrificial component 61 and each of the multiple sacrificial components 62 are removed concentrically from the end of the first portion P1 opposite to the storage region MA in the X direction. This forms a boundary portion BD including a portion with an arc shape when viewed from above. Furthermore, the etching solution does not reach the end of the second portion P2 on the XY plane containing sacrificial component 61 and each of the multiple sacrificial components 62 opposite to the storage region MA in the X direction. This forms a second portion P2 penetrating the boundary portion BD in the X direction. In a region further away from the storage region MA than the boundary portion BD and the second portion P2 penetrating the boundary portion BD in the X direction, a region where sacrificial component 61 and each of the multiple insulating layers 62 have not been removed is formed. This forms a break portion DP_L. The sacrificial components 60, 63 and 64 are removed in the same manner as in the first embodiment.

[0292] Next, as Figure 62 As shown, similarly to the first embodiment, wiring layers 20 and 22-25 are provided (replaced) in the areas (gaps) where sacrificial components 60-64 have been removed.

[0293] Next, similar to the first embodiment, an insulator 104 is embedded in each of the holes SHv_M and SHv_U.

[0294] Next, as Figure 63 As shown, similar to the first embodiment, spacers SP and conductors 105 (contacts LI) are embedded in the first portions P1, SH_M and SH_U of the hole SH_L.

[0295] The subsequent steps are the same as those shown in the first embodiment. Figures 34-37 same.

[0296] 1.5.3 Effects of this variation example

[0297] In the semiconductor memory device 3 of this variation, holes corresponding to components SLT and SLTv are formed in each of the lower stack L_SB, the middle stack M_SB, and the upper stack U_SB. Therefore, the semiconductor memory device 3 according to this variation can suppress substrate drilling in the same way as in the first embodiment.

[0298] Furthermore, in the semiconductor memory device 3 of this variation, after forming a hole SH_L corresponding to component SLT_L in the lower stack L_SB, a sacrificial component 103 and an insulator 107 are embedded in the hole SH_L. Next, after removing the sacrificial component 103, sacrificial components 60 to 64 are removed. This forms the break portion DP_L. In other words, the hole SHv_L corresponding to component SLTv_L is not formed in the lower stack L_SB. Therefore, substrate tunneling can be suppressed.

[0299] 2. Second Implementation Method

[0300] The semiconductor memory device according to the second embodiment will be described. In the semiconductor memory device 3 of this embodiment, the structure and manufacturing method of the lower stack L_SB, the middle stack M_SB, and the upper stack U_SB are different from those of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0301] 2.1 Planar Layout of Storage Cell Array

[0302] use Figure 64 The planar layout of the storage cell array 10 is described. Figure 64 This is a top view showing an example of the planar layout of the memory cell array 10 in the core region CR of the semiconductor memory device 3 according to the second embodiment.

[0303] Figure 64 The diagram shows the region corresponding to one block BLK contained in the memory cell array 10. Furthermore, the interlayer insulating film is omitted.

[0304] like Figure 64 As shown, each component SLT has a portion extending along the X direction and is configured to span the storage region MA and the contact region CA. Two component SLTs are arranged in the Y direction. The end of each component SLT on the opposite side of the storage region MA in the X direction is connected to component SLTv_L. Each component SLT is separated by the adjacent stack-up wiring.

[0305] The upper component SLT_U, the middle component SLT_M, and the lower component SLT_L span the storage area MA and the contact area CA. The end of the upper component SLT_U opposite to the storage area MA in the X-direction is connected to component SLTv_U. The end of the middle component SLT_M opposite to the storage area MA in the X-direction is connected to component SLTv_M. The end of the lower component SLT_L opposite to the storage area MA in the X-direction is connected to component SLTv_L.

[0306] Each component SHE has a portion extending along the X direction and is configured to span the memory region MA and the contact region CA. Multiple component SHEs are arranged in the Y direction. The end of each component SHE opposite to the memory region MA in the X direction is connected to component SLTv_U. Each component SHE is separated by adjacent wiring (at least the select gate line SGD).

[0307] Components SLTv_L, SLTv_M, and SLTv_U are configured in the contact area CA. Components SLTv_L, SLTv_M, and SLTv_U are configured in the order of components SLTv_U, SLTv_M, and SLTv_L, starting from the storage area MA side.

[0308] Component SLTv_L has a portion extending along the Y direction. Component SLTv_L is connected to the lower component SLT_L of each component SLT on the storage region MA side. Component SLTv_L will divide adjacent blocks BLK in the Y direction.

[0309] Component SLTv_M has a portion extending along the Y direction. Component SLTv_M is connected to the middle component SLT_M of each component SLT on the storage region MA side. Component SLTv_M will divide adjacent blocks BLK in the Y direction.

[0310] Component SLTv_U has a portion extending along the Y direction. Component SLTv_U is connected to the upper component SLT_U of each component SLT and each component SHE on the storage region MA side. Component SLTv_U will divide adjacent blocks BLK in the Y direction.

[0311] In addition, other block BLKs also have the same Figure 64 The same construction. In the case where the storage cell array 10 contains multiple block BLKs, for example, it is repeatedly configured in the Y direction. Figure 64 The structure shown.

[0312] The planar layout of the memory cell array 10 included in the semiconductor memory device 3 can also be other layouts. For example, the number of components SHEs arranged between two adjacent components SLTs can be designed to be any number. The number of string components SUs included in each BLK can be varied based on the number of components SHEs arranged between two adjacent components SLTs. The number of components SLTv only needs to be two or more and can be varied according to the construction of the memory cell array 10.

[0313] 2.2 Layout of Storage Area

[0314] The planar layout of the storage area MA is the same as that shown in the first embodiment. Figure 5 same.

[0315] 2.3 Planar layout of the contact area

[0316] Next, refer to Figure 64 The planar layout of the contact area CA is described.

[0317] Contacts CC are configured in the contact area CA, excluding components SLT, SHE, and SLTv. In this example, five contacts CC are arranged in the Y direction near the memory area MA. These five contacts CC are configured in the areas corresponding to the string components SU0 to SU4. These five contacts CC are connected, for example, to the select gate line SGD.

[0318] In the area corresponding to string component SU1, in addition to the contact CC near storage region MA, six other contacts CC are configured. Between the contact CC near storage region MA and component SLTv_U, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to word line WL10 and word line WL8, for example, starting from the storage region MA side. Between component SLTv_U and component SLTv_M, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to word line WL6 and word line WL4, for example, starting from the storage region MA side. Between component SLTv_M and component SLTv_L, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to word line WL2 and word line WL0, for example, starting from the storage region MA side.

[0319] In the region corresponding to string component SU3, six contacts CC are configured in addition to the contacts CC near memory region MA. Between the contacts CC near memory region MA and component SLTv_U, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to word line WL9 and word line WL7, for example, starting from the memory region MA side. Between component SLTv_U and component SLTv_M, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to word line WL5 and word line WL3, for example, starting from the memory region MA side. Between component SLTv_M and component SLTv_L, two contacts CC are arranged in the X direction. These two contacts CC are connected sequentially to word line WL1 and select gate line SGS, for example, starting from the memory region MA side.

[0320] The support post HR is appropriately positioned in the contact area CA, excluding components SLT, SHE, and SLTv, and contact CC. In this example, the support post HR is as shown in the first embodiment. Figure 5 Configure it in the same way.

[0321] Furthermore, the planar layout of the contact area CA of the memory cell array 10 included in the semiconductor memory device 3 can also be other layouts. For example, the number and configuration of the contacts CC and the support pillars HR can be appropriately changed.

[0322] 2.4 Cross-sectional structure of the storage area

[0323] use Figure 65 The cross-sectional structure of the storage region MA is described. Figure 65 This is an example of a cross-sectional structure along the memory region MA of the memory cell array 10 included in the semiconductor memory device 3 of the second embodiment. Figure 64 A cross-sectional view of line S1-S1. (See example...) Figure 65 As shown, in the storage cell array 10, in the storage region MA, from the first embodiment shown Figure 6 Insulator layers 43 and 43' have been removed from the cross-sectional structure. In the following description, the Z2 direction is defined as upward and the Z1 direction as downward.

[0324] The cross-sectional structure below the uppermost insulating layer 42 is the same as that shown in the first embodiment. Figure 6 The same. Above the uppermost insulating layer 42, wiring layers 20 and insulating layers 40 are alternately stacked. Above the uppermost insulating layer 40, wiring layers 24 and insulating layers 44 are alternately stacked. Above the uppermost insulating layer 44, wiring layers 25, insulating layers 45, and insulating layers 46 are stacked sequentially. The cross-sectional structure above insulating layer 46 is the same as shown in the first embodiment. Figure 6 same.

[0325] The structure of the memory column MP, component SLT, and component SHE is the same as shown in the first embodiment. Figure 6 same.

[0326] 2.5 Cross-sectional structure of the contact area

[0327] use Figure 66 and Figure 67 The cross-sectional structure of the contact area CA is described. Figure 66 This is an example of the cross-sectional structure of the contact region CA of the memory cell array 10 included in the semiconductor memory device 3 of the second embodiment, along... Figure 64 A cross-sectional view of line S2-S2. Figure 66 The cross-sectional structure of the storage region MA near the contact area CA is also shown. The cross-sectional structure of the storage region MA is similar to... Figure 65 same. Figure 66 As shown, in the storage cell array 10, in the contact area CA, from the first embodiment shown Figure 8Insulator layers 43 and 43' have been removed from the cross-sectional structure. In the following description, the Z2 direction is defined as upward and the Z1 direction as downward.

[0328] Each contact CC extends along the Z direction and has, for example, a cylindrical shape. Multiple contacts CC are respectively disposed on the select gate line SGS, word lines WL0 to WL10, and select gate line SGD.

[0329] First, the lower-level wiring contacts CC will be explained. The lower-level wiring contacts CC include the lower contact CC_L, the middle contact CC_M, and the upper contact CC_U.

[0330] The lower contact CC_L extends along the Z-direction and connects to any one of the wiring layers 22 and multiple wiring layers 23. In other words, the lower contact CC_L penetrates the wiring layer 23 above the wiring layer (select gate line SGS and word lines WL0 to WL2) to which the contact CC is connected, and the insulating layer 42. The lower contact CC_L includes a conductor 50 and an insulator 51 covering at least a portion of the side surface of the conductor 50. The middle contact CC_M is disposed above the lower contact CC_L and penetrates multiple insulating layers 60 and multiple insulating layers 40 in the Z-direction. The upper end of the lower contact CC_L and the lower end of the middle contact CC_M are connected at the boundary surface of the insulating layer 42 and the insulating layer 60. In other words, the upper end of the lower contact CC_L is connected to the lowermost insulating layer 60, which is disposed on the same layer as the lowermost wiring layer 20. The middle contact CC_M includes a conductor 50 and an insulator 51 covering the sides of the conductor 50. The upper contact CC_U is disposed above the middle contact CC_M and extends through multiple insulator layers 63 and 64 and multiple insulator layers 44 and 45 in the Z direction. The upper end of the middle contact CC_M and the lower end of the upper contact CC_U are connected at the boundary surface of the insulator layers 40 and 63. In other words, the upper end of the middle contact CC_M is connected to the lowest insulator layer 63, which is disposed on the same layer as the lowest wiring layer 24. The upper contact CC_U includes a conductor 50 and an insulator 51 covering at least a portion of the sides of the conductor 50.

[0331] The upper end of conductor 50 is located within insulating layer 46, and the lower end of conductor 50 is connected to the wiring layer to which conductor 50 is connected. The upper end of insulator 51 is located within insulating layer 46 at a lower position than the upper end of conductor 50, and the lower end of insulator 51 is connected to insulating layer 42 above the wiring layer to which conductor 50 is connected. In other words, insulator 51 covers the side surface of conductor 50 except for the upper and lower parts of conductor 50.

[0332] As described above, the lower wiring contact CC extends along the Z direction and penetrates the middle laminate M_SB (multiple insulating layers 60) and the upper laminate U_SB (multiple insulating layers 63 and insulating layers 64), connecting to any of the wiring layers 22 and multiple wiring layers 23, and at least a portion of its side surface is covered by insulator 51.

[0333] Next, the middle layer wiring contacts CC will be described. The middle layer wiring contacts CC include the middle contact CC_M and the upper contact CC_U.

[0334] The middle contact CC_M extends along the Z-direction and connects to any one of the multiple wiring layers 20. In other words, the middle contact CC_M penetrates the wiring layer 20 above the wiring layer (word lines WL3 to WL6) to which the contact CC is connected, and the insulating layer 40. The middle contact CC_M includes a conductor 50 and an insulator 51 covering at least a portion of the side surface of the conductor 50. The upper contact CC_U is disposed above the middle contact CC_M and penetrates multiple insulating layers 63 and 64 and multiple insulating layers 44 and 45 in the Z-direction. The upper end of the middle contact CC_M and the lower end of the upper contact CC_U are connected at the boundary surface of the insulating layer 40 and the insulating layer 63. In other words, the upper end of the middle contact CC_M is connected to the lowermost insulating layer 63 of the same layer as the lowermost wiring layer 24. The upper contact CC_U includes a conductor 50 and an insulator 51 covering at least a portion of the side surface of the conductor 50.

[0335] The upper end of conductor 50 is located within insulating layer 46, and the lower end of conductor 50 is connected to the wiring layer to which conductor 50 is connected. The upper end of insulator 51 is located within insulating layer 46 at a lower position than the upper end of conductor 50, and the lower end of insulator 51 is connected to insulating layer 40 above the wiring layer to which conductor 50 is connected. In other words, insulator 51 covers the side surface of conductor 50 except for the upper and lower parts of conductor 50.

[0336] As described above, the middle layer wiring contact CC extends along the Z direction and penetrates the upper stack U_SB (multiple insulating layers 63 and 64), is connected to any of the multiple wiring layers 20, and at least a portion of its side is covered by insulator 51.

[0337] Next, the upper-layer wiring contacts CC will be described. The upper-layer wiring contacts CC each include the upper contact CC_U.

[0338] The upper contact CC_U extends along the Z direction and is connected to any one of the multiple wiring layers 24 and 25. In other words, the upper contact CC_U corresponding to word lines WL7 to WL10 passes through the wiring layers 24 and 25 above the wiring layer to which the contact CC is connected, and the insulating layers 44 and 45. The upper contact CC_U corresponding to the select gate line SGD passes through the insulating layer 45 above the select gate line SGD. The upper contact CC_U includes a conductor 50 and an insulator 51 covering at least a portion of the side surface of the conductor 50.

[0339] The upper end of conductor 50 is located within insulating layer 46, and the lower end of conductor 50 is connected to the wiring layer to which conductor 50 is connected. The upper end of insulator 51 is located within insulating layer 46 at a lower position than the upper end of conductor 50, and the lower end of insulator 51 is connected to insulating layer 44 or 45 above the wiring layer to which conductor 50 is connected. In other words, insulator 51 covers the sides of conductor 50 except for the upper and lower parts of conductor 50.

[0340] As described above, the upper wiring contact CC extends along the Z direction and is connected to any of the multiple wiring layers 24 and 25, and at least a portion of its side is covered by an insulator 51.

[0341] For example, the cross-sectional area (XY cross-sectional area) of the lower contact CC_L and the middle contact CC_M along the XY plane increases from bottom to top. Similarly, the portion of the upper contact CC_U located lower than the portion of the upper conductor 50 not covered by the insulator 51 also increases from bottom to top along the XY plane. The portion of the upper conductor 50 in the upper contact CC_U not covered by the insulator 51 also increases from bottom to top along the XY plane. At the junction of the lower contact CC_L and the middle contact CC_M, the side surface of the lower contact CC_L is offset from the side surface of the middle contact CC_M. At the junction of the middle contact CC_M and the upper contact CC_U, the side surface of the middle contact CC_M is offset from the side surface of the upper contact CC_U.

[0342] Components SLTv_L (splitter DP_L), SLTv_M (splitter DP_M), and SLTv_U (splitter DP_U) are each formed to extend along the YZ plane, for example. Component SLTv_L extends along the Z and Y directions and splits wiring layer 22 and multiple wiring layers 23 in the X direction. The upper end of component SLTv_L is, for example, at the same position as the boundary surface of insulating layer 42 and insulating layer 60. The lower end of component SLTv_L is, for example, located within wiring layer 21. Component SLTv_M extends along the Z and Y directions and splits multiple wiring layers 20 in the X direction. The upper end of component SLTv_M is, for example, at the same position as the boundary surface of insulating layer 40 and insulating layer 63. The lower end of component SLTv_M is, for example, at the same position as the boundary surface of insulating layer 42 and insulating layer 60. Component SLTv_U extends along the Z and Y directions and divides multiple wiring layers 24 and 25 in the X direction. The upper end of component SLTv_U is located, for example, within insulating layer 46. The lower end of component SLTv_U is located, for example, at the same position as the boundary surface of insulating layer 40 and insulating layer 63. For example, the cross-sectional area (XY cross-sectional area) of components SLTv_L, SLTv_M, and SLTv_U along the XY plane increases from bottom to top.

[0343] Component SLTv_U is positioned closer to memory cylinder MP than component SLTv_M. Component SLTv_M is positioned closer to memory cylinder MP than component SLTv_L. In other words, component SLTv_U does not overlap with components SLTv_L and SLTv_M in the Z direction, and component SLTv_M does not overlap with component SLTv_L in the Z direction.

[0344] The upper-layer wiring contact CC is configured in the area between the memory cylinder MP and component SLTv_U. Additionally, the upper-layer wiring contact CC is configured above multiple wiring layers 20. The middle-layer wiring contact CC is configured in the area between component SLTv_U and component SLTv_M. Additionally, the middle-layer wiring contact CC is configured above wiring layer 22 and multiple wiring layers 23. The lower-layer wiring contact CC is configured in the area between component SLTv_M and component SLTv_L.

[0345] Insulator layer 61 and multiple insulating layers 62 are disposed further away from memory cylinder MP than component SLTv_L. In other words, component SLTv_L is disposed closer to memory cylinder MP than insulating layer 61 and multiple insulating layers 62. Component SLTv_L is in contact with wiring layer 22 and multiple wiring layers 23, as well as insulating layer 61 and multiple insulating layers 62. In other words, in the region further away from memory cylinder MP than component SLTv_L, the lower stack L_SB includes insulating layer 61 and multiple insulating layers 62, but does not include wiring layer 22 and multiple wiring layers 23. In the region further away from memory cylinder MP than component SLTv_L, insulating layer 41 and insulating layer 61 are sequentially stacked on wiring layer 21. Insulator layer 61 and wiring layer 22 are disposed on the same layer. Insulator layer 42 and insulating layer 62 are alternately stacked on insulating layer 61. Multiple insulating layers 62 and multiple wiring layers 23 are disposed on the same layer.

[0346] Multiple insulating layers 60 are disposed further away from the memory cylinder MP than component SLTv_M. In other words, component SLTv_M is disposed closer to the memory cylinder MP than the multiple insulating layers 60. Furthermore, component SLTv_M is disposed above wiring layer 22 and multiple wiring layers 23. Component SLTv_M is in contact with multiple wiring layers 20 and multiple insulating layers 60. In other words, in the region further away from the memory cylinder MP than component SLTv_M, the middle stack M_SB contains multiple insulating layers 60 but does not contain multiple wiring layers 20. In the region further away from the memory cylinder MP than component SLTv_M, insulating layers 60 and insulating layers 40 are alternately stacked above the uppermost insulating layer 42. Each of the multiple insulating layers 60 and each of the multiple wiring layers 20 are disposed on the same layer.

[0347] Multiple insulating layers 63 and 64 are disposed further away from the memory cylinder MP than component SLTv_U. In other words, component SLTv_U is disposed closer to the memory cylinder MP than the multiple insulating layers 63 and 64. Furthermore, component SLTv_U is disposed above multiple wiring layers 20. Component SLTv_U is in contact with multiple wiring layers 24 and 25, as well as multiple insulating layers 63 and 64. In other words, in the region further away from the memory cylinder MP than component SLTv_U, the upper stack U_SB includes multiple insulating layers 63 and 64, but does not include multiple wiring layers 24 and 25. In the region further away from the memory cylinder MP than component SLTv_U, insulating layers 63 and 44 are alternately stacked above the uppermost insulating layer 40. Each of the multiple insulating layers 63 and each of the multiple wiring layers 24 are disposed on the same layer. Above the top insulating layer 44, insulating layers 64, 45, and 46 are stacked in sequence. Insulating layer 64 and wiring layer 25 are located on the same layer.

[0348] The cross-sectional structure above the insulating layer 46 is the same as that shown in the first embodiment. Figure 8 same.

[0349] Figure 67 This is an example of the cross-sectional structure of the contact region CA of the memory cell array 10 included in the semiconductor memory device 3 of the second embodiment, along... Figure 64 A sectional view of line S3-S3. Figure 67 The cross-sectional structure of the storage region MA near the contact region CA is also shown. The cross-sectional structures of the regions of the contact region CA that are farther from the storage region MA than component SLTv_L, farther from the storage region MA than component SLTv_M, and farther from the storage region MA than component SLTv_U, are shown in the diagram, except that the contact CC is not formed. Figure 66 same.

[0350] In the contact area CA, closer to the storage area MA than component SLTv, the lower component SLT_L is connected to component SLTv_L and penetrates wiring layer 22 and multiple wiring layers 23. The upper end of the lower component SLT_L is, for example, at the same position as the upper end of component SLTv_L. The lower end of the lower component SLT_L is, for example, at the same position as the lower end of component SLTv_L. The middle component SLT_M is connected to component SLTv_M and penetrates multiple wiring layers 20. The upper end of the middle component SLT_M is, for example, at the same position as the upper end of component SLTv_M. The lower end of the middle component SLT_M is, for example, at the same position as the lower end of component SLTv_M. The upper component SLT_U is connected to component SLTv_U and penetrates multiple wiring layers 24 and wiring layer 25. The upper end of the upper component SLT_U is, for example, at the same position as the upper end of component SLTv_U. The lower end of the upper component SLT_U is located at the same position as the lower end of component SLTv_U. The cross-sectional structure in the storage region MA also has the same structure. The cross-sectional structure above the insulating layer 46 is the same as that shown in the first embodiment. Figure 9 same.

[0351] 2.6 Manufacturing method of semiconductor memory device

[0352] use Figures 68-86 The manufacturing method of the semiconductor memory device 3 according to the second embodiment will be described. Figure 68 , Figure 70 , Figure 72 , Figure 74 , Figure 76 , Figure 78 , Figure 80 , Figure 82 , Figure 83 and Figure 85 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3 during manufacturing of the second embodiment. Figure 68 , Figure 72 , Figure 76 , Figure 82 and Figure 85 Is with Figure 66 The corresponding cross-sectional structure. Figure 70 , Figure 74 , Figure 78 , Figure 80 and Figure 83 Is with Figure 67 The corresponding cross-sectional structure. Figure 69 , Figure 71 , Figure 73 , Figure 75 , Figure 77 , Figure 79 , Figure 81 , Figure 84 and Figure 86 This is a top view showing an example of the planar structure of the semiconductor memory device 3 during manufacturing according to the second embodiment. Figure 69 , Figure 71 , Figure 73 , Figure 75 , Figure 77 , Figure 79 , Figure 81 , Figure 84 and Figure 86 The interlayer insulating film is omitted. The following description of the formation steps of the memory pillars (MP) and support pillars (HR) is also omitted.

[0353] First, such as Figure 68 As shown, similarly to the first embodiment, after stacking a wiring layer 21, an insulating layer 41, and a sacrificial member 61 on the semiconductor substrate W2, four insulating layers 42 and three sacrificial member layers 62 are alternately stacked on the sacrificial member 61. The wiring layer 21 contains, for example, polysilicon. The insulating layers 41 and 42 contain, for example, silicon oxide. The sacrificial members 61 and 62 contain, for example, silicon nitride. Next, although not shown, similarly to the first embodiment, a hole corresponding to the lower pillar MP_L is provided, and the sacrificial member is embedded in the hole.

[0354] Next, as Figure 68 As shown, similarly to the first embodiment, a hole CH_L corresponding to the lower contact CC_L is provided. The lower end of the hole CH_L corresponding to the select gate line SGS reaches the upper surface of the lowermost insulating layer 42. The lower end of the hole CH_L corresponding to the word line WL1 reaches the upper surface of the next insulating layer 42 after the uppermost insulating layer 42. Next, similarly to the first embodiment, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_L, a sacrificial member 102 is embedded in the hole CH_L. The insulator 101 contains, for example, silicon oxide. The sacrificial member 102 contains, for example, polysilicon.

[0355] Next, as Figure 68 As shown, similarly to the first embodiment, a hole SHv_L corresponding to component SLTv_L is provided. The lower end of the hole SHv_L reaches into the wiring layer 21. Then, an insulator 104 is embedded in the hole SHv_L. Thus, component SLTv_L is formed. The insulator 104 contains, for example, silicon oxide. The planar structure viewed from above the lower laminate L_SB after embedding the insulator 104 in the hole SHv_L is as shown. Figure 69 As shown.

[0356] Next, as Figure 70As shown, similarly to the first embodiment, a hole SH_L corresponding to the lower component SLT_L is provided. The lower end of the hole SH_L reaches into the wiring layer 21. Then, a sacrificial component 103 is embedded in the hole SH_L. The planar structure of the lower laminate L_SB after embedding the sacrificial component 103 in the hole SH_L is as shown. Figure 71 As shown.

[0357] Next, as Figure 72 As shown, similarly to the first embodiment, four sacrificial members 60 and four insulating layers 40 are alternately stacked on top of the uppermost insulating layer 42. The insulating layer 40 contains, for example, silicon oxide. The sacrificial member 60 contains, for example, silicon nitride. Next, although not shown, similarly to the first embodiment, a hole corresponding to the central pillar MP_M is provided, and the sacrificial member is embedded in this hole.

[0358] Next, as Figure 72 As shown, similar to the hole CH_L, a hole CH_M corresponding to the middle contact CC_M is provided. The lower end of the hole CH_M corresponding to the select gate line SGS and the lower end of the hole CH_M corresponding to the word line WL1 reach the upper surface of the hole CH_L. The lower end of the hole CH_M corresponding to the word line WL3 reaches the upper surface of the bottom insulating layer 40. The lower end of the hole CH_M corresponding to the word line WL5 reaches the upper surface of the next insulating layer 40 after the top insulating layer 40. Next, similar to the first embodiment, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_M, the sacrificial member 102 is embedded in the hole CH_M.

[0359] Next, as Figure 72 As shown, similarly to hole SHv_L, hole SHv_M corresponding to component SLTv_M is provided. The lower end of hole SHv_M reaches the boundary surface of insulating layer 42 and insulating layer 60. Then, similarly to hole SHv_L, insulator 104 is embedded in hole SHv_M. Thus, component SLTv_M is formed. The planar structure (first from the side of the paper) viewed from above the lower laminate L_SB after embedding insulator 104 in hole SHv_M, and the planar structure (second from the side of the paper) viewed from above the middle laminate M_SB, are shown below. Figure 73 As shown.

[0360] Next, as Figure 74As shown, similarly to hole SH_L, hole SH_M corresponding to the middle component SLT_M is provided. The lower end of hole SH_M reaches the boundary surface of insulating layer 42 and insulating layer 60. Then, similarly to hole SH_L, sacrificial component 103 is embedded in hole SH_M. The planar structure (first from the side of the paper) viewed from above the lower laminate L_SB after embedding sacrificial component 103 in hole SH_M, and the planar structure (second from the side of the paper) viewed from above the middle laminate M_SB, are as follows. Figure 75 As shown.

[0361] Next, as Figure 76 As shown, similarly to the first embodiment, four sacrificial members 63 and four insulating layers 44 are alternately stacked on top of the uppermost insulating layer 40. Next, similarly to the first embodiment, sacrificial members 64, insulating layers 45 and 46a are sequentially stacked on top of the uppermost insulating layer 44. Insulating layers 44, 45, and 46a contain, for example, silicon oxide. Sacrificial members 63 and 64 contain, for example, silicon nitride. Next, although not shown, similarly to the first embodiment, a hole corresponding to the upper pillar MP_U is provided, similar to the hole MH_L. Next, similarly to the first embodiment, after removing the sacrificial members from the holes corresponding to the lower pillar MP_L and the middle pillar MP_M, memory pillars MP are formed in the holes corresponding to the lower pillar MP_L, the middle pillar MP_M, and the upper pillar MP_U.

[0362] Next, as Figure 76 As shown, similar to the hole CH_L, a hole CH_U corresponding to the upper contact CC_U is provided. The lower ends of the hole CH_U corresponding to the select gate line SGS, the word line WL1, the word line WL3, and the word line WL5 reach the upper surface of the hole CH_M. The lower end of the hole CH_U corresponding to the word line WL7 reaches the upper surface of the bottom insulating layer 44. The lower end of the hole CH_U corresponding to the word line WL9 reaches the upper surface of the next insulating layer 44 after the top insulating layer 44. The lower end of the hole CH_U corresponding to the select gate line SGD reaches the upper surface of the insulating layer 45. Next, similar to the hole CH_L, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_U, a sacrificial member 102 is embedded in the hole CH_U.

[0363] Next, as Figure 76As shown, similarly to hole SHv_L, hole SHv_U corresponding to component SLTv_U is provided. The lower end of hole SHv_U reaches the boundary surface of insulating layer 40 and insulating layer 63. Then, similarly to hole SHv_L, insulator 104 is embedded in hole SHv_U. Thus, component SLTv_U is formed. The planar structure of the lower laminate L_SB viewed from above (first from the side of the paper), the planar structure of the middle laminate M_SB viewed from above (second from the side of the paper), and the planar structure of the upper laminate U_SB viewed from above (third from the side of the paper) after embedding insulator 104 in hole SHv_U are shown below. Figure 77 As shown.

[0364] Next, as Figure 78 As shown, similar to hole SH_L, hole SH_U corresponding to upper component SLT_U is provided. The lower end of hole SH_U reaches the boundary surface of insulating layer 40 and insulating layer 63. The planar structures after forming hole SH_U, viewed from above the lower laminate L_SB (first from the side of the paper), the planar structures viewed from above the middle laminate M_SB (second from the side of the paper), and the planar structures viewed from above the upper laminate U_SB (third from the side of the paper) are as follows. Figure 79 As shown.

[0365] Next, as Figure 80 As shown, similarly to the first embodiment, the sacrificial member 103 embedded in the holes SH_L and SH_M is removed. The planar structures after removing the sacrificial member 103, viewed from above the lower laminate L_SB (first from the side of the paper), the planar structures viewed from above the middle laminate M_SB (second from the side of the paper), and the planar structures viewed from above the upper laminate U_SB (third from the side of the paper) are as follows: Figure 81 As shown.

[0366] Next, as Figure 82As shown, similarly to the first embodiment, sacrificial components 60 to 64 are removed. At this time, the etchant does not reach the region in the X direction that is further away from the memory cylinder MP than components SLTv_L, SLTv_M, and SLTv_U. Therefore, in the region further away from the memory cylinder MP than component SLTv_L, sacrificial component 61 and the plurality of sacrificial components 62 are not removed and are retained. In the region further away from the memory cylinder MP than component SLTv_M, the plurality of sacrificial components 60 are not removed and are retained. In the region further away from the memory cylinder MP than component SLTv_U, the plurality of sacrificial components 63 and 64 are not removed and are retained. Then, similarly to the first embodiment, wiring layers 20 and 22 to 25 are provided (replaced) in the region (gap) where sacrificial components 60 to 64 have been removed. Wiring layers 20 and 22 to 25, for example, contain tungsten.

[0367] Next, as Figure 83 As shown, similarly to the first embodiment, spacers SP and conductors 105 (contacts LI) are embedded in each of the holes SH_L, SH_M, and SH_U. This forms the component SLT. The planar structures (first from the side of the paper) viewed from above the lower laminate L_SB, the planar structures (second from the side of the paper) viewed from above the middle laminate M_SB, and the planar structures (third from the side of the paper) viewed from above the upper laminate U_SB after forming the component SLT are as follows: Figure 84 As shown.

[0368] Next, as Figure 85 As shown, similarly to the first embodiment, after the insulating layer 46b is provided on the insulating layer 46a, a hole EH corresponding to the contact CC is provided. The lower end of the hole EH reaches the upper surface of the hole CH_U. The insulating layer 46b contains, for example, silicon oxide. Insulating layers 46a and 46b correspond to insulating layer 46.

[0369] Next, as Figure 85 As shown, similarly to the first embodiment, the sacrificial component 102 in each of the holes CH_L, CH_M and CH_U is removed.

[0370] Next, as Figure 85As shown, similarly to the first embodiment, a conductor 106 is embedded in each of the holes CH_L, CH_M, and CH_U. This forms a contact CC. The conductor 106 contains, for example, tungsten. The insulator 101 and conductor 106 included in each contact CC correspond to insulator 51 and conductor 50, respectively. The planar structures (first from the side of the paper) viewed from above the lower laminate L_SB, the planar structures (second from the side of the paper) viewed from above the middle laminate M_SB, and the planar structures (third from the side of the paper) viewed from above the upper laminate U_SB after the contact CC is formed are as follows: Figure 86 As shown.

[0371] Alternatively, the formation of hole SH_L can be performed before the formation of hole SHv_L. The formation of hole SH_M can also be performed before the formation of hole SHv_M. The formation of hole SH_U can also be performed before the formation of hole SHv_U.

[0372] 2.7 Effects of this implementation method

[0373] In the semiconductor memory device 3 of this embodiment, holes corresponding to components SLT and SLTv are formed in each of the lower stack L_SB, the middle stack M_SB, and the upper stack U_SB. Therefore, the semiconductor memory device 3 according to this embodiment can suppress substrate drilling in the same way as in the first embodiment.

[0374] For example, to ensure withstand voltage, a certain distance is required between the contact CC of a wiring layer connected to a certain layer and the bottom wiring layer of the layer above it, such as between the lower wiring contact CC and the bottom wiring layer 20, or between the middle wiring contact CC and the bottom wiring layer 24.

[0375] In the semiconductor memory device 3 of this embodiment, the upper end of the lower contact CC_L is connected to the lowermost insulating layer 60, which is disposed on the same layer as the lowermost wiring layer 20. The upper end of the middle contact CC_M is connected to the lowermost insulating layer 63, which is disposed on the same layer as the lowermost wiring layer 24. Furthermore, multiple insulating layers 60 are provided in the middle laminate M_SB above the lower wiring contact CC. Multiple insulating layers 63 and 64 are provided in the upper laminate U_SB above the lower wiring contact CC. Multiple insulating layers 63 and 64 are provided in the upper laminate U_SB above the middle wiring contact CC. Therefore, the withstand voltage between the upper end of the lower contact CC_L and the lowermost wiring layer 20, and between the upper end of the middle contact CC_M and the lowermost wiring layer 24, can be ensured. In addition, since the distance between the upper end of the lower contact CC_L and the lowermost insulating layer 60, which is located on the same layer as the bottommost wiring layer 20, and the distance between the upper end of the middle contact CC_M and the insulating layer 63, which is located on the same layer as the bottommost wiring layer 24, can be shortened, the degradation of the current Icell flowing through the memory cell transistor MT can be suppressed.

[0376] 2.8 Examples of Variation

[0377] A modified example of the semiconductor memory device according to the second embodiment will be described. In this modified example of the semiconductor memory device 3, the structure and manufacturing method of the lower stack L_SB, the middle stack M_SB, and the upper stack U_SB are different from those of the second embodiment. Hereinafter, the description will focus on the differences from the second embodiment.

[0378] 2.8.1 Cross-sectional structure of the contact area

[0379] use Figure 87 The cross-sectional structure of the contact area CA is described. Figure 87 This is an example of the cross-sectional structure of the contact region CA of the memory cell array 10 included in the semiconductor memory device 3 of the second embodiment, along... Figure 64 A cross-sectional view of line S2-S2. Figure 87 The cross-sectional structure of the storage region MA near the contact area CA is also shown. For example... Figure 87 As shown, in the storage cell array 10, in the storage region MA and the contact region CA, as shown in the second embodiment... Figure 66 Insulating layers 43 and 43' are added to the cross-sectional structure. Additionally, in the memory cell array 10, a lower stop STP_L and a middle stop STP_M are added to the contact region CA. In the following description, the Z2 direction is defined as upward, and the Z1 direction as downward.

[0380] The construction of contact areas CA, contact CC, and components SLTv_L, SLTv_M, and SLTv_U is similar to... Figure 66 same.

[0381] The cross-sectional structure below the uppermost insulating layer 42 and Figure 66 same.

[0382] In the contact region CA, closer to the memory cylinder MP than component SLTv_L, the uppermost insulating layer 42 includes a lower stop portion STP_L. The lower stop portion STP_L functions as an etching stop during the formation step of the hole SHv_M corresponding to component SLTv_M. The lower stop portion STP_L is disposed below component SLTv_M. The upper end of the lower stop portion STP_L is connected to the lower end of component SLTv_M. The lower end of the lower stop portion STP_L is located above the lower end of the uppermost insulating layer 42. The lower stop portion STP_L includes a conductor 65 and an insulator 66. The conductor 65 may contain, for example, polysilicon. Alternatively, the conductor 65 may also contain HfO, ZrO, TaO, tungsten, or titanium. The insulator 66 covers the sides of the conductor 65. In other words, the lower stack L_SB includes a conductor 65 disposed above the uppermost wiring layer 23 and whose sides and bottom are covered by an insulator. Furthermore, the upper end of the conductor 65 is connected to the lower end of the component SLTv_M. The insulator 66 contains, for example, silicon oxide.

[0383] In the contact region CA, closer to the memory cylinder MP than component SLTv_M, an insulating layer 43 is disposed above the uppermost insulating layer 42. Insulating layer 43 may include, for example, TEOS. Wiring layer 20 and insulating layer 40 are alternately stacked above insulating layer 43. The uppermost insulating layer 40 includes a central stop portion STP_M. The central stop portion STP_M functions as an etching stop in the step of forming the hole SHv_U corresponding to component SLTv_U. The central stop portion STP_M is disposed below component SLTv_U. The upper end of the central stop portion STP_M is connected to the lower end of component SLTv_U. The lower end of the central stop portion STP_M is located above the lower end of the uppermost insulating layer 40. The central stop portion STP_M includes a conductor 65 and an insulator 66. The insulator 66 covers the side of the conductor 65. In other words, the middle stack M_SB includes a conductor 65 disposed above the uppermost wiring layer 20 and whose sides and bottom are covered by an insulator. Furthermore, the upper end of the conductor 65 is connected to the lower end of the component SLTv_U.

[0384] In the contact area CA, closer to the memory cylinder MP than component SLTv_U, an insulating layer 43' is disposed above the uppermost insulating layer 40. Insulating layer 43' may contain, for example, TEOS. Wiring layer 24 and insulating layer 44 are alternately stacked above insulating layer 43'. Wiring layer 25, insulating layer 45 and insulating layer 46 are stacked sequentially above the uppermost insulating layer 44.

[0385] In the contact region CA, which is further away from the memory cylinder MP than component SLTv_M, an insulating layer 43 is disposed above the uppermost insulating layer 42. Insulating layers 60 and 40 are alternately stacked on top of insulating layer 43.

[0386] In the contact area CA, which is further away from the memory cylinder MP than the component SLTv_U, an insulating layer 43' is disposed above the uppermost insulating layer 40. Insulating layers 63 and 44 are alternately stacked above the insulating layer 43'. Above the uppermost insulating layer 44, insulating layers 64, 45, and 46 are stacked in sequence.

[0387] The cross-sectional structure above the insulating layer 46 and Figure 66 same.

[0388] 2.8.2 Manufacturing method of semiconductor memory device

[0389] use Figures 88-91 The manufacturing method of the semiconductor memory device 3 in this variation example will be described. Figures 88-91 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 3 during manufacturing, as a variation of the second embodiment. The following description of the formation steps of the memory pillar MP and the support pillar HR is omitted.

[0390] First, such as Figure 88 As shown, similar to the second embodiment, after the wiring layer 21, the insulating layer 41 and the sacrificial member 61 are stacked on the semiconductor substrate W2, four insulating layers 42 and three sacrificial member layers 62 are stacked alternately on the sacrificial member 61.

[0391] Next, as Figure 88 As shown, similarly to the second embodiment, a hole CH_L corresponding to the lower contact CC_L and a hole PH_L corresponding to the lower stop STP_L are provided. The lower end of the hole PH_L reaches a position higher than the lower end of the uppermost insulating layer 42.

[0392] Next, as Figure 89As shown, similarly to the second embodiment, an insulator 101 is provided in the holes CH_L and PH_L. Thus, the side and bottom surfaces of each of the holes CH_L and PH_L are covered by the insulator 101. The insulator 101 corresponds to the insulator 66.

[0393] Next, as Figure 90 As shown, similarly to the second embodiment, a bottom removal step is performed on holes CH_L and PH_L. As a result, the insulator 101 on the bottom surface of hole PH_L is removed.

[0394] Next, as Figure 91 As shown, similarly to the second embodiment, sacrificial members 102 are embedded in the holes CH_L and PH_L. The sacrificial members 102, for example, contain polysilicon. The sacrificial members 102 correspond to the conductor 65.

[0395] Next, similar to the second embodiment, the steps of forming the hole SHv_L corresponding to the component SLTv_L and embedding the insulator 104 into the hole SHv_L are performed. Next, the steps of forming the hole SH_L corresponding to the lower component SLT_L and embedding the sacrificial component 103 into the hole SH_L are performed.

[0396] Next, an insulating layer 43 is disposed on the uppermost insulating layer 42. The insulating layer 43 contains, for example, TEOS. Then, similarly to the second embodiment, four sacrificial members 60 and four insulating layers 40 are alternately stacked on the insulating layer 43.

[0397] Next, similar to holes CH_L and PH_L, holes CH_M corresponding to the middle contact CC_M and PH_M corresponding to the middle stop STP_M are provided. The lower end of hole PH_L reaches a position higher than the lower end of the uppermost insulating layer 40.

[0398] Next, similarly to holes CH_L and PH_L, after the insulator 101 formation step and bottom removal step are performed on holes CH_M and PH_M, sacrificial components 102 are embedded in holes CH_M and PH_M.

[0399] Next, a hole SHv_M corresponding to component SLTv_M is formed. At this time, a lower stop portion STP_L is provided below the location where the hole SHv_M is formed, therefore the etching process stops at the upper surface of the lower stop portion STP_L. That is, the lower end of the hole SHv_M reaches the upper surface of the lower stop portion STP_L. Next, the step of embedding the insulator 104 into the hole SHv_M is performed. Next, the steps of forming the hole SH_M corresponding to the middle component SLT_M and embedding the sacrificial component 103 into the hole SH_M are performed.

[0400] Next, an insulating layer 43' is disposed on top of the uppermost insulating layer 40. The insulating layer 43' may contain, for example, TEOS. Next, similarly to the second embodiment, four sacrificial members 63 and four insulating layers 44 are alternately stacked on top of the insulating layer 43'. Next, similarly to the second embodiment, the sacrificial member 64, the insulating layer 45, and the insulating layer 46a are sequentially stacked on top of the uppermost insulating layer 44.

[0401] Next, similar to the hole CH_L, a hole CH_U corresponding to the upper contact CC_U is provided. Next, similar to the hole CH_L, after the insulator 101 formation step and the bottom removal step are performed on the hole CH_U, the sacrificial member 102 is embedded in the hole CH_U.

[0402] Next, a hole SHv_U corresponding to component SLTv_U is formed. At this time, since a central stop STP_M is provided below the location where the hole SHv_U is formed, the etching process stops at the upper surface of the central stop STP_M. That is, the lower end of the hole SHv_U reaches the upper surface of the central stop STP_M. Next, the step of embedding the insulator 104 into the hole SHv_U is performed.

[0403] The subsequent steps are the same as those shown in the second embodiment. Figures 78-86 same.

[0404] 2.8.3 Effects of this variation example

[0405] In the semiconductor memory device 3 of this variation, each of the lower stack L_SB, the middle stack M_SB, and the upper stack U_SB is provided with a hole corresponding to each of components SLT and SLTv. Therefore, the semiconductor memory device 3 according to this variation can suppress substrate drilling in the same way as in the second embodiment.

[0406] Furthermore, in the semiconductor memory device 3 of this variation, the lower stack L_SB includes a conductor 65 disposed above the uppermost wiring layer 23 and whose sides and bottom surfaces are covered by an insulator. The upper end of the conductor 65 is connected to the lower end of component SLTv_M. The middle stack M_SB includes a conductor 65 disposed above the uppermost wiring layer 20 and whose sides and bottom surfaces are covered by an insulator. The upper end of the conductor 65 is connected to the lower end of component SLTv_U. Therefore, when machining holes SHv_M and SHv_U, non-selective etching of the insulator layers 40, 43, and 44 and the sacrificial components 60, 63, and 64 can also be applied.

[0407] 3. Other

[0408] As described above, the semiconductor memory device (3) of the embodiment includes a first stack (L_SB), a second stack (M_SB), a memory pillar (MP), a first contact (CC), a first disconnection (DP_L), a second contact (CC), and a second disconnection (DP_M). The first stack (L_SB) includes a plurality of first wiring layers (22, 23) spaced apart from each other in a first direction (Z), and a plurality of first insulating layers (61, 62) disposed on the same layer as the plurality of first wiring layers. The second stack (M_SB) includes a plurality of second wiring layers (20) spaced apart from each other in the first direction (Z), and a plurality of second insulating layers (60) disposed on the same layer as the plurality of second wiring layers, and is disposed above the first stack (L_SB). The memory pillar (MP) extends through the plurality of first wiring layers (22, 23) and the plurality of second wiring layers (20) in the first direction (Z). The first contact (CC) extends along the first direction (Z) and penetrates the second stack (M_SB), connecting to the third wiring layer (SGS / WL0 / WL1 / WL2) among the plurality of first wiring layers (22, 23), and at least a portion of its side is covered by the first insulator (51). The first break (DP_L) extends along the first direction (Z) and the second direction (Y) intersecting the first direction, and breaks the plurality of first wiring layers (22, 23) in the third direction (X) intersecting the first and second directions. The second contact (CC) extends along the first direction (Z) and connects to the fourth wiring layer (WL3 / WL4 / WL5 / WL6) among the plurality of second wiring layers (20), and at least a portion of its side is covered by the second insulator (51). The second break section (DP_M) extends along the first direction (Z) and the second direction (Y) and breaks multiple second wiring layers (20) in the third direction (X). The second break section (DP_M) does not overlap with the first break section (DP_L) in the first direction (Z).

[0409] Furthermore, the implementation method is not limited to the form described above, and various variations are possible.

[0410] The manufacturing steps described in the above embodiments are merely examples and are not limited thereto. For example, other processes may be inserted between the manufacturing steps, or some steps may be omitted or combined. In addition, the manufacturing steps may be substituted within permissible limits.

[0411] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, as well as in the scope of the invention as described in the claims and their equivalents.

[0412] [Explanation of Symbols]

[0413] 1: Memory System

[0414] 2: Memory controller

[0415] 3: Semiconductor memory devices

[0416] 10: Memory cell array

[0417] 11: Instruction Register

[0418] 12: Address Register

[0419] 13: Sequencer

[0420] 14: Driver Module

[0421] 15: Line decoder module

[0422] 16: Sensing Amplifier Module

[0423] 21-28: Wiring layers

[0424] 30: Core membrane

[0425] 31: Semiconductor film

[0426] 32: Laminated film

[0427] 33: Tunnel insulation film

[0428] 34: Insulating film

[0429] 35: Barrier insulating film

[0430] 40-48: Insulating layer

[0431] 50: Conductor

[0432] 51, 52: Insulators

[0433] 60-64: Insulating layer

[0434] 102, 103: Sacrificial parts

[0435] 105, 106: Conductors

[0436] 101, 104: Insulators.

Claims

1. A semiconductor memory device comprising: The first layer stack includes a plurality of first wiring layers arranged spaced apart from each other in a first direction, and a plurality of first insulating layers disposed on the same layer as the plurality of first wiring layers; The second layer stack includes a plurality of second wiring layers spaced apart from each other in the first direction, and a plurality of second insulating layers disposed on the same layer as the plurality of second wiring layers, and is disposed above the first layer stack; A memory column that penetrates the plurality of first wiring layers and the plurality of second wiring layers in the first direction; The first contact extends along the first direction and penetrates the second layer stack, is connected to the third wiring layer among the plurality of first wiring layers, and at least a portion of its side is covered by the first insulator. The first break section extends along the first direction and the second direction intersecting the first direction, and breaks the plurality of first wiring layers in the third direction intersecting the first direction and the second direction; The second contact extends along the first direction and is connected to the fourth wiring layer among the plurality of second wiring layers, and at least a portion of its side is covered by the second insulator. and The second segment extends along the first and second directions, severing the plurality of second wiring layers in the third direction; and The second segment does not overlap with the first segment in the first direction.

2. The semiconductor memory device according to claim 1, wherein The first contact extends through the plurality of second wiring layers.

3. The semiconductor memory device according to claim 2, wherein... The first segment is positioned closer to the memory column than the second segment.

4. The semiconductor memory device according to claim 3, wherein The first contact is disposed in the region between the memory column and the first break portion. The second contact is disposed in the area between the first break and the second break.

5. The semiconductor memory device according to claim 4, further comprising: The third contact is connected to the upper end of the first contact; and The fourth contact is connected to the upper end of the second contact; The sum of the distance from the upper end of the first contact to the lower end of the first contact and the distance from the lower end of the first contact to the memory column, and the sum of the distance from the upper end of the second contact to the lower end of the second contact and the distance from the lower end of the second contact to the memory column, are averaged.

6. The semiconductor memory device according to claim 2, wherein The first break portion is positioned closer to the memory pillar than the plurality of first insulating layers. The second break portion is positioned closer to the memory pillar than the plurality of second insulating layers and above the plurality of first insulating layers.

7. The semiconductor memory device according to claim 6, wherein Each of the plurality of first insulating layers is connected to each of the plurality of first wiring layers. Each of the plurality of second insulating layers is connected to each of the plurality of second wiring layers.

8. The semiconductor memory device according to claim 6, wherein The first break section is connected to the plurality of first wiring layers and the plurality of first insulation layers. The second break section is connected to the plurality of second wiring layers and the plurality of second insulation layers.

9. The semiconductor memory device according to claim 8, wherein The second contact is disposed above the plurality of first insulating layers.

10. The semiconductor memory device according to claim 2, wherein The first segment includes: The boundary portion, extending along the first direction and the second direction, is the boundary portion between each of the plurality of first wiring layers and each of the plurality of first insulating layers; and The third insulator penetrates the boundary portion in the third direction.

11. The semiconductor memory device of claim 10, wherein... The boundary portion includes a part that has an arc shape when viewed from above.

12. The semiconductor memory device according to claim 11, further comprising a first component, The first component extends along the first direction and the third direction and divides the plurality of first wiring layers in the second direction. The first component has a first portion comprising a first conductor and a fourth insulator, and a second portion comprising the third insulator. The second part is connected to each of the plurality of first wiring layers and each of the plurality of first insulation layers.

13. The semiconductor memory device according to claim 1, wherein The first contact extends through the plurality of second insulating layers.

14. The semiconductor memory device of claim 13, wherein... The second segment is positioned closer to the memory column than the first segment.

15. The semiconductor memory device of claim 14, wherein... The second contact is disposed in the region between the memory column and the second break portion. The first contact is located in the area between the second break and the first break.

16. The semiconductor memory device of claim 13, wherein... The first break portion is positioned closer to the memory pillar than the plurality of first insulating layers. The second break portion is positioned closer to the memory pillar than the plurality of second insulating layers and above the plurality of first wiring layers.

17. The semiconductor memory device of claim 16, wherein... The first break section is connected to the plurality of first wiring layers and the plurality of first insulation layers. The second break section is connected to the plurality of second wiring layers and the plurality of second insulation layers.

18. The semiconductor memory device according to claim 17, wherein The second contact is positioned above the plurality of first wiring layers.

19. The semiconductor memory device according to claim 13, wherein The first contact includes: The fifth contact is connected to the third wiring layer; and The sixth contact penetrates the plurality of second insulating layers in the first direction and is connected to the upper end of the fifth contact; The upper end of the fifth contact is connected to the lowest insulating layer among the plurality of second insulating layers.

20. The semiconductor memory device of claim 13, wherein The first layer also includes a conductor. The conductor is positioned above the uppermost wiring layer among the plurality of first wiring layers, and its sides and bottom are covered by an insulator. The upper end of the conductor is connected to the lower end of the second segment.

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