NAND flash memory devices and methods of manufacturing NAND flash memory devices

Abstract

The present disclosure relates to a NAND flash memory device (10). The NAND flash memory device (10) comprises a semiconductor channel layer (12) extending along a first axis, a first dielectric layer (13) arranged above the semiconductor channel layer (12), a charge storage layer (14) arranged on the first dielectric layer (13), a second dielectric layer (15) arranged on the charge storage layer (14), and a plurality of gate structures (19) arranged above the second dielectric layer (15) and along the first axis, wherein each gate structure (19) comprises a first section (16) and a second section (17), wherein the first section (16) and the second section (17) are designed to have different work functions, and wherein the first section (16) and the second section (17) are arranged next to each other along the first axis.

Description

Technical Field

[0001] This disclosure relates to NAND flash memory devices and methods for manufacturing NAND flash memory devices. This disclosure also relates to methods for operating NAND flash memory devices. Background Technology

[0002] NAND flash memory is a type of memory that stores information in a non-volatile manner in the form of charge carriers (electrons or holes) in a charge-trapping layer or in a floating gate that is part of the flash cell transistor. The concentration of stored charge carriers corresponds to information bits and can be read by the resulting threshold voltage offset of the flash cell. Typically, quantum tunneling is used to change the charge carrier concentration, thereby writing or erasing information. To limit the threshold voltage variability between cells in the programming state, a scheme called Incremental Step Pulse Programming (ISPP) is used, in which a series of pulses with increasing amplitude are applied to the gate until the target threshold voltage value is reached. The curve showing the threshold voltage offset relative to the fresh state as a function of the pulse amplitude is called the ISPP curve and provides important information related to the performance of the flash cell.

[0003] To increase bit density, the size of flash memory cells has shrunk with each generation of technology. Since around 2015, mainstream manufacturing technology has shifted from planar devices to vertical 3D structures, where flash memory strings consist of cylindrical memory holes along which flash memory cells are stacked. Memory strings can thus be manufactured by first depositing a stack of alternating phase layers, then etching the memory holes and filling them with memory and channel layers. These 3D structures allow for increased bit density by adding more cells to the string rather than scaling the cell size. However, as the number of cells on the string increases, etching the memory holes becomes more challenging due to the increased aspect ratio. This has led to a renewed push to shrink the vertical cell pitch, which includes the flash memory cell gate length and gate spacing.

[0004] The transition from a floating gate to a charge-trapping layer and the continuous shrinking of cells both contribute to a degradation in programming characteristics, characterized by the programming start voltage and programming efficiency. The programming start voltage is defined as the voltage at which a significant threshold voltage shift of the cell is observed. In the ISPP curve, this corresponds to the point where the curve begins to rise. Programming efficiency is the rate at which the cell threshold voltage changes with increasing applied voltage. In the ISPP curve, this corresponds to the slope of the curve in the quasi-linear region. These two metrics (start voltage and efficiency) determine the voltage required to achieve the target threshold voltage shift corresponding to the cell's programming state. Because generating high voltages on-chip is costly, lower programming voltages are generally desirable. Additionally, high programming efficiency is beneficial for the cell's interference characteristics because it increases the difference between threshold voltage shifts occurring during pass-through and programmable modes. It also increases the window between different programming levels in multi-level cell operation.

[0005] Gate-side injection has been proposed to improve the programming characteristics of (miniaturized) flash memory cells. In this approach, during programming operations, electrons are injected from the gate, rather than from the channel. This decouples the capacitive coupling that determines field compensation during programming operations from the capacitive coupling that determines the effect of the programmed charge on the channel threshold voltage. If the memory stack is designed such that the capacitance towards the gate is smaller than the capacitance towards the channel, an ISPP slope greater than the conventional maximum of 1 can be obtained. Another advantage is that gate-side injection reduces degradation of oxides adjacent to the channel, which improves cycle durability.

[0006] While gate-side injection significantly improves programming compared to conventional channel-side injection, erasure typically results in a substantial degradation. This is because erasure requires injecting holes into a charge-trapping layer, where the holes recombine with existing electrons and provide a positive charge to offset the programmed threshold voltage (V). T Offset. In conventional schemes, both electrons and holes can be injected from the channel side, which is composed of intrinsic or lightly doped semiconductors. However, for gate-side injection, carriers are injected from the gate material that meets the word line resistivity requirements. However, it is known that gate materials favor electron injection at the expense of hole injection, or vice versa. Within the specification of maximum resistivity, no material is optimized for both programming and erasing memory operations simultaneously. Summary of the Invention

[0007] Therefore, the objective is to provide an improved NAND flash memory device and an improved method for manufacturing the NAND flash memory device. Specifically, the objective is to provide a NAND flash memory device capable of efficiently performing memory operations.

[0008] This objective is achieved by the embodiments provided in the appended independent claims. Advantageous implementations of the embodiments of this disclosure are further defined in the dependent claims.

[0009] A first aspect of this disclosure provides a NAND flash memory device, comprising: a semiconductor channel layer extending along a first axis; a first dielectric layer disposed above the semiconductor channel layer; a charge storage layer disposed on the first dielectric layer; a second dielectric layer disposed on the charge storage layer; and a plurality of gate structures disposed along the first axis above the second dielectric layer; wherein each gate structure includes a first segment and a second segment, wherein the first segment and the second segment are designed to have different work functions, and wherein the first segment and the second segment are disposed adjacent to each other along the first axis.

[0010] This provides the advantage of offering a NAND flash memory device that allows for efficient memory operations (programming and erasing) via gate-side injection. To achieve this advantage, the gate structure has a split-gate design with a first segment and a second segment, wherein the first segment is optimized for gate-side injection of electrons (for programming) and the second segment is optimized for gate-side injection of holes (for erasing).

[0011] For example, the work function (and / or Fermi level) of the first segment has a beneficial alignment with the edge of the second dielectric layer for electron injection; while the second segment of the gate structure has a beneficial alignment for hole injection. As a result, the gate structure allows for the efficient injection of electrons and holes into the charge storage layer (also known as the charge trapping layer).

[0012] The second dielectric layer may be a tunneling oxide layer, and / or the first dielectric layer may be a barrier oxide layer.

[0013] In one embodiment of the first aspect, the charge storage layer includes a plurality of gaps arranged to intermittently discontinuously within the charge storage layer; wherein the gaps and the gate structure are arranged alternately along a first axis. This provides the advantage that injected charge carriers can be confined to a finite volume below the respective gate. This finite volume may be referred to as a charge trapping region.

[0014] The gap may extend to the first dielectric layer and / or the second dielectric layer.

[0015] In one embodiment of the first aspect, the gap is at least partially filled with air and / or oxide material. This provides the advantage that charge carriers can be efficiently confined to the charge trapping region.

[0016] In one embodiment of the first aspect, the charge storage layer comprises a silicon nitride material.

[0017] In one embodiment of the first aspect, the work function of the first segment of the corresponding gate structure ranges from 3.5 eV to 5 eV; and / or the work function of the second segment of the corresponding gate structure ranges from 4.5 eV to 6 eV. This provides the advantage that the first segment can be optimized for electron injection, while the second segment can be optimized for hole injection.

[0018] In one embodiment of the first aspect, the difference in work function between the first segment and the second segment of the corresponding gate structure is at least 0.5 eV, preferably at least 1 eV. For example, the difference is between 1 eV and 2 eV.

[0019] In one embodiment of the first aspect, the first and second segments of the respective gate structures comprise different materials and / or different doping.

[0020] In one embodiment of the first aspect, the first segment and / or the second segment of the corresponding gate structure comprises polysilicon material, metal, or metal nitride.

[0021] For example, the first and second segments can each be formed from highly doped polysilicon or metal. The first segment can be made of an n-type material (e.g., N+ polysilicon) that is highly favorable for electron injection, while the second segment can be made of a p-type material (e.g., P+ polysilicon) that is highly favorable for hole injection.

[0022] The metal can be any of W, Ti, Ta, Al, Mo, Ru, Co, Cu, Ir, or Pt. The metal nitride can be any of TiN or TaN.

[0023] In one embodiment of the first aspect, the first and second segments of the respective gate structure have different widths along the first axis. This provides the advantage that the gate structure can be further optimized for electron and hole injection.

[0024] In one embodiment of the first aspect, the corresponding gate structure includes an isolation layer disposed between the first segment and the second segment. This provides the advantage that the gate structure can be further optimized for electron and hole injection.

[0025] In one embodiment of the first aspect, each of the gate structures includes a third segment arranged along a first axis adjacent to the second segment; wherein the third segment is designed to have the same work function as the first segment, or wherein the third segment is designed to have a work function that differs from the work function of the first segment by less than 0.1 eV. This provides the advantage that the gate structure can be further optimized for electron and hole injection.

[0026] For example, the first and third segments of the corresponding gate structure are made of the same material. The second segment may be made of a different material and sandwiched between the first and third segments.

[0027] A second aspect of this disclosure provides a method for operating a NAND flash memory device according to a first aspect of this disclosure, the method comprising: applying a first bias voltage to at least one of a gate structure to allow negative charge carriers, particularly electrons, to be injected through a first segment of the gate structure into a charge storage layer below the gate structure, wherein at least a portion of the negative charge carriers are stored in the charge storage layer; and applying a second bias voltage to said at least one of the gate structures to allow positive charge carriers, particularly holes, to be injected through a second segment of the gate structure into the charge storage layer below the gate structure, wherein at least a portion of the positive charge carriers recombine with negative charge carriers stored in the charge storage layer.

[0028] The application of the first bias voltage corresponds to programming (i.e., writing via electron injection), while the application of the second bias voltage corresponds to erasing (via hole injection).

[0029] A third aspect of this disclosure provides a method for manufacturing a NAND flash memory device, the method comprising: forming a semiconductor channel layer extending along a first axis; forming a first dielectric layer disposed over the semiconductor channel layer; forming a charge storage layer disposed on the first dielectric layer; forming a second dielectric layer disposed on the charge storage layer; and forming a plurality of gate structures disposed along the first axis over the second dielectric layer; wherein each gate structure includes a first segment and a second segment, wherein the first segment and the second segment are designed to have different work functions, and wherein the first segment and the second segment are disposed adjacent to each other along the first axis.

[0030] This provides the advantage of offering a NAND flash memory device that allows for efficient memory operations (programming and erasing) via gate-side injection. To achieve this advantage, the gate structure has a split-gate design with a first segment and a second segment, wherein the first segment can be optimized for gate-side electron injection (programming) and the second segment can be optimized for gate-side hole injection (erasing).

[0031] In one embodiment of the third aspect, the method further includes: forming a plurality of gaps in the charge storage layer; wherein the gaps are arranged to discontinuate the charge storage layer; and wherein the gaps and the gate structure are arranged alternately along a first axis.

[0032] In one embodiment of the third aspect, forming the corresponding gate structure includes: depositing a sacrificial layer over a second dielectric layer; selectively removing a first portion of the sacrificial layer to expose a first region, and depositing material for a first segment of the gate structure in the first region; and removing a second portion of the sacrificial layer to expose a second region, and depositing material for a second segment of the gate structure in the second region. This provides the advantage that the segments of the gate structure can be formed in an efficient manner.

[0033] The first region and the region may each include or be formed by a number of cavities in the sacrificial layer.

[0034] In one embodiment of the third aspect, the first and second portions of the sacrificial layer are each removed by etching with an etchant, wherein the first portion is designed to be etched at a higher etch rate than the second portion.

[0035] The sacrificial layer can be formed of silicon nitride (SiN) or silicon germanium (SiGe) materials, wherein the nitrogen content of SiN or the germanium content of SiGe differs in the first and second parts of the sacrificial layer.

[0036] In one embodiment of the third aspect, the gaps in the charge storage layer are at least partially filled with air and / or oxide materials.

[0037] In one embodiment of the third aspect, the charge storage layer comprises a silicon nitride material.

[0038] In one embodiment of the third aspect, the work function of the first segment of the corresponding gate structure ranges from 3.5 eV to 5 eV; and / or the work function of the second segment of the corresponding gate structure ranges from 4.5 eV to 6 eV.

[0039] In one embodiment of the third aspect, the difference in work function between the first segment and the second segment of the corresponding gate structure is at least 0.5 eV, preferably at least 1 eV.

[0040] In one embodiment of the third aspect, the first and second segments of the corresponding gate structure comprise different materials and / or different doping.

[0041] In one embodiment of the third aspect, the first and / or second segments of the corresponding gate structure comprise polysilicon material, metal, or metal nitride.

[0042] In one embodiment of the third aspect, the first segment and the second segment of the corresponding gate structure have different widths along the first axis.

[0043] In one embodiment of the third aspect, the corresponding gate structure includes an isolation layer disposed between the first segment and the second segment.

[0044] In one embodiment of the third aspect, each of the gate structures includes a third segment arranged along a first axis next to the second segment; wherein the third segment is designed to have the same work function as the first segment, or wherein the third segment is designed to have a work function that differs from the work function of the first segment by less than 0.1 eV. Attached Figure Description

[0045] The above aspects and implementations are explained in the following specific embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram of a NAND flash memory device according to one embodiment is shown; Figures 2A to 2B Simulation results of memory operation in a NAND flash memory device according to one embodiment are shown; Figure 3 A simulation of charge carrier injection in the charge storage layer of a NAND flash memory device according to one embodiment is shown; Figure 4 This is a schematic diagram of a NAND flash memory device according to an embodiment; Figure 5 This is a schematic diagram of a NAND flash memory device according to an embodiment; Figure 6 This is a schematic diagram of a NAND flash memory device according to an embodiment; Figure 7 This is a schematic diagram of a NAND flash memory device according to an embodiment; and Figures 8A-8F The steps of a method for manufacturing a NAND flash memory device according to one embodiment are shown; Detailed Implementation

[0046] Figure 1 A schematic diagram of a NAND flash memory device 10 according to one embodiment is shown.

[0047] NAND flash memory device 10 includes: a semiconductor channel layer 12 extending along a first axis; a first dielectric layer 13 disposed above the semiconductor channel layer; a charge storage layer 14 disposed on the first dielectric layer 13; a second dielectric layer 15 disposed on the charge storage layer 14; and a plurality of gate structures 19 disposed along the first axis above the second dielectric layer 15; wherein each gate structure 19 includes a first segment 16 and a second segment 17, wherein the first segment 16 and the second segment 17 are designed to have different work functions, and wherein the first segment 16 and the second segment 17 are disposed next to each other along the first axis.

[0048] Thus, for each gate structure 19, the memory device 10 may have a split-gate design with two segments (segment 16 and segment 17, respectively). The work function (or Fermi level) of one segment 16 may have a beneficial alignment with the second dielectric layer 15 for electron injection; the other segment 17 may have a beneficial alignment with layer 15 for hole injection. During programming (i.e., writing), electrons can be injected into the charge storage layer 14 through the first segment 16, while no significant charge is injected into the other segment 17. During erasure, the opposite is true; holes are now injected through the second segment 17.

[0049] The first dielectric layer can be a barrier oxide layer. For example, the barrier oxide layer prevents charge from leaking from the charge storage layer. The first dielectric layer can be formed of an oxide material (e.g., SiO2), optionally having a high-k liner of Al2O3 or HfO2.

[0050] The second dielectric layer can be a tunneling oxide layer. This tunneling oxide layer allows controlled charge carriers to tunnel during programming and erasing operations. For example, the second dielectric layer is a silicon oxynitride (SiON) layer with a nitrogen content of up to 20%.

[0051] The channel layer 12 may be made of silicon, specifically polycrystalline silicon in a 3D string or monocrystalline silicon in a planar cell. The channel layer 12 may be disposed on a substrate 11 such as an oxide substrate.

[0052] The first axis can correspond to the direction of the channel, that is Figure 1 The x-axis is shown in the Cartesian coordinate system.

[0053] The first segment 16 and the second segment 17 of each gate structure 19 may include different materials and / or different doping.

[0054] For example, the first segment 16 and / or the second segment 17 of each gate structure 19 include polysilicon material, metal, or metal nitride.

[0055] For example, the first segment 16 and the second segment 17 can each be formed from highly doped polysilicon or metal. For such materials, the Fermi level can be significantly biased towards the conduction band (in the case of n-type metal / doped) or significantly biased towards the valence band (in the case of p-type metal / doped). The first segment 16 can be made of an n-type material that is highly favorable for electron injection (e.g., n+ polysilicon), while the second segment 17 can be made of a p-type material that is highly favorable for hole injection (e.g., p+ polysilicon).

[0056] The metal can be any of W, Ti, Ta, Al, Mo, Ru, Co, Cu, Ir, or Pt. The metal nitride can be any of TiN or TaN.

[0057] As an alternative to an all-metal gate or an all-polysilicon gate, the gate may comprise a combination of metal and polysilicon segments. This allows for richer differences in work function between the segments, thus providing a wider optimization window for the injection of both types of charge carriers.

[0058] For example, the work function of the first segment 16 of the corresponding gate structure 19 ranges from 3.5 eV to 5 eV. This facilitates the injection of electrons into the charge storage layer 14 through the first segment 16. The work function of the second segment 17 of the corresponding gate structure 19 can range from 4.5 eV to 6 eV. This facilitates the injection of holes into the charge storage layer 14 through the second segment 17.

[0059] For example, the difference in work function between the first segment 16 and the second segment 17 of the corresponding gate structure 19 is at least 0.5 eV, preferably at least 1 eV. Preferably, the difference is between 1 eV and 2 eV.

[0060] The following table shows exemplary materials for the first segment 16 and / or the second segment 17 and their work functions (WF), with the work function ranges as follows:

[0061] In addition to the material itself, the work function of a material can depend on other factors, such as the deposition method or the layer thickness.

[0062] Optionally, the charge storage layer 14 may include a plurality of gaps 18 arranged to intermittently discontinuously within the charge storage layer 14. The gaps 18 and the gate structure 19 may be arranged alternately along a first axis. In this manner, injected charge carriers (electrons and holes) can be efficiently confined to a finite volume beneath the respective gate. This finite volume may be referred to as the charge trapping region.

[0063] The gap 18 can be formed by a cutout in the charge storage layer 14 (also known as a "charge trapping layer" or CTL), confining the injected carriers to a finite volume below the gate. Since the electric field is highest around the gate corners, carriers are preferentially injected from these corners, meaning that the various main injection points of the carriers to the CTL 14 are separated by the gate length. With gate length miniaturization and the presence of the gap 18 in the CTL 14, carriers can completely occupy this finite volume, allowing recombination to occur as with conventional erasure. For example, without the CTL cutout, the electric field would cause carriers to be pushed towards the gate spacing region, increasing the separation between the two types of carriers. This migration is avoided by forming a charge trapping region via the gap 18.

[0064] like Figure 1 As shown, gap 18 may extend to the second dielectric layer 15. However, gap 18 may also extend to the first dielectric layer 13.

[0065] The gap 18 (CTL notch) can be formed by an air gap. However, the gap 18 may also include an oxide material, or a combination of an air gap and an oxide.

[0066] Figure 2A and 2B Simulation results of memory operation in a NAND flash memory device according to one embodiment are shown.

[0067] Figure 2A and 2B The left figure illustrates programming NAND flash memory with different gate designs using Incremental Stepped Pulse Programming (ISPP). During ISPP, a series of pulses with increasing amplitude are applied to the gate to achieve the target threshold voltage. Therefore, the top left figure shows the threshold voltage offset ΔV relative to the fresh state. T It is the pulse amplitude V PGM The function is shown in the lower left figure. T The corresponding slope changes. The boxes on the right of the two graphs on the left show some simulation parameters.

[0068] Figure 2A and 2B The diagram on the right shows the corresponding erase operation in the same memory structure using the Incremental Step Pulse Erase (ISPE) process.

[0069] Figure 2A The simulation was performed using a NAND flash memory device 10 with three different split-gate structures: - A split gate with a work function difference of -1.1 / 1.1 eV between the first segment 16 and the second segment 17 is marked as SG1 in the figure.

[0070] - A split gate with a work function difference of -0.6 / 0.6 eV between the first section 16 and the second section 17 is marked as SG2 in the figure.

[0071] - The two full-gate references of segments 16 and 17 with the same work function are labeled Ref in the figure.

[0072] Therefore, the values ​​of -1.1 / 1.1 eV and -0.6 / 0.6 eV refer to the Si gap reference. That is, the case of -1.1 / 1.1 eV represents a work function difference of 2.2 eV, while the case of -0.6 / 0.6 eV represents a work function difference of 1.2 eV.

[0073] In each case, segments 16 and 17 have a length of 5 nm along the first axis (channel direction). "10 / 15 nm" in the illustration indicates that the total gate length is 10 nm and the gate pitch is 15 nm.

[0074] Figure 2A Simulation results show that the split-gate design with different work functions achieves significant ISPE improvements at certain scale-down dimensions, trading some ISPP performance for others. However, the split-gate design still achieves an ISPP slope > 1. Simulations also indicate that a larger work function difference between gate segments 16 and 17 improves the benefits.

[0075] Figure 2B The simulations were performed using a NAND flash memory device 10 with six different split-gate configurations having different gate lengths and gate spacings: - The gate length of the split gate is 50 nm, which is divided into two segments 16 and 17 with a width of 25 nm, and is marked as SG'1 in the figure; - The gate length of the split gate is 20 nm, which is divided into two segments 16 and 17 with a width of 10 nm, and is marked as SG'2 in the figure; - The gate length of the split gate is 10 nm, which is divided into two segments 16 and 17 with a width of 5 nm, and is marked as SG'3 in the figure; - Full gate references with the same geometry as SG'1 to SG'3 and no work function difference between gate segments are marked as Ref1 to Ref3 in the figure.

[0076] For each split gate SG'1-SG'3, the work function difference between the first segment 16 and the second segment 17 is -1.1 / 1.1 eV.

[0077] Figure 2B Simulation results show that the split-gate design has significant advantages in ISPE, at the cost of some performance loss in ISPP. Full-gate devices Ref1 to Ref3 exhibit a steep ISPP and low start-up voltage, with the slope becoming steeper and the start-up voltage lower as the gate length decreases. However, the ISPE characteristics of full-gate devices do not provide a significant erase effect, with Ref1, the most miniaturized, even exhibiting slight programming characteristics. For split-gate devices SG'1-SG'3, the ISPP slope is not as steep as that of full-gate devices, and the programming start-up voltage is not as low, but for the gate length with the highest miniaturization, the slope is still greater than 1. However, split gates (especially SG'3 and SG'2) show significant advantages in ISPE characteristics, exhibiting clear erase characteristics similar to conventional channel-side operation.

[0078] These simulation results show that changing the width of the gate segment allows for further optimization of memory operations.

[0079] Figure 3A simulation of charge carrier injection in the charge storage layer 14 beneath the gate structure 19 of a NAND flash memory device 10 according to an embodiment is shown, with particular emphasis on the distribution of trapped charge. Figure 1 on the contrary, Figure 3 In each gate structure 19, the first segment 16 is located on the right side, while the second segment 17 is located on the left side.

[0080] For example, during programming ( Figure 3 On the left side (ISPP), a first bias voltage is applied to at least one of the gate structures 19 to allow negative charge carriers (especially electrons) to be injected through the first segment 16 of the gate structure into the charge storage layer 14 beneath the gate structure. Figure 3 In the simulation, a bias voltage is applied to the central gate structure 19. At least a portion of the injected negative charge carriers are stored in the charge storage layer 14 beneath the gate structure, such as... Figure 3 The charge distribution in the sample is shown in the figure.

[0081] Conversely, during the erasure ( Figure 3 (ISPE on the right side) A second bias voltage is applied to the gate structure 19 to allow positive charge carriers (especially holes) to be injected into the charge storage layer 14 through the second segment 17 of the gate structure. At least a portion of the positive charge carriers recombine with negative charge carriers stored in the charge storage layer 14.

[0082] Figure 3 The captured charge profile confirms that two types of charge carriers (electrons and holes) can be injected from the split gate, with electrons injected from the corner of the gate on the low work function side (e.g., the first segment 16) and holes injected from the corner of the gate on the high work function side (e.g., the second segment 17). Although the main injection sites are separated from each other, the two types of charge carriers are distributed within a finite volume of the charge-trapping region defined by the notch 18 (e.g., the air gap).

[0083] Figure 4 A NAND flash memory device 10 according to one embodiment is shown, wherein a first segment 16 and a second segment 17 of a corresponding gate structure 19 have different widths along a first axis (channel direction).

[0084] This "thickness" of the gate structure or segment can be adapted to the requirements of the ISPP and ISPE characteristics of the memory cell. ISPP operation is usually more critical, so the segment used for electron injection can be larger than the segment used for hole injection.

[0085] Figure 5 A NAND flash memory device 10 according to one embodiment is shown, wherein each gate structure includes a third segment 21 arranged along a first axis next to a second segment 17.

[0086] The third segment 21 can be designed to have a work function that is substantially the same as that of the first segment 16, or to have a work function that differs from that of the first segment 16 by less than 0.1 eV.

[0087] For example, the first segment 16 and the third segment 21 of the corresponding gate structure are made of the same material and / or have the same width along the first axis.

[0088] Sections 16, 17, and 21 can form a sandwich structure, with the electron-injected material located on the outer side (sections 16 and 21) and the hole-injected material located on the inner side (section 17). This provides two corners for electron injection, where the electric field is enhanced. This would be beneficial for programming operations, but likely at the expense of erasing operations. However, in cases where erasing operations are less critical, this is a worthwhile trade-off.

[0089] Figure 6 and 7 Another exemplary NAND memory device 10 with a “sandwich” split gate design is shown.

[0090] In these examples, the isolation layer 22 is arranged between the first gate segment 16 and the second gate segment 17, for example, according to a MIM (metal-insulator-metal) structure.

[0091] exist Figure 6 In the example shown, gap 18 (e.g., an air gap) extends through charge storage layer 14 and the first dielectric layer 13 and the second dielectric layer 15. Figure 7 In the example shown, gap 18 extends only through charge storage layer 14 and second dielectric layer 15.

[0092] In summary, the above design of the NAND flash memory device 10 improves the erase performance in NAND flash memory cells using gate-side injection by dividing the gate into multiple segments or sections. Each segment can be optimized for different types of carrier injection by correctly selecting the work function (in the case of metals) or doping type (in the case of polysilicon).

[0093] It should be noted that, although Figure 1 as well as Figures 3 to 7 The NAND flash memory device 10 is shown as a planar (2D) device, primarily for simplicity. The NAND flash memory device 10 can also have a vertical (3D) design.

[0094] According to another embodiment, the NAND flash memory structure includes a gate structure with an isolation layer 22 disposed between two gate segments 16, 17 made of the same material and / or having substantially the same work function. Thus, for example, only electrons are injected from the gate side for programming (writing). This arrangement of the isolation layer 22 results in a double-slope ISPP curve, where the smaller the width of the isolation layer 22, the more pronounced the high slope.

[0095] Figures 8A-8F The figures illustrate the steps of a method for manufacturing a NAND flash memory device 10 according to one embodiment. These figures are highly schematic and depict exemplary planar (2D) structures. Additional manufacturing steps are added when manufacturing a vertical (3D) memory structure. Figures 8A to 8F (Not shown) may be added, and / or the order of manufacturing steps may be different.

[0096] like Figure 8A As shown, the method includes forming the following layers: a semiconductor channel layer 12 extending along a first axis; a first dielectric layer 13 disposed above the semiconductor channel layer 12; a charge storage layer 14 disposed on the first dielectric layer 13; and a second dielectric layer 15 disposed on the charge storage layer 14. Each of these layers can be formed by a suitable deposition process.

[0097] For example, the semiconductor channel layer 12 may be formed on a substrate 11 such as an oxide substrate.

[0098] In 3D memory design, the channel layer 12, along with layers 13, 14, and 15, can be deposited within memory vias (also called channel holes). The memory vias can be, for example, SiO2 polysilicon or SiN. x Cylindrical holes are etched in a layer stack such as SiO2 stack. The deposition of layers 12-15 in the memory holes can be performed in reverse order, that is, the second dielectric layer 15 can be deposited first, and the channel layer 12 is deposited last in the memory holes. After the deposition of the channel layer 12, the remaining portion of the memory holes can be filled with SiO2 layers.

[0099] The method further includes forming a plurality of gate structures 19 above the second dielectric layer along a first axis, wherein each gate structure includes a first segment 16 and a second segment 17, the first segment 16 and the second segment 17 being designed to have different work functions and arranged next to each other along the first axis.

[0100] Figures 8B to 8E Possible processes for forming these gate structures 19 are shown. In the case of a 3D memory design, the gate structures 19 may be fabricated prior to at least some of the forming layers 12-15.

[0101] like Figure 8BAs shown, a sacrificial layer 81 may be deposited on a second dielectric layer 15, and a first portion of the sacrificial layer 81 may be selectively removed to expose a first region 82. The first region 82 may include a plurality of cavities in the sacrificial layer 81.

[0102] Subsequently, as Figure 8C As shown, the material of the first segment 16 of the gate structure can be deposited in the first region 82, for example, in a cavity.

[0103] Next, as Figure 8D As shown, the second portion of the sacrificial layer 81 can be removed to expose the second region 83, and as... Figure 8E As shown, the material of the second segment 17 of the gate structure can be deposited in the second region 83. The second region 83 may include several cavities in the sacrificial layer 81.

[0104] In this manner, a plurality of gate structures 19 can be formed, wherein each gate structure includes a first segment 16 and a second segment 17, wherein segments 16 and 17 are arranged next to each other along a first axis and are designed to have different work functions.

[0105] For example, Figures 8B to 8E The process steps shown correspond to a replacement metal gate (RMG) process, in which the etch rate of the sacrificial layer 81 is differentiated. For example, the first and second portions of the sacrificial layer 81 are each removed by etching with an etchant, wherein the first portion is etched at a higher etch rate than the second portion.

[0106] One way to achieve this is to change the composition of the sacrificial layer, such as the nitrogen content in a SiN sacrificial layer. The RMG process can be performed in two steps: first, the high-etch-rate portion of the sacrificial layer 81 is etched, and then the material of the first segment 16 (e.g., the first gate metal) is deposited, such as... Figure 8B and 8C As shown. This is followed by etching of the low-etch-rate portion of the sacrificial layer 81 and deposition of material (e.g., second gate metal) in the second segment 17, as... Figure 8D and 8E As shown. Between these two steps, the material in the first segment 16 of the RMG trench can be etched back, so that it exists only in the gate cavity. Subsequently, the material in the second segment 17 can fill the remaining portion of the gate cavity and the RMG trench.

[0107] like Figure 8F As shown, the method further includes a step of forming a plurality of gaps 18 in the charge storage layer 14, wherein the gaps 18 are arranged to discontinuity in the charge storage layer 14, and wherein the gaps 18 are arranged alternately with the gate structure 19 along a first axis (channel direction). The gaps 18 may also be formed in an earlier step (e.g., before the gate structure 19 is formed).

[0108] In the case of 3D memory design, gap 18 can be an air gap structure formed on the sidewall of the memory hole. For example, the basic steps for forming a 3D NAND memory structure with such an air gap structure include the following steps: forming a layer stack over a substrate, the layer stack comprising an alternating sequence of gate layers and gate spacer layers; forming a first recessed region in the sidewalls surrounding the memory aperture by laterally etching back the gate layer from the memory aperture of the layer stack; forming a lateral memory stack in each of the first recessed regions by depositing a barrier oxide layer and subsequently depositing a charge trapping material; forming a second recessed region in the sidewalls by laterally etching back the gate spacer layer from the memory aperture; forming a dummy layer in the second recessed region; after forming the lateral memory stack and the dummy layer, lining the sidewalls of the memory aperture with a liner; after lining the sidewalls, subjecting the dummy layer to a thermal processing step suitable for converting each dummy layer into an air gap structure, wherein the air gap structure is laterally formed between the liner and the gate spacer layer; forming a tunneling oxide layer along the liner in the memory aperture; and forming a channel layer along the tunneling oxide layer. Here, the phrase "air gap structure" refers to the space or gap enclosed by a pair of lateral memory stacks, a liner, and a gate spacer layer.

[0109] Here, a layer stack can be formed on a substrate and includes an alternating sequence of gate layers and gate spacer layers. The gate layer can be a nitride-containing layer (such as a SiN layer), thus forming a sacrificial gate layer intended to be replaced by an RMG stack in subsequent process steps. The gate spacer layers can be oxide-containing layers, such as SiO2 layers or another suitable interlayer dielectric (e.g., low-k). The liner can be a low-thermal oxide (LTO) layer, such as LTO SiO2.

[0110] The heat treatment that converts each dummy layer into an air gap structure can be achieved by performing thermal annealing (e.g., in a reaction chamber or furnace). As those skilled in the art will know, the thermal energy required to achieve a sufficient conversion rate depends on the specific dummy material of the dummy layer. For example, for any of the dummy materials described above, heating the structure or its surrounding environment to approximately 500°C will generally be sufficient to completely convert the dummy layer without leaving significant residue in the resulting air gap.

[0111] The lateral depth or extension of the air gap structure is determined by the lateral thickness or extension of the dummy layer, and correspondingly by the lateral depth or extension of the second recessed area.

[0112] In the claims and in the description herein, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plural. A single element may perform the function of several entities or items recited in the claims. The mere fact that certain measures are stated in mutually different dependent claims does not imply that combinations of these measures cannot be used in an advantageous implementation.

Claims

1. A NAND flash memory device (10), comprising: Semiconductor channel layer (12) extending along the first axis; A first dielectric layer (13) disposed above the semiconductor channel layer (12); A charge storage layer (14) is disposed on the first dielectric layer (13). A second dielectric layer (15) disposed on the charge storage layer (14); and A plurality of gate structures (19) are arranged above the second dielectric layer (15) and along the first axis. Each gate structure (19) includes a first segment (16) and a second segment (17), wherein the first segment (16) and the second segment (17) are designed to have different work functions, and wherein the first segment (16) and the second segment (17) are arranged next to each other along the first axis.

2. The NAND flash memory device (10) according to claim 1. The charge storage layer (14) includes a plurality of gaps (18) arranged to discontinuate the charge storage layer (14); The gap (18) and the gate structure (19) are arranged alternately along the first axis.

3. The NAND flash memory device (10) according to claim 2. Its features are, The gap (18) is at least partially filled with air and / or oxide material.

4. The NAND flash memory device (10) according to any one of the preceding claims. Its features are, The charge storage layer (14) comprises silicon nitride material.

5. The NAND flash memory device (10) according to any one of the preceding claims. The work function of the first segment (16) of the corresponding gate structure (19) ranges from 3.5 eV to 5 eV; and / or The work function of the second segment (17) of the corresponding gate structure (19) ranges from 4.5 eV to 6 eV.

6. The NAND flash memory device (10) according to any one of the preceding claims. Its features are, The difference in work function between the first segment (16) and the second segment (17) of the corresponding gate structure (19) is at least 0.5 eV, preferably at least 1 eV.

7. The NAND flash memory device (10) according to any one of the preceding claims. Its features are, The first segment (16) and the second segment (17) of the corresponding gate structure (19) include different materials and / or different doping.

8. The NAND flash memory device (10) according to any one of the preceding claims. Its features are, The first segment (16) and / or the second segment (17) of the corresponding gate structure (19) include polysilicon material, metal, or metal nitride.

9. The NAND flash memory device according to any one of the preceding claims (10). Its features are, The first segment (16) and the second segment (17) of the corresponding gate structure (19) have different widths along the first axis.

10. The NAND flash memory device according to any one of the preceding claims (10). Its features are, The corresponding gate structure (19) includes an isolation layer disposed between the first segment (16) and the second segment (17).

11. The NAND flash memory device (10) according to any one of the preceding claims. Each gate structure (19) includes a third segment (21) arranged along the first axis next to the second segment (17); The third segment (21) is designed to have the same work function as the first segment (16), or the third segment (21) is designed to have a work function with a difference of less than 0.1 eV from the work function of the first segment (16).

12. A method for operating a NAND flash memory device (10) according to any one of the preceding claims, characterized in that, The method includes: A first bias voltage is applied to at least one of the gate structures (19) to allow negative charge carriers, particularly electrons, to be injected through a first segment (16) of the gate structure into a charge storage layer (14) beneath the gate structure (19), wherein at least a portion of the negative charge carriers are stored in the charge storage layer (14); and A second bias is applied to at least one of the gate structures (19) to allow positive charge carriers, especially holes, to be injected through a second segment (17) of the gate structure into a charge storage layer (14) below the gate structure (19), wherein at least a portion of the positive charge carriers recombine with negative charge carriers stored in the charge storage layer (14).

13. A method for manufacturing a NAND flash memory device (10), the method comprising: A semiconductor channel layer (12) extending along the first axis is formed. A first dielectric layer (13) is formed above the semiconductor channel layer (12); A charge storage layer (14) is formed on the first dielectric layer (13). A second dielectric layer (15) is formed on the charge storage layer (14); and Multiple gate structures (19) are formed above the second dielectric layer (15) and arranged along the first axis. Each gate structure (19) includes a first segment (16) and a second segment (17), wherein the first segment (16) and the second segment (17) are designed to have different work functions, and wherein the first segment (16) and the second segment (17) are arranged next to each other along the first axis.

14. The method according to claim 13, characterized in that, Also includes: Multiple gaps (18) are formed in the charge storage layer (14); The gap (18) is arranged to discontinuate the charge storage layer (14); and The gap (18) and the gate structure (19) are arranged alternately along the first axis.

15. The method according to claim 13 or 14, Its features are, The formation of the corresponding gate structure (19) includes: A sacrificial layer (81) is deposited above the second dielectric layer (15); Selectively remove a first portion of the sacrificial layer to expose a first region (82), and deposit material of a first segment (16) of the gate structure in the first region (82); and The second portion of the sacrificial layer (81) is removed to expose the second region (83), and the material of the second segment (17) of the gate structure is deposited in the second region (83).

16. The method according to claim 15, Its features are, The first and second portions of the sacrificial layer (81) are each removed by etching with an etchant, wherein the first portion is designed to be etched at a higher etch rate than the second portion.

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