Ferroelectric memory, chip package structure and electronic device

Abstract

This application provides a ferroelectric memory, a chip packaging structure, and an electronic device. The ferroelectric memory provided includes a selector component, a first electrode, a second electrode, and a ferroelectric layer, with the ferroelectric layer and the selector component located between the first and second electrodes. The selector component includes: a semiconductor layer in contact with the ferroelectric layer; an insulating layer in contact with the semiconductor layer and the first electrode; and the ferroelectric layer in contact with the second electrode. In this ferroelectric memory, the selector component is connected to the ferroelectric layer through the semiconductor layer, forming a metal-ferroelectric-semiconductor-insulator-metal structure. The selector component can achieve current nonlinearity and capacitive voltage division benefits, while the ferroelectric layer further provides positive feedback to increase the nonlinear benefits of the selector. Thus, while meeting the storage requirements for normal ferroelectric switching, it achieves better selectivity characteristics, reduces the impact of half-selection interference, and improves the anti-interference capability of the ferroelectric memory.

Description

Technical Field

[0001] This application relates to the field of storage, and more particularly to a ferroelectric memory, a chip packaging structure, and an electronic device. Background Technology

[0002] Existing ferroelectric memories (FEMs) store information using two opposite ferroelectric polarization directions under ±Vop. During writing, +Vop (-Vop) is applied to store a 1 (or 0), and during reading, -Vop is applied to detect the presence or absence of polarization switching current to read a 1 (or 0). To achieve high-density storage, array structures such as crossbar arrays are often used to miniaturize each ferroelectric cell to 4F2. However, this also introduces voltage interference problems, such as erroneous switching during half-selection, resulting in poor anti-interference capabilities of the FEM. Existing FEMs can suppress interference by using an external series nonlinear selector connected to a metal wire. However, the series selector is mainly based on metal-insulator-metal (MIM) materials. Limited by the tunneling properties of MIM materials, achieving high nonlinearity is difficult, thus resulting in poor anti-interference capabilities of the FEM. Summary of the Invention

[0003] This application provides a ferroelectric memory, a chip packaging structure, and an electronic device to solve the problem of poor anti-interference capability of ferroelectric memory caused by voltage interference in high-density storage.

[0004] In a first aspect, this application provides a ferroelectric memory, comprising a selector assembly, a first electrode, a second electrode, and a ferroelectric layer, wherein the ferroelectric layer and the selector assembly are located between the first electrode and the second electrode; the selector assembly includes: a semiconductor layer in contact with the ferroelectric layer; an insulating layer in contact with the semiconductor layer and the first electrode; and the ferroelectric layer in contact with the second electrode.

[0005] In the low bias (half-select) state provided by this application, due to the low conductivity and non-conductivity, and the small capacitance and large voltage division of the selector itself, a small proportion of the applied voltage acts on the ferroelectric layer. The ferroelectric layer is less likely to flip and change the stored information, thereby improving the anti-interference capability of the ferroelectric layer. Furthermore, in the ferroelectric memory with this selector in this application, the selector composed of a semiconductor layer and an insulating layer is connected to the ferroelectric layer through the semiconductor layer to form a metal-ferroelectric-semiconductor-insulator-metal (MFSIM) structure. The selector can achieve current nonlinearity and capacitive voltage division benefits, while the ferroelectric layer further promotes the selector to increase nonlinearity benefits. Thus, while meeting the storage requirements of normal ferroelectric flipping, a better selection characteristic is achieved to reduce the impact of half-select interference and improve the anti-interference capability of the ferroelectric memory.

[0006] In one possible implementation of the first aspect, the first electrode, the insulating layer, the semiconductor layer, the ferroelectric layer, and the second electrode are stacked sequentially.

[0007] In one possible implementation of the first aspect, the first electrode, the insulating layer, the semiconductor layer, the ferroelectric layer, and the second electrode are arranged sequentially around each other from the inside out or from the outside in;

[0008] Alternatively, the first electrode, the ferroelectric layer, the semiconductor layer, the insulating layer, and the second electrode are arranged sequentially from the outside to the inside.

[0009] In one possible implementation of the first aspect, the insulating layer is made of at least one of silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), or hexagonal boron nitride (h-BN). In one possible implementation of the first aspect, the semiconductor layer is made of a single-element semiconductor material.

[0010] In one possible implementation of the first aspect, the elemental semiconductor material includes at least one of silicon (Si) and germanium (Ge).

[0011] In one possible implementation of the first aspect, the material of the semiconductor layer includes an alloy material.

[0012] In one possible implementation of the first aspect, the alloy material includes germanium-silicon (SiGe).

[0013] In one possible implementation of the first aspect, the material of the semiconductor layer includes a III-V compound.

[0014] In one possible implementation of the first aspect, the III-V compound includes at least one of gallium arsenide (GaAs) and indium phosphide (InP).

[0015] In one possible implementation of the first aspect, the material of the semiconductor layer includes a wide-gap semiconductor material.

[0016] In one possible implementation of the first aspect, the wide-gap semiconductor material includes at least one of zinc oxide (ZnO), gallium nitride (GaN), niobium pentoxide (Nb₂O₅), titanium dioxide (TiO₂), tantalum pentoxide (Ta₂O₅), nickel oxide (NiO), or silicon carbide (SiC).

[0017] In one possible implementation of the first aspect, the material of the semiconductor layer includes a two-dimensional semiconductor material.

[0018] In one possible implementation of the first aspect, the two-dimensional semiconductor material includes at least one of molybdenum disulfide (MoS2) and tungsten diselenide (WSe2).

[0019] In one possible implementation of the first aspect, the material of the ferroelectric layer includes at least one of hafnium zirconium oxide (HfZrO) and lead zirconate titanate (PZT).

[0020] In one possible implementation of the first aspect, the thickness of the semiconductor layer is 1–10 nm, the thickness of the insulating layer is 1–4 nm, and the thickness of the ferroelectric layer is 4–50 nm.

[0021] In one possible implementation of the first aspect, the thickness of the semiconductor layer is 1–2.5 nm, and the thickness of the insulating layer is 0.5–2 nm.

[0022] It should be noted that by controlling the thickness of the semiconductor layer and the insulating layer within the above-mentioned range, such as within the range of 3nm, the tunneling efficiency is higher, which can make the ferroelectric storage faster and is conducive to achieving high-speed read and write.

[0023] In one possible implementation of the first aspect, the material of the first electrode or the second electrode is graphene, heavily doped silicon, gold (Au), or aluminum.

[0024] At least one of Al, copper Cu, tungsten W, titanium nitride TiN, or tantalum nitride TaN.

[0025] Secondly, this application provides a method for fabricating a ferroelectric memory, comprising: forming a stacked structure of a first electrode, a second electrode, a ferroelectric layer, and a selector assembly; the ferroelectric layer and the selector assembly being located between the first electrode and the second electrode; the selector assembly comprising: a semiconductor layer in contact with the ferroelectric layer; an insulating layer in contact with the semiconductor layer and in contact with the first electrode; and the ferroelectric layer in contact with the second electrode.

[0026] In the low bias (half-select) state provided by this application, due to the low conductivity and non-conductivity, and the small capacitance and large voltage division of the selector itself, a small proportion of the applied voltage acts on the ferroelectric layer. The ferroelectric layer is less likely to flip and change the stored information, thereby improving the anti-interference capability of the ferroelectric layer. Furthermore, in the ferroelectric memory with this selector in this application, the selector composed of a semiconductor layer and an insulating layer is connected to the ferroelectric layer through the semiconductor layer to form a metal-ferroelectric-semiconductor-insulator-metal (MFSIM) structure. The selector can achieve current nonlinearity and capacitive voltage division benefits, while the ferroelectric layer further promotes the selector to increase nonlinearity benefits. Thus, while meeting the storage requirements of normal ferroelectric flipping, a better selection characteristic is achieved to reduce the impact of half-select interference and improve the anti-interference capability of the ferroelectric memory.

[0027] In one possible implementation of the second aspect of this application, the method for fabricating a ferroelectric memory includes: forming a second electrode; forming an insulating layer on one side of the second electrode, with the second electrode in contact with the insulating layer; forming a semiconductor layer on the side of the insulating layer away from the second electrode, with the insulating layer in contact with the semiconductor layer; forming a ferroelectric layer on the side of the semiconductor layer away from the insulating layer, with the semiconductor layer in contact with the ferroelectric layer; and forming a first electrode on the side of the ferroelectric layer away from the semiconductor layer, with the first electrode in contact with the ferroelectric layer.

[0028] In one possible implementation of the second aspect of this application, the method for fabricating a ferroelectric memory includes: forming a first electrode; forming an insulating layer, wherein the first electrode is disposed in contact with the insulating layer; forming a semiconductor layer, wherein the insulating layer is disposed in contact with the semiconductor layer; forming a ferroelectric layer, wherein the semiconductor layer is disposed in contact with the ferroelectric layer; and forming a second electrode, wherein the ferroelectric layer is disposed in contact with the second electrode.

[0029] In one possible implementation of the second aspect of this application, the method for fabricating a ferroelectric memory includes: forming a first electrode; forming a ferroelectric layer, wherein the first electrode is disposed in contact with the ferroelectric layer; forming a semiconductor layer, wherein the ferroelectric layer is disposed in contact with the semiconductor layer; forming an insulating layer, wherein the semiconductor layer is disposed in contact with the insulating layer; and forming a second electrode, wherein the insulating layer is disposed in contact with the second electrode.

[0030] Thirdly, a ferroelectric memory chip includes a processor and a ferroelectric memory as provided in the first aspect of this application, wherein the processor and the ferroelectric memory are electrically connected.

[0031] Fourthly, this application provides a chip packaging structure, the semiconductor packaging structure including a substrate and a ferroelectric memory chip as described in the third aspect of this application, the substrate and the ferroelectric memory chip being electrically connected.

[0032] Fifthly, this application provides an electronic device, including a circuit board and a chip package structure as provided in the fourth aspect of this application, wherein the circuit board and the semiconductor package structure are electrically connected. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of an electronic device provided in an embodiment of this application;

[0034] Figure 2a This is a schematic diagram of the structure of a ferroelectric memory provided in an embodiment of this application;

[0035] Figure 2b This is a circuit structure diagram of a memory cell provided in this application;

[0036] Figure 2c This is a circuit diagram of a memory array provided in this application;

[0037] Figure 3 This is a schematic diagram of the structure of a ferroelectric memory provided in this application;

[0038] Figure 4 This is a schematic diagram of another ferroelectric memory provided in this application;

[0039] Figure 5 This is a schematic diagram of the interface of another ferroelectric memory provided in this application;

[0040] Figure 6 This is a schematic diagram of another ferroelectric memory provided in this application;

[0041] Figure 7a This is a schematic diagram of the band structure of a selector provided in this application;

[0042] Figure 7b This is a schematic diagram showing the relationship between the band structure and the width of each component of a selector provided in this application;

[0043] Figure 7c This is a schematic diagram illustrating the relationship between the capacitance value and voltage of a selector provided in this application;

[0044] Figure 7d This is a schematic diagram illustrating the relationship between the conductance and voltage values ​​of a selector provided in this application;

[0045] Figure 7e This is a schematic diagram showing the relationship between the proportion of ferroelectric voltage division to applied voltage and time in a selector provided in this application;

[0046] Figure 8a This is a PV schematic diagram of a ferroelectric memory provided in this application;

[0047] Figure 8bThis is a schematic diagram showing the relationship between the energy bands and the widths of various structures in a ferroelectric memory provided in this application.

[0048] Figure 8c This is a schematic diagram illustrating the relationship between the capacitance value and voltage of a ferroelectric memory provided in this application;

[0049] Figure 8d This is a schematic diagram illustrating the relationship between the conductivity and voltage of a ferroelectric memory provided in this application;

[0050] Figures 9a-9e This is a schematic diagram of a method for fabricating a ferroelectric memory provided in this application;

[0051] Figure 9f This is a flowchart of a method for fabricating a ferroelectric memory provided in this application;

[0052] Figures 10a-10e This is a schematic diagram of another method for preparing ferroelectric memory provided in this application;

[0053] Figure 10f This is a flowchart of another method for preparing ferroelectric memory provided in this application. Detailed Implementation

[0054] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0055] In the following description, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0056] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0057] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0058] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0059] Exemplary embodiments are described in this application with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0060] The ferroelectric memory provided in this application can be applied to high-density storage such as DRAM, system-on-a-chip (SoC), high-performance computing (HPC), and various near-memory computing, in-memory computing (PIM), and in-memory computing systems; the application scenarios are terminal devices such as mobile phones, PCs, and servers that include the above system architecture.

[0061] Figure 1An electronic device 200 is provided for embodiments of this application. This electronic device 200 can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, or a communication electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle high-density digital video discs (DVDs), etc. Financial terminal products include automated teller machines (ATMs), self-service terminals, etc. Communication electronics products include servers, storage devices, radar, base stations, and other communication equipment. The embodiments of this application do not impose any special restrictions on the specific form of the above-mentioned electronic devices.

[0062] Electronic device 200 includes a bus 205, and a system-on-chip (SOC) 210 and a read-only memory (ROM) 220 connected to the bus 205. The SOC 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. The ROM 220 can be used to store non-volatile data, such as audio files and video files. The ROM 220 can be a PROM (programmable read-only memory), an EPROM (erasable programmable read-only memory), flash memory, etc. In addition, electronic device 200 may also include a communication chip 230 and a power management chip 240. The communication chip 230 can be used for protocol stack processing, or for amplifying and filtering analog radio frequency signals, or simultaneously performing the above functions. The power management chip 240 can be used to supply power to other chips.

[0063] In one implementation, the SOC210 may include an application processor (AP) for processing applications.

[0064] 211 is an image processing unit (GPU) 212 for processing image data, and 213 is random access memory (RAM) 213 for caching data. The aforementioned AP 211, GPU 212, and RAM 213 can be integrated into a single die, or integrated into multiple dies and packaged in a single package structure, such as using 2.5D, 3D packaging, or other advanced packaging technologies. In one embodiment, the AP 211 and GPU 212 are integrated into one die, and RAM 213 is integrated into another die; these two dies are packaged in a single package structure to achieve faster inter-die data transfer rates and higher data transfer bandwidth.

[0065] Figure 2a This is a schematic diagram of the structure of a ferroelectric memory chip provided in an embodiment of this application. The ferroelectric memory chip 1 can be as follows: Figure 1 The RAM213 shown is referenced. Figure 2aAs shown, the ferroelectric memory chip 1 includes a memory array 11 and peripheral circuitry 12. The peripheral circuitry 12 includes one or more of the following circuit structures: a decoder 121, a driver 122, a timing controller 123, a buffer 124, or an input / output driver 125. In one embodiment, the memory array 11 includes multiple memory cells 10 arranged in an array. Each memory cell 10 may include a gating transistor and at least one ferroelectric memory. Each memory cell 10 can be used to store 1 bit or more bits of data. The memory cell 10 may also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 10 is electrically connected to a corresponding signal line (WL, BL, etc.). By receiving the control level output from one or more of the signal lines such as word lines WL and bit lines BL, the memory cell 10 to be read or written in the memory array 11 is selected, thereby changing the polarization direction of the ferroelectric memory in the memory cell 10, thus realizing data read / write operations. The decoder 121 is used to decode the address of the memory cell 10. Decoder 121 decodes the received address to determine the memory cell 10 to be accessed. Driver 122 controls the signal line level based on the decoding result generated by decoder 121, thereby enabling access to the specified memory cell 10. Buffer 124 buffers the read data, for example, using FIFO (first-in first-out). Timing controller 123 controls the timing of buffer 124 and controls driver 122 to drive the signal lines in memory array 11. Input / output driver 125 drives transmission signals, such as the received data signal and the data signal to be sent, enabling long-distance transmission of data signals. The storage principle of ferroelectric memory chips is to change the polarization direction of the ferroelectric memory through an electric field, thereby storing different amounts of charge to represent different data storage states. Since the polarization direction of the ferroelectric memory can be maintained after the electric field is removed, ferroelectric memory chips are non-volatile memories, and the stored data can be retained for a long time without periodic refresh, thus significantly reducing power consumption. The aforementioned memory array 11 can be integrated with one or more circuit structures in the peripheral circuit 12 (i.e., one or more of 121, 122, 123, 124, 125) into a single memory chip.

[0066] Figure 2b The circuit structure diagram of one of the storage cells 10 of FeRAM is given, as follows: Figure 2b The memory cell 10 includes at least two ferroelectric memories C and one transistor Tr, for example, Figure 2b Three ferroelectric memories (e.g.) are given as examples. Figure 2bFerroelectric memories C1, C2, and C3). Here, transistor Tr can be a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0067] In addition, the memory cell 10 also includes word line (WL), bit line (BL), and plate line (PL) signal lines. In this memory cell 10, the first terminal of transistor Tr is electrically connected to the bit line BL, the control terminal of transistor Tr is electrically connected to the word line WL, the second terminal of transistor Tr is electrically connected to the first electrode of the ferroelectric memory C, and the second electrode of the ferroelectric memory C is electrically connected to the plate line PL. One of the drain or source terminals of transistor Tr is called the first terminal, and the corresponding other terminal is called the second terminal. The control terminal of transistor Tr is the gate.

[0068] Figure 2b The illustrated memory cell 10 can be used to store multiple bits of data, thereby increasing the storage capacity of each memory cell. In particular, these ferroelectric memories C share a single transistor Tr, which further reduces the number of transistors in each memory cell 10, thereby increasing storage density.

[0069] The above Figure 2b The storage cells 10 shown can be arranged in an array to form a storage array, wherein each storage cell 10 has the same circuit structure, for example, Figure 2c The illustrated storage array exemplarily includes four storage cells: storage cell 101, storage cell 102, storage cell 103, and storage cell 104. Those skilled in the art can design the arrangement and number of storage cells 10 in the storage array according to the storage capacity requirements of the ferroelectric memory chip. In one embodiment, the storage array may further include more storage cells 10, and these storage cells 10 may be arranged in mutually perpendicular X, Y, and Z directions to form a three-dimensional storage array.

[0070] like Figure 3 The diagram shown is a structural schematic of a ferroelectric memory 30 provided in this application. This ferroelectric memory 30 can be applied in… Figures 2a-2cThe ferroelectric memory 30, as shown in the diagram, comprises a first electrode 301, a second electrode 305, a ferroelectric layer 304, and a selector assembly 300. The selector assembly 300 includes a semiconductor layer 303 and an insulating layer 302. Further, ignoring the polarization effect of the ferroelectric layer 304, the selector assembly, the first electrode 301, and the second electrode 305 form a selector. The semiconductor layer 303 and the insulating layer 302 are disposed between the first electrode 301 and the ferroelectric layer 304, or alternatively between the second electrode 305 and the ferroelectric layer 304. It should be noted that in both of these arrangements, the insulating layer 302 contacts the first electrode 301, the semiconductor layer 303 contacts the ferroelectric layer 304, and the ferroelectric layer 304 contacts the second electrode 305.

[0071] In one possible implementation, the ferroelectric memory 30 is formed by stacking a first electrode 301, an insulating layer 302, a semiconductor layer 303, a ferroelectric layer 304, and a second electrode 305 from top to bottom. The insulating layer 302 is in contact with the first electrode 301, and the semiconductor layer 303 is in contact with the ferroelectric layer 304.

[0072] Specifically, the materials of each layer of the ferroelectric memory 30 are shown in the following examples:

[0073] In one example, the first electrode 301 and the second electrode 305 are both metals, such as gold (Au), aluminum (Al), copper (Cu), tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN). In another example, the first electrode 301 and the second electrode 305 are doped semiconductors with good conductivity. In yet another example, the first electrode 301 and the second electrode 305 are half-metallic graphene.

[0074] Ferroelectric layer 304, in one example, is a ferroelectric material, such as hafnium zirconium oxide (HfZrO) or lead zirconate titanate (PZT); in another example, ferroelectric layer 304 is a two-dimensional ferroelectric material, such as indium selenide (α-In2Se3).

[0075] Semiconductor layer 303, in one example, is a single-element semiconductor material, such as silicon (Si) or germanium (Ge); in another example, semiconductor layer 303 can be a group IIIV compound, such as gallium arsenide (GaAs) or indium phosphide (InP); in yet another example, semiconductor layer 303 is a wide-gap semiconductor material, such as zinc oxide (ZnO), gallium nitride (GaN), niobium pentoxide (Nb₂O₅), titanium dioxide (TiO₂), tantalum pentoxide (Ta₂O₅), nickel oxide (NiO), or silicon carbide (SiC); in yet another embodiment, semiconductor layer 303 is a two-dimensional semiconductor material, such as molybdenum disulfide (MoS₂) or tungsten diselenide (WSe₂).

[0076] In one example, insulating layer 302 is a three-dimensional material, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO2). In another example, insulating layer 302 is a two-dimensional insulating material, such as hexagonal boron nitride (h-BN).

[0077] In another possible implementation, the ferroelectric memory 30 layers are stacked from top to bottom as a first electrode 301, a ferroelectric layer 304, a semiconductor layer 303, an insulating layer 302, and a second electrode 305. The insulating layer 302 is in contact with the first electrode 301, and the semiconductor layer 303 is in contact with the ferroelectric layer 304.

[0078] Specifically, the materials of each layer of the ferroelectric memory 30 are shown in the following examples:

[0079] In one example, the first electrode 301 and the second electrode 305 are both metals, such as gold (Au), aluminum (Al), copper (Cu), tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN). In another example, the first electrode 301 and the second electrode 305 are doped semiconductors with good conductivity. In yet another example, the first electrode 301 and the second electrode 305 are half-metallic graphene.

[0080] Ferroelectric layer 304, in one example, is a ferroelectric material, such as hafnium zirconium oxide (HfZrO) or lead zirconate titanate (PZT); in another example, ferroelectric layer 304 is a two-dimensional ferroelectric material, such as indium selenide (α-In2Se3).

[0081] Semiconductor layer 303, in one example, is a single-element semiconductor material, such as silicon (Si) or germanium (Ge); in another example, semiconductor layer 303 can be a group IIIV compound, such as gallium arsenide (GaAs) or indium phosphide (InP); in yet another example, semiconductor layer 303 is a wide-gap semiconductor material, such as zinc oxide (ZnO), gallium nitride (GaN), niobium pentoxide (Nb2O5), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), nickel oxide (NiO), or silicon carbide (SiC); in yet another embodiment, semiconductor layer 303 is a two-dimensional semiconductor material, such as molybdenum disulfide (MoS2) or tungsten diselenide (WSe2).

[0082] In one example, insulating layer 302 is a three-dimensional material, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO2). In another example, insulating layer 302 is a two-dimensional insulating material, such as hexagonal boron nitride (h-BN).

[0083] like Figure 4 The diagram shown is a structural schematic of another ferroelectric memory 40 provided in this application. It can be seen that... Figure 4 This is a top view of the ferroelectric memory 40 structure, and... Figure 3 The difference between the embodiments shown is that, Figure 4 The capacitor structure shown is cylindrical, or it can be understood as a concentric ring structure.

[0084] To further illustrate Figure 4 The complete structure of the ferroelectric memory shown is as follows: Figure 5 The image shown is a cross-sectional view of the ferroelectric memory 40 along the A-A' tangent.

[0085] pass Figure 4 , Figure 5 It can be seen that this ferroelectric memory 40 can be applied in... Figures 2a-2c The ferroelectric memory 40 is shown in the memory cell. The structure of the ferroelectric memory 40 includes a first electrode 301, a second electrode 305, a ferroelectric layer 304, and a selector assembly 300. The selector assembly 300 includes a semiconductor layer 303 and an insulating layer 302. Furthermore, ignoring the polarization effect of the ferroelectric layer 304, the selector assembly, the first electrode 301, and the second electrode 305 form a selector.

[0086] In one possible implementation, Figure 4 That is, a top view schematic diagram of this implementation, the second electrode 305 is located at the center of concentric circles, the ferroelectric layer 304 is disposed around the second electrode 305 and in contact with the second electrode 305; the semiconductor layer 303 is disposed around the ferroelectric layer 304 and in contact with the ferroelectric layer 304; the insulating layer 302 is disposed around the semiconductor layer 303 and in contact with the semiconductor layer 303; the first electrode 301 is disposed around the insulating layer 302 and in contact with the insulating layer 302. Figure 5 It can be seen that the first electrode 301, the insulating layer 302, the semiconductor layer 303, and the ferroelectric layer 304 are axially symmetrical about the center line of the second electrode 305 along the thickness direction of the ferroelectric memory.

[0087] In another possible implementation, the second electrode 305 is located at the center of concentric circles, the insulating layer 302 is disposed around the second electrode 305 and in contact with the second electrode 305; the semiconductor layer 303 is disposed around the insulating layer 302 and in contact with the insulating layer 302; the ferroelectric layer 304 is disposed around the semiconductor layer 303 and in contact with the semiconductor layer 303; and the first electrode 301 is disposed around the ferroelectric layer 304 and in contact with the ferroelectric layer 304. This implementation is achieved through... Figure 4 A reasonable derivation can yield a top-down structural diagram of this implementation method.

[0088] Specifically, the materials of each layer of the ferroelectric memory 40 are shown in the following example:

[0089] In one example, the first electrode 301 and the second electrode 305 are both metals, such as gold (Au), aluminum (Al), copper (Cu), tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN). In another example, the first electrode 301 and the second electrode 305 are doped semiconductors with good conductivity. In yet another example, the first electrode 301 and the second electrode 305 are half-metallic graphene.

[0090] Ferroelectric layer 304, in one example, is a ferroelectric material, such as hafnium zirconium oxide (HfZrO) or lead zirconate titanate (PZT); in another example, ferroelectric layer 304 is a two-dimensional ferroelectric material, such as indium selenide (α-In2Se3).

[0091] Semiconductor layer 303, in one example, is a single-element semiconductor material, such as silicon (Si) or germanium (Ge); in another example, semiconductor layer 303 can be a group IIIV compound, such as gallium arsenide (GaAs) or indium phosphide (InP); in yet another example, semiconductor layer 303 is a wide-gap semiconductor material, such as zinc oxide (ZnO), gallium nitride (GaN), niobium pentoxide (Nb₂O₅), titanium dioxide (TiO₂), tantalum pentoxide (Ta₂O₅), nickel oxide (NiO), or silicon carbide (SiC); in yet another embodiment, semiconductor layer 303 is a two-dimensional semiconductor material, such as molybdenum disulfide (MoS₂) or tungsten diselenide (WSe₂).

[0092] In one example, insulating layer 302 is a three-dimensional material, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO2). In another example, insulating layer 302 is a two-dimensional insulating material, such as hexagonal boron nitride (h-BN).

[0093] like Figure 6 The diagram shown is a structural schematic of another ferroelectric memory 50 provided in this application. This ferroelectric memory 50 can be applied in... Figures 2a-2c The ferroelectric memory 50, as shown in the diagram, comprises a first electrode 301, a second electrode 305, a ferroelectric layer 304, and a selector assembly 300. The selector assembly 300 includes a semiconductor layer 303 and an insulating layer 302. Further, ignoring the polarization effect of the ferroelectric layer 304, the selector assembly, the first electrode 301, and the second electrode 305 form a selector. The semiconductor layer 303 and the insulating layer 302 are disposed between the first electrode 301 and the ferroelectric layer 304, or alternatively between the second electrode 305 and the ferroelectric layer 304. It should be noted that in both of these arrangements, the insulating layer 302 contacts either the first electrode 301 or the second electrode 305, the semiconductor layer 303 contacts the ferroelectric layer 304, and the ferroelectric layer 304 contacts the second electrode 305.

[0094] The ferroelectric memory 50 structure is similar to Figure 3 The ferroelectric memory 30 shown is different in that... Figure 3 The ferroelectric memory 30 shown is a structure grown in a vertical direction, while Figure 6 The ferroelectric memory 50 shown is a structure that grows in a horizontal direction.

[0095] In one possible implementation, the ferroelectric memory 50 is formed from right to left by a first electrode 301, an insulating layer 302, a semiconductor layer 303, a ferroelectric layer 304, and a second electrode 305, with the insulating layer 302 in contact with the first electrode 301 and the semiconductor layer 303 in contact with the ferroelectric layer 304.

[0096] In another possible implementation, the ferroelectric memory 30 layers are grown from right to left as a first electrode 301, a ferroelectric layer 304, a semiconductor layer 303, an insulating layer 302, and a second electrode 305. The insulating layer 302 is in contact with the first electrode 301, and the semiconductor layer 303 is in contact with the ferroelectric layer 304.

[0097] Specifically, the materials of each layer of the ferroelectric memory 50 are shown in the following example:

[0098] In one example, the first electrode 301 and the second electrode 305 are both metals, such as gold (Au), aluminum (Al), copper (Cu), tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN). In another example, the first electrode 301 and the second electrode 305 are doped semiconductors with good conductivity. In yet another example, the first electrode 301 and the second electrode 305 are half-metallic graphene.

[0099] Ferroelectric layer 304, in one example, is a ferroelectric material, such as hafnium zirconium oxide (HfZrO) or lead zirconate titanate (PZT); in another example, ferroelectric layer 304 is a two-dimensional ferroelectric material, such as indium selenide (α-In2Se3).

[0100] Semiconductor layer 303, in one example, is a single-element semiconductor material, such as silicon (Si) or germanium (Ge); in another example, semiconductor layer 303 can be a group IIIV compound, such as gallium arsenide (GaAs) or indium phosphide (InP); in yet another example, semiconductor layer 303 is a wide-gap semiconductor material, such as zinc oxide (ZnO), gallium nitride (GaN), niobium pentoxide (Nb2O5), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), nickel oxide (NiO), or silicon carbide (SiC); in yet another embodiment, semiconductor layer 303 is a two-dimensional semiconductor material, such as molybdenum disulfide (MoS2) or tungsten diselenide (WSe2).

[0101] In one example, insulating layer 302 is a three-dimensional material, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO2). In another example, insulating layer 302 is a two-dimensional insulating material, such as hexagonal boron nitride (h-BN).

[0102] Figures 7a-7e All with Figure 6 The simulation results are shown using the selector in the ferroelectric memory as an example. Figure 7a The diagram shown is a schematic diagram of the energy band structure of this type of selector. Figure 7b This is a schematic diagram showing the relationship between the band structure of this type of selector and the width of each structure in the ferroelectric memory. Figure 7c This is a schematic diagram showing the relationship between the capacitance value and voltage of this type of selector. Figure 7d This is a schematic diagram showing the relationship between the conductance and voltage values ​​of this type of selector; Figure 7e This is a schematic diagram showing the relationship between the ferroelectric voltage division ratio (Vfe / Vapp) of this type of selector and time.

[0103] Ignoring the effects of ferroelectric polarization, the simulation calculates the function of the selector component. Figure 7b Shown in Figure 6 The energy band structure of the ferroelectric memory shown is illustrated under different bias voltages. Figure 7b As can be seen, by using the ferroelectric layer to connect the semiconductor and the insulating layer to connect the electrode layer of the present invention, the semiconductor layer can be depleted under low bias voltage, and the selector exhibits a high-resistance state, i.e. Figure 7b As shown by the black line in the diagram. This ferroelectric memory consists of an insulating layer and a semiconductor layer connected in series, resulting in a relatively low selector capacitance. Under high bias, the energy band of the semiconductor layer bends, i.e., as... Figure 7b As shown by the red and orange lines, the selector can more easily tunnel through the insulating layer to the semiconductor strong inversion layer to conduct; on the other hand, the formed strong inversion layer increases the selector capacitance.

[0104] Figure 7c and Figure 7d The capacitance and conductance of the selector section extracted at high frequencies are shown respectively. Figure 7c and Figure 7dIt can be seen that the low-bias selector exhibits low capacitance and low conductance, while the high-bias selector exhibits high capacitance and high conductance. It can also be seen that with appropriate semiconductor bandgap design, the selector can achieve bidirectional conduction under both positive and negative biases. When the selector is at a high bias (full selection), because it is conducting and its capacitance is increased, the voltage drop is smaller, allowing current to charge and discharge the ferroelectric layer. The ferroelectric layer receives a larger proportion of voltage, making it easier to flip and complete read / write operations. Conversely, when the selector is at a low bias (half selection), because its low conductance prevents conduction and its capacitance is smaller, the voltage drop is larger, resulting in a smaller proportion of the applied voltage acting on the ferroelectric layer. The ferroelectric layer is less likely to flip and change the stored information.

[0105] like Figure 7e As shown, the current nonlinearity and capacitance gain of the selector show that the Fe layer receives a larger proportion of voltage Vfe / Vapp under full selection of Vop in a shorter time, while the half selection of Vop / 2 receives a smaller proportion of voltage Vfe / Vapp, thus suppressing the half selection interference effect.

[0106] like Figure 8a As shown, Figure 6 The diagram shown illustrates the changes in polarization from initial negative polarization (-P) to positive polarization (+P) and from positive polarization (+P) to negative polarization (-P) under high bias (all selected) conditions in the ferroelectric memory structure. This can also be referred to as a PV diagram. Considering the ferroelectric polarization reversal, it can be seen that the polarization reversal process further promotes the nonlinearity of the selector current and the capacitance gain. Under high bias (all selected), through... Figure 8a The I-II process shows that from the initial negative polarization (-P) to positive polarization (+P), the charge induced by the ferroelectric layer within the semiconductor layer changes from negative to positive; through Figure 8a The III-IV process shows that during the process from positive polarization (+P) to negative polarization (-P), the charge generated in the semiconductor layer induced by the ferroelectric layer changes from positive to negative.

[0107] Figure 8b This application Figure 6 The diagram shows the relationship between the energy bands of the ferroelectric memory and the widths of the various structures within it. Figure 8c This is a schematic diagram illustrating the relationship between the capacitance value and voltage of the ferroelectric memory provided in this application. Figure 8d This is a schematic diagram illustrating the relationship between the conductivity and voltage of the ferroelectric memory provided in this application. Figure 8b , Figure 8c and Figure 8dAs can be seen, due to the change in charge from positive to negative induced within the semiconductor layer by the ferroelectric layer, the threshold for forming the n(p) inversion layer is significantly reduced. The selector's conductivity increases more rapidly as the ferroelectricity gradually flips, and the capacitance also increases more quickly from low to high, further increasing the voltage on the ferroelectric layer and promoting ferroelectric flipping, thus forming positive feedback. This process, from initial negative polarization (-P) to positive polarization (+P), is illustrated in the graph showing the relationship between the capacitance and voltage of the ferroelectric memory. Figure 8c The relationship between conductivity and voltage is shown in dashed line II. Figure 8d The dashed line II in the diagram; for the process from positive polarization (+P) to negative polarization (-P), the graph showing the relationship between the capacitance and voltage of the ferroelectric memory is shown below. Figure 8c The relationship between the conductance and voltage values ​​is shown in the dashed line IV. Figure 8d The dashed line IV in the middle.

[0108] The ferroelectric memory of this application exhibits minimal change in polarization charge during half-selection under low bias (half-selection) conditions. The initial polarization increases the selector's turn-on threshold, resulting in a large selector voltage division ratio. This reduces the ferroelectric voltage division ratio, suppressing half-selection interference. The process is as follows: Figure 8a As shown by solid lines I and III, the capacitance value changes with the voltage value as the voltage changes from negative to positive. Figure 8c For the solid line I, the conductivity value changes with the voltage value (see Figure 1). Figure 8c The solid line I; the change in capacitance with voltage from positive to negative is shown in the diagram. Figure 8c For solid line III, the conductivity value changes with voltage value (see Figure 1). Figure 8c The solid line III.

[0109] Furthermore, through Figure 8a As can be seen, compared with the existing MFM (Metal-Ferroelectric-Metal) structure, the MFSIM (Metal-Ferroelectric-Semiconductor-Insulator-Metal) structure provided in this application has a steeper flip in the P and V coordinate diagram. This ensures full flipping under high bias (full selection) state and suppresses flipping under low bias (half selection) state, thereby providing the storage performance of ferroelectric memory.

[0110] The fabrication method for the ferroelectric memory provided in this application involves forming a stacked structure of a first electrode 301, a second electrode 305, a ferroelectric layer 304, and a selector assembly 300 through a certain process. The specific fabrication process is described in detail in the following embodiments.

[0111] like Figures 9a-9eThe diagram shown is a schematic representation of a method for fabricating a ferroelectric memory provided in this application. Figure 3 The ferroelectric memory shown can be prepared by this method; Figure 9f This is a flowchart of the method for preparing a ferroelectric memory provided in this application.

[0112] S901: As Figure 9a As shown, a second electrode 305 is formed;

[0113] Regarding the material used for the second electrode 305, in one example, the second electrode 305 is a metal, such as gold (Au), aluminum (Al), copper (Cu), tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN); in another example, the second electrode 305 is a doped semiconductor with good conductivity, such as heavily doped silicon; in yet another example, the second electrode 305 is a half-metal graphene.

[0114] S902: As Figure 9b As shown, a ferroelectric layer 304 is formed. In one possible implementation, the ferroelectric layer 304 is formed on one side of the second electrode. Regarding the material used for the ferroelectric layer 304, in one example, the ferroelectric layer 304 is a ferroelectric material, such as hafnium zirconium oxide (HfZrO) or lead zirconate titanate (PZT). In another example, the ferroelectric layer 304 is a two-dimensional ferroelectric material, such as indium selenide (α-In2Se3).

[0115] S903: such as Figure 9c As shown, a semiconductor layer 303 is formed. In one possible implementation, the semiconductor layer 303 is formed on the side of the ferroelectric layer 304 away from the second electrode 305, and the semiconductor layer 303 is disposed in contact with the insulating layer 302.

[0116] Regarding the material used for semiconductor layer 303, in one example, semiconductor layer 303 is a single-element semiconductor material, such as Si or Ge; in another example, semiconductor layer 303 can be a group IIIV compound, such as gallium arsenide (GaAs) or indium phosphide (InP); in yet another example, semiconductor layer 303 is a wide-gap semiconductor material, such as zinc oxide (ZnO), gallium nitride (GaN), niobium pentoxide (Nb₂O₅), titanium dioxide (TiO₂), tantalum pentoxide (Ta₂O₅), nickel oxide (NiO), or silicon carbide (SiC); in yet another example, semiconductor layer 303 is a two-dimensional semiconductor material, such as molybdenum disulfide (MoS₂) or tungsten diselenide (WSe₂); and in yet another example, semiconductor layer 303 is an alloy material, such as germanium-silicon (SiGe).

[0117] S904: such as Figure 9dAs shown, an insulating layer 302 is formed; in one possible implementation, the insulating layer 302 is formed on the side of the semiconductor layer 303 away from the ferroelectric layer 304, and the insulating layer 302 is disposed in contact with the semiconductor layer 303.

[0118] Regarding the material used for the insulating layer 302, in one example, the insulating layer 302 is a three-dimensional material, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO2). In another example, the insulating layer 302 is a two-dimensional insulating material, such as hexagonal boron nitride (h-BN).

[0119] S905: As Figure 9e As shown, a first electrode 301 is formed; in one possible implementation, the first electrode 301 is formed on the side of the insulating layer 302 away from the semiconductor layer 303, and the first electrode 301 is disposed in contact with the insulating layer 302.

[0120] Regarding the material used for the first electrode 301, in one example, the first electrode 301 is a metal, such as gold (Au), aluminum (Al), copper (Cu), tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN); in another example, the first electrode 301 is a doped semiconductor with good conductivity, such as heavily doped silicon; in yet another example, the first electrode 301 is a half-metal graphene.

[0121] like Figures 10a-10e The diagram shown is a schematic representation of a method for preparing a ferroelectric capacitor according to this application. Figure 4 and Figure 5 The ferroelectric memory shown can be prepared by this method; Figure 10f This is a flowchart of the method for fabricating ferroelectric memory provided in this application. It should be noted that... Figures 10a-10e This is a top view of the fabrication steps of the ferroelectric memory provided in this application. The ferroelectric memory is cylindrical in three-dimensional space, and its cross-section is as shown. Figure 5 As shown in the diagram, it will not be shown separately in this preparation process.

[0122] S1001: As Figure 10a As shown, a first electrode 301 is formed, and the first electrode 301 is hollowed out;

[0123] Regarding the material used for the first electrode 301, in one example, the first electrode 301 is a metal, such as gold (Au), aluminum (Al), copper (Cu), tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN); in another example, the first electrode 301 is a doped semiconductor with good conductivity, such as heavily doped silicon; in yet another example, the first electrode 301 is a half-metal graphene.

[0124] S1002: As Figure 10bAs shown, an insulating layer 302 is formed at the hollowed-out position in the first electrode 301, and the insulating layer 302 is hollowed out.

[0125] In one possible implementation, the insulating layer 302 grows from the outside to the inside along the inner wall of the electrode 301, that is, the first electrode 301 is arranged in contact with the insulating layer 302, and the thickness of the insulating layer can be selected from 1-4 nm.

[0126] Regarding the material used for the insulating layer 302, in one example, the insulating layer 302 is a three-dimensional material, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO2). In another example, the insulating layer 302 is a two-dimensional insulating material, such as hexagonal boron nitride (h-BN).

[0127] S1003: As Figure 10c As shown, a semiconductor layer 303 is formed at the hollowed-out location in the insulating layer 302, and the semiconductor layer 303 is hollowed out; in one possible implementation, the semiconductor layer 303 grows from the outside to the inside along the inner wall of the insulating layer 302, that is, the insulating layer 302 is disposed around the semiconductor layer 303 in contact, and the thickness of the semiconductor layer 303 can be selected from 1-10nm.

[0128] Regarding the material used for semiconductor layer 303, in one example, semiconductor layer 303 is a single-element semiconductor material, such as Si or Ge; in another example, semiconductor layer 303 can be a group IIIV compound, such as gallium arsenide (GaAs) or indium phosphide (InP); in yet another example, semiconductor layer 303 is a wide-gap semiconductor material, such as zinc oxide (ZnO), gallium nitride (GaN), niobium pentoxide (Nb₂O₅), titanium dioxide (TiO₂), tantalum pentoxide (Ta₂O₅), nickel oxide (NiO), or silicon carbide (SiC); in yet another example, semiconductor layer 303 is a two-dimensional semiconductor material, such as molybdenum disulfide (MoS₂) or tungsten diselenide (WSe₂); and in yet another example, semiconductor layer 303 is an alloy material, such as germanium-silicon (SiGe).

[0129] S1004: As Figure 10d As shown, a ferroelectric layer 304 is formed at the hollowed-out location in the semiconductor layer 303, and the ferroelectric layer 304 is hollowed out; in one possible implementation, the ferroelectric layer 304 grows from the outside to the inside along the inner wall of the semiconductor layer 303, that is, the semiconductor layer 303 is disposed around the ferroelectric layer 304 in contact, and the thickness of the ferroelectric layer 304 can be selected from 4-50nm.

[0130] Regarding the material used for the ferroelectric layer 304, in one example, the ferroelectric layer 304 is a ferroelectric material, such as hafnium zirconium oxide (HfZrO) or lead zirconate titanate (PZT); in another example, the ferroelectric layer 304 is a two-dimensional ferroelectric material, such as indium selenide (α-In2Se3).

[0131] S1005: As Figure 10e As shown, a second electrode 305 is formed at the hollowed-out position in the ferroelectric layer 304; in one possible implementation, the second electrode 305 grows from the outside to the inside along the inner wall of the ferroelectric layer 304 until it fills the hollowed-out space, that is, the ferroelectric layer 304 is arranged in contact with the second electrode 305.

[0132] Regarding the material used for the second electrode 305, in one example, the second electrode 305 is a metal, such as gold (Au), aluminum (Al), copper (Cu), tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN); in another example, the second electrode 305 is a doped semiconductor with good conductivity, such as heavily doped silicon; in yet another example, the second electrode 305 is a half-metal graphene.

[0133] In another possible implementation of this embodiment, after forming the first electrode 301, a ferroelectric layer 304 is formed, that is, the first electrode 305 is disposed in contact with the ferroelectric layer 304; the next step is to form a semiconductor layer 303, that is, the ferroelectric layer 304 is disposed in contact with the semiconductor layer 303; the next step is to form an insulating layer 302, that is, the semiconductor layer 303 is disposed in contact with the insulating layer 302; finally, a second electrode 305 is formed, that is, the insulating layer 302 is disposed in contact with the second electrode 305.

[0134] It should be understood that in the various embodiments of this application, the order of the above processes does not imply the order of execution. Some or all steps may be executed in parallel or sequentially. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

Claims

1. A ferroelectric memory, characterized in that, include: The system comprises a selector assembly, a first electrode, a second electrode, and a ferroelectric layer, wherein the ferroelectric layer and the selector assembly are located between the first electrode and the second electrode. The selector component includes: The semiconductor layer is in contact with the ferroelectric layer; An insulating layer is in contact with the semiconductor layer and with the first electrode; The ferroelectric layer is in contact with the second electrode.

2. The ferroelectric memory according to claim 1, characterized in that, The first electrode, the insulating layer, the semiconductor layer, the ferroelectric layer, and the second electrode are stacked sequentially.

3. The ferroelectric memory according to claim 1, characterized in that, The first electrode, the insulating layer, the semiconductor layer, the ferroelectric layer, and the second electrode are arranged sequentially from the inside out or from the outside in.

4. The ferroelectric memory according to any one of claims 1-3, characterized in that, The insulating layer is made of at least one of silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), or hexagonal boron nitride (h-BN).

5. The ferroelectric memory according to any one of claims 1-4, characterized in that, The semiconductor layer is made of elemental semiconductor materials.

6. The ferroelectric memory according to claim 5, characterized in that, The elemental semiconductor material includes at least one of silicon (Si) and germanium (Ge).

7. The ferroelectric memory according to any one of claims 1-4, characterized in that, The semiconductor layer is made of an alloy material.

8. The ferroelectric memory according to claim 7, characterized in that, The alloy material includes germanium-silicon (SiGe).

9. The ferroelectric memory according to any one of claims 1-4, characterized in that, The semiconductor layer is made of a III-V compound.

10. The ferroelectric memory according to claim 9, characterized in that, The III-V compounds include at least one of gallium arsenide (GaAs) or indium phosphide (InP).

11. The ferroelectric memory according to any one of claims 1-4, characterized in that, The semiconductor layer is made of a wide-gap semiconductor material.

12. The ferroelectric memory according to claim 11, characterized in that, The wide-gap semiconductor material includes at least one of zinc oxide (ZnO), gallium nitride (GaN), niobium pentoxide (Nb2O5), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), nickel oxide (NiO), or silicon carbide (SiC).

13. The ferroelectric memory according to any one of claims 1-4, characterized in that, The semiconductor layer is made of a two-dimensional semiconductor material.

14. The ferroelectric memory according to claim 14, characterized in that, The two-dimensional semiconductor material includes at least one of molybdenum disulfide (MoS2) or tungsten diselenide (WSe2).

15. The ferroelectric memory according to any one of claims 1-14, characterized in that, The ferroelectric layer is made of at least one of hafnium zirconium oxide (HfZrO), indium selenide (α-In2Se3), or lead zirconate titanate (PZT).

16. The ferroelectric memory according to any one of claims 1-15, characterized in that, The thickness of the semiconductor layer is 1–10 nm, the thickness of the insulating layer is 1–4 nm, and the thickness of the ferroelectric layer is 4–50 nm.

17. The ferroelectric memory according to claim 16, characterized in that, The thickness of the semiconductor layer is 1–2.5 nm, and the thickness of the insulating layer is 0.5–2 nm.

18. The ferroelectric memory according to any one of claims 1-17, characterized in that, The material of the first electrode or the second electrode is at least one of graphene, heavily doped silicon, gold (Au), aluminum (Al), copper (Cu), tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN).

19. A method for fabricating a ferroelectric memory, characterized in that, include: A stacked structure is formed consisting of a first electrode, a second electrode, a ferroelectric layer, and a selector assembly; The ferroelectric layer and the selector assembly are located between the first electrode and the second electrode; The selector assembly includes: a semiconductor layer in contact with the ferroelectric layer; an insulating layer in contact with the semiconductor layer and the first electrode; and the ferroelectric layer in contact with the second electrode.

20. The method for preparing a ferroelectric memory according to claim 19, characterized in that, include: Form the second electrode; An insulating layer is formed on one side of the second electrode, and the second electrode is in contact with the insulating layer; The semiconductor layer is formed on the side of the insulating layer away from the second electrode, and the insulating layer is in contact with the semiconductor layer; The ferroelectric layer is formed on the side of the semiconductor layer away from the insulating layer, and the semiconductor layer is in contact with the ferroelectric layer; The first electrode is formed on the side of the ferroelectric layer away from the semiconductor layer, and the first electrode is in contact with the ferroelectric layer.

21. The method for preparing a ferroelectric memory according to claim 19, characterized in that, include: Form the first electrode; The insulating layer is formed, and the first electrode is disposed in contact with the insulating layer. The semiconductor layer is formed therefrom, and the insulating layer is disposed in contact with the semiconductor layer. The ferroelectric layer is formed therein, and the semiconductor layer is disposed in contact with the ferroelectric layer. The second electrode is formed, and the ferroelectric layer is disposed in contact with the second electrode.

22. The method for preparing a ferroelectric memory according to claim 19, characterized in that, include: Form the first electrode; The ferroelectric layer is formed, and the first electrode is disposed in contact with the ferroelectric layer. The semiconductor layer is formed therefrom, and the ferroelectric layer is disposed in contact with the semiconductor layer. The insulating layer is formed therearound the insulating layer, and the semiconductor layer is disposed in contact with the insulating layer. The second electrode is formed, and the insulating layer is disposed around the second electrode in contact with it.

23. A ferroelectric memory chip, characterized in that, It includes a processor and a ferroelectric memory as described in any one of claims 1-18, wherein the processor is electrically connected to the ferroelectric memory.

24. A chip packaging structure, characterized in that, The semiconductor package structure includes a substrate and a ferroelectric memory chip as described in claim 23, wherein the substrate and the ferroelectric memory chip are electrically connected.

25. An electronic device, characterized in that, The electronic device includes a circuit board and a chip package structure as described in claim 24, wherein the circuit board and the chip package structure are electrically connected.

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