Ferroelectric capacitor and method of making, memory array, memory, and electronic device

Abstract

Embodiments of the present application provide a ferroelectric capacitor, a preparation method thereof, a memory array, a memory and an electronic device, and relate to the technical field of semiconductors, and are used to improve the anti-interference capability of the ferroelectric capacitor. The ferroelectric capacitor comprises a first electrode and a second electrode arranged oppositely, and a ferroelectric layer between the first electrode and the second electrode. The ferroelectric layer comprises a main body layer and a first interface layer arranged in layers. The main body layer comprises a doping element and a hafnium oxide-based material. The first interface layer comprises an oxide of a first element and an oxide of a second element, the difference between the ionic radius of the first element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstrom, and the difference between the ionic radius of the second element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstrom. The ferroelectric capacitor described above is applied to a memory, thereby improving the performance of the memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a ferroelectric capacitor and its preparation method, a memory array, a memory, and an electronic device. Background Technology

[0002] Ferroelectric random access memory (FRAM) has been widely used in embedded storage, neural networks, the Internet of Things, and artificial intelligence due to its advantages such as non-volatility, high speed, high durability, and low power consumption.

[0003] However, as the storage density of ferroelectric memories gradually increases, the physical distance between adjacent memory cells gradually decreases, leading to increasingly severe interference problems between memory cells in ferroelectric memories. For example, when operating on the ferroelectric capacitor in the target memory cell, the ferroelectric capacitors in its adjacent memory cells are easily affected by the target operating voltage, causing changes to the information stored in the ferroelectric capacitors, or even complete rewriting. Summary of the Invention

[0004] This application provides a ferroelectric capacitor and its preparation method, a storage array, a memory, and an electronic device to improve the anti-interference capability of ferroelectric capacitors.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a ferroelectric capacitor is provided. The ferroelectric capacitor includes a first electrode and a second electrode disposed opposite to each other, and a ferroelectric layer located between the first electrode and the second electrode. The ferroelectric layer includes a main body layer and a first interface layer stacked thereon. The main body layer includes a dopant element and a hafnium oxide-based material. The first interface layer includes an oxide of a first element and an oxide of a second element, wherein the difference between the ionic radius of the first element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms, and the difference between the ionic radius of the second element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms.

[0007] In the ferroelectric capacitor provided in this application embodiment, the ionic radius of the first element is relatively close to that of hafnium, and the ionic radius of the second element is also relatively close to that of hafnium. This results in fewer lattice dislocations in the portion of the main layer near the first interface layer, and fewer lattice dislocations in the portion of the first interface layer near the main layer. The interface quality between the first interface layer and the main layer can be higher, thereby promoting further crystallization of the main layer, reducing the number of domains with lower coercive field strength and smaller size in the main layer, and increasing the number of domains with higher coercive field strength, faster switching speed, and larger size, thereby improving the anti-interference capability of the ferroelectric capacitor.

[0008] Similarly, the ionic radii of the first element and the second element are both relatively close to the ionic radius of hafnium. This smaller difference between the ionic radii of the first element and the second element can further reduce the lattice dislocations inside the first interface layer. Consequently, there are fewer lattice dislocations in the portion of the first interface layer closer to the main layer, resulting in better interface quality between the first interface layer and the main layer. This can further promote the crystallization of the main layer and improve the anti-interference capability of the ferroelectric capacitor.

[0009] In addition, after the host layer is further crystallized, the number of domains with larger coercive electric field strength, faster flipping speed and larger size in the host layer increases, which can also improve the storage window of the ferroelectric capacitor.

[0010] In some embodiments, the difference between the ionic radius of the first element and the ionic radius of the second element is less than or equal to 0.1 angstroms.

[0011] In this way, the ionic radii of the first element and the second element in the first interface layer are more similar, there are fewer lattice dislocations inside the first interface layer, and the interface between the first interface layer and the main layer has better quality. This is conducive to further improving the crystallization quality of the main layer, reducing the number of domains with small coercive field strength and small size in the main layer, and improving the anti-interference ability of the ferroelectric capacitor.

[0012] In some embodiments, the binding energy of the oxide of the first element and the binding energy of the oxide of the second element are both greater than or equal to the binding energy of hafnium oxide.

[0013] In the ferroelectric capacitor provided in this application embodiment, the binding energy of the oxide of the first element and the binding energy of the oxide of the second element are both greater than or equal to the binding energy of hafnium oxide. This makes the first interface layer more capable of confining oxygen ions, thereby improving the stability of oxygen ions in the ferroelectric layer, reducing the probability of oxygen vacancies in the ferroelectric layer, regulating the built-in electric field of the ferroelectric layer, alleviating the asymmetry of the coercive electric field, improving the problem that the ferroelectric capacitor is easily affected by small voltage disturbances in a certain polarity direction, and thus optimizing the anti-interference capability of the ferroelectric capacitor.

[0014] In some embodiments, one of the first element and the second element is the same as the dopant element.

[0015] With this configuration, the first interface layer and the main body layer have the same elements. The portion of the main body layer near the first interface layer can have fewer lattice dislocations, and the portion of the first interface layer near the main body layer can also have fewer lattice dislocations. This is beneficial for further improving the crystal quality of the main body layer, further reducing the number of domains with smaller coercive field strength and smaller size in the main body layer, and enhancing the anti-interference capability of the ferroelectric capacitor.

[0016] In some embodiments, the doping element is zirconium, the first element is niobium, and the second element is zirconium.

[0017] At this point, the ionic radius of the first element is similar to that of hafnium, and the ionic radius of the second element is also similar to that of hafnium. The ionic radii of the first element and the second element are close, resulting in fewer lattice dislocations inside the first interface layer and fewer lattice dislocations in the part of the main layer near the first interface layer. The interface between the first interface layer and the main layer has better quality, which is beneficial to further improve the crystallization quality of the main layer, reduce the number of domains with small coercive field strength and small size in the main layer, and improve the anti-interference ability of the ferroelectric capacitor.

[0018] Meanwhile, the second element is the same as the dopant element, so that the first interface layer and the main layer have the same element. The part of the main layer near the first interface layer can have fewer lattice dislocations, and the part of the first interface layer near the main layer can also have fewer lattice dislocations, which is beneficial to further improve the crystal quality of the main layer.

[0019] Furthermore, when the first element in the first interface layer is niobium and the second element is zirconium, the binding energy of the oxides of the first element and the second element is greater than or equal to the binding energy of hafnium oxide. This results in a stronger binding ability between the first element and oxygen ions, and a stronger binding ability between the second element and oxygen ions. The first interface layer has a strong ability to bind oxygen ions, making it less likely to undergo oxidation reactions with the first electrode and / or the second electrode. The probability of generating oxygen vacancies in the ferroelectric layer is also low. This allows for the adjustment of the built-in electric field of the ferroelectric layer, improving the asymmetry of the coercive electric field strength of the ferroelectric layer, and optimizing the anti-interference capability of the ferroelectric capacitor.

[0020] In some embodiments, the first element and the second element are distributed alternately along a direction away from the main layer.

[0021] In some embodiments, along the direction away from the main layer, the concentration of the first element gradually increases, the concentration of the second element gradually decreases, and the binding energy of the oxide of the first element is greater than the binding energy of the oxide of the second element.

[0022] Because the binding energy of the oxide of the first element is greater than that of the oxide of the second element, the first element has a greater confinement effect on oxygen ions. Along the direction away from the main layer, the concentration of the first element gradually increases, while the concentration of the second element gradually decreases. This allows the portion of the first interface layer farther from the main layer to have a greater confinement effect on oxygen ions. Even if this portion of the first interface layer, farther from the main layer, comes into contact with the first or second electrode, the probability of generating oxygen vacancies in this portion is low. This is beneficial for optimizing the built-in electric field of the ferroelectric layer and improving the anti-interference capability of the ferroelectric capacitor.

[0023] In some embodiments, along a direction away from the main body layer, at different locations in the first interface layer, the concentration of the first element is the same as the concentration of the second element.

[0024] In some embodiments, the ferroelectric layer further includes a second interface layer located on the side of the main layer opposite to the first interface layer; the second interface layer includes an oxide of the first element and an oxide of the second element.

[0025] Similar to the first interface layer, the second interface layer includes oxides of the first element and oxides of the second element, which can reduce the number of lattice dislocations in the portion of the main layer near the second interface layer, improve the interface quality between the second interface layer and the main layer, promote further crystallization of the main layer, and improve the anti-interference capability of the ferroelectric capacitor.

[0026] In this embodiment, a first interface layer and a second interface layer are respectively provided on both sides of the main body layer. The first interface layer and the second interface layer simultaneously promote further crystallization of the main body layer, so that the crystallization quality of the main body layer can be better and the anti-interference ability of the ferroelectric capacitor can be stronger.

[0027] In a second aspect, a method for fabricating a ferroelectric capacitor is provided. The method includes forming a first electrode. A ferroelectric layer is formed on one side of the first electrode. The ferroelectric layer includes a host layer and a first interface layer stacked thereon. The host layer includes a dopant element and a hafnium oxide-based material. The first interface layer includes an oxide of a first element and an oxide of a second element. The difference between the ionic radius of the first element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms, and the difference between the ionic radius of the second element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms. A second electrode is formed on the side of the ferroelectric layer away from the first electrode.

[0028] In some embodiments, forming a ferroelectric layer on one side of the first electrode includes: forming a host layer on one side of the first electrode using an atomic layer deposition process; and forming a first interface layer on one side of the first electrode using an atomic layer deposition process.

[0029] In some embodiments, the atomic layer deposition process for forming a first interface layer on one side of the first electrode includes: forming a first sublayer of a first preset thickness, the first sublayer comprising an oxide of the first element; forming a second sublayer of a second preset thickness, the second sublayer comprising an oxide of the second element; repeating the above steps until the sum of the thickness of the first sublayer and the thickness of the second sublayer reaches the preset thickness.

[0030] In some embodiments, the atomic layer deposition process for forming a first interface layer on one side of the first electrode includes: forming a first sublayer, wherein the concentration of the first element in the first sublayer is less than the concentration of the second element; forming a second sublayer, wherein the concentration of the first element in the second sublayer is the same as the concentration of the second element; forming a third sublayer, wherein the concentration of the first element in the third sublayer is greater than the concentration of the second element; wherein the third sublayer is farther away from the host layer than the first sublayer, and the second sublayer is located between the first sublayer and the third sublayer; and the binding energy of the oxide of the first element is greater than the binding energy of the oxide of the second element.

[0031] In some embodiments, in the first sublayer, the concentration ratio of the first element to the second element is 1:3; in the second sublayer, the concentration ratio of the first element to the second element is 1:1; and in the third sublayer, the concentration ratio of the first element to the second element is 3:1.

[0032] In some embodiments, along a direction away from the main body layer, at different locations in the first interface layer, the concentration of the first element is the same as the concentration of the second element.

[0033] In some embodiments, forming a ferroelectric layer on one side of the first electrode further includes: forming a second interface layer on the side of the main layer away from the first interface layer using an atomic layer deposition process; the second interface layer includes an oxide of the first element and an oxide of the second element.

[0034] Thirdly, a memory array is provided. The memory array includes multiple memory cells, multiple board lines, and multiple bit lines. Each memory cell includes a ferroelectric capacitor as described in any of the above embodiments, or a ferroelectric capacitor prepared by the method described in any of the above embodiments. Each board line is connected to multiple memory cells. Each bit line is connected to multiple memory cells.

[0035] In some embodiments, the ferroelectric capacitor includes a first electrode and a second electrode disposed opposite to each other; the plate line is connected to the first electrode, and the bit line is connected to the second electrode.

[0036] Fourthly, a method for fabricating a memory array is provided. The method includes: forming a plurality of alternatingly stacked first dielectric layers and a plurality of second dielectric layers on a substrate; etching the plurality of first dielectric layers and the plurality of second dielectric layers along the thickness direction of the substrate to form a plurality of first holes; forming a ferroelectric layer in the plurality of first holes; the ferroelectric layer being located on the hole walls of the plurality of first holes, and the ferroelectric layer and the bottom wall of the first holes enclosing a second hole; the ferroelectric layer including a stacked body layer and a first interface layer; forming bit lines in the second holes; etching the second dielectric layer to form voids; the voids exposing a portion of the surface of the ferroelectric layer; and forming plate lines in the voids, the plate lines being in contact with the ferroelectric layer.

[0037] The main body layer includes a doped element and a hafnium oxide-based material; the first interface layer includes an oxide of a first element and an oxide of a second element, wherein the difference between the ionic radius of the first element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms, and the difference between the ionic radius of the second element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms.

[0038] In some embodiments, before forming the ferroelectric layer in the plurality of first holes, the preparation method further includes: sequentially forming a first sacrificial layer and a second sacrificial layer in the plurality of first holes; wherein, under the same etching conditions, the etching rate of the first sacrificial layer is greater than the etching rate of the second sacrificial layer.

[0039] In some embodiments, etching the second dielectric layer to form a void includes: etching the second dielectric layer using a first wet etching process until the first sacrificial layer is exposed; and etching the first sacrificial layer and the second sacrificial layer using a second wet etching process until the ferroelectric layer is exposed; wherein the etching solution used in the first wet etching process is different from the etching solution used in the second wet etching process.

[0040] Fifthly, a memory is provided. The memory includes a controller and a memory array as described in any of the above embodiments, or a memory array fabricated by the method described in any of the above embodiments. The controller is electrically connected to the memory array.

[0041] Sixthly, an electronic device is provided. The electronic device includes a circuit board and a memory as described in any of the above embodiments, the memory being located on the circuit board and electrically connected to the circuit board.

[0042] The technical effects of any of the design methods in aspects two through six can be found in the technical effects of different design methods in aspect one, and will not be repeated here. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0044] Figure 1 A structural block diagram of an electronic device provided in an embodiment of this application;

[0045] Figure 2 A structural block diagram of a memory provided in an embodiment of this application;

[0046] Figure 3 This is a structural block diagram of another memory provided in an embodiment of this application;

[0047] Figure 4 A signal diagram showing the influence of a target memory cell on an adjacent memory cell, provided in an embodiment of this application;

[0048] Figure 5 A hysteresis loop diagram of a ferroelectric capacitor provided in an embodiment of this application;

[0049] Figure 6 A schematic diagram of the domain distribution inside a ferroelectric layer provided in an embodiment of this application;

[0050] Figure 7A A three-dimensional structural diagram of a storage array provided for related technologies;

[0051] Figure 7B for Figure 7A A schematic cross-sectional view of the provided storage array at N-N';

[0052] Figure 7C A schematic diagram of the domain distribution inside another ferroelectric layer provided in an embodiment of this application;

[0053] Figure 8 This is a schematic diagram of the structure of a ferroelectric capacitor provided in an embodiment of this application;

[0054] Figure 9 This is a schematic diagram of another ferroelectric capacitor provided in an embodiment of this application;

[0055] Figure 10 The graph shows the variation of polarization intensity of a ferroelectric capacitor without a first interface layer under different interference voltages.

[0056] Figure 11A graph showing the variation of polarization intensity of a ferroelectric capacitor with a first interface layer under different interference voltages.

[0057] Figure 12 This is a schematic diagram of the structure of a ferroelectric layer provided in an embodiment of this application;

[0058] Figure 13 This is a schematic diagram of another ferroelectric layer structure provided in an embodiment of this application;

[0059] Figure 14 This is a schematic diagram of another ferroelectric layer structure provided in an embodiment of this application;

[0060] Figure 15 This is a schematic diagram of the structure of another ferroelectric capacitor provided in the embodiments of this application;

[0061] Figure 16 A flowchart illustrating the fabrication process of a ferroelectric capacitor provided in this application embodiment;

[0062] Figure 17 A flowchart illustrating the fabrication process of another ferroelectric capacitor provided in this application embodiment;

[0063] Figures 18 to 21 All of these are flowcharts illustrating the fabrication process of ferroelectric capacitors provided in the embodiments of this application;

[0064] Figure 22 A circuit diagram of a storage array provided in an embodiment of this application;

[0065] Figure 23 This is a schematic diagram of the structure of a storage array provided in an embodiment of this application;

[0066] Figure 24 A flowchart illustrating the fabrication process of a storage array provided in this application embodiment;

[0067] Figure 25 This is a schematic diagram of the structure of the storage array during fabrication corresponding to step S101 provided in the embodiments of this application;

[0068] Figure 26 This is a schematic diagram of the structure of the storage array during preparation corresponding to step S102 provided in the embodiments of this application;

[0069] Figure 27 This is a schematic diagram of the structure of the storage array during fabrication corresponding to step S103 provided in the embodiments of this application;

[0070] Figure 28 for Figure 27 The diagram shows a cross-sectional view of the storage array at point M-M'.

[0071] Figure 29 for Figure 28The diagram shown is an enlarged view of the storage array at point AA;

[0072] Figure 30 A flowchart illustrating the fabrication process of a storage array provided in this application embodiment;

[0073] Figure 31 for Figure 28 Another enlarged schematic diagram of the storage array at AA is shown;

[0074] Figure 32 This is a flowchart illustrating the fabrication process of another storage array provided in an embodiment of this application;

[0075] Figure 33 This is a schematic diagram of the structure of a storage array during the fabrication process corresponding to step S104 provided in the embodiments of this application;

[0076] Figure 34 This is a schematic diagram of another storage array structure corresponding to step S104 in the embodiments of this application.

[0077] Figure 35 This is a schematic diagram of the structure of the storage array during fabrication corresponding to step S105 provided in the embodiments of this application;

[0078] Figure 36 This is a schematic diagram of the structure of a storage array during the fabrication process corresponding to step S106 provided in the embodiments of this application;

[0079] Figure 37 This is a schematic diagram of another storage array structure corresponding to step S106 in the embodiments of this application.

[0080] Figure 38 This is a schematic diagram of the structure of the storage array during preparation corresponding to step S107 provided in the embodiments of this application;

[0081] Figure 39 This is a schematic diagram of the structure of the storage array during the preparation of steps S151 and S152 provided in the embodiments of this application. Detailed Implementation

[0082] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0083] In the following embodiments of this application, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0084] In the embodiments of this application, "upper", "lower", "left" and "right" are not limited to the orientation of the components in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0085] In this application, unless the context otherwise requires, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to," throughout the specification and claims. In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0086] Exemplary embodiments are described in this application with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0087] This application provides an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, or a communication electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, game consoles, cameras, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), set-top boxes, etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle high-density digital video discs (DVDs), automotive automatic driving assistance systems, navigation and infotainment systems, powertrain and battery management systems, etc. Financial terminal products include automated teller machines (ATMs), POS (Point of Sale) machines, and other self-service terminals. This application does not impose any special restrictions on the specific form of the electronic equipment.

[0088] Figure 1 This is a schematic diagram of the structure of an electronic device 100 provided in an embodiment of this application. Figure 1 As shown, the electronic device 100 may include a bus 110 and a system-on-chip (SOC) 120 connected to the bus 110. The SOC 120 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 120 may include an application processor (AP) 121 for processing applications, a graphics processing unit (GPU) 122 for processing image data, and a first random access memory (RAM) 123 for caching high-speed data. The first RAM 123 may be static random access memory (SRAM), etc. The AP 121, GPU 122, and first RAM 123 may be integrated into a single die or disposed in multiple dies.

[0089] For example Figure 1 As shown, the electronic device 100 may further include a second RAM 130 connected to the SOC 120 via a bus 110. This second RAM 130 may be dynamic random access memory (DRAM). The second RAM 130 can be used to store volatile data, such as temporary data generated by the SOC 120. The storage capacity of the second RAM 130 is typically larger than that of the first RAM 123, but its read speed is typically slower than that of the first RAM 123.

[0090] In addition, the electronic device 100 may also include a communication chip 140 and a power management chip 150 connected to the SOC 120 via a bus 110. The communication chip 140 may be used for protocol stack processing, or for amplifying, filtering, or performing other processing on analog radio frequency signals, or simultaneously performing the above functions. The power management chip 150 may be used to supply power to other chips. In one embodiment, the SOC 120 and the second RAM 130 may be packaged in a single package structure, such as using 2.5D (dimension) or 3D packaging, to achieve a faster inter-chip data transfer rate.

[0091] Figure 2 This is a structural block diagram of a memory 200 that can be applied in an electronic device, provided as an embodiment of this application. In one embodiment, the memory 200 may be... Figure 1 The first RAM 123 can also be the second RAM 130. This application does not limit the application scenario of the memory 200. In one possible implementation, the memory 200 can also be a RAM located outside the SOC 120. This application does not limit the location of the memory 200 in the electronic device or its positional relationship with the SOC 120.

[0092] In some examples, electronic device 100 may include a circuit board, on which the memory 200 is located and connected.

[0093] like Figure 2 As shown, the memory 200 includes a memory array 210. Furthermore, the memory 200 may also include a controller 220 for accessing the memory array 210, wherein the controller 220 controls read and write operations on the memory array 210.

[0094] It is understood that the memory 200 may include at least one memory array 210, that is, the memory 200 may include one or more memory arrays 210. The memory array 210 may include multiple memory cells 211, multiple word lines, multiple board lines, and multiple bit lines, and each of the multiple memory cells 211 can be used to store 1 bit or more bits of data. For example, the memory cell 211 can store the information "0" or "1".

[0095] The controller 220 in the memory may include Figure 3 One or more of the following circuit structures are shown: decoder 221, driver 222, timing controller 223, buffer 224, or input / output driver 225.

[0096] The decoder 221 decodes the received address to determine the memory cell 211 to be accessed. The driver 222 controls the signal line level based on the decoding result generated by the decoder 221, thereby enabling access to the specified memory cell 211. The buffer 224 buffers the read data, for example, using a first-in-first-out (FIFO) buffering method. The timing controller 223 controls the timing of the buffer 224 and controls the driver 222 to drive the signal lines in the memory array 210. The input / output driver 225 drives the transmission signals, such as the received data signal and the data signal to be sent, enabling the data signal to be transmitted over long distances.

[0097] The aforementioned memory array 210, decoder 221, driver 222, timing controller 223, buffer 224, and input / output driver 225 can be integrated into a single chip or into multiple chips respectively.

[0098] The memory involved in this application may be a ferroelectric random access memory (FeRAM).

[0099] Ferroelectric memories have been widely used in embedded storage, neural networks, the Internet of Things, and artificial intelligence due to their advantages such as non-volatility, high speed, high durability, and low power consumption.

[0100] Compared to traditional ferroelectric materials such as lead zirconate titanate, barium titanate, and strontium bismuth tantalate, ferroelectric capacitors made of hafnium-based ferroelectric materials exhibit faster switching speeds and lower operating voltages. When hafnium-based ferroelectric materials are used for the ferroelectric layer of a ferroelectric capacitor, the thickness of the ferroelectric layer can be reduced to the 1nm level, giving hafnium-based ferroelectric capacitors a significant advantage in constructing high-density ferroelectric memories in two-dimensional or three-dimensional applications.

[0101] As memory integration becomes increasingly sophisticated, the pitch between memory cells gradually decreases, exacerbating the problem of interference between adjacent cells. Specifically, when an operation is performed on a target memory cell in the memory array, adjacent cells, due to their proximity, will sense the applied operating voltage and be affected by it.

[0102] For example, such as Figure 4 As shown, when the target memory cell performs a write "0" operation, it receives the operating voltage Vdd from the plate line PL and the bit line BL, and adjacent memory cells are subjected to positive-phase interference of Vdd / 3. When the target memory cell performs a write "1" operation, it receives the operating voltage -Vdd from the plate line PL and the bit line BL, and adjacent memory cells are subjected to negative-phase interference of -Vdd / 3.

[0103] Figure 5 The hysteresis loop of a ferroelectric capacitor is shown, where the horizontal axis represents the electric field strength and the vertical axis represents the polarization intensity. For example... Figure 5 As shown, the polarization of a ferroelectric capacitor can reverse when the electric field strength is Vdd / -Vdd. When the interference voltage is Vdd / 3, the polarization of the ferroelectric capacitor is easily altered. Furthermore, the superposition of multiple interference pulses can completely change the polarity of the ferroelectric capacitor, rewriting the stored information in the memory cell containing the ferroelectric capacitor.

[0104] This is because, during the fabrication process of ferroelectric capacitors, such as... Figure 6 As shown, multiple domains with relatively small coercive electric field strengths often form within the ferroelectric layer of a ferroelectric capacitor. When subjected to an electric field stronger than their coercive electric field strength, these domains will flip, causing leakage of stored charge and altering the original stored information in the memory cells. When multiple interference pulses are superimposed, the polarity of these domains can even be rewritten, increasing the risk of errors (i.e., misprints) in the ferroelectric layer's stored information. Figure 6 The polarization direction of a domain is indicated by an "arrow".

[0105] To solve the above problems, such as Figure 7A and Figure 7BAs shown, the related technology incorporates an insertion layer between the ferroelectric layer and the electrodes (plate line PL or bit line BL). This insertion layer, made of materials such as alumina or silicon oxide, acts as a voltage divider. Thus, when the ferroelectric capacitor receives interference voltage, a portion of the interference voltage is applied to the insertion layer, and the other portion to the ferroelectric layer. The actual voltage received by the ferroelectric layer is less than the interference voltage, making it difficult for the interference voltage to change the polarity of the ferroelectric layer. This effectively increases the coercive electric field strength of the ferroelectric layer, thereby increasing the switching barrier of the ferroelectric capacitor and improving its resistance to small-voltage interference.

[0106] However, when an operating voltage is applied to the ferroelectric capacitor, a portion of this voltage is also applied to the intercalation layer, making it difficult for the operating voltage to reverse the polarity of the ferroelectric capacitor. The intercalation layer reduces the storage window of the ferroelectric capacitor and increases power consumption. Simultaneously, the intercalation layer increases the overall thickness of the ferroelectric capacitor, hindering the miniaturization of the storage cell containing it. For example, when the deposition window size is limited, the introduction of the intercalation layer can reduce the deposition window of the ferroelectric layer, leading to incomplete deposition or the presence of voids within the ferroelectric layer.

[0107] To improve the resistance of ferroelectric capacitors to small voltage interference, another related technique involves increasing the annealing temperature of the ferroelectric layer. Increasing the annealing temperature improves the crystallinity of the ferroelectric layer, reduces the number of domains with low coercive field strength and small size, and promotes the formation of domains with similar characteristics to those in the ferroelectric layer. Figure 7C The domains shown have consistent coercive field strength, fast flipping speed, and large size, thereby improving the ability of the ferroelectric layer to resist small voltage interference. Figure 7C The polarization direction of a domain is indicated by an "arrow".

[0108] However, to improve memory storage density, memory fabrication processes are being optimized, and the structure of memory cells is gradually shifting from two-dimensional planar structures to high-density array structures such as three-dimensional vertical and three-dimensional stacked structures. To integrate more memory cells, ferroelectric capacitors within the cells are typically fabricated using back-end processes. During the fabrication of ferroelectric memories, if a high annealing temperature is used for the ferroelectric layer, the annealing process will subject the transistors fabricated in the front-end processes to secondary high temperatures, severely impacting transistor performance (e.g., leakage current, resistance, switching speed), which is detrimental to high-density memory integration.

[0109] To address the aforementioned issues, this application provides a ferroelectric capacitor 300. The ferroelectric capacitor 300 is applied to the storage arrays and memories provided in the above embodiments.

[0110] Figure 8This is a schematic diagram of the structure of a ferroelectric capacitor 300 provided in an embodiment of this application. Figure 8 As shown, the ferroelectric capacitor 300 may include a first electrode 10 and a second electrode 20 disposed opposite to each other, and a ferroelectric layer 30 located between the first electrode 10 and the second electrode 10.

[0111] The ferroelectric layer 30 includes a main layer 31 and a first interface layer 32 stacked together. The main layer 31 includes a dopant element and a hafnium oxide-based material. The first interface layer 32 includes an oxide of a first element and an oxide of a second element, wherein the difference between the ionic radius of the first element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms, and the difference between the ionic radius of the second element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms.

[0112] In some examples, the first electrode 10 and the second electrode 20 may be made of a metal-containing material, such as a metal, a conductive metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof.

[0113] For example, the materials of the first electrode 10 and the second electrode 20 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), niobium nitride (NbN), molybdenum nitride (MoN), or combinations thereof.

[0114] In some examples, such as Figure 8 As shown, both the first electrode 10 and the second electrode 20 are single-layer structures. In this case, the materials of the first electrode 10 and the second electrode 20 can be the same or different.

[0115] In other examples, such as Figure 9 As shown, both the first electrode 10 and the second electrode 20 can be multilayer structures. Figure 9 The illustration is based on the example where both the first electrode 10 and the second electrode 20 have a double-layer structure.

[0116] For example, such as Figure 9 As shown, the first electrode 10 may include a first sub-electrode 11 and a second sub-electrode 12 stacked together, with the first sub-electrode 11 located on the side of the second sub-electrode 12 away from the ferroelectric layer 30. The second electrode 20 may include a third sub-electrode 21 and a fourth sub-electrode 22 stacked together, with the third sub-electrode 21 located on the side of the fourth sub-electrode 22 away from the ferroelectric layer 30.

[0117] In this design, the first sub-electrode 11 and the third sub-electrode 21 are both made of metal, while the second sub-electrode 12 and the fourth sub-electrode 22 are both made of conductive metal carbide, conductive metal nitride, or conductive metal oxide. For example, the first sub-electrode 11 and the third sub-electrode 21 are both made of tungsten, while the second sub-electrode 12 and the fourth sub-electrode 22 are both made of titanium nitride.

[0118] In the ferroelectric capacitor 300 provided in the embodiments of this application, the first electrode 10 includes a first sub-electrode 11 and a second sub-electrode 12. The material of the first sub-electrode 11 is metal, which is beneficial to reducing the overall resistivity of the first electrode 10. The material of the second sub-electrode 12 includes one of conductive metal carbide, conductive metal nitride or conductive metal oxide, which is beneficial to improving the connection stability between the first electrode 10 and the ferroelectric layer 30 and reducing the contact resistance between the first electrode 10 and the ferroelectric layer 30.

[0119] Similarly, the second electrode 20 may include a third sub-electrode 21 and a fourth sub-electrode 22 stacked together. The material of the third sub-electrode 21 is metal, which helps to reduce the overall resistivity of the second electrode 20. The material of the fourth sub-electrode 22 includes one of conductive metal carbide, conductive metal nitride or conductive metal oxide, which helps to improve the connection stability between the second electrode 20 and the ferroelectric layer 30 and reduce the contact resistance between the second electrode 20 and the ferroelectric layer 30.

[0120] In some examples, the first interface layer 32 may be located on the side of the main body layer 31 closer to the first electrode 10. In other examples, such as Figure 8 and Figure 9 As shown, the first interface layer 32 can be located on the side of the main body layer 31 near the second electrode 20.

[0121] The aforementioned hafnium oxide-based materials refer to ferroelectric materials based on hafnium oxide material systems. For example, the material of the ferroelectric layer 30 can be zirconium (Zr)-doped hafnium dioxide (HfO2), silicon (Si)-doped HfO2, aluminum (Al)-doped HfO2, lanthanum (La)-doped HfO2, yttrium (Y)-doped HfO2, gadolinium (Gd)-doped HfO2, strontium (Sr)-doped HfO2, etc.

[0122] Alternatively, the aforementioned hafnium oxide-based material can also be a hafnium zirconium oxide (HZO) system material. For example, the ferroelectric layer 30 can be lanthanum (La)-doped HZO, yttrium (Y)-doped HZO, strontium (Sr)-doped HZO, gadolinium (Gd)-doped HZO, gadolinium-lanthanum (Gd / La) co-doped HZO, etc.

[0123] The doping element can also be one or more of nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, neodymium, magnesium, barium, gallium, calcium, and carbon.

[0124] In some examples, the first element can be one of zirconium (Zr), niobium (Nb), indium (In), tantalum (Ta), ruthenium (Ru), nickel (Ni), tin (Sn), or iridium (Ir). The second element can be one of zirconium, niobium, indium, tantalum, ruthenium, nickel, tin, or iridium. Of course, the first and second elements are different elements.

[0125] The ionic radius of hafnium is 0.71 Å, that of zirconium is 0.72 Å, that of niobium is 0.69 Å, that of indium is 0.8 Å, that of tantalum is 0.64 Å, that of ruthenium is 0.68 Å, that of nickel is 0.69 Å, that of tin is 0.69 Å, and that of iridium is 0.625 Å.

[0126] It can be seen that the difference between the ionic radii of elements such as zirconium, niobium, indium, tantalum, ruthenium, nickel, tin, or iridium and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms. When the first and second elements are zirconium, niobium, indium, tantalum, ruthenium, nickel, tin, or iridium, the difference between the ionic radii of the first and second elements and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms.

[0127] Wherein, when the first element or the second element is zirconium, the material of the first interface layer 32 may include zirconium oxide; when the first element or the second element is niobium, the material of the first interface layer 32 may include niobium oxide; when the first element or the second element is indium, the material of the first interface layer 32 may include indium oxide; when the first element or the second element is tantalum, the material of the first interface layer 32 may include tantalum oxide; when the first element or the second element is ruthenium, the material of the first interface layer 32 may include ruthenium oxide; when the first element or the second element is nickel, the material of the first interface layer 32 may include nickel oxide; when the first element or the second element is tin, the material of the first interface layer 32 may include tin oxide; when the first element or the second element is iridium, the material of the first interface layer 32 may include iridium oxide.

[0128] In the ferroelectric capacitor 300 provided in this application embodiment, the ionic radius of the first element is relatively close to that of hafnium, and the ionic radius of the second element is also relatively close to that of hafnium. This results in fewer lattice dislocations in the portion of the main layer 31 near the first interface layer 32, and fewer lattice dislocations in the portion of the first interface layer 32 near the main layer 31. The interface quality between the first interface layer 32 and the main layer 31 can be higher, thereby promoting further crystallization of the main layer 31, reducing the number of domains with lower coercive field strength and smaller size in the main layer 31, and increasing the number of domains with higher coercive field strength, faster switching speed, and larger size, thereby improving the disturbance immunity of the ferroelectric capacitor 300.

[0129] Similarly, the ionic radii of the first element and the second element are both relatively close to the ionic radius of hafnium. This smaller difference between the ionic radii of the first element and the second element can further reduce the lattice dislocations inside the first interface layer 32. Consequently, the portion of the first interface layer 32 closer to the main layer 31 will have fewer lattice dislocations, resulting in better interface quality between the first interface layer 32 and the main layer 31. This can further promote the crystallization of the main layer 31 and improve the anti-interference capability of the ferroelectric capacitor 300.

[0130] In addition, after the main body layer 31 is further crystallized, the number of domains with larger coercive electric field strength, faster flipping speed and larger size in the main body layer 31 increases, which can also improve the storage window (margin) of the ferroelectric capacitor 300.

[0131] Figure 10 The curves showing the polarization intensity variation of a ferroelectric capacitor without a first interface layer under different interference voltages. Figure 11 The curves showing the change in polarization intensity of the ferroelectric capacitor with the first interface layer under different interference voltages are shown. Figure 10 and Figure 11 The horizontal axis represents voltage in volts (V), and the vertical axis represents polarization intensity in microcoulombs per square centimeter (μC / cm²). 2 ).

[0132] Figure 10 and Figure 11 The curves showing the variation of polarization intensity of the ferroelectric capacitors when the interference voltage V0 is 0.8V, 1.0V, 1.2V, 1.6V, 2.0V, and 2.4V are all presented. (Comparison) Figure 10 and Figure 11It can be seen that when the interference voltage is relatively small (e.g., interference voltage V0 is 0.8, 1.0, or 1.2), the change in polarization intensity of the ferroelectric capacitor with the first interface layer is smaller than that of the ferroelectric capacitor without the first interface layer. Especially when the interference voltage V0 is 1.0, the change in polarization intensity (i.e., the interference intensity) of the ferroelectric capacitor with the first interface layer is significantly smaller than that of the ferroelectric capacitor without the first interface layer. The first interface layer 32 effectively improves the resistance of the ferroelectric capacitor 300 to smaller interference voltages.

[0133] At the same time, through comparison Figure 10 and Figure 11 It is evident that when the interference voltage is relatively large (e.g., interference voltage V0 is 1.6, 2.0, or 2.4) (equivalent to a relatively large operating voltage), the residual polarization intensity of the ferroelectric capacitor with the first interface layer is greater than that of the ferroelectric capacitor without the first interface layer. Therefore, the first interface layer can increase the storage window of the memory, thereby ensuring the accuracy of read and write operations of the memory cell using the ferroelectric capacitor 300 and improving the performance of the memory. Here, "residual polarization intensity" refers to the polarization intensity that still exists in the ferroelectric capacitor when the electric field strength drops to zero.

[0134] Unlike related technologies that use an insertion layer between the ferroelectric layer and the electrode, the ferroelectric capacitor 300 provided in this application provides a first interface layer 32 disposed inside the ferroelectric layer 30. The placement of the first interface layer 32 does not easily affect the difficulty of polarity reversal of the ferroelectric capacitor 300, nor does it affect the overall thickness of the ferroelectric capacitor 300. When the ferroelectric capacitor is applied to a memory cell, it does not limit the miniaturization of the memory cell size.

[0135] Compared with related technologies that improve the crystallization quality of ferroelectric layers by increasing the annealing temperature, the ferroelectric capacitor 300 provided in this application embodiment can improve the crystallization quality of the main body layer 31 by setting the first interface layer 32. When the ferroelectric capacitor 300 is applied to the memory array, the fabrication process of the ferroelectric capacitor is less likely to affect the performance of the transistors fabricated by the previous process, which is beneficial to ensuring the yield of the memory array using the ferroelectric capacitor 300.

[0136] In some embodiments, the difference between the ionic radius of the first element and the ionic radius of the second element is less than or equal to 0.1 angstroms.

[0137] In this way, the ionic radii of the first element and the second element in the first interface layer 32 are more similar, there are fewer lattice dislocations inside the first interface layer 32, and the interface between the first interface layer 32 and the main layer 31 has better quality. This is conducive to further improving the crystallization quality of the main layer 31, reducing the number of domains with small coercive field strength and small size in the main layer 31, and improving the anti-interference ability of the ferroelectric capacitor 300.

[0138] In some embodiments, the binding energy of the oxide of the first element and the binding energy of the oxide of the second element are both greater than or equal to the binding energy of hafnium oxide.

[0139] In this case, the first element can be one of zirconium, niobium, indium, and tantalum. The second element can be one of zirconium, niobium, indium, and tantalum.

[0140] Oxygen vacancies in the ferroelectric layer often induce a built-in electric field in a certain direction within the ferroelectric layer. Depending on the net content of oxygen vacancies at different locations, an asymmetric coercive field phenomenon will occur, where the positive coercive field strength is greater than the negative coercive field strength, or vice versa. This results in a serious deviation in the positive and negative polarity reversal capability of the ferroelectric layer, and a certain polarity direction is extremely susceptible to small voltage disturbances.

[0141] In the ferroelectric capacitor 300 provided in this application embodiment, the binding energy of the oxide of the first element and the binding energy of the oxide of the second element are both greater than or equal to the binding energy of hafnium oxide. This makes the first interface layer 32 more capable of confining oxygen ions, thereby improving the stability of oxygen ions in the ferroelectric layer 30, reducing the probability of oxygen vacancies in the ferroelectric layer 30, regulating the built-in electric field of the ferroelectric layer 30, alleviating the asymmetry of the coercive electric field, improving the problem that the ferroelectric capacitor is easily affected by small voltage disturbances in a certain polarity direction, and thus optimizing the anti-interference capability of the ferroelectric capacitor 300.

[0142] In some embodiments, one of the first element and the second element is the same as the dopant element.

[0143] With this configuration, the first interface layer 32 and the main body layer 31 have the same elements. The portion of the main body layer 31 near the first interface layer 32 can have fewer lattice dislocations, and the portion of the first interface layer 32 near the main body layer 31 can also have fewer lattice dislocations. This is beneficial for further improving the crystal quality of the main body layer 31, reducing the number of domains with smaller coercive field strength and smaller size in the main body layer 31, and enhancing the anti-interference capability of the ferroelectric capacitor 300.

[0144] In some examples, the doping element in the main layer 31 is zirconium, and the first element in the first interface layer 32 is niobium, and the second element is zirconium.

[0145] At this point, the ionic radius of the first element is similar to that of hafnium, and the ionic radius of the second element is also similar to that of hafnium. The ionic radii of the first element and the second element are close to each other. There are fewer lattice dislocations inside the first interface layer 32, and fewer lattice dislocations in the part of the main layer 31 near the first interface layer 32. The interface between the first interface layer 32 and the main layer 31 has better quality, which is conducive to further improving the crystallization quality of the main layer 31, reducing the number of domains with small coercive field strength and small size in the main layer 31, and improving the anti-interference capability of the ferroelectric capacitor 300.

[0146] Meanwhile, the second element is the same as the dopant element, so that the first interface layer 32 and the main body layer 31 have the same element. The part of the main body layer 31 near the first interface layer 32 can have fewer lattice dislocations, and the part of the first interface layer 32 near the main body layer 31 can have fewer lattice dislocations, which is beneficial to further improve the crystal quality of the main body layer 31.

[0147] Furthermore, when the first element in the first interface layer 32 is niobium and the second element is zirconium, the binding energy of the oxides of the first element and the second element is greater than that of hafnium oxide. This results in a stronger binding ability between the first element and oxygen ions, and a stronger binding ability between the second element and oxygen ions. The first interface layer 32 has a strong ability to bind oxygen ions, making it less likely to undergo oxidation reactions with the first electrode 10 and / or the second electrode 20. This reduces the probability of oxygen vacancies being generated in the ferroelectric layer 30, thereby adjusting the built-in electric field of the ferroelectric layer 30, improving the asymmetry of the coercive electric field strength of the ferroelectric layer 30, and optimizing the anti-interference capability of the ferroelectric capacitor 300.

[0148] Figures 12 to 14 These are schematic diagrams illustrating the structure of a ferroelectric layer 30 provided in embodiments of this application. The element types in the first interface layer 32 have been described above; the following section, in conjunction with… Figures 12 to 14 The distribution of the first and second elements in the first interface layer 32 is introduced.

[0149] In some embodiments, such as Figure 12 As shown, along the direction Z away from the main layer 31, the first element and the second element are distributed alternately.

[0150] For example, such as Figure 8 , Figure 9 and Figure 12As shown, the first interface layer 32 may include multiple first sublayers 321 and multiple second sublayers 322. Along the direction Z away from the main layer 31, the multiple first sublayers 321 and multiple second sublayers 322 are alternately stacked. The first sublayer 321 may include a first element, and the second sublayer 322 may include a second element. Taking niobium as the first element and zirconium as the second element as an example, the material of the first sublayer 321 may be niobium oxide, and the material of the second sublayer 322 may be zirconium oxide.

[0151] In this embodiment, the number of the first sub-layer 321 and the second sub-layer 322 is not limited, and can be designed according to actual needs. Figure 8 and Figure 9 The first interface layer 32 includes two first sub-layers 321 and three second sub-layers 322 as an example for illustration. Figure 12 The following is an example of the first interface layer 32, which includes a first sub-layer 321 and two second sub-layers 322.

[0152] The thickness of the first sublayer 321 and the thickness of the second sublayer 322 can be the same or different.

[0153] For example, the thickness of the first sublayer 321 and the thickness of the second sublayer 322 can both be 0.2 nanometers (nm), and the thickness of the first interface layer 32 can be 1 nm.

[0154] In other embodiments, such as Figure 13 As shown, along the direction Z away from the main layer 31, the concentration of the first element is the same as the concentration of the second element at different positions in the first interface layer 32.

[0155] At this point, the first element and the second element are evenly distributed in the first interface layer 32. When preparing the first interface layer 32, an atomic layer deposition process can be used to deposit the first element and the second element in sequence with the same number of cycles to form the first interface layer 32.

[0156] In some other embodiments, such as Figure 14 As shown, along the direction Z away from the main layer 31, the concentration of the first element gradually increases, the concentration of the second element gradually decreases, and the binding energy of the oxide of the first element is greater than that of the oxide of the second element.

[0157] In some examples, such as Figure 14 As shown, the first interface layer 32 can be sequentially moved away from the first sub-layer 321, the second sub-layer 322, and the third sub-layer 323 of the main layer 31. Among them, the concentration of the first element in the first sub-layer 321 is less than the concentration of the second element, the concentration of the first element in the second sub-layer 322 is the same as the concentration of the second element, and the concentration of the first element in the third sub-layer 323 is greater than the concentration of the second element.

[0158] For example, in the first sublayer 321, the concentration ratio of the first element to the second element is 1:3. In the second sublayer 322, the concentration ratio of the first element to the second element is 1:1. In the third sublayer 323, the concentration ratio of the first element to the second element is 1:3.

[0159] Since the binding energy of the oxide of the first element is greater than that of the oxide of the second element, the first element has a greater confinement effect on oxygen ions. Along the direction Z away from the main layer 31, the concentration of the first element gradually increases, while the concentration of the second element gradually decreases. This allows the portion of the first interface layer 32 away from the main layer 31 to have a greater confinement effect on oxygen ions. Even if the portion of the first interface layer 32 away from the main layer 31 comes into contact with the first electrode 10 or the second electrode 20, the probability of generating oxygen vacancies in this portion is low. This is beneficial for optimizing the built-in electric field of the ferroelectric layer 30 and improving the anti-interference capability of the ferroelectric capacitor 300.

[0160] It is understood that, in addition to the first and second elements mentioned above, the first interface layer may also include other elements. The difference between the ionic radius of the other elements and the ionic radius of hafnium may be greater than zero and less than or equal to 0.1 angstroms, or greater than 0.1 angstroms.

[0161] In some embodiments, such as Figure 15 As shown, the ferroelectric layer 30 also includes a second interface layer 33, which is located on the side of the main layer 31 away from the first interface layer 32. The second interface layer 33 includes an oxide of the first element and an oxide of the second element.

[0162] It is understandable that when the first interface layer 32 is located between the main body layer 31 and the first electrode 31, the second interface layer 33 is located between the main body layer 31 and the second electrode 20. When the first interface layer 32 is located between the main body layer 31 and the second electrode 32, the second interface layer 33 is located between the main body layer 31 and the first electrode 10.

[0163] Similar to the first interface layer 32, the second interface layer 33 includes oxides of the first element and oxides of the second element, which can reduce the number of lattice dislocations in the portion of the main layer 31 near the second interface layer 33, improve the interface quality between the second interface layer 33 and the main layer 31, promote further crystallization of the main layer 31, and improve the anti-interference capability of the ferroelectric capacitor 300.

[0164] In this embodiment, a first interface layer 32 and a second interface layer 33 are respectively provided on both sides of the main body layer 31. The first interface layer 32 and the second interface layer 33 simultaneously promote the further crystallization of the main body layer 31, so that the crystallization quality of the main body layer 31 can be better and the anti-interference ability of the ferroelectric capacitor 300 can be stronger.

[0165] In some examples, the distribution of the first and second elements in the second interface layer 33 can be the same as the distribution of the first and second elements in the first interface layer 32.

[0166] For example, when the first element and the second element are alternately distributed in the first interface layer 32 along the direction Z away from the main layer 31, the first element and the second element in the second interface layer 33 are also alternately distributed along the direction Z away from the main layer 31.

[0167] like Figure 15 As shown, when the first interface layer 32 can include multiple alternating first sub-layers 321 and multiple second sub-layers 322 along the direction Z away from the main layer 31, the second interface layer 33 can include multiple alternating fourth sub-layers 331 and multiple fifth sub-layers 332.

[0168] The fourth sublayer 331 and the first sublayer 321 both include a first element, and the fifth sublayer 332 and the second sublayer 322 both include a second element. Taking niobium as the first element and zirconium as the second element as an example, the materials of the fourth sublayer 331 and the first sublayer 321 can be niobium oxide, and the materials of the fifth sublayer 332 and the second sublayer 322 can be zirconium oxide.

[0169] For example, when the concentration of the first element gradually increases and the concentration of the second element gradually decreases in the first interface layer 32 along the direction Z away from the main layer 31, in the second interface layer 33, the concentration of the first element gradually increases and the concentration of the second element gradually decreases along the direction Z away from the main layer 31. In this case, the binding energy of the oxide of the first element is greater than the binding energy of the oxide of the second element.

[0170] When the first interface layer can include a stacked configuration, and the first, second, and third sub-layers are sequentially farther away from the main layer, the second interface layer can include a stacked configuration, and the fourth, fifth, and sixth sub-layers are sequentially farther away from the main layer.

[0171] In the first and fourth sublayers, the concentration of the first element is less than that of the second element; in the fifth and second sublayers, the concentration of the first element is the same as that of the second element; and in the sixth and third sublayers, the concentration of the first element is greater than that of the second element.

[0172] In one possible implementation, in the first and fourth sublayers, the concentration ratio of the first element to the second element is 1:3; in the second and fifth sublayers, the concentration ratio of the first element to the second element is 1:1; and in the third and sixth sublayers, the concentration ratio of the first element to the second element is 3:1.

[0173] As the concentration of the first element in the first interface layer gradually increases along the direction away from the main layer, and the concentration of the first element in the second interface layer also gradually increases, the portion of the first interface layer away from the main layer has a stronger binding capacity for oxygen ions, and the portion of the second interface layer away from the main layer also has a stronger binding capacity for oxygen ions. Oxygen vacancies are not easily generated on the side of the ferroelectric layer near the first electrode, nor are oxygen vacancies easily generated on the side of the ferroelectric layer near the second electrode. This helps to improve the problem of oxygen vacancies affecting the internal electric field of the ferroelectric layer, and thus affecting the coercive electric field strength of the ferroelectric capacitor, thereby improving the anti-interference capability of the ferroelectric capacitor.

[0174] For example, when the concentration of the first element is the same as the concentration of the second element at different positions of the first interface layer 32 along the direction Z away from the main layer 31, the concentration of the first element is the same as the concentration of the second element at different positions of the second interface layer 33 along the direction Z away from the main layer 31.

[0175] In the ferroelectric capacitor 300 provided in this application embodiment, the distribution of the first element and the second element in the second interface layer 33 is the same as that in the first interface layer 32. The preparation process of the first interface layer 32 and the second interface layer 33 can be the same, which helps to simplify the preparation process of the ferroelectric capacitor 300 and reduce the preparation cost of the ferroelectric capacitor 300.

[0176] In other examples, the distribution of the first and second elements in the second interface layer 33 may differ from the distribution of the first and second elements in the first interface layer 32.

[0177] For example, when the first element and the second element are alternately distributed in the first interface layer 32 along the direction Z away from the main layer 31, the concentration of the first element gradually increases and the concentration of the second element gradually decreases in the second interface layer 33 along the direction Z away from the main layer 31. Alternatively, when the first element and the second element are alternately distributed in the first interface layer 32 along the direction Z away from the main layer 31, the concentration of the first element is the same as the concentration of the second element at different positions in the second interface layer 33 along the direction Z away from the main layer 31.

[0178] For example, when the concentration of the first element in the first interface layer 32 gradually increases and the concentration of the second element gradually decreases along the direction Z away from the main layer 31, the first and second elements are alternately distributed in the second interface layer 33 along the direction Z away from the main layer 31. Alternatively, when the concentration of the first element in the first interface layer 32 gradually increases and the concentration of the second element gradually decreases along the direction Z away from the main layer 31, the concentration of the first element and the concentration of the second element are the same at different positions in the second interface layer 33 along the direction Z away from the main layer 31.

[0179] For example, when the concentration of the first element is the same as the concentration of the second element at different positions in the first interface layer 32 along the direction Z away from the main layer 31, the concentration of the first element gradually increases and the concentration of the second element gradually decreases in the second interface layer 33 along the direction Z away from the main layer 31. Or, when the concentration of the first element is the same as the concentration of the second element at different positions in the first interface layer 32 along the direction Z away from the main layer 31, the first element and the second element are alternately distributed in the second interface layer 33 along the direction Z away from the main layer 31.

[0180] It is understandable that, in addition to ferroelectric memory, ferroelectric capacitor 300 can also be applied to storage devices such as dynamic random access memory (DRAM), non-volatile random access memory (NAND), cache memory, hard disk drive (HDD), and storage class memory (SCM).

[0181] This application provides a method for manufacturing a ferroelectric capacitor 300. For example... Figure 16 As shown, the preparation method includes steps S100 to S300.

[0182] S100, such as Figure 17 As shown, the first electrode 10 is formed.

[0183] For example, the first electrode 10 can be formed using atomic layer deposition (ALD) and / or chemical vapor deposition (CVD) processes.

[0184] In some examples, the material of the first electrode 10 may include a metal-containing material, such as a metal, a conductive metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof.

[0185] In some examples, such as Figure 17 As shown, the first electrode 10 can be a single-layer structure.

[0186] In other examples, the first electrode 10 can be a multilayer structure. See also Figure 9The first electrode 10 may include a first sub-electrode 11 and a second sub-electrode 12 stacked together, wherein the material of the first sub-electrode 11 is different from that of the second sub-electrode 12. For example, the material of the first sub-electrode 11 may be tungsten, and the material of the second sub-electrode 12 may be titanium nitride.

[0187] For example, when the material of the first sub-electrode 11 is tungsten, a chemical vapor deposition process can be used, with tungsten tetrafluoride (WF4) and hydrogen (H2) as reactants, to form the first sub-electrode 11.

[0188] In some examples, the thickness of the first sub-electrode 11 can be 100 nm to 300 nm. For example, the thickness of the first sub-electrode 11 can be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc.

[0189] For example, when the material of the second sub-electrode 12 is titanium nitride, an atomic layer deposition process can be used to form the second sub-electrode 12 by using titanium chloride (TiCl4) as a precursor for titanium ions and ammonia (NH3) as a precursor for nitrogen ions.

[0190] In some examples, the thickness of the second sub-electrode 12 can be 2 nm to 5 nm. For example, the thickness of the second sub-electrode 12 can be 2 nm, 3 nm, 4 nm, 5 nm, etc.

[0191] It is understandable that when the first electrode 10 has a multilayer structure, the first electrode 10 may include not only the first sub-electrode 11 and the second sub-electrode 12, but also other sub-electrodes.

[0192] S200, such as Figure 17 As shown, a ferroelectric layer 30 is formed on one side of the first electrode 10. The ferroelectric layer 30 includes a main layer 31 and a first interface layer 32 stacked together. The main layer 31 includes a doped element and a hafnium oxide-based material. The first interface layer 32 includes an oxide of a first element and an oxide of a second element. The difference between the ionic radius of the first element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms.

[0193] In some examples, such as Figure 17 As shown, the first interface layer 32 is located on the side of the main body layer 31 near the first electrode 10.

[0194] In other examples, see Figure 8 The first interface layer 32 is located on the side of the main body layer 31 away from the first electrode 10.

[0195] In some examples, atomic layer deposition (ALD) can be used to form the ferroelectric layer 30.

[0196] In some examples, see Figure 9 When the first electrode 10 includes a first sub-electrode 11 and a second sub-electrode 12, the ferroelectric layer 30 may be located on the side of the second sub-electrode 12 away from the first sub-electrode 11.

[0197] In some examples, the thickness of the main layer 31 can be greater than or equal to 3 nm. For example, the thickness of the main layer 31 can be 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 10 nm, etc.

[0198] S300, such as Figure 17 As shown, a second electrode 20 is formed on the side of the ferroelectric layer 30 away from the first electrode 10.

[0199] For example, the second electrode 20 can be formed using atomic layer deposition and / or chemical vapor deposition processes.

[0200] In some examples, the material of the second electrode 20 may include a metal-containing material, such as a metal, a conductive metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof.

[0201] In some examples, such as Figure 17 As shown, the second electrode 20 can be a single-layer structure. In this case, the material of the second electrode 20 can be the same as or different from the material of the first electrode 10.

[0202] In other examples, the second electrode 20 can be a multilayer structure. For example, see [link to relevant documentation]. Figure 9 The second electrode 20 may include a third sub-electrode 21 and a fourth sub-electrode 22 stacked together, with the third sub-electrode 21 located on the side of the fourth sub-electrode 22 away from the ferroelectric layer 30. The material of the third sub-electrode 21 is different from the material of the fourth sub-electrode 22.

[0203] For example, the material of the third sub-electrode 21 can be tungsten, and the material of the fourth sub-electrode 22 can be titanium nitride.

[0204] For example, when the material of the third sub-electrode 21 is tungsten, a chemical vapor deposition process can be used, with tungsten tetrafluoride and hydrogen as reactants, to form the third sub-electrode 21.

[0205] In some examples, the thickness of the third sub-electrode 21 can be 100 nm to 300 nm. For example, the thickness of the third sub-electrode 21 can be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc.

[0206] For example, when the material of the fourth sub-electrode 22 is titanium nitride, an atomic layer deposition process can be used to form the fourth sub-electrode 22 by using titanium chloride as a precursor for titanium ions and ammonia as a precursor for nitrogen ions.

[0207] In some examples, the thickness of the fourth sub-electrode 22 can be 2 nm to 5 nm. For example, the thickness of the fourth sub-electrode 22 can be 2 nm, 3 nm, 4 nm, 5 nm, etc.

[0208] It is understood that when the second electrode 20 has a multilayer structure, it may include not only the third sub-electrode 21 and the fourth sub-electrode 22, but also other sub-electrodes. In this embodiment, the thickness of the third sub-electrode 21 and the fourth sub-electrode 22 is not limited and can be designed according to actual needs.

[0209] The beneficial effects that can be achieved by the preparation method provided in this application are the same as those that can be achieved by the ferroelectric capacitor 300 provided in any of the above embodiments, and will not be repeated here.

[0210] Below, in conjunction with Figures 18 to 20 The above step S200 will be further described below.

[0211] In some embodiments, such as Figure 18 As shown, step S200 includes steps S210 and S220. In this embodiment, the order of operations for steps S210 and S220 is not limited; step S210 can be performed first, followed by step S220, or vice versa.

[0212] S210. Using atomic layer deposition process, a host layer 31 is formed on one side of the first electrode 10.

[0213] In some examples, the material of the host layer 31 includes zirconium-doped hafnium dioxide.

[0214] At this point, atomic layer deposition (ALD) can be used, with tetrakis(dimethylamino)hafnium (TDMA-Hf) as the hafnium-based precursor, ozone (O3) as the oxygen-based precursor, and tetrakis(dimethylamino)zirconium (TDMA-Zr) as the zirconium-based precursor, to form the host layer according to a deposition pattern of "one cycle of hafnium oxide + one cycle of zirconium oxide".

[0215] It is understandable that, in addition to TDMA-Hf, tetrakis(ethylmethylamino)hafnium (TEMA-Hf) or tri(dimethylamino)cyclopentadienyltris(dimethylamino)hafnium (CP-Hf) can also be used as hafnium precursors.

[0216] In addition to TDMA-Zr, tetrakis(ethylmethylamino)zirconium (TEMA-Zr) or isopropylidene(cyclopentadienyl)zirconium(9-fluorenyl)dichloride (CP-Zr) can also be used as zirconium-based precursors.

[0217] In addition to O3, water (H2O) can also be used as an oxygen precursor.

[0218] S220. An atomic layer deposition process is used to form a first interface layer 32 on one side of the first electrode 10.

[0219] In some examples, the material of the first interface layer 32 includes zirconium niobium oxide, where the first element is niobium and the second element is zirconium.

[0220] For example, tert-butylimino tris(diethylamino)niobium (TBTDE-Nb) can be used as a niobium-based precursor, TDMA-Zr, TEMA-Zr or CP-Zr can be used as a zirconium-based precursor, and O3 or H2O can be used as an oxygen-based precursor. An atomic layer deposition process can be used to form a first interface layer 32 on one side of the first electrode 10.

[0221] It is understandable that the preparation process of the first interface layer 32 will differ depending on the distribution of the first and second elements in the first interface layer 32. The following will combine... Figure 19 and Figure 20 The above step S220 will be further described.

[0222] In some examples, along the direction away from the main layer 31, the first element and the second element in the first interface layer 32 are distributed alternately. At this time, as... Figure 19 As shown, step S220 includes steps S221 and S222.

[0223] S221, Form a first sublayer 321 with a first preset thickness, the first sublayer 321 including an oxide of a first element.

[0224] For example, the first element is niobium, and the material of the first sublayer 321 is niobium oxide.

[0225] For example, the first preset thickness can be 0.1nm, 0.2nm, 0.3nm, 0.4nm, 0.5nm, etc.

[0226] For example, an atomic layer deposition process can be used, with TBTDE-Nb as a niobium-based precursor and O3 as an oxygen-based precursor, to form a first sublayer 321 of a first predetermined thickness.

[0227] S222, forming a second sublayer 322 with a second preset thickness, the second sublayer 322 comprising an oxide of a second element. The first preset thickness may be the same as or different from the second preset thickness.

[0228] For example, the second element is zirconium, and the material of the second sublayer 322 is zirconium oxide.

[0229] For example, the second preset thickness can be 0.1nm, 0.2nm, 0.3nm, 0.4nm, 0.5nm, etc.

[0230] For example, an atomic layer deposition process can be used, with TDMA-Zr as a zirconium-based precursor and O3 as an oxygen-based precursor, to form a second sublayer 322 of a second predetermined thickness.

[0231] Repeat steps S221 and S222 until the sum of the thicknesses of the first sublayer 321 and the second sublayer 322 reaches the preset thickness. It is understood that both the first and second preset thicknesses are less than the preset thickness. When the sum of the first and second preset thicknesses equals the preset thickness, there is no need to repeat steps S221 and S222.

[0232] For example, the preset thickness can be 0.4nm, 0.6nm, 0.7nm, 0.8nm, 0.9nm, 1nm, 1.5nm, 2nm, etc.

[0233] In other embodiments, along the direction away from the main layer 31, the concentration of the first element in the first interface layer 32 gradually increases, the concentration of the second element gradually decreases, and the binding energy of the oxide of the first element is greater than the binding energy of the oxide of the second element. At this time, as... Figure 20 As shown, step S220 includes steps S223 to S225.

[0234] S223, forming the first sublayer 321, in which the concentration of the first element is less than the concentration of the second element.

[0235] S224, forming a second sublayer 322, in which the concentration of the first element is the same as the concentration of the second element.

[0236] S225, forming a third sublayer 323, in which the concentration of the first element is greater than the concentration of the second element.

[0237] Among them, the third sub-layer 323 is farther away from the main layer 31 than the first sub-layer 321, and the second sub-layer 322 is located between the first sub-layer 321 and the third sub-layer 323.

[0238] In some examples, step S220 can be performed before step S210. In this case, in order to make the third sub-layer 323 farther away from the main layer 31 than the first sub-layer 321, the steps can be performed in the following order: first step S225, then step S224, and finally step S223.

[0239] In some other examples, step S220 can be performed after step S210. In this case, in order to make the third sub-layer 323 farther away from the main layer 31 than the first sub-layer 321, step S223 can be performed first, then step S224, and finally step S225.

[0240] For example, in the first sublayer 321, the concentration ratio of the first element to the second element is 1:3; in the second sublayer 322, the concentration ratio of the first element to the second element is 1:1; and in the third sublayer 323, the concentration ratio of the first element to the second element is 3:1.

[0241] At this time, the concentration of the first element in the third sublayer 323 can be relatively high, and the concentration of the second element can be relatively low. The third sublayer 323 has a greater restrictive effect on oxygen ions. Even if it comes into contact with the first electrode or the second electrode, the probability of generating oxygen vacancies in the third sublayer 323 is relatively low. This is beneficial to optimizing the built-in electric field of the ferroelectric layer 30 and improving the anti-interference capability of the ferroelectric capacitor 300.

[0242] For example, when preparing the first interface layer 32 using atomic layer deposition, the number of cycles corresponding to the first element and the number of cycles corresponding to the second element can be controlled, thereby controlling the concentration of the first element and the concentration of the second element in the first sublayer 321, the second sublayer 322 and the third sublayer 323.

[0243] The preparation process of the first sublayer 321, the second sublayer 322, and the third sublayer 323 will be described below, taking niobium as the first element and zirconium as the second element.

[0244] In some examples, atomic layer deposition (ALD) can be used, employing TBTDE-Nb as a niobium-based precursor, O3 as an oxygen-based precursor, and TDMA-Zr as a zirconium-based precursor, following the "1-cycle NbO" process. x +3cycle ZrO x The depositional process of “” formed the first sublayer 321.

[0245] In some examples, atomic layer deposition (ALD) can be used, employing TBTDE-Nb as a niobium-based precursor, O3 as an oxygen-based precursor, and TDMA-Zr as a zirconium-based precursor, following the "2-cycle NbO" process. x +2cycle ZrO x The depositional process of “" forms the second sublayer 322.

[0246] In some examples, atomic layer deposition (ALD) can be used, employing TBTDE-Nb as a niobium-based precursor, O3 as an oxygen-based precursor, and TDMA-Zr as a zirconium-based precursor, following the "3-cycle NbO" process. x +1 cycle ZrO x The depositional process of “” formed the third sublayer 323.

[0247] In addition to TDMA-Zr, TEMA-Zr or CP-Zr can also be used as zirconium-based precursors, and in addition to O3, H2O can also be used as an oxygen-based precursor.

[0248] In some other embodiments, the concentration of the first element is the same as the concentration of the second element at different locations on the first interface layer 32 along a direction away from the main body layer 31.

[0249] At this time, the concentrations of the first element and the second element at different positions of the first interface layer 32 can also be controlled by controlling the cycle number corresponding to the first element and the cycle number corresponding to the second element, so that the concentrations of the first element and the second element are the same at different positions of the first interface layer 32 along the direction away from the main body layer 31.

[0250] In some embodiments, such as Figure 21 As shown, step S200 also includes step S230.

[0251] S230. Using atomic layer deposition (ALD) technology, a second interface layer 33 is formed on the side of the main layer 31 away from the first interface layer 32. The second interface layer 33 comprises an oxide of the first element and an oxide of the second element.

[0252] For example, the distribution of the first element and the second element in the second interface layer 33 can be the same as the distribution of the first element and the second element in the first interface layer 32.

[0253] This application provides a storage array. The storage array is applied to the memory provided in the above embodiments. Figure 22 This is a circuit diagram of a storage array 400 provided in an embodiment of this application. Figure 23 This is a schematic diagram of the structure of a storage array 400 provided in an embodiment of this application.

[0254] like Figure 22 As shown, the storage array 400 includes multiple storage cells 410, multiple board lines PL, and multiple bit lines BL. Each board line PL is connected to multiple storage cells 410, and each bit line BL is also connected to multiple storage cells 410. Different storage cells 410 can be electrically connected via board lines PL and bit lines BL. One or more of the board lines PL and bit lines BL are used to select the storage cell 410 to be read or written in the storage array 400 by receiving the control level output from the control circuit, thereby realizing data read and write operations.

[0255] The storage unit 410 includes the ferroelectric capacitor 300 provided in any of the above embodiments, or the ferroelectric capacitor 300 prepared by the preparation method provided in any of the above embodiments.

[0256] In some examples, see Figure 22 The ferroelectric capacitor 300 includes a first electrode and a second electrode arranged opposite to each other. The first electrode is connected to the plate line PL, and the second electrode is connected to the bit line BL.

[0257] In some examples, such as Figure 23 As shown, bit line BL can be reused as the first electrode 10 of ferroelectric capacitor 300, and plate line PL can be reused as the second electrode 20 of ferroelectric capacitor 300. Of course, plate line PL can also be reused as the first electrode 10 of ferroelectric capacitor 300, and bit line BL can be reused as the second electrode 20 of ferroelectric capacitor 300.

[0258] The plate line PL can be a single-layer structure or a multi-layer structure. The bit line BL can be a single-layer structure or a multi-layer structure.

[0259] In some embodiments, such as Figure 23 As shown, the memory array 400 may also include a substrate 01, multiple plate lines PL may be spaced apart along the thickness direction Q of the substrate 01, bit lines BL may extend along the thickness direction Q of the substrate 01 and pass through the multiple plate lines PL, and the ferroelectric layer 30 of the ferroelectric capacitor 300 may be located on the sidewall of the bit line BL and between the bit line BL and the plate lines PL.

[0260] In some examples, such as Figure 23As shown, the storage array 400 may further include a first dielectric layer 02, which is located between two adjacent board lines PL. The material of the first dielectric layer 02 is an insulating material. The first dielectric layer 02 serves to separate the two adjacent board lines PL.

[0261] In some examples, such as Figure 23 As shown, the memory array 400 may further include a third dielectric layer 011, which may be located on the side of the bit line BL and the board line PL away from the substrate 01. The memory array 400 may further include a first contact post V1 and a second contact post V2, the first contact post V1 penetrating the third dielectric layer 011 and connected to the bit line BL, and the second contact post V2 penetrating the third dielectric layer 011 and connected to the board line PL.

[0262] The first contact post V1 can transmit electrical signals to the bit line BL, or transmit signals on the bit line BL to the outside of the memory array 400. Similarly, the second contact post V2 can transmit electrical signals to the board line PL, or transmit signals on the board line PL to the outside of the memory array.

[0263] The beneficial effects that the storage array provided in this application embodiment can achieve are the same as those that the ferroelectric capacitor 300 provided in any of the above embodiments can achieve, and will not be repeated here.

[0264] This application provides a method for fabricating a storage array, such as... Figure 24 As shown, the preparation method includes steps S101 to S106.

[0265] S101, such as Figure 25 As shown, a plurality of first dielectric layers 02 and a plurality of second dielectric layers 03 are alternately stacked on a substrate 01.

[0266] The second dielectric layer 03 can serve as a temporary support structure to separate two adjacent first dielectric layers 02. In this case, the first dielectric layer 02 is the film layer farthest from the substrate 01 among the aforementioned "multiple first dielectric layers 02 and multiple second dielectric layers 03".

[0267] In some examples, multiple first dielectric layers 02 and multiple second dielectric layers 03 may be stacked alternately along the thickness direction Q of the substrate 01.

[0268] In some examples, the material of the first dielectric layer 02 can be silicon oxide, and the material of the second dielectric layer 03 can be silicon nitride.

[0269] At this point, plasma-enhanced chemical vapor deposition (PECVD) can be used to form the first dielectric layer O2 through a plasma reaction using silane (SiH4) and nitrous oxide (N2O) gas. Then, chemical vapor deposition (CVD) can be used to form the second dielectric layer O3 through a chemical ion reaction using SiH4 and ammonia (NH3).

[0270] In some examples, the thickness of the second dielectric layer 03 can be greater than the thickness of the first dielectric layer 02.

[0271] In some examples, the thickness of the first dielectric layer 02 can be 10nm to 100nm. For example, the thickness of the first dielectric layer 02 can be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc.

[0272] In some examples, the thickness of the second dielectric layer 03 can be 100nm to 500nm. For example, the thickness of the second dielectric layer 03 can be 100nm, 200nm, 300nm, 400nm, 500nm, etc.

[0273] It is understood that the number of the first dielectric layer and the second dielectric layer is not limited in the embodiments of this application, and can be designed according to actual needs. Figure 25 The following is an example of forming six first dielectric layers and five second dielectric layers on substrate 01.

[0274] S102, such as Figure 26 As shown, multiple first dielectric layers 02 and multiple second dielectric layers 03 are etched along the thickness direction Q of the substrate 01 to form multiple first holes H1.

[0275] In some examples, photoresist can be formed first, and then patterned using a development process to define the position of the first hole H1. Then, using the photoresist as a mask, multiple first dielectric layers 02 and multiple second dielectric layers 03 are etched along the thickness direction Q of the substrate 01 using a dry etching process to form multiple first holes H1.

[0276] For example, fluoride can be selected as the etching gas to etch multiple first dielectric layers 02 and multiple second dielectric layers 03.

[0277] For example, an anti-reflective coating can be formed before forming the photoresist. The anti-reflective coating can improve the patterning effect of the photoresist and increase the resolution of the pattern in the photoresist after patterning.

[0278] S103, such as Figure 27 and Figure 28 As shown, a ferroelectric layer 30 is formed in a plurality of first holes H1. The ferroelectric layer 30 is located on the hole wall of the plurality of first holes H1, and the ferroelectric layer 30 and the bottom wall of the first holes H1 form a second hole H2.

[0279] Figure 29 for Figure 28 The image shown is a magnified view of the memory array at point AA. In some examples, such as... Figure 29 As shown, the ferroelectric layer 30 includes a main layer 31 and a first interface layer 32 stacked together. The main layer 31 includes a dopant element and a hafnium oxide-based material. The first interface layer 32 includes an oxide of a first element and an oxide of a second element. The difference between the ionic radius of the first element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms, and the difference between the ionic radius of the second element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms.

[0280] In some examples, along the direction Z away from the main layer 31, the first and second elements are distributed alternately. In this case, as... Figure 29 As shown, the first interface layer 32 may include multiple first sublayers 321 and multiple second sublayers 322. Along the direction away from the main layer 31, the multiple first sublayers 321 and multiple second sublayers 322 are alternately stacked. The first sublayer 321 may include a first element, and the second sublayer 322 may include a second element. Taking niobium as the first element and zirconium as the second element as an example, the material of the first sublayer 321 may be niobium oxide, and the material of the second sublayer 322 may be zirconium oxide.

[0281] In other examples, along a direction away from the main layer 31, at different locations in the first interface layer 32, the concentration of the first element is the same as the concentration of the second element.

[0282] In some other examples, along the direction away from the main layer 31, the concentration of the first element gradually increases, the concentration of the second element gradually decreases, and the binding energy of the oxide of the first element is greater than the binding energy of the oxide of the second element.

[0283] In some examples, such as Figure 30 As shown, step S103 may include steps S131 and S132.

[0284] S131. Using atomic layer deposition process, a host layer 31 is formed in multiple first holes H1.

[0285] The specific implementation process of step S131 can refer to the specific implementation process of step S210 in the above embodiment, and will not be repeated here.

[0286] S132. Using atomic layer deposition process, a first interface layer 32 is formed in multiple first holes H1.

[0287] It is understandable that the preparation process of the first interface layer 32 will also be different when the distribution of the first element and the second element in the first interface layer 32 is different.

[0288] For example, when the first element and the second element are alternately distributed along the direction away from the main layer 31, the specific implementation process of step S132 can refer to steps S221 and S222 provided in the above embodiment.

[0289] For example, when the concentration of the first element gradually increases and the concentration of the second element gradually decreases along the direction away from the main layer 31, the specific implementation process of step S132 can be referred to steps S223 to S225.

[0290] Figure 31 for Figure 28 Another magnified view of the memory array at AA is shown. In other examples, such as... Figure 31 As shown, in addition to the main body layer 31 and the first interface layer 32, the ferroelectric layer 30 may also include a second interface layer 33 located on the side of the main body layer 31 away from the first interface layer 32. The second interface layer 33 also includes oxides of the first element and oxides of the second element, wherein the difference between the ionic radius of the first element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms, and the difference between the ionic radius of the second element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms.

[0291] At this time, as Figure 32 As shown, step S103 may also include step S133.

[0292] S133. Using atomic layer deposition process, a second interface layer 33 is formed in multiple first pores H1.

[0293] For example, the distribution of the first element and the second element in the second interface layer 33 can be the same as the distribution of the first element and the second element in the first interface layer 32. The specific implementation process of step S133 can also refer to the specific implementation process of step S132 in the above embodiments, and will not be repeated here.

[0294] In some examples, when along the direction Z away from the main layer 31, the first and second elements are alternately distributed in the second interface layer 33. At this time, as... Figure 31As shown, the second interface layer 33 may include a fourth sublayer 331 and a fifth sublayer 332. The fourth sublayer 331 includes a first element, and the fifth sublayer 332 includes a second element. Taking niobium as the first element and zirconium as the second element as an example, the material of the fourth sublayer 331 can be niobium oxide, and the material of the fifth sublayer 332 can be zirconium oxide.

[0295] S104, such as Figure 33 and Figure 34 As shown, bit line BL is formed in the second hole H2.

[0296] For example, the material of the bit line BL can be a metal-containing material, such as a metal, a conductive metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the material of the bit line BL may include titanium, titanium nitride, tantalum nitride, titanium carbonitride, tantalum carbonitride, tungsten, tungsten nitride, ruthenium, iridium, ruthenium oxide, iridium oxide, niobium nitride, molybdenum nitride, or a combination thereof.

[0297] In some examples, such as Figure 33 As shown, the bit line BL can be a single-layer structure.

[0298] In other examples, the bit line BL can be a multi-layered structure. For example, as... Figure 34 As shown, the bit line BL may include a first conductive layer 04 and a second conductive layer 05. The first conductive layer 04 is located on the side of the second conductive layer 05 away from the ferroelectric layer 30, and the materials of the first conductive layer 04 and the second conductive layer 05 are different.

[0299] Taking tungsten as the material of the first conductive layer 04 and titanium nitride as the material of the second conductive layer 05 as an example, the above step S104 may include: firstly, using atomic layer deposition (ALD) with TiCl4 as a precursor for titanium ions and NH3 as a precursor for nitrogen ions, the second conductive layer 05 is formed. Then, using chemical vapor deposition (CVD) with WF4 and H2 as reactants, the first conductive layer 04 is formed.

[0300] In some examples, the thickness of the first conductive layer 04 can be 100 nm to 300 nm. For example, the thickness of the first conductive layer 04 can be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc. In some examples, the thickness of the second conductive layer 05 can be 2 nm to 5 nm. For example, the thickness of the second conductive layer 05 can be 2 nm, 3 nm, 4 nm, 5 nm, etc.

[0301] The second conductive layer 05 can serve as a seed layer, formed on the ferroelectric layer 30, to enhance the adhesion between the first conductive layer 04 and the ferroelectric layer 30. The first conductive layer 04 is made of metal, which helps to reduce the overall resistivity of the bit line BL and reduce the power consumption on the bit line BL.

[0302] It is understandable that the bit line BL can be reused as the first electrode 10 or the second electrode 20 of a ferroelectric capacitor.

[0303] In some examples, after the bit line BL is formed, the memory array can be chemically and mechanically polished using a chemical mechanical polishing (CMP) process to remove the material of the bit line BL located outside the second via H2.

[0304] S105, such as Figure 35 As shown, the second dielectric layer 03 is etched to form voids U. Voids U expose part of the surface of the ferroelectric layer 30.

[0305] In some examples, a wet etching process can be used to etch the second dielectric layer 03 to form voids U.

[0306] S106, such as Figure 36 As shown, a plate line PL is formed in the void U, and the plate line PL is in contact with the ferroelectric layer 30.

[0307] For example, the material of the board line PL can be a metal-containing material, such as a metal, a conductive metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the material of the board line PL may include titanium, titanium nitride, tantalum nitride, titanium carbonitride, tantalum carbonitride, tungsten, tungsten nitride, ruthenium, iridium, ruthenium oxide, iridium oxide, niobium nitride, molybdenum nitride, or a combination thereof.

[0308] In some examples, such as Figure 36 As shown, the board line PL can be a single-layer structure. In other examples, the board line PL can be a multi-layer structure. For example, as... Figure 37 As shown, the board line PL may include a third conductive layer 06 and a fourth conductive layer 07. The third conductive layer 06 is located on the side of the fourth conductive layer 07 away from the ferroelectric layer 30. The third conductive layer 06 and the fourth conductive layer 07 are made of different materials.

[0309] Taking tungsten as the material of the third conductive layer 06 and titanium nitride as the material of the fourth conductive layer 07 as an example, the above step S106 may include: firstly, using atomic layer deposition (ALD) with TiCl4 as a precursor for titanium ions and NH3 as a precursor for nitrogen ions, the fourth conductive layer 07 is formed. Then, using chemical vapor deposition (CVD) with WF4 and H2 as reactants, the third conductive layer 06 is formed through a reduction reaction.

[0310] In some examples, the thickness of the third conductive layer 06 can be 100 nm to 300 nm. For example, the thickness of the third conductive layer 06 can be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc. In some examples, the thickness of the fourth conductive layer 07 can be 2 nm to 5 nm. For example, the thickness of the fourth conductive layer 07 can be 2 nm, 3 nm, 4 nm, 5 nm, etc.

[0311] The fourth conductive layer 07 can serve as a seed layer, formed on the ferroelectric layer 30 and the first dielectric layer 02, to enhance the adhesion between the third conductive layer 06 and the ferroelectric layer 30, and to enhance the adhesion between the third conductive layer 06 and the first dielectric layer 02. The material of the third conductive layer 06 is metal, which helps to reduce the overall resistivity of the board line PL and reduce the power consumption on the board line PL.

[0312] In the case where the bit line BL is reused as the first electrode 10 of the ferroelectric capacitor, the plate line PL can be reused as the second electrode 20 of the ferroelectric capacitor. In the case where the bit line BL is reused as the second electrode 20 of the ferroelectric capacitor, the plate line PL can be reused as the first electrode 10 of the ferroelectric capacitor.

[0313] In some examples, after the board lines PL are formed, the memory array can be chemically and mechanically polished using a chemical mechanical polishing process to remove the material of the board lines PL located outside the gaps U.

[0314] In some embodiments, such as Figure 38 As shown, before forming the ferroelectric layer 30 in the plurality of first holes H1, the preparation method further includes step S107.

[0315] S107. A first sacrificial layer 08 and a second sacrificial layer 09 are sequentially formed in multiple first holes H1. Under the same etching conditions, the etching rate of the first sacrificial layer 08 is greater than the etching rate of the second sacrificial layer 09.

[0316] In some examples, the material of the first sacrificial layer 08 may include silicon oxide, and the material of the second sacrificial layer 09 may include polycrystalline silicon.

[0317] In some examples, the thickness of the first sacrificial layer 08 and the thickness of the second sacrificial layer 09 can both be 1 nm to 10 nm. For example, the thickness of the first sacrificial layer 08 and the thickness of the second sacrificial layer 09 can both be 1 nm, 2 nm, 5 nm, 8 nm, 10 nm, etc.

[0318] In some examples, a chemical vapor deposition process can be used to form a first sacrificial layer 08 on the pore wall of the first hole H1 via plasma reaction using SiH4 gas and N2O gas. After the formation of the first sacrificial layer 08, SiH4 gas is continuously introduced into the reaction chamber to promote its decomposition at high temperature, thereby forming a second sacrificial layer 09 on the first sacrificial layer 08.

[0319] In this embodiment of the application, before fabricating the ferroelectric layer 30, a first sacrificial layer 08 and a second sacrificial layer 09 are formed on the sidewalls of multiple first holes H1. This allows the first sacrificial layer 08 and the second sacrificial layer 09 to protect the ferroelectric layer 30, preventing damage to the ferroelectric layer during the subsequent etching of the second dielectric layer. This helps to ensure the performance of the ferroelectric capacitor 300 where the ferroelectric layer 30 is located, thereby ensuring the performance of the memory array.

[0320] Based on this, such as Figure 39 As shown, step S105 may include steps S151 and S152.

[0321] S151. Use the first wet etching process to etch the second dielectric layer 03 until the first sacrificial layer 08 is exposed.

[0322] S152. The first sacrificial layer 08 and the second sacrificial layer 09 are etched using a second wet etching process until the ferroelectric layer 30 is exposed. The etching solution used in the first wet etching process is different from the etching solution used in the second wet etching process.

[0323] For example, the first wet etching process can use a phosphoric acid (H3PO4) solution as the etching solution to etch the second dielectric layer 03. For instance, the memory array prepared in step S104 can be placed in an H3PO4 solution and immersed for 30 minutes to etch the second dielectric layer 03 laterally until the second sacrificial layer 09 is exposed.

[0324] Understandably, the etching time of the first wet etching process can be designed based on the reaction rate between the etching solution and the second dielectric layer O3. The etching time is not limited to 30 minutes when the etching solution and the material of the second dielectric layer are different.

[0325] For example, the second wet etching process can use hydrofluoric acid (HF) solution as the etching solution to etch the first sacrificial layer 08 and the second sacrificial layer 09 until the ferroelectric layer 30 is exposed.

[0326] Since the etching rate of the first sacrificial layer 08 is greater than that of the second sacrificial layer 09 under the same etching conditions, the etching speed of the first sacrificial layer 08 can be faster when the second wet etching process is used, which is beneficial to shorten the time of the second wet etching process and improve the fabrication efficiency of the memory array.

[0327] Since the etching rate of the second sacrificial layer 09 is less than that of the first sacrificial layer 08 under the same etching conditions, the etching rate of the second sacrificial layer 09 can be slower when using the second wet etching process. This is beneficial for better control of the progress of the second wet etching process, avoiding damage to the ferroelectric layer 30 by the etching solution in the second wet etching process, and ensuring the yield of the ferroelectric layer 30.

[0328] In some embodiments, see Figure 23 The preparation method may also include step S108.

[0329] S108. Form multiple first contact posts V1 and multiple second contact posts V2. Each first contact post V1 is connected to a bit line BL, and each second contact post V2 is connected to a plate line PL.

[0330] The first contact post V1 can transmit electrical signals to the bit line BL, or transmit signals on the bit line BL to the outside of the memory array. Similarly, the second contact post V2 can transmit electrical signals to the board line PL, or transmit signals on the board line PL to the outside of the memory array.

[0331] In some examples, a third dielectric layer 011 may be formed before forming the plurality of first contact posts V1 and the plurality of second contact posts V2, the third dielectric layer 011 covering the bit line BL. Each first contact post V1 penetrates the third dielectric layer 011 and is connected to the bit line BL, and each second contact post V2 penetrates the third dielectric layer 011 and is connected to the board line PL.

[0332] In some examples, the material of the third dielectric layer 011 can be the same as the material of the first dielectric layer 02.

[0333] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0334] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A ferroelectric capacitor, characterized in that, include: The first and second electrodes are positioned relative to each other; A ferroelectric layer is located between the first electrode and the second electrode, and the ferroelectric layer includes a main body layer and a first interface layer stacked together. The main body layer includes doped elements and hafnium oxide-based materials; the first interface layer includes oxides of a first element and oxides of a second element, wherein the difference between the ionic radius of the first element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms, and the difference between the ionic radius of the second element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms.

2. The ferroelectric capacitor according to claim 1, characterized in that, The difference between the ionic radius of the first element and the ionic radius of the second element is less than or equal to 0.1 angstroms.

3. The ferroelectric capacitor according to claim 1 or 2, characterized in that, The binding energy of the oxide of the first element and the binding energy of the oxide of the second element are both greater than or equal to the binding energy of hafnium oxide.

4. The ferroelectric capacitor according to any one of claims 1 to 3, characterized in that, One of the first element and the second element is the same as the dopant element.

5. The ferroelectric capacitor according to any one of claims 1 to 4, characterized in that, The doping element is zirconium, the first element is niobium, and the second element is zirconium.

6. The ferroelectric capacitor according to any one of claims 1 to 5, characterized in that, Along the direction away from the main layer, the first element and the second element are distributed alternately.

7. The ferroelectric capacitor according to any one of claims 1 to 5, characterized in that, Along the direction away from the main layer, the concentration of the first element gradually increases, the concentration of the second element gradually decreases, and the binding energy of the oxide of the first element is greater than the binding energy of the oxide of the second element.

8. The ferroelectric capacitor according to any one of claims 1 to 5, characterized in that, Along a direction away from the main body layer, at different locations in the first interface layer, the concentration of the first element is the same as the concentration of the second element.

9. The ferroelectric capacitor according to any one of claims 1 to 8, characterized in that, The ferroelectric layer further includes a second interface layer; The second interface layer is located on the side of the main body layer opposite to the first interface layer; the second interface layer includes an oxide of the first element and an oxide of the second element.

10. A method for preparing a ferroelectric capacitor, characterized in that, include: Form the first electrode; A ferroelectric layer is formed on one side of the first electrode. The ferroelectric layer includes a main layer and a first interface layer stacked together. The main layer includes a doping element and a hafnium oxide-based material. The first interface layer includes an oxide of a first element and an oxide of a second element. The difference between the ionic radius of the first element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms. The difference between the ionic radius of the second element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms. A second electrode is formed on the side of the ferroelectric layer away from the first electrode.

11. The preparation method according to claim 10, characterized in that, A ferroelectric layer is formed on one side of the first electrode, comprising: An atomic layer deposition process is used to form a host layer on one side of the first electrode; An atomic layer deposition process is used to form a first interface layer on one side of the first electrode.

12. The preparation method according to claim 11, characterized in that, The method employs atomic layer deposition to form a first interface layer on one side of the first electrode, comprising: A first sublayer of a first predetermined thickness is formed, wherein the first sublayer comprises an oxide of the first element; A second sublayer of a second predetermined thickness is formed, the second sublayer comprising an oxide of the second element; Repeat the above steps until the sum of the thickness of the first sub-layer and the thickness of the second sub-layer reaches the preset thickness.

13. The preparation method according to claim 11, characterized in that, The method employs atomic layer deposition to form a first interface layer on one side of the first electrode, comprising: A first sublayer is formed, in which the concentration of the first element is less than the concentration of the second element; A second sublayer is formed, in which the concentration of the first element is the same as the concentration of the second element; A third sublayer is formed, in which the concentration of the first element is greater than the concentration of the second element; The third sublayer is farther from the main layer than the first sublayer, and the second sublayer is located between the first sublayer and the third sublayer; the binding energy of the oxide of the first element is greater than the binding energy of the oxide of the second element.

14. The preparation method according to claim 13, characterized in that, In the first sublayer, the concentration ratio of the first element to the concentration of the second element is 1:3; In the second sublayer, the concentration ratio of the first element to the second element is 1:1; In the third sublayer, the concentration ratio of the first element to the second element is 3:

1.

15. The preparation method according to claim 11, characterized in that, Along a direction away from the main body layer, at different locations in the first interface layer, the concentration of the first element is the same as the concentration of the second element.

16. The preparation method according to any one of claims 11 to 15, characterized in that, A ferroelectric layer is formed on one side of the first electrode, and the method further includes: An atomic layer deposition process is used to form a second interface layer on the side of the main layer away from the first interface layer; the second interface layer includes an oxide of the first element and an oxide of the second element.

17. A storage array, characterized in that, include: Multiple storage cells, including ferroelectric capacitors as described in any one of claims 1 to 9, or ferroelectric capacitors prepared by the preparation method as described in any one of claims 10 to 16; Multiple board lines, each of which is connected to multiple of the memory cells; Multiple bit lines, each bit line being connected to multiple memory cells.

18. The storage array according to claim 17, characterized in that, The ferroelectric capacitor includes a first electrode and a second electrode arranged opposite to each other; the plate line is connected to the first electrode, and the bit line is connected to the second electrode.

19. A method for fabricating a memory array, characterized in that, include: Multiple first dielectric layers and multiple second dielectric layers are formed alternately on a substrate; Along the thickness direction of the substrate, the plurality of first dielectric layers and the plurality of second dielectric layers are etched to form a plurality of first holes; A ferroelectric layer is formed in the plurality of first holes; the ferroelectric layer is located on the hole wall of the plurality of first holes, and the ferroelectric layer and the bottom wall of the first holes form a second hole; The ferroelectric layer includes a main layer and a first interface layer stacked together. A bit line is formed in the second hole; The second dielectric layer is etched to form voids; the voids expose a portion of the surface of the ferroelectric layer. A plate line is formed in the gap, and the plate line is in contact with the ferroelectric layer; The main body layer includes a doped element and a hafnium oxide-based material; the first interface layer includes an oxide of a first element and an oxide of a second element, wherein the difference between the ionic radius of the first element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms, and the difference between the ionic radius of the second element and the ionic radius of hafnium is greater than zero and less than or equal to 0.1 angstroms.

20. The preparation method according to claim 19, characterized in that, Before forming the ferroelectric layer in the plurality of first holes, the preparation method further includes: A first sacrificial layer and a second sacrificial layer are sequentially formed in the plurality of first holes; wherein, under the same etching conditions, the etching rate of the first sacrificial layer is greater than the etching rate of the second sacrificial layer.

21. The preparation method according to claim 20, characterized in that, The etching of the second dielectric layer to form voids includes: The second dielectric layer is etched using a first wet etching process until the first sacrificial layer is exposed; The first sacrificial layer and the second sacrificial layer are etched using a second wet etching process until the ferroelectric layer is exposed; the etching solution used in the first wet etching process is different from the etching solution used in the second wet etching process.

22. A memory, characterized in that, include: The storage array as described in claim 17 or 18, or the storage array prepared by the method described in any one of claims 19 to 21; The controller is electrically connected to the storage array.

23. An electronic device, characterized in that, include: Circuit board; The memory of claim 22, wherein the memory is located on the circuit board and is electrically connected to the circuit board.

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