Magnetic storage device, and method for manufacturing a magnetic storage device

Abstract

Provided are a magnetic storage device capable of ensuring flatness of an electrode provided between a switching element and a magnetoresistance effect element, and a manufacturing method of the magnetic storage device. A magnetic storage device of an embodiment includes a selector body, an MTJ body provided above the selector body, and an electrode provided between the selector body and the MTJ body. The electrode includes a first sub-electrode having a first conductive body and a second conductive body located at a position closer to the MTJ body than the first conductive body and in contact with the first conductive body. The first conductive body has a crystal structure. The second conductive body has an amorphous structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to a magnetic storage device and a method for manufacturing a magnetic storage device. Background Technology

[0002] Magnetoresistive random access memory (MRAM) is known to use magnetoresistive elements as storage elements. The magnetoresistive element is connected in series with a switching element to function as a storage cell. Summary of the Invention

[0003] A magnetic storage device is provided that ensures the flatness of the electrodes disposed between the switching element and the magnetoresistive effect element, and a method for manufacturing the magnetic storage device is provided.

[0004] The magnetic storage device of this embodiment includes a selector body, an MTJ body disposed above the selector body, and an electrode disposed between the selector body and the MTJ body. The electrode includes a first sub-electrode having a first conductor and a second conductor located closer to the MTJ body than the first conductor and connected to the first conductor. The first conductor has a crystalline structure. The second conductor has an amorphous structure. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example of the configuration of the magnetic storage device according to the first embodiment.

[0006] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the magnetic storage device according to the first embodiment.

[0007] Figure 3 This is a perspective view showing an example of the three-dimensional structure of the memory cell array included in the magnetic storage device according to the first embodiment.

[0008] Figure 4 This is an example of a cross-sectional structure of the memory cell array included in the magnetic storage device according to the first embodiment, along... Figure 3 A cross-sectional view along line IV-IV.

[0009] Figure 5 This is an example of a cross-sectional structure of the memory cell array included in the magnetic storage device according to the first embodiment, along... Figure 3 A cross-sectional view of the VV line.

[0010] Figure 6 This is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive element included in the magnetic storage device according to the first embodiment.

[0011] Figure 7 This is a flowchart illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment.

[0012] Figure 8 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment.

[0013] Figure 9 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment.

[0014] Figure 10 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment.

[0015] Figure 11 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment.

[0016] Figure 12 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment.

[0017] Figure 13 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment.

[0018] Figure 14 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment.

[0019] Figure 15 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the first embodiment.

[0020] Figure 16 This is a cross-sectional view used to illustrate the process of exposing the upper surface of the intermediate electrode in the manufacturing method of the memory cell array in the magnetic storage device of the comparative example.

[0021] Figure 17 This is an example of a cross-sectional structure of the memory cell array included in the magnetic storage device according to the second embodiment, along... Figure 3 A cross-sectional view along line IV-IV.

[0022] Figure 18 This is an example of a cross-sectional structure of the memory cell array included in the magnetic storage device according to the second embodiment, along... Figure 3A cross-sectional view of the VV line.

[0023] Figure 19 This is a flowchart illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment.

[0024] Figure 20 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment.

[0025] Figure 21 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment.

[0026] Figure 22 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment.

[0027] Figure 23 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment.

[0028] Figure 24 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment.

[0029] Figure 25 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment.

[0030] Figure 26 This is a cross-sectional view illustrating an example of a method for manufacturing a memory cell array in a magnetic storage device according to the second embodiment.

[0031] Explanation of reference numerals in the attached figures

[0032] 1, 1A…magnetic storage device; 10, 10A…memory cell array; 11…row selection circuit; 12…column selection circuit; 13…decoding circuit; 14…write circuit; 15…read circuit; 16…voltage generation circuit; 17…input / output circuit; 18…control circuit; 21, 22…conductors; 23…electrode; 24…selector body; 25…electrode; 26…MTJ body; 27, 28…conductors; 31…ferromagnetic material; 32…… …Non-magnetic material, 33…Ferromagnetic material, 34…Non-magnetic material, 35…Ferromagnetic material, 36…Non-magnetic material, 40-45…Insulator, 51, 52…Mask, 122…Conductive layer, 123…Electrode layer, 124…Selector layer, 126…MTJ layer, 251, 252, 253…Sub-electrodes, 252a, 252b…Conductors, 1251, 1253…Sub-electrode layers, 1252a, 1252b…Conductive layers. Detailed Implementation

[0033] Hereinafter, embodiments will be described with reference to the accompanying drawings. The embodiments illustrate apparatuses and methods for embodying the technical concept of the invention. The drawings are schematic or conceptual. The dimensions, scales, etc., of each drawing may not be the same as reality. Some structural illustrations have been omitted. The shading lines added to the plan views may not be related to the raw materials or properties of the constituent elements. In this specification, the same reference numerals are added to constituent elements having substantially the same function and structure. The numbers, text, etc., added to the reference numerals are used for reference based on the same reference numerals and to distinguish similar elements from each other. Furthermore, in this specification, "a laminated film containing A / B" indicates a laminated structure of a film containing element A and a film containing element B.

[0034] 1. First Implementation Method

[0035] The magnetic storage device according to the first embodiment will be described. The magnetic storage device according to the first embodiment includes, for example, a magnetic storage device based on perpendicular magnetization that uses an element having a magnetoresistance effect through a magnetic tunnel junction (MTJ) as a resistance-changing element. Furthermore, in the following description, this resistance-changing element will also be referred to as a magnetoresistance effect element (MTJ).

[0036] 1.1 Composition

[0037] First, the configuration of the magnetic storage device according to the first embodiment will be described.

[0038] 1.1.1 Composition of Magnetic Storage Devices

[0039] Figure 1 This is a block diagram illustrating an example of the configuration of the magnetic storage device according to the first embodiment. Figure 1 As shown, the magnetic storage device 1 includes a storage cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a write circuit 14, a read circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0040] The storage cell array 10 includes multiple storage cells MC, each corresponding to a group of rows and columns. Storage cells MC located in the same row are connected to the same word line WL. Storage cells MC located in the same column are connected to the same bit line BL.

[0041] Row selection circuit 11 is connected to memory cell array 10 via word line WL. The decoding result (row address) of address ADD from decoding circuit 13 is provided to row selection circuit 11. Row selection circuit 11 sets the word line WL corresponding to the row based on the decoding result of address ADD to the selected state.

[0042] Column selection circuit 12 is connected to memory cell array 10 via bit line BL. The decoding result (column address) of address ADD from decoding circuit 13 is provided to column selection circuit 12. Column selection circuit 12 sets the bit line BL corresponding to the column based on the decoding result of address ADD to the selected state.

[0043] Decoding circuit 13 decodes the address ADD from input / output circuit 17. Decoding circuit 13 provides the decoding result of address ADD to row selection circuit 11 and column selection circuit 12. Address ADD includes the selected row address and column address.

[0044] The write circuit 14 writes data to the storage unit MC. The write circuit 14 includes, for example, a write driver (not shown).

[0045] The readout circuit 15 reads data from the storage cell MC. The readout circuit 15 includes, for example, a sense amplifier (not shown).

[0046] The voltage generation circuit 16 uses the power supply voltage supplied by an external device (not shown) to the magnetic storage device 1 to generate voltages for various operations of the storage cell array 10. For example, the voltage generation circuit 16 generates various voltages required during a write operation and outputs them to the write circuit 14. Additionally, for example, the voltage generation circuit 16 generates various voltages required during a read operation and outputs them to the read circuit 15.

[0047] Input / output circuit 17 manages communication with the external magnetic storage device 1. Input / output circuit 17 transmits the address ADD from the external magnetic storage device 1 to the decoding circuit 13. Input / output circuit 17 transmits the control signal CNT and command CMD from the external magnetic storage device 1 to the control circuit 18. Input / output circuit 17 transmits the data DAT from the external magnetic storage device 1 to the write circuit 14, and outputs the data DAT transmitted from the read circuit 15 to the external magnetic storage device 1.

[0048] The control circuit 18 controls the operation of the row selection circuit 11, column selection circuit 12, decoding circuit 13, writing circuit 14, reading circuit 15, voltage generation circuit 16, and input / output circuit 17 within the magnetic storage device 1 based on the control signal CNT and the command CMD.

[0049] 1.1.2 Composition of Storage Cell Array

[0050] Next, use Figure 2 The configuration of the storage cell array 10 of the magnetic storage device 1 according to the first embodiment will be described. Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 10 included in the magnetic storage device 1 according to the first embodiment. Figure 2 In the text, the word line WL and the bit line BL are indicated by categorization using markers containing the index "<>".

[0051] like Figure 2 As shown, the memory cells MC are arranged in a matrix within the memory cell array 10, and are connected to multiple bit lines BL (BL... <0> BL <1> BL <n>One or more word lines WL (WL) <0> WL <1> ..., WL <m>Establish a correspondence between the group of 1 item in ) (M and N are natural numbers). That is, the storage unit MC<i,j> (0≤i≤M、0≤j≤N) connected to word line WL With bit line BL <j>between.

[0052] Storage unit MC<i,j> Including series-connected switching elements SEL<i,j> and magnetoresistive element MTJ<i,j> .

[0053] The switching element SEL is a 2-terminal switching element. It differs from 3-terminal switching elements such as transistors in that it does not have a third terminal. When the voltage applied between the two terminals is less than the threshold voltage Vth (voltage applied between the two terminals < threshold voltage Vth), the switching element SEL is in a high-resistance state. This high-resistance state is, for example, an "OFF" state, which is electrically non-conductive. When the voltage applied between the two terminals is greater than or equal to the threshold voltage Vth (voltage applied between the two terminals ≥ threshold voltage Vth), the switching element SEL is in a low-resistance state. This low-resistance state is, for example, an "ON" state, which is electrically conductive. More specifically, for example, when the voltage applied to the corresponding memory cell MC is less than the threshold voltage Vth (voltage applied to the corresponding memory cell MC < threshold voltage Vth), the switching element SEL, acting as a high-resistance insulator, cuts off the current. That is, it becomes a OFF state. When the voltage applied to the corresponding memory cell MC is greater than or equal to the threshold voltage Vth (the voltage applied to the corresponding memory cell MC is ≥ the threshold voltage Vth), the switching element SEL, acting as a conductor with low resistance, allows current to flow. That is, it becomes in the ON state. Regardless of the polarity of the voltage applied between the two terminals (regardless of the direction of the flowing current), the switching element SEL switches between allowing current to flow or cutting off current in accordance with the magnitude of the voltage applied to the corresponding memory cell MC. In the following description, the switching element SEL will also be referred to as the "selector body".

[0054] The magnetoresistive element (MTJ) changes between a low-resistance state and a high-resistance state depending on the current controlled by the switching element (SEL). In other words, the resistance state of the MTJ can be switched between low and high resistance states by the current controlled by the switching element (SEL). Data can be written to the MTJ through changes in its resistance state, and the written data is retained non-volatilely, thus functioning as a readable storage element. In the following description, the magnetoresistive element (MTJ) will also be referred to as the "MTJ body".

[0055] 1.1.3 Construction of Storage Cell Array

[0056] Next, the structure of the memory cell array 10 of the magnetic storage device 1 according to the first embodiment will be described. In the following description, an xyz orthogonal coordinate system will be used. The X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction relative to the surface of the semiconductor substrate used in the formation of the magnetic storage device 1. The term "down" and its derivatives and related terms indicate a smaller coordinate position on the z-axis. The term "up" and its derivatives and related terms indicate a larger coordinate position on the z-axis. Shaded lines are appropriately added in the perspective view. The shaded lines added in the perspective view are not necessarily related to the materials or characteristics of the constituent elements to which the shaded lines are added. Illustrations of structures such as interlayer insulating films are omitted in the perspective view and cross-sectional view.

[0057] 1.1.3.1 Three-dimensional structure of memory cell array

[0058] use Figure 3 An example of the three-dimensional structure of the memory cell array 10 will be described. Figure 3 This is a perspective view showing an example of the three-dimensional structure of the storage cell array 10 included in the magnetic storage device 1 according to the first embodiment.

[0059] The memory cell array 10 is disposed above a semiconductor substrate (not shown).

[0060] like Figure 3 As shown, the memory cell array 10 includes multiple conductors (wiring) 21, multiple conductors (wiring) 28, and multiple memory cells MC.

[0061] Above the multiple conductors 21, multiple conductors 28 are disposed.

[0062] Each of the multiple conductors 21 has a portion extending in the X direction. The multiple conductors 21 are arranged in the Y direction and separated from each other. Each conductor 21 is used as a word line WL.

[0063] Each of the plurality of conductors 28 has a portion extending in the Y direction. The plurality of conductors 28 are arranged in the X direction and are separated from each other. Each conductor 28 is used as a bit line BL.

[0064] Conductors 21 and 28 are arranged separately from each other in the Z direction. At the intersections of the multiple conductors 21 and 28, a memory cell MC is provided. In other words, each memory cell MC is arranged in a columnar shape between the word line WL and the bit line BL that establish the association. The memory cell MC, for example, has a configuration where a switching element SEL is located below a magnetoresistive element MTJ.

[0065] Furthermore, the memory cell array 10 may have a structure in which conductors 28, memory cells MC, and conductors 21 are stacked in this order.

[0066] 1.1.3.2 Cross-sectional structure of the memory cell array

[0067] use Figure 4 as well as Figure 5 An example of the cross-sectional structure of the memory cell array 10 will be described. Figure 4 This is an example of a cross-sectional structure of the memory cell array 10 included in the magnetic storage device 1 according to the first embodiment, along... Figure 3 A cross-sectional view along line IV-IV. Figure 5 This is an example of a cross-sectional structure of the memory cell array 10 included in the magnetic storage device 1 according to the first embodiment, along... Figure 3 A cross-sectional view of the VV line.

[0068] like Figure 4 as well as Figure 5 As shown, the memory cell array 10 includes multiple conductors 21, multiple conductors 22, multiple electrodes 23, multiple selector bodies 24, multiple electrodes 25, multiple MTJ bodies 26, multiple conductors 27, multiple conductors 28, and insulators 40 to 45.

[0069] Above a semiconductor substrate (not shown), for example, a plurality of conductors 21 are disposed. The plurality of conductors 21 are arranged along the Y direction. Each of the plurality of conductors 21 extends along the X direction. Each of the plurality of conductors 21 is conductive and functions as a word line WL.

[0070] An insulator 40 is provided in the region between two adjacent conductors 21 in the Y direction. Thus, the multiple conductors 21 are mutually insulated. The insulator 40 is made of an insulating material, for example, containing silicon oxide (SiO2) or silicon nitride (SiN). Alternatively, the insulator 40 may be made of multiple insulating materials.

[0071] Furthermore, the multiple conductors 21 and the insulators 40 can be disposed on the upper surface of the semiconductor substrate, or they can be disposed separately from the semiconductor substrate without being in contact with it.

[0072] Multiple conductors 22 are disposed on the upper surface of each of the multiple conductors 21. The multiple conductors 22 disposed on the upper surface of the same conductor 21 are arranged in the X direction. Each of the multiple conductors 22 is conductive. The single conductor 21 and the multiple conductors 22 disposed on the upper surface of the conductor 21 are collectively referred to as the word line WL.

[0073] On the upper surface of each of the plurality of conductors 22, one corresponding electrode 23 from a plurality of electrodes 23 is disposed. Each of the plurality of electrodes 23 is conductive and functions as the lower electrode BE.

[0074] On the upper surface of each of the plurality of electrodes 23, one corresponding selector body 24 is provided from a plurality of selector bodies 24. Each of the plurality of selector bodies 24 functions as a switching element SEL.

[0075] On the upper surface of each of the multiple selector bodies 24, one corresponding electrode 25 from a plurality of electrodes 25 is disposed. Each of the plurality of electrodes 25 functions as an intermediate electrode ME.

[0076] Each of the plurality of electrodes 25 includes conductors 251, 252, and 253. In the following description, conductor 251 will also be referred to as "sub-electrode 251". Conductor 252 will also be referred to as "sub-electrode 252". Conductor 253 will also be referred to as "sub-electrode 253".

[0077] A sub-electrode 251 is disposed on the upper surface of the selector body 24. The sub-electrode 251 is disposed to improve the characteristics of the selector body 24. The sub-electrode 251 is made of a conductive material, for example, containing at least one element or compound selected from carbon (C) and carbon nitride (CN). The sub-electrode 251 has, for example, an amorphous structure. The thickness of the sub-electrode 251 is, for example, more than 2 nanometers (nm) and less than 20 nanometers (nm). If the thickness of the sub-electrode 251 is within such a range, the peeling of the sub-electrode 251 from the upper surface of the selector body 24 can be suppressed.

[0078] Sub-electrode 252 is disposed on the upper surface of sub-electrode 251. Sub-electrode 252 includes conductors 252a and 252b. The thickness of sub-electrode 252 is, for example, 20 nanometers (nm) or more and 50 nanometers (nm) or less.

[0079] Conductor 252a is disposed on the upper surface of sub-electrode 251. Conductor 252b is disposed on the upper surface of conductor 252a. In other words, conductor 252b is located closer to the MTJ body 26 than conductor 252a and is in contact with conductor 252a. Conductor 252b is disposed to ensure the flatness of electrode 25 (intermediate electrode ME).

[0080] Conductors 252a and 252b are made of conductive materials. Conductors 252a and 252b may contain at least one element or compound selected from high-melting-point metal elements and compounds of high-melting-point metal elements. In this embodiment, a high-melting-point metal is, for example, a material with a melting point higher than that of iron (Fe) and cobalt (Co). Such conductive materials may contain, for example, at least one element or compound selected from titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). Furthermore, conductor 252b contains impurities. To enable electrode 25 to function as an electrode, the impurities contained in conductor 252b may be materials that are conductive even when the conductor 252b contains such impurities. Such impurities may contain, for example, at least one element or compound selected from aluminum (Al), silicon (Si), boron (B), and carbon (C). Thus, conductor 252b contains a compound of the aforementioned conductive material and the aforementioned impurities, and is conductive. The conductive material and impurities described above used in conductor 252b can be appropriately combined.

[0081] Furthermore, conductors 252a and 252b may also contain impurities such as elements contained in the gas used in the manufacturing process of the magnetic storage device 1, and elements mixed into the aforementioned portion from its surroundings. Conductor 252b may also contain impurities different from those described above.

[0082] The conductor 252a has a crystalline structure. The thickness of the conductor 252a is, for example, 10 nanometers (nm) or more and 40 nanometers (nm) or less.

[0083] The conductor 252b containing the aforementioned impurities has an amorphous structure. As described later, the upper surface of the conductor 252b has higher flatness compared to a crystalline structure where the upper surface becomes convex downwards through an etching process. Generally, the higher the concentration of impurities contained in the conductor, the higher the resistance of the conductor. Since the conductor 252b contains the aforementioned impurities, the resistance of the conductor 252b is higher than that of the conductor 252a. Furthermore, the thicker the conductor 252b, the higher its resistance. Therefore, the thicker the conductor 252b in the sub-electrode 252, the higher the resistance of the sub-electrode 252, and the higher the resistance of the electrode 25. Preferably, the resistance of the electrode 25 is low. Therefore, the thickness of the conductor 252b is set to be thinner than that of the conductor 252a. The thickness of the conductor 252b is such that the flatness of the upper surface of the conductor 252b can be ensured through the etching process described later. The thickness of conductor 252b is, for example, 10 nanometers (nm).

[0084] Sub-electrode 253 is disposed on the upper surface of sub-electrode 252 and on the upper surface of insulator 42. Sub-electrode 253 is made of a conductive material, such as containing at least one element or compound selected from titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). Sub-electrode 253, for example, has a crystalline structure.

[0085] Furthermore, electrode 25 (intermediate electrode ME) is not limited to Figure 4 as well as Figure 5 The electrode 25 may also include other layers, for example. Furthermore, if the characteristics of the selector body 24 can be sufficiently ensured, the electrode 25 may not include the sub-electrode 251. If the flatness of the electrode 25 can be sufficiently ensured by the conductor 252b, the electrode 25 may not include the sub-electrode 253.

[0086] In the following description, the structure including conductor 22, electrode 23, selector body 24, sub-electrode 251, and sub-electrode 252 will be referred to as a "first stack". The memory cell array 10 includes a plurality of first stacks. An insulator 42 is provided on each side of the plurality of first stacks in such a way that it covers the side. That is, the insulator 42 covers the side of conductor 22, the side of electrode 23, the side of selector body 24, the side of sub-electrode 251, and the side of sub-electrode 252. The insulator 42 is provided, for example, from the upper surface of conductor 21 to the upper surface of sub-electrode 252. In addition, an insulator 42 is also provided on the upper surface of conductor 21 and the upper surface of insulator 40 between two adjacent first stacks in the X or Y direction. The insulator 42 is made of an insulating material, such as silicon nitride. In addition, the insulator 42 may also be made of multiple insulating materials.

[0087] An insulator 41 is disposed on the upper surface of the insulator 42. The insulator 41 is embedded, for example, from the position of the upper surface of the insulator 42 disposed on the upper surface of the conductor 21 to the position of the upper surface of the sub-electrode 252. The insulator 41 is made of an insulating material, such as silicon oxide or silicon nitride. Alternatively, the insulator 41 may be made of multiple insulating materials.

[0088] On the upper surface of each of the plurality of sub-electrodes 253 (the plurality of electrodes 25), one corresponding MTJ body 26 from the plurality of MTJ bodies 26 is disposed. Each of the plurality of MTJ bodies 26 functions as a magnetoresistive element MTJ. Details regarding the configuration of the MTJ bodies 26 will be described later.

[0089] On the upper surface of each of the plurality of MTJ bodies 26, one corresponding conductor 27 of a plurality of conductors 27 is disposed. Each of the plurality of conductors 27 functions as a hard mask during the processing of the sub-electrode 253 and the MTJ body 26. The conductor 27 is made of a conductive material, such as containing at least one element or compound selected from titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

[0090] In the following description, the structure including sub-electrode 253, MTJ body 26, and conductor 27 will be referred to as a "second stack". The memory cell array 10 includes multiple second stacks. An insulator 44 is provided on each side of the multiple second stacks in such a way that it covers the side. That is, the insulator 44 covers the side of the sub-electrode 253, the side of the MTJ body 26, and the side of the conductor 27. The insulator 44 is provided, for example, from the position of the upper surface of the insulator 41 to the position of the upper surface of the conductor 27. In addition, an insulator 44 is also provided on the upper surface of the insulator 41 and the upper surface of the insulator 42 between two adjacent second stacks in the X or Y direction. The insulator 44 is made of an insulating material, such as silicon nitride. In addition, the insulator 44 may also be made of multiple insulating materials.

[0091] An insulator 43 is disposed on the upper surface of the insulator 44. The insulator 43 is embedded, for example, from the position of the upper surface of the insulator 44 disposed on the upper surface of the insulator 41 to the position of the upper surface of the conductor 27. The insulator 43 is made of an insulating material, such as silicon oxide or silicon nitride. Alternatively, the insulator 43 may be made of multiple insulating materials.

[0092] A conductor 28 is provided in such a way that it is in contact with the upper surface of each of the plurality of conductors 27 arranged in the Y direction. The plurality of conductors 28 are arranged in the X direction. Each of the plurality of conductors 28 extends along the Y direction. Each of the plurality of conductors 28 is conductive and functions as a bit line BL.

[0093] An insulator 45 is provided in the region between two adjacent conductors 28 in the X direction. Thus, the multiple conductors 28 are mutually insulated. The insulator 45 is made of an insulating material, such as silicon oxide or silicon nitride. Alternatively, the insulator 45 may be made of multiple insulating materials.

[0094] 1.1.4 Cross-sectional structure of magnetoresistive element

[0095] Next, use Figure 6 An example of the cross-sectional structure of the magnetoresistive element MTJ, i.e., the MTJ body, of the magnetic storage device 1 according to the first embodiment will be described. Figure 6 This is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive element MTJ included in the magnetic storage device 1 according to the first embodiment.

[0096] The MTJ body 26 used as a magnetoresistive element includes a ferromagnetic body 31, a non-magnetic body 32, a ferromagnetic body 33, a non-magnetic body 34, a ferromagnetic body 35, and a non-magnetic body 36.

[0097] Ferromagnetic material 31 is a conductive film exhibiting ferromagnetism. Ferromagnetic material 31 has an easy magnetization axis in a direction perpendicular to the film surface (Z direction). Ferromagnetic material 31 contains iron (Fe). Ferromagnetic material 31 may also contain at least one element selected from cobalt (Co) and nickel (Ni). Additionally, ferromagnetic material 31 may also contain boron (B). More specifically, for example, ferromagnetic material 31 contains cobalt-iron-boron (CoFeB), iron boride (FeB), or cobalt boride (CoB). Ferromagnetic material 31 is used as a storage layer SL.

[0098] A nonmagnetic body 32 is disposed on the lower surface of the ferromagnetic body 31. The nonmagnetic body 32 is a nonmagnetic insulating film. The nonmagnetic body 32 is used as a tunnel barrier layer TB. The nonmagnetic body 32 is disposed between the ferromagnetic body 31 and the ferromagnetic body 33, forming a magnetic tunnel junction together with the ferromagnetic body 31 and the ferromagnetic body 33. In addition, when an initial amorphous layer such as cobalt iron boron (CoFeB) is used as the interface layer between the ferromagnetic body 31 and the ferromagnetic body 33, the nonmagnetic body 32 functions as a seed material for growing a crystalline film from the interface with the ferromagnetic body 31 during the crystallization process of the ferromagnetic body 31. Similarly, when cobalt iron boron (CoFeB) is used as the interface layer of the ferromagnetic body 33, the nonmagnetic body 32 also functions as a seed material relative to the ferromagnetic body 33. Here, the initial amorphous layer refers to a layer that is amorphous immediately after film formation and crystallizes after annealing. The nonmagnetic body 32 has a tetragonal or cubic crystal structure with the film surface oriented at the (001) plane. Magnesium oxide (MgO) is an example of an oxide used for the nonmagnetic body 32. Magnesium oxide (MgO) has a NaCl structure. When magnesium oxide (MgO) is used for the nonmagnetic body 32, the (001) interface of magnesium oxide (MgO) is integrated with the (001) interface of cobalt iron boron (CoFeB). Therefore, cobalt iron boron (CoFeB) undergoes crystal growth through annealing, resulting in a body-centered cubic structure with (001) orientation.

[0099] A ferromagnetic body 33 is disposed on the lower surface of the non-magnetic body 32. The ferromagnetic body 33 is a conductive film possessing ferromagnetism. The ferromagnetic body 33 is used as a reference layer RL. The ferromagnetic body 33 has an easy magnetization axis in a direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic body 33 is fixed. Figure 6 In the example, the magnetization direction of the ferromagnetic material 33 is from the ferromagnetic material 33 toward the ferromagnetic material 31. Furthermore, "the magnetization direction is fixed" means that the magnetization direction will not change due to a torque of a magnitude capable of reversing the magnetization direction of the ferromagnetic material 31. Typically, an interface layer is used in the ferromagnetic material 33. As the interface layer of the ferromagnetic material 33, an initial amorphous layer such as cobalt-iron-boron (CoFeB) can be used. Moreover, an auxiliary ferromagnetic layer is provided such that the surface in contact with the cobalt-iron-boron (CoFeB) layer is on the opposite side to the surface in contact with the magnesium oxide (MgO) layer. This auxiliary ferromagnetic layer, for example, comprises an alloy film selected from at least one of cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd). This auxiliary ferromagnetic layer becomes a laminate containing Co / Pt, a laminate containing Co / Pd, or the like. The cobalt-iron-boron (CoFeB) layer, which serves as the initial amorphous layer, is stacked with the aforementioned CoPt, CoPd, Co / Pt-containing laminated films, Co / Pd-containing laminated films, etc. In this case, the interface layer in the ferromagnetic body 33, such as the aforementioned CoFeB layer, has MgO with a (001) orientation formed on the side closer to the nonmagnetic body 32 compared to the other layers.

[0100] A non-magnetic body 34 is disposed on the lower surface of the ferromagnetic body 33. The non-magnetic body 34 is a conductive film having a non-magnetic properties. The non-magnetic body 34 is used as a spacer layer SP. The non-magnetic body 34 contains, for example, elements selected from ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr), or alloys thereof. The thickness of the non-magnetic body 34 is, for example, less than 2 nanometers (nm).

[0101] A ferromagnetic body 35 is disposed on the lower surface of the non-magnetic body 34. In other words, the ferromagnetic body 35 is disposed on the side opposite to the ferromagnetic body 31, relative to the ferromagnetic body 33. The ferromagnetic body 35 is a conductive film with ferromagnetism. The ferromagnetic body 35 is used as a offset cancellation layer SCL. The ferromagnetic body 35 has an easy magnetization axis in a direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic body 35 is fixed. Figure 6 In this example, the magnetization direction of the ferromagnetic body 35 is from the ferromagnetic body 33 toward the ferromagnetic body 35. The ferromagnetic body 35 may, for example, comprise an alloy layer selected from at least one of cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd). Alternatively, the ferromagnetic body 35 may also be a laminate containing Co / Pt, or a laminate containing Co / Pd, etc.

[0102] Ferromagnetic materials 33 and 35 are antiferromagnetically coupled through a nonmagnetic material 34. That is, ferromagnetic materials 33 and 35 are coupled with magnetization directions that are antiparallel to each other. This coupling structure of ferromagnetic material 33, nonmagnetic material 34, and ferromagnetic material 35 is called a SAF (Synthetic Anti-Ferromagnetic) structure. Through the SAF structure, ferromagnetic material 35 can counteract the effect of the leakage magnetic field of ferromagnetic material 33 on the change in the magnetization direction of ferromagnetic material 31. Therefore, ferromagnetic material 35 can reduce the leakage magnetic field of the actual ferromagnetic material 33.

[0103] A non-magnetic body 36 is disposed on the lower surface of the ferromagnetic body 35. The non-magnetic body 36 is a conductive film having a non-magnetic properties. The non-magnetic body 36 is used as an underlayer (UL). The non-magnetic body 36 contains, for example, at least one element selected from zirconium (Zr), hafnium (Hf), tungsten (W), chromium (Cr), molybdenum (Mo), niobium (Nb), titanium (Ti), tantalum (Ta), vanadium (V), ruthenium (Ru), and platinum (Pt).

[0104] The MTJ body 26 can achieve either a low-resistance state or a high-resistance state depending on whether the magnetization directions of the storage layer SL and the reference layer RL are parallel or antiparallel. In this embodiment, the magnetization direction of the storage layer SL relative to the magnetization direction of the reference layer RL is controlled by flowing a write current through the MTJ body 26. Specifically, a write method utilizing the spin transfer torque generated by the current flowing through the MTJ body 26 is employed.

[0105] In MTJ body 26, the direction from storage layer SL towards reference layer RL is... Figure 6 When a write current Ic0 of a certain magnitude flows in the direction of arrow A1, the relative magnetization directions of the storage layer SL and the reference layer RL become parallel. In this parallel state, the resistance of the MTJ body 26 is at its lowest, and the MTJ body 26 is set to a low-resistance state. This low-resistance state is called the "P (Parallel) state," for example, it is defined as the state of data "0".

[0106] Additionally, in MTJ body 26, in the direction from the reference layer RL towards the storage layer SL, i.e. Figure 6 When a write current Ic1, which is larger than the write current Ic0, flows in the direction of arrow A2, the relative magnetization directions of the storage layer SL and the reference layer RL become antiparallel. In this antiparallel state, the resistance of the MTJ body 26 is the highest, and the MTJ body 26 is set to a high-resistance state. This high-resistance state is called the "AP (Anti-Parallel) state," for example, it is defined as the state of data "1".

[0107] Furthermore, the methods for specifying data "1" and data "0" are not limited to the examples above. For example, the P state can also be specified as data "1" and the AP state as data "0".

[0108] In addition, MTJ body 26 is not limited to Figure 6 The structure of the MTJ body 26 may include other layers, or each magnetic body may consist of multiple layers.

[0109] 1.2 Manufacturing Method of Memory Cell Array

[0110] Next, the manufacturing method of the storage cell array 10 of the magnetic storage device 1 according to the first embodiment will be described. Figure 7 This is a flowchart illustrating an example of a method for manufacturing a storage cell array 10 in a magnetic storage device 1 according to the first embodiment. Figures 8-15 This is a cross-sectional view illustrating an example of a method for manufacturing a storage cell array 10 in a magnetic storage device 1 according to the first embodiment. Figures 8-15 Is with Figure 4 The corresponding sectional view.

[0111] First of all, Figure 7 In S11, a plurality of conductors 21 and an insulator 40 are formed on the upper surface of the semiconductor substrate (not shown) that serves as the wafer WF.

[0112] Specifically, after a conductive layer is formed on the upper surface of a semiconductor substrate, a mask with partial openings, except for the area corresponding to the word line WL, is formed by photolithography or the like. Then, by anisotropic etching of the formed mask, the conductive layer is cut to form a plurality of conductors 21 arranged along the Y direction, and a hole reaching the semiconductor substrate is formed. The anisotropic etching in this process is, for example, RIE (Reactive Ion Etching). Then, an insulator 40 is buried in the formed hole. Thus, the insulator 40 is formed.

[0113] Next, in Figure 7 In S12, a conductor 22, an electrode 23, a selector body 24, a sub-electrode 251, a conductor 252a, and a conductor 252b are formed on the upper surface of each of the plurality of conductors 21.

[0114] Specifically, such as Figure 8 As shown, a conductor layer 122, an electrode layer 123, a selector layer 124, a sub-electrode layer 1251, a conductor layer 1252a, and a conductor layer 1252b are sequentially formed on the upper surfaces of the plurality of conductors 21 and the upper surface of the insulator 40.

[0115] Sub-electrode layer 1251 contains at least one element or compound selected from carbon (C) and carbon nitride (CN). Sub-electrode layer 1251, for example, contains carbon (C). Conductor layers 1252a and 1252b contain at least one element or compound selected from high-melting-point metals and compounds of high-melting-point metal elements. Conductor layers 1252a and 1252b, for example, contain titanium nitride (TiN). Additionally, conductor layer 1252b contains at least one element or compound selected from aluminum (Al), silicon (Si), boron (B), and carbon (C). Conductor layer 1252b, for example, contains aluminum (Al).

[0116] The conductive layers 1252a and 1252b are formed, for example, by sputtering as follows. In this sputtering process, the steps of forming conductive layer 1252a and forming conductive layer 1252b are performed consecutively. First, on the upper surface of sub-electrode layer 1251 (above selector layer 124), conductive layer 1252a is formed by sputtering a conductive material (at least one element or compound selected from high-melting-point metals and compounds of high-melting-point metal elements). The thickness of conductive layer 1252a is, for example, 20 nanometers (nm). Next, on the upper surface of conductive layer 1252a, conductive layer 1252b is formed by co-sputtering a conductive material (at least one element or compound selected from high-melting-point metals and compounds of high-melting-point metal elements) and an impurity (at least one element or compound selected from aluminum (Al), silicon (Si), boron (B), and carbon (C)). In the process of forming the conductive layer 1252b, the aforementioned impurities are added to ensure flatness. As a result, the conductive layer 252b has an amorphous structure. The thickness of the conductive layer 1252b is thicker than the amount (thickness) removed by etching, as described later. The thickness of the conductive layer 1252b is, for example, the amount (thickness) removed by etching + 10 nanometers (nm). The amount removed by etching is, for example, 3 nanometers (nm) or more and 5 nanometers (nm) or less. Furthermore, the conductive layers 1252a and 1252b can also be formed in the same manner as described above using ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition).

[0117] Next, as Figure 9 As shown, multiple masks 51 are formed. The multiple masks 51 are configured to have openings in portions of the conductor layer 122, electrode layer 123, selector layer 124, sub-electrode layer 1251, conductor layer 1252a, and conductor layer 1252b, excluding the regions corresponding to the manufactured conductor 22, electrode 23, selector body 24, sub-electrode 251, and sub-electrode 252. The multiple masks 51, for example, contain titanium nitride (TiN) to protect the portions that function as conductor 22, electrode 23, selector body 24, sub-electrode 251, and sub-electrode 252 during ion beam etching (IBE), as described later. The multiple masks 51 are, for example, provided as multiple cylindrical structures arranged in a matrix on the upper surface of the conductor layer 1252b, each of which protects a region corresponding to one memory cell MC.

[0118] Next, as Figure 9 As shown, the conductor layer 122, electrode layer 123, selector layer 124, sub-electrode layer 1251, conductor layer 1252a, and conductor layer 1252b are etched by ion beam etching. As a result, portions of the conductor layer 122, electrode layer 123, selector layer 124, sub-electrode layer 1251, conductor layer 1252a, and conductor layer 1252b that are not protected by the multiple masks 51 are removed, exposing the multiple conductors 21 and insulator 40 located beneath these portions. Through such ion beam etching, as... Figure 10 As shown, conductor layer 122, electrode layer 123, selector layer 124, sub-electrode layer 1251, conductor layer 1252a, and conductor layer 1252b are processed to form multiple conductors 22, multiple electrodes 23, multiple selector bodies 24, multiple sub-electrodes 251, multiple conductors 252a, and multiple conductors 252b. That is, a structure is formed in which conductors 22, electrodes 23, selector bodies 24, sub-electrodes 251, conductors 252a, and conductors 252b are stacked. In other words, multiple first stacks are formed, each including conductor 22, electrode 23, selector body 24, sub-electrode 251, and sub-electrode 252.

[0119] Next, in Figure 7 In S13, such as Figure 11 As shown, an insulator 42 is formed on the upper surface of each of the plurality of conductors 21, on the upper surface of the insulator 40, on the upper surface of each of the plurality of first stacks, and on the side surface of each of the plurality of first stacks. That is, an insulator 42 is formed on the upper surface of the conductor 252b, and on the side surface of each of the conductor 22, the electrode 23, the selector body 24, the sub-electrode 251, the conductor 252a, and the conductor 252b.

[0120] Next, in Figure 7 In S14, such as Figure 11 As shown, the insulator 41 is embedded from the position of the upper surface of the insulator 42 disposed on the upper surface of the conductor 21 to the position of the upper surface of the insulator 42 disposed on the upper surface of the conductor 252b.

[0121] Next, in Figure 7 In S15, such as Figure 11 As shown, the upper surfaces of insulator 41 and insulator 42 are planarized. Planarization in this process is performed, for example, by CMP (Chemical Mechanical Polishing).

[0122] Next, in Figure 7 In S16, the upper surface of the conductor 252b is exposed.

[0123] Specifically, by etching back, a portion of insulator 41, a portion of insulator 42, and a portion of the upper surface of conductor 252b are removed, exposing the upper surface of conductor 252b.

[0124] It exists in the process Figure 7 After planarization in S15, the thickness of the insulator 42 differs near the center and the ends of the region MAT where the memory cell array 10 is configured. For example, the thickness of the insulator 42 near the center is greater than that near the ends. Therefore, in this process, in order to expose the upper surface of all the conductors 252b configured in the region MAT, over-etching is performed based on the difference between the thickness of the insulator 42 near the center and the thickness of the insulator 42 near the ends. For example, the ratio of the etching rate of the conductive material (e.g., titanium nitride) contained in the conductors 252a and 252b to the etching rate of the insulating material (e.g., silicon nitride) contained in the insulators 42 and 43 is set to approximately 1, and the back-etching time is extended by approximately 30%. Thus, as Figure 12 As shown, not only a portion of insulator 41 and a portion of insulator 42, but also a portion of the upper surface of conductor 252b is removed, exposing the upper surface of conductor 252b. The thickness of conductor 252b after etching back is, for example, 10 nanometers (nm). The etching back in this process is, for example, RIE.

[0125] Next, in Figure 7 In S17, sub-electrodes 253, MTJ bodies 26, and conductors 27 are formed on the upper surfaces of the plurality of first-layer stacks, respectively.

[0126] Specifically, such as Figure 13 As shown, a sub-electrode layer 1253 and an MTJ layer 126 are sequentially formed on the upper surface of the conductor 252b, the upper surface of the insulator 41, and the upper surface of the insulator 42. The MTJ layer 126 is... Figure 6 The MTJ body 26 described herein is a laminate formed by stacking the layers in a flat manner according to their stacking order.

[0127] Next, a plurality of conductors 27 are formed. The plurality of conductors 27 are formed by photolithography or the like, creating openings in portions of the sub-electrode layer 1253 and the MTJ layer 126, excluding the regions corresponding to the fabricated sub-electrodes 253 and MTJ bodies 26. The plurality of conductors 27 may contain, for example, titanium nitride, to protect the portions that function as sub-electrodes 253 and MTJ bodies 26 during ion beam etching. The plurality of conductors 27 may be provided, for example, as a plurality of cylindrical structures arranged in a matrix on the upper surface of the MTJ layer 126, each of which protects a region corresponding to a memory cell MC.

[0128] Next, the sub-electrode layer 1253 and the MTJ layer 126 are etched using ion beam etching. This removes portions of the sub-electrode layer 1253 and the MTJ layer 126 that are not protected by the plurality of conductors 27, exposing the insulators 41 and 42 beneath these portions. Through such ion beam etching, as... Figure 14 As shown, sub-electrode layer 1253 and MTJ layer 126 are processed to form a plurality of sub-electrodes 253 and a plurality of MTJ bodies 26. Sub-electrodes 253 are formed on the upper surface of conductor 252b. MTJ bodies 26 are formed on the upper surface of sub-electrodes 253 (above conductor 252b). That is, a structure is formed in which sub-electrodes 253, MTJ bodies 26, and conductors 27 are stacked. In other words, a plurality of second stacked bodies are formed, each including a sub-electrode 253, an MTJ body 26, and a conductor 27.

[0129] Next, in Figure 7 In S18, an insulator 44 is formed on the upper surface of the insulator 41, the upper surface of the insulator 42, and the side surfaces of the plurality of second stacked bodies.

[0130] Specifically, after forming insulating layers on the upper surface of insulator 41, the upper surface of insulator 42, the upper surfaces of each of the plurality of second-layer stacks, and the side surfaces of each of the plurality of second-layer stacks, the insulator on the upper surfaces of each of the plurality of second-layer stacks is removed by back etching. Thus, as... Figure 15 As shown, insulator 44 is formed.

[0131] Next, in Figure 7 In S19, such as Figure 15 As shown, the insulator 43 is embedded from the position of the upper surface of the insulator 44 on the upper surface of the insulator 41 to the position of the upper surface of the conductor 27.

[0132] Next, in Figure 7 In S20, such as Figure 15 As shown, the upper surfaces of conductor 27, insulator 43, and insulator 44 are planarized. This planarization process is performed, for example, by CMP.

[0133] Next, in Figure 7 In S21, a plurality of conductors 28 and insulators 45 are formed on the upper surfaces of the plurality of second stacked bodies, the upper surface of insulator 43, and the upper surface of insulator 44.

[0134] Specifically, after conductive layers are formed on the upper surfaces of the multiple second-layer stacks, the upper surface of insulator 43, and the upper surface of insulator 44, a mask with partial openings except for the region corresponding to the bit line BL is formed by photolithography or the like. Then, by using anisotropic etching of the formed mask, the conductive layers are cut to form multiple conductors 28 arranged along the X direction, and holes reaching insulators 43 and 44 are formed. The anisotropic etching in this process is, for example, RIE. Then, insulator 45 is embedded in the formed holes. Thus, insulator 45 is formed.

[0135] By implementing in this way Figure 7 S11 to S21 form Figure 4 as well as Figure 5 The layered structure shown.

[0136] Through the above processes, a configuration corresponding to the memory cell array 10 is formed on the wafer WF. Then, the wafer WF is cut into chip units to form the magnetic storage device 1.

[0137] The magnetic storage device 1 is formed through the manufacturing process described above. Furthermore, the manufacturing process described above is merely an example and is not limited to it. For example, other processes may be inserted between the manufacturing processes, or some processes may be omitted or combined. Additionally, the manufacturing processes may be interchanged to the extent possible.

[0138] 1.3 Effects of this implementation method

[0139] According to the magnetic storage device 1 of the first embodiment, the flatness of the electrode 25 (intermediate electrode ME) can be ensured. Hereinafter, the effects of the magnetic storage device 1 according to the first embodiment will be described in detail.

[0140] Figure 16 This is a cross-sectional view illustrating the process of exposing the upper surface of the intermediate electrode in the manufacturing method of the memory cell array in the comparative example magnetic storage device. The comparative example magnetic storage device includes a selector body, an MTJ body disposed above the selector body, and an intermediate electrode 61 disposed between the selector body and the MTJ body. Figure 16 The comparative example magnetic storage device includes an intermediate electrode 61, insulators 63 disposed on the upper surface and sides of the intermediate electrode 61, and insulators 62 embedded between the insulators 63. The intermediate electrode 61, for example, comprises titanium nitride. The intermediate electrode 61 has a crystalline structure. The insulators 62 and 63, for example, comprise silicon nitride.

[0141] When over-etching (etching back) is performed with the ratio of the etching rate of titanium nitride contained in intermediate electrode 61 to the etching rate of silicon nitride contained in insulators 62 and 63 set to approximately 1, it is considered that ideally, the upper surfaces of intermediate electrode 61 and the upper surfaces of insulators 62 and 63 become coplanar after etching.

[0142] However, in reality as Figure 16 As shown, there are cases where titanium nitride is etched more than silicon nitride (titanium nitride is over-etched), and the upper surface of the intermediate electrode 61 is etched to a point below the upper surfaces of the insulators 62 and 63, resulting in a downward convex shape on the upper surface of the intermediate electrode 61. Furthermore, the more the etching progresses, the greater the height (depth) of the convex shape.

[0143] In the crystal structure of titanium nitride, it is known that the (111) facet on silicon oxide (SiO2) has a preferred orientation, that is, a preferred orientation in the direction perpendicular to the film surface (upper surface) (hereinafter referred to as the "normal direction"). Because titanium nitride has this orientation, and because the height of the convex shape increases with etching progress as described above, the reason for the over-etching of titanium nitride is considered to be that the etching rate varies depending on the orientation of the crystal facet. More specifically, it is believed that, as... Figure 16 As shown, the etching rate (E / R) in the normal direction is greater than the etching rate (E / R) in the direction parallel to the film surface (upper surface) (hereinafter referred to as "parallel direction"). In other words, it is believed that the crystallinity of titanium nitride may lead to over-etching of titanium nitride.

[0144] In this embodiment, a selector layer 124 is formed. Above the selector layer 124, a conductive layer 1252a is formed using the aforementioned conductive material. On the upper surface of the conductive layer 1252a, a conductive layer 1252b is formed using the aforementioned conductive material and the aforementioned impurities. The conductive layer 1252b with the aforementioned impurities has an amorphous structure. By processing the selector layer 124, and the conductive layers 1252a and 1252b thus formed, a selector body 24 and a sub-electrode 252 including the conductors 252a and 252b are formed. Although the conductive layers 1252a and 1252b (sub-electrode 252) have a preferred orientation in the normal direction, in the conductive layer 252b with an amorphous structure formed as described above, the difference in etching rate between the normal direction and the parallel direction disappears. Therefore, in the process of exposing the conductor 252b ( Figure 7 In S16), the upper surface of the conductor 252b does not become a convex shape downwards; the upper surface of the conductor 252b is parallel to... Figure 16 The planarity of the intermediate electrode 61 with a crystal structure (a crystal structure in which the upper surface is convex downwards through an etch-back process) is higher than that of the other electrode. Therefore, the upper surface of the sub-electrode 253 disposed on the upper surface of the conductor 252b is also higher than that of the sub-electrode disposed on the upper surface of a crystal structure in which the upper surface is convex downwards through an etch-back process. Therefore, according to the magnetic storage device 1 and the manufacturing method of the magnetic storage device 1 according to this embodiment, the planarity of the electrode 25 can be ensured. Furthermore, the planarity of the upper surface of the sub-electrode 253 is higher than that of the sub-electrode 253 disposed on the upper surface of a crystal structure in which the upper surface is convex downwards through an etch-back process. Therefore, the upper surfaces of each layer comprising the MTJ body 26 disposed on the upper surface of the sub-electrode 253 are also higher than that of the sub-electrode 253 disposed on the upper surface of a crystal structure in which the upper surface is convex downwards through an etch-back process. Therefore, according to the magnetic storage device 1 and the manufacturing method of the magnetic storage device 1 according to this embodiment, the characteristics (e.g., coercivity) of the MTJ body 26 can be improved.

[0145] Furthermore, the thickness of conductor 252b is thinner than the thickness of conductor 252a. Therefore, the resistance of sub-electrode 252 is lower than that of the case where sub-electrode 252 is entirely amorphous. Therefore, according to the magnetic storage device 1 and the manufacturing method of magnetic storage device 1 according to this embodiment, the resistance of electrode 25 can be reduced compared to the case where sub-electrode 252 is entirely amorphous.

[0146] 2. Second Implementation Method

[0147] The magnetic storage device according to the second embodiment will be described. In the magnetic storage device 1A according to the second embodiment, the cross-sectional structure of the sub-electrode 252 and the manufacturing method of the storage cell array 10A are different from those of the first embodiment. Hereinafter, the differences from the first embodiment will be described.

[0148] 2.1 Cross-sectional structure of the memory cell array

[0149] use Figure 17 as well as Figure 18 An example of the cross-sectional structure of the memory cell array 10A will be described. Figure 17 This is an example of a cross-sectional structure of the memory cell array 10A included in the magnetic storage device 1A according to the second embodiment, shown along the path shown in the first embodiment. Figure 3 A cross-sectional view along line IV-IV. Figure 18 This is an example of a cross-sectional structure of the memory cell array 10A included in the magnetic storage device 1A according to the second embodiment, shown along the path shown in the first embodiment. Figure 3 A cross-sectional view of the VV line.

[0150] like Figure 17 as well as Figure 18 As shown, the memory cell array 10A includes multiple conductors 21, multiple conductors 22, multiple electrodes 23, multiple selector bodies 24, multiple electrodes 25, multiple MTJ bodies 26, multiple conductors 27, multiple conductors 28, and insulators 40 to 45.

[0151] The sub-electrode 252 is made of a conductive material, for example, containing at least one element or compound selected from high-melting-point metal elements and compounds of high-melting-point metal elements. Such a conductive material may contain, for example, at least one element or compound selected from titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). Additionally, the sub-electrode 252 contains impurities. To enable the electrode 25 to function as an electrode, the impurities contained in the sub-electrode 252 can be materials that are conductive in the presence of these impurities. Such impurities may contain, for example, at least one element or compound selected from aluminum (Al), silicon (Si), boron (B), and carbon (C). Thus, the sub-electrode 252 contains a compound of the aforementioned conductive material and the aforementioned impurities, and is conductive. The aforementioned conductive material and the aforementioned impurities used in the sub-electrode 252 can be appropriately combined. The thickness of the sub-electrode 252 is, for example, 20 nanometers (nm) or more and 50 nanometers (nm) or less.

[0152] Furthermore, the sub-electrode 252 may also contain impurities such as elements contained in the gas used in the manufacturing process of the magnetic storage device 1, and elements mixed into the aforementioned portion from its surroundings. Alternatively, the sub-electrode 252 may also contain impurities different from those described above.

[0153] Sub-electrode 252 includes conductors 252a and 252b. Conductor 252b is located on the upper side of sub-electrode 252. In other words, conductor 252b is located on the MTJ body 26 side closer to conductor 252a than conductor 252a and is in contact with conductor 252a. Conductor 252b is formed by ion implantation as described later. Therefore, sub-electrode 252 has the aforementioned impurity concentration gradient in a direction perpendicular to the upper surface of sub-electrode 252 (normal direction), and conductors 252a and 252b are integrated. The aforementioned impurity concentration in conductor 252b is higher than that in conductor 252a. Conductor 252b is the portion within sub-electrode 252 with a relatively high concentration of the aforementioned impurities. Conductor 252b has an amorphous structure. As described later, the upper surface of conductor 252b has higher flatness compared to a crystalline structure where the upper surface becomes convex downwards through an etching process. The thickness of conductor 252b is, for example, the depth of ions implanted via ion implantation. A peak concentration of the aforementioned impurities exists within the range from the upper surface of conductor 252b to the depth of ions implanted via ion implantation. In other words, sub-electrode 252 has the peak concentration of the aforementioned impurities within conductor 252b. Conductor 252a is the portion within sub-electrode 252 where the concentration of the aforementioned impurities is relatively low. Within conductor 252a, the concentration of the aforementioned impurities decreases the closer it is to the lower surface of sub-electrode 252. Conductor 252a has a crystalline structure.

[0154] The cross-sectional structure of the memory cell array 10A other than the sub-electrode 252 is the same as that shown in the first embodiment. Figure 4 as well as Figure 5 It's the same.

[0155] 2.2 Manufacturing Method of Memory Cell Array

[0156] The manufacturing method of the storage cell array 10A of the magnetic storage device 1A according to the second embodiment will be described. Figure 19 This is a flowchart illustrating an example of a method for manufacturing a memory cell array 10A in a magnetic storage device 1A according to the second embodiment. Figures 20-26 This is a cross-sectional view illustrating an example of a method for manufacturing a storage cell array 10A in a magnetic storage device 1A according to the second embodiment. Figures 20-26 Is with Figure 17 The corresponding sectional view.

[0157] exist Figure 19 In the flowchart shown, the first embodiment is shown Figure 7 In the flowchart, S12 is replaced by S31. Figure 7 S32 is added between S15 and S16 in the flowchart. Apart from S31 and S32, it is consistent with the flowchart shown in the first embodiment. Figure 7 The flowcharts are the same.

[0158] First, it is implemented in the same manner as the first embodiment. Figure 19 After the S11, Figure 19 In S31, a conductor 22, an electrode 23, a selector body 24, a sub-electrode 251, and a conductor 252a are formed on the upper surface of each of the plurality of conductors 21.

[0159] Specifically, such as Figure 20 As shown, a conductor layer 122, an electrode layer 123, a selector layer 124, a sub-electrode layer 1251, and a conductor layer 1252a are sequentially formed on the upper surfaces of the plurality of conductors 21 and the insulator 40.

[0160] Sub-electrode layer 1251 contains at least one element or compound selected from carbon (C) and carbon nitride (CN). For example, sub-electrode layer 1251 contains carbon (C). Conductor layer 1252a contains at least one element or compound selected from high-melting-point metals and compounds of high-melting-point metal elements. For example, conductor layer 1252a contains titanium nitride (TiN).

[0161] The conductive layer 1252a is formed, for example, by sputtering. On the upper surface of the sub-electrode layer 1251 (above the selector layer 124), the conductive layer 1252a is formed by sputtering a conductive material (at least one element or compound selected from high-melting-point metals and compounds of high-melting-point metal elements). The thickness of the conductive layer 1252a is, for example, the amount removed by etching (thickness) + 30 nanometers (nm). The amount removed by etching is, for example, 3 nanometers (nm) or more and 5 nanometers (nm) or less. Alternatively, the conductive layer 1252a can also be formed by ALD or CVD in the same manner as described above.

[0162] Next, as Figure 21 As shown, multiple masks 52 are formed. The multiple masks 52 are configured to have openings in portions of the conductor layer 122, electrode layer 123, selector layer 124, sub-electrode layer 1251, and conductor layer 1252a, excluding the regions corresponding to the manufactured conductors 22, electrodes 23, selector layers 24, sub-electrodes 251, and sub-electrodes 252, through photolithography or the like. The multiple masks 52, for example, contain titanium nitride (TiN) to protect the portions that function as conductors 22, electrodes 23, selector layers 24, sub-electrodes 251, and sub-electrodes 252 during ion beam etching. The multiple masks 52 are, for example, provided as multiple cylindrical structures arranged in a matrix on the upper surface of the conductor layer 1252a, each of which protects a region corresponding to one memory cell MC.

[0163] Next, as Figure 21 As shown, the conductor layer 122, electrode layer 123, selector layer 124, sub-electrode layer 1251, and conductor layer 1252a are etched by ion beam etching. As a result, portions of the conductor layer 122, electrode layer 123, selector layer 124, sub-electrode layer 1251, and conductor layer 1252a that are not protected by the multiple masks 52 are removed, exposing the multiple conductors 21 and insulator 40 located beneath these portions. Through such ion beam etching, as... Figure 22 As shown, conductor layer 122, electrode layer 123, selector layer 124, sub-electrode layer 1251, and conductor layer 1252a are processed to form multiple conductors 22, multiple electrodes 23, multiple selector bodies 24, multiple sub-electrodes 251, and multiple conductors 252a. That is, a structure is formed in which conductors 22, electrodes 23, selector bodies 24, sub-electrodes 251, and conductors 252a are stacked. In other words, multiple first stacks are formed, each including conductor 22, electrode 23, selector body 24, sub-electrode 251, and sub-electrode 252.

[0164] After implementation Figure 19 After S31, the same procedure as in the first embodiment is followed. Figure 19 S13 to S15. First, as... Figure 23 As shown, an insulator 42 is formed on the upper surface of each of the plurality of conductors 21, the upper surface of the insulator 40, the upper surface of each of the plurality of first laminates, and the side surface of each of the plurality of first laminates. That is, an insulator 42 is formed on the upper surface of the conductor 252a, and on the side surface of the conductor 22, the electrode 23, the selector body 24, the sub-electrode 251, and the conductor 252a. Next, an insulator 41 is embedded from the position of the upper surface of the insulator 42 provided on the upper surface of the conductor 21 to the position of the upper surface of the insulator 42 provided on the upper surface of the conductor 252b. Next, the upper surfaces of the insulator 41 and the upper surfaces of the insulator 42 are planarized.

[0165] Next, in Figure 19 In S32, a conductor 252b is formed on the upper side of the conductor 252a.

[0166] Specifically, such as Figure 24 As shown, impurities are added to the conductor 252a from its upper surface side via ion implantation. The impurities comprise at least one element or compound selected from aluminum (Al), silicon (Si), boron (B), and carbon (C). For example, the impurities include aluminum (Al).

[0167] When implanted ions reach the selector body 24 and the sub-electrode 251 (or the vicinity of the selector body 24 and the sub-electrode 251), the characteristics of the selector body 24 and the sub-electrode 251 may degrade. Therefore, the accelerating voltage used in ion implantation is preferably set to an accelerating voltage that does not reach the sub-electrode 251. Furthermore, for example, it is preferable that the ion implantation depth is set to a depth less than half the film thickness of the sub-electrode 252 (e.g., 10 nanometers (nm)), and the peak concentration of impurities is set to a depth approximately half the ion implantation depth (e.g., 5 nanometers (nm)). Thus, as... Figure 25 As shown, the upper part of the sub-electrode 252 changes from a crystalline structure to an amorphous structure, and a conductor 252b is formed on the upper part of the sub-electrode 252.

[0168] Next, the same procedure as in the first embodiment is followed. Figure 19 S16. Therefore, as... Figure 26 As shown, a portion of insulator 41, a portion of insulator 42, and a portion of the upper surface of conductor 252b are removed, exposing the upper surface of conductor 252b.

[0169] Next, the same procedure as in the first embodiment is followed. Figure 19 S17 to S21. Thus, [the following is formed]. Figure 17 as well as Figure 18 The layered structure shown.

[0170] Through the above process, a configuration equivalent to the memory cell array 10A is formed on the wafer WF. Then, the wafer WF is cut into chip units to form the magnetic storage device 1A.

[0171] The magnetic storage device 1A is formed through the manufacturing process described above. Furthermore, the manufacturing process described above is merely an example and is not limited to it. For example, other processes may be inserted between the manufacturing processes, or some processes may be omitted or combined. Additionally, the manufacturing processes may be interchanged to the extent possible.

[0172] 2.3 Effects of this implementation method

[0173] In this embodiment, a selector layer 124 is formed, and a conductive layer 1252a is formed above the selector layer 124 using the aforementioned conductive material. By processing the selected layer 124 and the conductive layer 1252a thus formed, a selector body 24 and a sub-electrode 252 including the conductor 252a are formed. The aforementioned impurities are added to the conductor 252a from its upper surface. As a result, a conductor 252b is formed on the upper portion of the conductor 252a (sub-electrode 252). The conductor 252b has an amorphous structure. Therefore, in the conductor 252b with its amorphous structure, the difference in etching rate between the normal direction and the parallel direction disappears. Thus, in the process of exposing the conductor 252b (…),… Figure 19 In S16), the upper surface of the conductor 252b does not become convex downwards, and the flatness of the upper surface of the conductor 252b is higher compared to the case where the upper surface becomes convex downwards through the etching process. Therefore, according to the magnetic storage device 1A and the manufacturing method of the magnetic storage device 1A according to this embodiment, the flatness of the electrode 25 can be ensured, and the characteristics of the MTJ body 26 can be improved.

[0174] Furthermore, the aforementioned impurities are added via ion implantation, thereby forming a conductor 252b on the upper side of the sub-electrode 252. Therefore, the sub-electrode 252 has the aforementioned impurity concentration gradient in the normal direction, and the conductors 252a and 252b are integrated. The concentration of the aforementioned impurities in the conductor 252b is higher than the concentration of the aforementioned impurities in the conductor 252a. The sub-electrode 252 has a peak concentration of the aforementioned impurities within the conductor 252b. Additionally, the penetration depth of the impurity ion implantation is set to be less than half the film thickness of the sub-electrode 252 (the sum of the film thicknesses of the integrated conductors 252a and 252b). For example, when the film thickness of the sub-electrode 252 is set to 30 nanometers (nm) and the penetration depth of the impurity ion implantation is set to 10 nanometers (nm), the thickness of the conductor 252a is 20 nanometers (nm), and the thickness of the conductor 252b is 10 nanometers (nm). Therefore, the thickness of conductor 252b is thinner than the thickness of conductor 252a. Consequently, the resistance of sub-electrode 252 is lower than in the case where sub-electrode 252 is entirely amorphous. Therefore, according to the magnetic storage device 1A and its manufacturing method as described in this embodiment, similar to the first embodiment, the resistance of electrode 25 can be reduced compared to the case where sub-electrode 252 is entirely amorphous.

[0175] 3. Variations, etc.

[0176] As described above, the magnetic storage device (1) according to the embodiment includes a selector body (24), an MTJ body (26) disposed above the selector body, and an electrode (25) disposed between the selector body and the MTJ body. The electrode (25) includes a first sub-electrode (252), which has a first conductor (252a) and a second conductor (252b) located on the side closer to the MTJ body (26) than the first conductor and connected to the first conductor. The first conductor (252a) has a crystalline structure. The second conductor (252b) has an amorphous structure.

[0177] Furthermore, the implementation method is not limited to the manner described above, and various modifications are possible.

[0178] Furthermore, the flowcharts described in the above embodiments can be rearranged in the order of their processing to the extent possible.

[0179] In the first embodiment, the conductor 252b may also not contain the aforementioned conductive material and the aforementioned impurity compound. For example, the conductor 252b may be composed of a material having an amorphous structure (amorphous material) and possess conductivity. The amorphous material may also be a material unrelated to the aforementioned conductive material (an amorphous material that does not contain the material of the conductor 252a). In this case, similar to the first embodiment, the upper surface of the conductor 252b has higher flatness compared to the case where the upper surface becomes convex downwards due to a crystal structure formed by an etching process. Furthermore, in this case, for example, in the process of forming the conductor layer 1252a, the conductor layer 1252a is formed by sputtering a conductive material (at least one element or compound selected from high-melting-point metals and compounds of high-melting-point metal elements). In the process of forming the conductor layer 1252b, the conductor layer 1252b is formed by sputtering using the aforementioned amorphous material. Furthermore, conductive layers 1252a and 1252b can also be formed in the same manner as described above using ALD or CVD. In the conductor 252b with an amorphous structure, the difference in etching rates between the normal direction and the parallel direction disappears. Therefore, similar to the first embodiment, the upper surface of the conductor 252b has higher flatness compared to the case where the upper surface becomes convex downwards due to a crystalline structure formed by a back etching process.

[0180] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in a variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents.< / j> < / m> < / n>

Claims

1. A magnetic storage device comprising: Select the device; MTJ body, disposed above the selector body; and An electrode is disposed between the selector body and the MTJ body. The electrode includes a first sub-electrode, which has a first conductor and a second conductor located closer to the MTJ body than the first conductor and connected to the first conductor. The first conductor has a crystalline structure. The second conductor has an amorphous structure.

2. The magnetic storage device according to claim 1, The second conductor contains impurities.

3. The magnetic storage device according to claim 2, The impurities contain at least one element or compound selected from aluminum (Al), silicon (Si), boron (B), and carbon (C).

4. The magnetic storage device according to claim 2 or 3, The first conductor and the second conductor contain at least one element or compound selected from titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

5. The magnetic storage device according to claim 1, The second conductor is made of an amorphous material.

6. The magnetic storage device according to claim 5, The first conductor contains at least one element or compound selected from titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

7. The magnetic storage device according to claim 1, The first sub-electrode contains impurities. The concentration of impurities in the second conductor is higher than the concentration of impurities in the first conductor.

8. The magnetic storage device according to claim 7, The impurities contain at least one element or compound selected from aluminum (Al), silicon (Si), boron (B), and carbon (C).

9. The magnetic storage device according to claim 7 or 8, The first sub-electrode contains at least one element or compound selected from titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

10. The magnetic storage device according to claim 1, The first sub-electrode contains impurities. The first sub-electrode has a concentration gradient of the impurities in a direction perpendicular to the upper surface of the first sub-electrode, and the second conductor has a peak concentration of the impurities.

11. The magnetic storage device according to claim 1, The thickness of the second conductor is thinner than the thickness of the first conductor.

12. The magnetic storage device according to claim 1, The first sub-electrode has a preferred orientation in a direction perpendicular to the upper surface of the first sub-electrode.

13. The magnetic storage device according to claim 1, The electrode also includes a second sub-electrode disposed between the selector body and the first conductor. The second sub-electrode contains at least one element or compound selected from carbon (C) and carbon nitride (CN).

14. The magnetic storage device according to claim 1, The electrode also includes a third sub-electrode disposed between the second conductor and the MTJ body. The third sub-electrode contains at least one element or compound selected from titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

15. The magnetic storage device according to claim 1, The MTJ body includes: First ferromagnetic material; Second ferromagnetic material; The third ferromagnetic body is disposed on the side opposite to the first ferromagnetic body relative to the second ferromagnetic body; A first non-magnetic body is disposed between the first ferromagnetic body and the second ferromagnetic body; A second non-magnetic body is disposed between the second ferromagnetic body and the third ferromagnetic body; and The third non-magnetic body is disposed on the lower surface of the third ferromagnetic body.

16. A method for manufacturing a magnetic storage device, comprising: Form a selector layer; Above the selector layer, a first conductor layer is formed using a first conductive material; On the upper surface of the first conductive layer, a second conductive layer is formed using a second conductive material and impurities; A selector body is formed by processing the selector layer, a first conductor is formed by processing the first conductor layer, and a second conductor is formed by processing the second conductor layer. An insulator is formed on the upper surface of the second conductor and on the side surfaces of the selector body, the first conductor, and the second conductor, respectively. The upper surface of the second conductor is exposed by removing a portion of the insulator and a portion of the upper surface of the second conductor. as well as An MTJ body is formed above the second conductor.

17. The method for manufacturing a magnetic storage device according to claim 16, The removal of a portion of the insulator and a portion of the upper surface of the second conductor includes over-etching.

18. A method for manufacturing a magnetic storage device, comprising: Form a selector layer; Above the selector layer, a first conductor layer is formed using a first conductive material; A selector body is formed by processing the selector layer, and a first conductor is formed by processing the first conductor layer; An insulator is formed on the upper surface of the first conductor and on the respective sides of the selector body and the first conductor; By adding impurities to the first conductor, a second conductor is formed on the upper part of the first conductor; The upper surface of the second conductor is exposed by removing a portion of the insulator and a portion of the upper surface of the second conductor. as well as An MTJ body is formed above the second conductor.

19. The method for manufacturing a magnetic storage device according to claim 18, The addition of impurities to the first conductor includes the addition of the impurities by ion implantation.

20. The method for manufacturing a magnetic storage device according to claim 18, The removal of a portion of the insulator and a portion of the upper surface of the second conductor includes over-etching.

Images