storage device

Abstract

The present disclosure provides a storage device capable of accurately reading out data. The storage device of an embodiment is provided with a memory circuit including a memory cell block and a sense amplifier circuit, and a control circuit. The memory cell includes a variable resistance element and a switching element, and stores data corresponding to a resistance state of the variable resistance element. The sense amplifier circuit includes a first circuit portion through which a first current corresponding to a first value obtained by a readout operation of target data flows, a second circuit portion through which a second current corresponding to a second value obtained by a readout operation of reference data flows, a third circuit portion connected in parallel to the second circuit portion and through which a third current flows, and an output portion that outputs a detection signal based on a relationship between a magnitude of the first current and a magnitude of a total current of the second and third currents. The control circuit includes an adjustment circuit that adjusts the third current for each of the sense amplifier circuits.

Description

Technical Field

[0001] Embodiments of the present invention relate to storage devices. Background Technology

[0002] A memory device is proposed that integrates multiple memory cells, each including a magnetoresistive element (variable resistor element) and a selector (switching element), on a semiconductor substrate. Summary of the Invention

[0003] A storage device is provided that can improve the reading operation of data stored in the storage unit.

[0004] The storage device according to the embodiment includes: a memory circuit comprising a plurality of memory cell blocks, each including a plurality of memory cells, and a plurality of sense amplifier circuits respectively provided for each of the plurality of memory cell blocks; and a control circuit that controls the memory circuit, wherein each of the plurality of memory cells includes a variable resistor element and a switching element connected in series with the variable resistor element, and stores data corresponding to one of a low resistance state and a high resistance state of the variable resistor element, and each of the plurality of sense amplifier circuits includes: a first circuit portion in which a first current corresponding to a first value obtained by a first readout operation flows, the first readout operation being an operation of reading object data stored in a selected memory cell among the plurality of memory cells; a second circuit portion; and a third circuit portion. The circuit comprises: a first circuit section in which a second current flows corresponding to a second value obtained by a second readout action, the second readout action being the action of reading reference data written to the selected memory cell during a write action performed after the first readout action; a third circuit section connected in parallel with the second circuit section in which a third current flows when the second current flows in the second circuit section; and an output section that outputs a detection signal corresponding to the object data based on the magnitude of the first current and the magnitude of the combined current of the second and third currents; the control circuit includes an adjustment circuit that adjusts the third current flowing in the third circuit section for each of the plurality of sense amplifier circuits. Attached Figure Description

[0005] Figure 1 This is a block diagram schematically illustrating the basic structure of a storage device according to an embodiment.

[0006] Figure 2 This is a perspective view schematically illustrating the configuration of the storage cell blocks of the storage device according to an embodiment.

[0007] Figure 3 This is a cross-sectional view schematically illustrating the basic configuration of the magnetoresistive element of a storage device according to an embodiment.

[0008] Figure 4 This is a cross-sectional view schematically illustrating the basic configuration of the selector of the storage device according to an embodiment.

[0009] Figure 5 This is a flowchart illustrating the self-reference readout operation in the storage device of an embodiment.

[0010] Figure 6 This is a timing chart illustrating the self-reference readout operation in the storage device of the embodiment.

[0011] Figure 7 This is a circuit diagram illustrating the configuration of the sense amplifier circuit of the storage device according to an embodiment.

[0012] Figure 8 This is a diagram schematically illustrating the relationship between various currents flowing in the transistors included in the sensing amplifier circuit of the storage device in an embodiment.

[0013] Figure 9 This is a diagram illustrating a method for determining the offset voltage of a storage device according to an embodiment.

[0014] Figure 10 This is a flowchart illustrating the operation of the storage device according to an embodiment.

[0015] Figure 11 This is a diagram illustrating the fine-tuning process in the storage device of an embodiment.

[0016] Label Explanation

[0017] 10… Bottom wiring, 20… Top wiring, 30… Memory cell, 40… Magnetoresistive element (variable resistance element), 41… Memory layer, 42… Reference layer, 43… Tunnel barrier layer, 50… Selector (switching element), 51… Bottom electrode, 52… Top electrode, 53… Selector material layer, 100… Memory device, 200… Memory circuit, 210… Memory cell block, 220… Sensing amplifier circuit, 300… Control circuit, 310… Adjustment circuit, 311… Holding circuit, 312… Fine-tuning circuit, 320… Action control circuit, 400… Measurement circuit, T11… NMOS transistor (first transistor, first circuit section), T12… NMOS transistor (second transistor, second circuit section), T13… NMOS transistor (third transistor, third circuit section), T14~T17… NMOS transistors, T21~T26… PMOS transistors, SOUT… Output section Detailed Implementation

[0018] The embodiments will now be described with reference to the accompanying drawings.

[0019] Figure 1 This is a block diagram schematically illustrating the basic structure of a storage device according to an embodiment.

[0020] Figure 1 The storage device 100 shown includes a memory circuit 200 and a control circuit 300 for controlling the memory circuit 200. The memory circuit 200 and the control circuit 300 are disposed within the same semiconductor integrated circuit chip.

[0021] The memory circuit 200 includes a plurality of memory cell blocks 210 and a plurality of sense amplifier circuits 220 respectively provided for each of the plurality of memory cell blocks 210. That is, one sense amplifier circuit 220 is provided for each memory cell block 210. Each of the plurality of memory cell blocks 210 includes a plurality of memory cells. Furthermore, Figure 1 This is a block diagram, not a diagram showing the actual configuration of the memory cell block 210 and the sense amplifier circuit 220, etc.

[0022] Figure 2 This is a schematic perspective view illustrating the configuration of the storage cell block 210. Furthermore, the X, Y, and Z directions shown in the figure intersect each other. Specifically, the X, Y, and Z directions are orthogonal to each other.

[0023] The memory cell block 210 includes: a plurality of lower wirings 10 each extending in the X direction; a plurality of upper wirings 20 each extending in the Y direction; and a plurality of memory cells 30 connected between the plurality of lower wirings 10 and the plurality of upper wirings 20. One of the lower wirings 10 and the upper wirings 20 corresponds to a word line, and the other of the lower wirings 10 and the upper wirings 20 corresponds to a bit line.

[0024] Each of the multiple storage cells 30 includes a magnetoresistive element (a non-volatile variable resistor element) 40 that presents either a low resistance state or a high resistance state, and a selector (switching element) 50 connected in series with the magnetoresistive element 40, and stores different information (data) corresponding to the resistance state of the magnetoresistive element 40.

[0025] The magnetoresistive element 40 and the selector 50 are stacked in the Z direction. That is, the magnetoresistive element 40 and the selector 50 are stacked in a direction perpendicular to the plane (XY plane) in which the plurality of memory cells 30 are arranged.

[0026] Figure 3 This is a schematic cross-sectional view showing the basic structure of the magnetoresistive element 40.

[0027] The magnetoresistive element 40 is an MTJ (Magnetic Tunnel Junction) element, including a storage layer 41, a reference layer 42, and a tunnel barrier layer 43, having the storage layer 41, reference layer 42, and tunnel barrier layer 43 in... Figure 1 The structure is obtained by stacking layers in the Z direction.

[0028] Storage layer 41 is a ferromagnetic layer with a variable magnetization direction. Reference layer 42 is a ferromagnetic layer with a fixed magnetization direction. Tunnel barrier layer 43 is an insulating layer, a non-magnetic layer disposed between storage layer 41 and reference layer 42. Furthermore, a variable magnetization direction means that the magnetization direction changes relative to a predetermined write current. A fixed magnetization direction means that the magnetization direction remains constant relative to a predetermined write current.

[0029] When the magnetization direction of the storage layer 41 is parallel to the magnetization direction of the reference layer 42, the magnetoresistive element 40 is in a low-resistance state. When the magnetization direction of the storage layer 41 is antiparallel to the magnetization direction of the reference layer 42, the magnetoresistive element 40 is in a high-resistance state. Therefore, the storage cell 30 can store data corresponding to either the low-resistance state or the high-resistance state of the magnetoresistive element 40. That is, the storage cell 30 can store binary data corresponding to the resistance state set for the magnetoresistive element 40.

[0030] Specifically, the resistance state of the magnetoresistive element 40 can be set to either a low resistance state or a high resistance state by flowing a write current in the magnetoresistive element 40, and the resistance state set in the magnetoresistive element 40 can be read out by flowing a read current in the magnetoresistive element 40.

[0031] In addition, Figure 3 The diagram shows a top-free type magnetoresistive element 40 with the storage layer 41 located on the upper side of the reference layer 42, but a bottom-free type magnetoresistive element 40 with the storage layer 41 located on the lower side of the reference layer 42 can also be used.

[0032] Figure 4 This is a schematic cross-sectional view showing the basic structure of selector 50.

[0033] The selector 50 is a two-terminal switching element, including a lower electrode 51, an upper electrode 52, and a selector material layer 53 disposed between the lower electrode 51 and the upper electrode 52. The lower electrode 51, the upper electrode 52, and the selector material layer 53 are located within... Figure 1 The structure is obtained by stacking layers in the Z direction.

[0034] The selector material layer 53 is essentially an insulating layer. However, when the voltage applied between the two terminals (between the lower electrode 51 and the upper electrode 52) exceeds the threshold voltage, the resistance drops significantly, resulting in a conductive state. Therefore, the selector 50 has the following characteristic: when the voltage applied between the lower electrode 51 and the upper electrode 52 exceeds the threshold voltage, it transitions from the off (OFF) state to the on (ON) state.

[0035] With the configuration described above, when a voltage is applied between the lower wiring 10 and the upper wiring 20, and the voltage applied between the lower electrode 51 and the upper electrode 52 is above a threshold voltage, the selector 50 becomes in the conducting state. As a result, current can flow in the magnetoresistive element 40 connected in series with the selector 50, allowing the magnetoresistive element 40 to be written to (set to a low resistance state or a high resistance state) or read out (detect to a low resistance state or a high resistance state).

[0036] In addition, Figure 2 In this configuration, the magnetoresistive element 40 is located on the lower side of the selector 50, but the magnetoresistive element 40 can also be located on the upper side of the selector 50.

[0037] Return to Figure 1 As explained, each sensing amplifier circuit 220 has the function of reading (detecting) the object data (which becomes the data to be read) stored in a selected storage cell among the multiple storage cells included in the corresponding storage cell block 210. That is, the sensing amplifier circuit 220 has the function of reading (detecting) the object data corresponding to the resistance state (low resistance state or high resistance state) of the magnetoresistive effect element 40 included in the selected storage cell 30.

[0038] First, the self-reference readout using the sense amplifier circuit 220 will be explained below.

[0039] As previously described, a magnetoresistive element has two resistance states: a low resistance state and a high resistance state. The resistance state of a magnetoresistive element is determined by comparing the value (voltage or current value) obtained based on the resistance state set for the magnetoresistive element with a reference value.

[0040] Figure 5 This is a flowchart illustrating the self-reference readout process. Figure 6 It is a timing chart showing the actions read from the reference.

[0041] First, during the first readout operation performed by RD1, a first value based on the object data stored in the selected memory cell 30 is obtained (S11). That is, a first value is obtained based on the object resistance state (resistance state corresponding to the readout object data) set in the magnetoresistive effect element 40 included in the selected memory cell 30. Specifically, a readout current flows in the magnetoresistive effect element 40, and a first voltage is obtained as the first value.

[0042] Next, during the write operation performed in the period WT following period RD1, reference data is written to the selected memory cell 30 (S12). That is, for the magnetoresistive element 40 included in the selected memory cell 30, one of the low resistance state and the high resistance state is set as the reference resistance state. Specifically, a write current flows in the magnetoresistive element 40 to set the reference resistance state of the magnetoresistive element 40.

[0043] Next, in the second readout operation performed during period RD2 after period WT, a second value based on the reference data stored in the selected memory cell 30 is obtained (S13). That is, a second value based on the reference resistance state set in the magnetoresistive effect element 40 included in the selected memory cell 30 is obtained. Specifically, a readout current flows in the magnetoresistive effect element 40, and a second voltage is obtained as the second value.

[0044] Then, during the detection operation (determination operation) performed during the period SEN after period RD2, the object data stored in the storage unit 30 before the first readout operation is detected based on the first and second values ​​obtained in the first and second readout operations, respectively (S14). The detection operation is performed in the sensing amplifier circuit 220 as follows.

[0045] Figure 7 This is a circuit diagram showing the configuration of the sense amplifier circuit 220.

[0046] The sensing amplifier circuit 220 includes NMOS transistors T11~T17 and PMOS transistors T21~T26.

[0047] During the first half of the SEN detection operation, transistors T14 and T15, and transistors T21, T22, and T23 are set to the on state, while transistors T16 and T17, and transistor T26 are set to the off state. Furthermore, a voltage (first value) V1 is applied to the gate of transistor T11 (the first transistor, the first circuit section), and a voltage (second value) V2 is applied to the gate of transistor T12 (the second transistor, the second circuit section). Then, a voltage (third value) V3 is applied to the gate of transistor T13 (the third transistor, the third circuit section), which is connected in parallel with transistor T12.

[0048] Based on the states of the transistors described above, a current (first current) I11 corresponding to voltage V1 flows in transistor T11, a current (second current) I12 corresponding to voltage V2 flows in transistor T12, and a current (third current) I13 corresponding to voltage V3 flows in transistor T13.

[0049] During the latter half of SEN, transistors T21, T22, and T23 are set to the off state. The potential of node N1 at the connection between transistors T14 and T24 is determined by the current I11 before transistors T21, T22, and T23 are set to the off state. The potential of node N2 at the connection between transistors T15 and T25 is determined by the sum of the currents I12 and I13 (I12+I13) before transistors T21, T22, and T23 are set to the off state. Furthermore, by setting transistors T16 and T17 and transistor T26 to the on state, the potential difference between node N1 and node N2 increases due to the positive feedback of the circuit formed by transistors T14, T15, T24, and T25, thus determining the potentials of node N1 and node N2.

[0050] The potential (voltage) of node N2 obtained as described above is output from the output section SOUT as a detection signal (H-level signal or L-level signal) corresponding to the object data. That is, based on the relationship between the magnitude of current I11 and the magnitude of the total current (I12+I13) of currents I12 and I13, the detection signal corresponding to the object data is output from the output section SOUT.

[0051] Specifically, when the magnitude of current I11 is smaller than the magnitude of the total current (I12+I13), the output section SOUT outputs a signal (either an H-level signal or an L-level signal) indicating that the target data is the same as the reference data as the detection signal. When the magnitude of current I11 is larger than the magnitude of the total current (I12+I13), the output section SOUT outputs a signal (either an H-level signal or an L-level signal) indicating that the target data is different from the reference data as the detection signal.

[0052] Figure 8 It is a diagram that schematically illustrates the relationship between the various currents flowing in transistors T11, T12, and T13.

[0053] The current IL corresponds to the current I11 flowing in transistor T11 when the magnetoresistive element 40 is in a low-resistance state, and the current IH corresponds to the current I11 flowing in transistor T11 when the magnetoresistive element 40 is in a high-resistance state. The current IM is the current between IL and IH, and corresponds to the total current (I12+I13) of the currents I12 and I13 flowing in transistor T12 when the reference resistance state of the magnetoresistive element 40 is low. In this case, the current I11 flowing in transistor T11 (corresponding to current IL) and the current I12 flowing in transistor T12 (corresponding to current IL) when the object resistance state of the magnetoresistive element 40 is low are essentially the same. Therefore, the difference between current IM and current IL (IM-IL) corresponds to the current I13 flowing in transistor T13.

[0054] As can be seen from the above, in order to accurately detect the object data stored in the storage cell 30, it is necessary to accurately set the value of the current I13. For example, it is preferable to set the current I13 flowing in the transistor T13 in such a way that the value of (IH-IM) is equal to the value of (IM-IL).

[0055] Therefore, the voltage V3 applied to transistor T13 is adjusted so that the current I13 flowing in transistor T13 is the exact value described above. In the following description, the voltage V3 applied to transistor T13 is sometimes referred to as the offset voltage.

[0056] Figure 9 This is a graph illustrating the method for determining the aforementioned offset voltage (voltage V3). The horizontal axis represents the offset voltage applied to transistor T13, and the vertical axis represents the error rate when reading object data from the memory cell.

[0057] Characteristic (a) is the error rate when the magnetoresistive element 40 is set to a low resistance state as the reference resistance state, and characteristic (b) is the error rate when the magnetoresistive element 40 is set to a high resistance state as the reference resistance state. The reference resistance state of the magnetoresistive element 40 is the low resistance state.

[0058] As described above, the total current (I12 + I13) flowing in transistors T12 and T13 increases as the offset voltage (voltage V3) increases. Furthermore, in case (a) where the magnetoresistive element 40 is in a low-resistance state, the current I11 flowing in transistor T11 is small. Therefore, in the case of a low-resistance state for the magnetoresistive element 40, the error rate decreases as the offset voltage increases. Conversely, in case (b) where the magnetoresistive element 40 is in a high-resistance state, the error rate decreases as the offset voltage decreases.

[0059] Therefore, in order to reduce the error rate in either the case where the magnetoresistive element 40 is set to a low resistance state or the case where the magnetoresistive element 40 is set to a high resistance state, the offset voltage at the intersection of characteristic (a) and characteristic (b) becomes the ideal optimal offset voltage Vopt.

[0060] The aforementioned offset voltage is preferably constant for all the sense amplifier circuits 220 included in the memory circuit 200. That is, the offset voltage is preferably constant for all the memory cell blocks 210 included in the memory circuit 200.

[0061] However, in reality, the offset voltage has a systematic distribution corresponding to the location of the memory cell block 210 due to factors such as process variations. Specifically, the resistance value of the magnetoresistive element 40 has a systematic distribution depending on the location of the memory cell block 210. Therefore, the ideal optimal offset voltage value is not fixed. Therefore, if the offset voltage of all the sense amplifier circuits 220 included in the memory circuit 200 is set to a fixed value, the error rate may vary depending on the location of the memory cell block 210, resulting in a memory cell block 210 with a larger error rate.

[0062] In this embodiment, in order to suppress the error rate to a low level in each of the plurality of memory cell blocks 210, the offset voltage of each of the plurality of sense amplifier circuits 220 is adjusted. That is, in this embodiment, the current I13 flowing in the transistor T13 is adjusted for each of the plurality of sense amplifier circuits 220.

[0063] The above actions are by Figure 1 The control circuit 300 shown is used for this purpose. The structure and operation of the control circuit 300 will be explained below.

[0064] like Figure 1As shown, the control circuit 300 includes an adjustment circuit 310 and an action control circuit 320. The adjustment circuit 310 includes a holding circuit 311 and a fine-tuning circuit 312. Additionally, a measuring circuit 400 is provided outside the control circuit 300. Furthermore, if possible, the measuring circuit 400 can also be provided within the control circuit 300.

[0065] As described above, the adjustment circuit 310 adjusts the current I13 flowing in transistor T13 for each of the multiple sense amplifier circuits 220. Specifically, the adjustment circuit 310 adjusts the offset voltage (voltage V3) applied to the gate of transistor T13 when current I13 flows in transistor T13. That is, the adjustment circuit 310 adjusts current I13 (adjusts the offset voltage) so that the total current (I12+I13) is between the current I11 flowing in transistor T11 when the magnetoresistive element 40 is in a low resistance state and the current I11 flowing in transistor T11 when the magnetoresistive element 40 is in a high resistance state.

[0066] The following is for reference Figure 10 The flowchart shown is for Figure 1 The operation of the storage device shown will be explained. Furthermore, Figure 10 Steps S21, S22, and S23 are basically performed before shipment, while step S24 is basically performed after shipment (during the actual action after shipment).

[0067] First, a routine test is performed (S21). The routine test is a general test performed on the memory circuit 200, etc.

[0068] Next, an offset voltage test is performed (S22). Specifically, the offset voltage is measured in each memory cell block 210 by the measuring circuit 400.

[0069] As already described, the offset voltage is systematically distributed based on the location of the memory cell block 210, etc. Therefore, it can be considered that the multiple memory cells 30 included in the same memory cell block 210 have substantially the same characteristics. Therefore, in this embodiment, the same offset voltage is set for the same memory cell block 210.

[0070] For example, the optimal offset voltage obtained with respect to a single memory cell 30 (denoted as memory cell 30-1) can be used as the offset voltage for the memory cell block 210 including memory cell 30-1. Alternatively, the average of multiple optimal offset voltages obtained with respect to multiple memory cells 30 (denoted as memory cells 30-1 to 30-n) can be used as the offset voltage for the memory cell block 210 including memory cells 30-1 to 30-n. In this way, the offset voltage is obtained for each of the multiple memory cell blocks 210 included in the memory cell circuit 200.

[0071] As described above, multiple offset voltages are obtained based on the results of pre-performed tests on each of the multiple memory cell blocks 210. The obtained multiple offset voltages are held in the holding circuit 311 (S23). That is, the holding circuit 311 holds the offset voltages of each of the multiple sense amplifier circuits 220 as adjustment control values ​​for adjusting the current I13 of the transistor T13.

[0072] As described above, the pre-shipment actions are performed by maintaining the offset voltage in the holding circuit 311 as an adjustment control value.

[0073] After shipment, the user performs actual write and read operations on the storage unit circuit 200.

[0074] When performing a read operation, data is read from the selected storage unit 30 based on the operating principle already explained. In this embodiment, when performing a read operation, the offset voltage (adjustment control value) held by the holding circuit 311 is finely adjusted by the fine-tuning circuit 312 (S24).

[0075] Figure 11 This is a diagram illustrating the fine-tuning process performed by the fine-tuning circuit 312. Figure 11 The above figure shows the distribution of the offset voltage before fine-tuning. Figure 11 The following figure shows the distribution of offset voltage after fine-tuning. The horizontal axis represents the position of memory cell block 210, and the vertical axis represents the relationship between offset voltage and effective offset voltage. The points shown in the figure correspond to the offset voltage for each memory cell block 210 obtained through the processing of steps S21 to S23 described above.

[0076] As already described, the offset voltage typically varies systematically depending on the location of memory cell block 210. Figure 11 In the example shown in the figure above, the offset voltage is relatively low in regions P1, P3 and P5, and relatively high in regions P2 and P4.

[0077] Therefore, in this embodiment, in order to reduce the difference between offset voltages to some extent, the offset voltages of the memory cell blocks 210 included in regions P1, P3, and P5 are shifted as a whole, thereby reducing the difference between the offset voltages of the memory cell blocks 210 included in regions P1, P3, and P5 and the offset voltages of the memory cell blocks 210 included in regions P2 and P4. That is, by using the fine-tuning circuit 312 to fine-tune the offset voltages held by the holding circuit 311, the difference between offset voltages is reduced to some extent.

[0078] As described above, the offset voltage generation process is performed (the offset voltage generation process after fine-tuning).

[0079] When the motion control circuit 320 reads the object data stored in the selected storage unit 30, it uses the finely tuned offset voltage to control the first read operation, the write operation, and the second read operation as described above.

[0080] As described above, in this embodiment, an adjustment circuit 310 is provided to adjust the current I13 flowing in the transistor T13 for each of the plurality of sense amplifier circuits 220. Therefore, even if the adjustment control value (offset voltage in the above embodiment) for obtaining the optimal current I13 differs among the plurality of memory cell blocks 210 (even if it differs among the plurality of sense amplifier circuits 220), an accurate adjustment control value can be set for each of the plurality of memory cell blocks 210 (each of the plurality of sense amplifier circuits 220). Therefore, in this embodiment, object data stored in the memory cell 30 can be read accurately.

[0081] Furthermore, in the above-described embodiment, a magnetoresistive element was used as the variable resistor element, but other variable resistor elements that can present either a low resistance state or a high resistance state and store different information according to each resistance state can also be used.

[0082] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included in the scope and spirit of the invention, and are included in the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A storage device comprising: A memory circuit includes multiple memory cell blocks, each comprising multiple memory cells, and multiple sense amplifier circuits respectively provided for each of the multiple memory cell blocks; and The control circuit controls the memory circuit. Its features are, Each of the plurality of storage units includes a variable resistor element and a switching element connected in series with the variable resistor element, and stores data corresponding to either a low resistance state or a high resistance state of the variable resistor element. Each of the plurality of sensing amplifier circuits includes: In the first circuit section, a first current flows corresponding to a first value obtained by a first readout action, the first readout action being the action of reading object data stored in a selected memory cell among the plurality of memory cells; The second circuit section contains a second current flowing in which a second value corresponding to a second value obtained through a second read operation is flowed, the second read operation being the operation of reading reference data written to the selected memory cell during a write operation performed after the first read operation; A third circuit section, connected in parallel with the second circuit section, wherein a third current flows when the second current flows in the second circuit section; and The output section outputs a detection signal corresponding to the object data based on the relationship between the magnitude of the first current and the combined magnitude of the second and third currents. The control circuit includes an adjustment circuit that adjusts the third current flowing in the third circuit section for each of the plurality of sense amplifier circuits.

2. The storage device according to claim 1, characterized in that, The first circuit section, the second circuit section, and the third circuit section each include a first transistor, a second transistor, and a third transistor, respectively.

3. The storage device according to claim 2, characterized in that, The adjustment circuit adjusts the voltage applied to the gate of the third transistor when the third current flows in the third circuit section.

4. The storage device according to claim 1, characterized in that, The adjustment circuit adjusts the third current so that the total current is between the first current when the variable resistor element is in a low resistance state and the first current when the variable resistor element is in a high resistance state.

5. The storage device according to claim 1, characterized in that, The adjustment circuit includes a holding circuit that holds the adjustment control value of the third current for each of the plurality of sense amplifier circuits.

6. The storage device according to claim 5, characterized in that, The adjustment control value is held in the holding circuit based on the results of a prior test of the plurality of memory cell blocks.

7. The storage device according to claim 5, characterized in that, The adjustment circuit further includes a fine-tuning circuit, which fine-tunes the adjustment control value held by the holding circuit.

8. The storage device according to claim 1, characterized in that, The control circuit further includes an action control circuit, which controls the first read action, the write action, and the second read action.

9. The storage device according to claim 1, characterized in that, When the magnitude of the first current is smaller than the magnitude of the total current, the output section outputs a signal indicating that the object data is the same as the reference data as the detection signal. When the magnitude of the first current is larger than the magnitude of the total current, the output section outputs a signal indicating that the object data is different from the reference data as the detection signal.

10. The storage device according to claim 1, characterized in that, The variable resistor element and the switching element are stacked in a direction perpendicular to the plane in which the plurality of memory cells are arranged.

11. The storage device according to claim 1, characterized in that, The variable resistance element is a magnetoresistive element.

12. The storage device according to claim 1, characterized in that, The switching element is a two-terminal switching element, which has the characteristic of changing from the off state to the on state when the voltage applied between its two terminals becomes a threshold voltage or higher.

13. The storage device according to claim 1, characterized in that, The variable resistor element has the characteristic of storing different information depending on its resistance state.

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