storage device

Abstract

The embodiment provides a storage device with excellent characteristics and reliability. The storage device of the embodiment includes first and second lower wirings (10) adjacent to each other, first and second upper wirings (20) adjacent to each other, a first memory cell (30) between the first lower wiring and the first upper wiring, a second memory cell (30) between the first lower wiring and the second upper wiring, a third memory cell (30) between the second lower wiring and the first upper wiring, and an insulating portion between the first lower wiring and the second lower wiring. The first, second and third memory cells each include a variable resistance storage element (40) and a switching element (50) including a lower electrode (51), an upper electrode (52) and a switching material layer (53). At least one surface of the variable resistance storage element, the upper surface of the first lower wiring and the upper surface of the insulating portion is provided with a layer portion (53a, 53b) containing the same material as the switching material layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to storage devices. Background Technology

[0002] A memory device is proposed in which multiple memory cells, including variable resistance storage elements such as magnetoresistive elements and selectors (switching elements), are stacked on a semiconductor substrate.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2020-047663 Summary of the Invention

[0004] The embodiment provides a storage device with excellent characteristics and reliability, which can reliably electrically isolate adjacent memory cells.

[0005] The storage device of the embodiment includes: first and second lower wirings extending along a first direction and adjacent to each other; first and second upper wirings extending along a second direction intersecting the first direction and adjacent to each other; a first memory unit disposed between the first lower wirings and the first upper wirings; a second memory unit disposed between the first lower wirings and the second upper wirings; a third memory unit disposed between the second lower wirings and the first upper wirings; and an insulating portion disposed between the first lower wirings and the second lower wirings. The first, second, and third memory cells each include a variable resistance storage element and a switching element disposed on the upper side of the variable resistance storage element, which are stacked along a third direction intersecting the first and second directions. The switching element includes a lower electrode, an upper electrode, and a switching material layer. The switching material layer includes a portion located between the lower electrode and the upper electrode, and is configured to cover at least the upper portion of the upper surface of the lower electrode and the side surface of the lower electrode. At least one of the side surface of the variable resistance storage element included in the first memory cell, the upper surface of the first lower wiring, and the upper surface of the insulating portion is provided with a layer portion containing the same material as the switching material layer. Attached Figure Description

[0006] Figure 1 This is a perspective view schematically showing the basic structure of a storage device according to an embodiment.

[0007] Figure 2A This is a cross-sectional view schematically illustrating the specific configuration of the storage device in the embodiment.

[0008] Figure 2B This is a cross-sectional view schematically illustrating the specific configuration of the storage device in the embodiment.

[0009] Figure 3A This is a cross-sectional view schematically illustrating an example of the configuration of the main body portion of the magnetoresistive element of a storage device according to an embodiment.

[0010] Figure 3B This is a cross-sectional view schematically illustrating another example of the configuration of the main body portion of the magnetoresistive element of the storage device according to an embodiment.

[0011] Figure 4A This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0012] Figure 4B This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0013] Figure 5A This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0014] Figure 5B This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0015] Figure 6A This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0016] Figure 6B This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0017] Figure 7A This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0018] Figure 7B This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0019] Figure 8A This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0020] Figure 8B This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0021] Figure 9A This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0022] Figure 9B This is a cross-sectional view schematically illustrating a part of a method for manufacturing a storage device according to an embodiment.

[0023] Figure 10A This is a cross-sectional view schematically illustrating the configuration of a first modified example of the storage device according to the embodiment.

[0024] Figure 10B This is a cross-sectional view schematically illustrating the configuration of a first modified example of the storage device according to the embodiment.

[0025] Figure 11A This is a cross-sectional view schematically illustrating the configuration of a second modified example of the storage device according to the embodiment.

[0026] Figure 11B This is a cross-sectional view schematically illustrating the configuration of a second modified example of the storage device according to the embodiment.

[0027] Figure 12A This is a cross-sectional view schematically illustrating the configuration of a third variation of the storage device according to the embodiment.

[0028] Figure 12B This is a cross-sectional view schematically illustrating the configuration of a third variation of the storage device according to the embodiment.

[0029] Explanation of reference numerals in the attached figures 10…lower wiring; 20…upper wiring; 30…memory cell; 40…Magnetoresistive effect element (variable resistance storage element); 41…Main body; 41a…Storage layer; 41b…Reference layer; 41c…Tunnel barrier layer; 42…sidewall insulation layer; 50…Selector (switching element); 51…Lower electrode; 52…Upper electrode; 52a…protruding part; 52b…material part; 53…Selector Material Layer (Switch Material Layer); Layers 53a, 53b, 53c… 60…insulating part; 70…insulating part; 80…space; 91…mask pattern; 92…insulating part; 100…insulating layer. Detailed Implementation

[0030] The embodiments will now be described with reference to the accompanying drawings.

[0031] Figure 1 This is a perspective view schematically showing the basic structure of a storage device according to an embodiment.

[0032] The storage device of this embodiment includes a plurality of lower wirings 10 extending along the X direction, a plurality of upper wirings 20 extending along the Y direction, and a plurality of memory units 30 disposed between the plurality of lower wirings 10 and the plurality of upper wirings 20.

[0033] One of the lower wiring 10 and the upper wiring 20 corresponds to a word line, and the other of the lower wiring 10 and the upper wiring 20 corresponds to a bit line.

[0034] Each memory cell 30 includes a magnetoresistive element (a non-volatile variable resistance storage element) 40 and a selector (a 2-terminal switching element) 50, and has a structure in which the magnetoresistive element 40 and the selector 50 are stacked along the Z direction.

[0035] Furthermore, the X, Y, and Z directions intersect each other. Specifically, the X, Y, and Z directions are orthogonal to each other.

[0036] Figure 2A and Figure 2B These are cross-sectional views schematically illustrating the specific configuration of the storage device in this embodiment. Figure 2A It is a cross-sectional view along the X direction. Figure 2B It is a cross-sectional view along the Y direction.

[0037] The storage device of this embodiment is disposed on a lower region including a semiconductor substrate (not shown) and an insulating layer 100, and includes a plurality of lower wirings 10, a plurality of upper wirings 20, a plurality of memory cells 30, a plurality of insulating portions 60, and a plurality of insulating portions 70.

[0038] As described above, a plurality of lower wirings 10 extend along the X direction, and a plurality of upper wirings 20 extend along the Y direction. The lower wirings 10 and the upper wirings 20 are formed, for example, of a conductive material such as tungsten (W).

[0039] Multiple memory cells 30 are disposed between multiple lower wirings 10 and multiple upper wirings 20. Each memory cell 30 includes a magnetoresistive element 40 and a selector 50 stacked along the Z direction.

[0040] The magnetoresistive effect element 40 is an STT (Spin Transfer Torque) type MTJ (Magnetic Tunnel Junction) element with vertical magnetization, including a main body 41 and a sidewall insulating layer 42.

[0041] Figure 3A and Figure 3B These are cross-sectional views, respectively, schematically illustrating one example and another example of the structure of the main body 41 of the magnetoresistive effect element 40.

[0042] The main body 41 includes a storage layer (first magnetic layer) 41a, a reference layer (second magnetic layer) 41b, and a tunnel barrier layer (non-magnetic layer) 41c.

[0043] Storage layer 41a is a strongly magnetic layer with a variable magnetization direction, for example, formed of a CoFeB layer containing cobalt (Co), iron (Fe), and boron (B). The variable magnetization direction refers to the change in magnetization direction relative to a specified write current.

[0044] Reference layer 41b is a strongly magnetic layer with a fixed magnetization direction, such as a CoFeB layer containing cobalt (Co), iron (Fe), and boron (B), or a superlattice layer containing cobalt (Co) and platinum (Pt). A fixed magnetization direction means that the magnetization direction remains unchanged relative to a specified write current.

[0045] The tunnel barrier layer 41c is an insulating layer disposed between the storage layer 41a and the reference layer 41b, for example, formed of an MgO layer containing magnesium (Mg) and oxygen (O).

[0046] When the magnetization direction of the storage layer 41a is parallel to the magnetization direction of the reference layer 41b, the main body portion 41 of the magnetoresistive element 40 is in a low-resistance state with relatively low resistance. When the magnetization direction of the storage layer 41a is antiparallel to the magnetization direction of the reference layer 41b, the main body portion 41 of the magnetoresistive element 40 is in a high-resistance state with relatively high resistance. Therefore, the magnetoresistive element 40 can store binary data based on the resistance state of the main body portion 41.

[0047] The sidewall insulating layer 42 functions to protect the main body portion 41, including portions disposed along the sidewalls of the main body portion 41 and portions disposed along the sidewalls of the lower electrode 51 of the selector 50, described later. The sidewall insulating layer 42 is formed, for example, of an insulating material such as silicon nitride (SiN).

[0048] The selector 50 is disposed on the upper side of the magnetoresistive effect element 40, and includes a lower electrode 51, an upper electrode 52, and a selector material layer (switch material layer) 53.

[0049] The lower electrode 51 includes a portion containing a specified conductive material as its main component, and also functions as the upper electrode of the magnetoresistive effect element 40. The specified conductive material is selected, for example, from carbon (C), tungsten (W), and titanium nitride (TiN).

[0050] The upper electrode 52 includes a portion containing a specified conductive material as its main component. The specified conductive material is selected, for example, from carbon (C) and tungsten nitride (WN).

[0051] The material of the selector material layer 53 is essentially an insulating material, for example, a material containing zirconium oxide (ZrOx) as the main component can be used as the material of the selector material layer 53. By using a zirconium oxide-containing material as the material of the selector material layer 53, a selector 50 with excellent properties can be obtained. Alternatively, a material containing zinc (Zn) and tellurium (Te) (ZnTe) can be added to the zirconium oxide in the selector material layer 53. By using such a material in the selector material layer 53, the characteristics of the selector 50 can be further improved.

[0052] For the material of selector layer 53, in addition to materials containing zirconium (Zr) oxide as the main component, materials containing hafnium (Hf) oxide as the main component or scandium (Sc) oxide as the main component can also be used. These materials are difficult to process by RIE (Reactive Ion Etching).

[0053] The selector material layer 53 includes a portion located between the lower electrode 51 and the upper electrode 52, and is configured to cover at least the upper portion of the upper surface of the lower electrode 51 and the side surface of the lower electrode 51. In this embodiment, a sidewall insulating layer 42 is also provided on the side surface (sidewall) of the lower electrode 51, therefore the selector material layer 53 is configured to cover at least the upper surface of the lower electrode 51 and the side surface of the sidewall insulating layer 42.

[0054] The selector material layer 53 has the shape described above, and therefore also includes a portion located outside the portion between the lower electrode 51 and the upper electrode 52.

[0055] However, the selector material layers 53 included in adjacent memory cells 30 are separated from each other. More specifically, as described below.

[0056] Adjacent lower wirings 10 are designated as first and second lower wirings 10, and adjacent upper wirings 20 are designated as first and second upper wirings 20. Furthermore, a memory unit 30 located between the first lower wiring 10 and the first upper wiring 20 is designated as a first memory unit 30, a memory unit 30 located between the first lower wiring 10 and the second upper wiring 20 is designated as a second memory unit 30, and a memory unit 30 located between the second lower wiring 10 and the first upper wiring 20 is designated as a third memory unit 30.

[0057] As specified above, the selector material layer 53 included in the first memory cell 30 and the selector material layer 53 included in the second memory cell 30 are separated from each other in at least the upper side of the plane encompassing the lower surface of the lower electrode 51 included in the first memory cell 30 and the lower surface of the lower electrode 51 included in the second memory cell 30.

[0058] Similarly, the selector material layer 53 included in the first memory cell 30 and the selector material layer 53 included in the third memory cell 30 are separated from each other in at least the upper side of the plane that includes the lower surface of the lower electrode 51 included in the first memory cell 30 and the lower surface of the lower electrode 51 included in the third memory cell 30.

[0059] Furthermore, under the conditions specified above, the upper electrode 52 included in the first memory unit 30 and the upper electrode 52 included in the third memory unit 30 are continuously arranged. More specifically, the upper electrode 52 included in the first memory unit 30 and the upper electrode 52 included in the third memory unit 30 are continuously arranged along the first upper wiring 20.

[0060] The selector 50 has the characteristic of changing from an off state to an on state when the voltage applied between the lower electrode 51 and the upper electrode 52 becomes a threshold voltage or higher.

[0061] Therefore, when a voltage is applied between the lower wiring 10 and the upper wiring 20, and the voltage applied between the lower electrode 51 and the upper electrode 52 is above the threshold voltage, the selector 50 is turned on. As a result, current flows through the magnetoresistive element 40 connected in series with the selector 50, enabling writing or reading from the magnetoresistive element 40.

[0062] Multiple insulating portions 60 are respectively disposed between adjacent lower wirings 10 and extend along the X direction. That is, adjacent lower wirings 10 are insulated from each other by the insulating portions 60. Each insulating portion 60 is formed of an insulating material such as silicon oxide or silicon nitride.

[0063] The plurality of insulating portions 70 each include portions disposed between adjacent upper wirings 20 and portions disposed between adjacent memory cells 30 in the X direction, and extend along the Y direction. That is, adjacent upper wirings 20 and adjacent memory cells 30 in the X direction are insulated from each other by the insulating portions 70. Each insulating portion 70 is formed of an insulating material such as silicon oxide or silicon nitride.

[0064] Multiple spaces 80 are provided on the upper side of each of the multiple insulating portions 60. The multiple spaces 80 are respectively provided between memory cells 30 that are adjacent to each other in the Y direction. That is, the memory cells 30 that are adjacent to each other in the Y direction are insulated from each other by the spaces 80. A protruding portion 52a protrudes from the upper electrode 52 in the upper part of the space 80, and a material portion 52b formed of the material of the upper electrode 52 is provided in the lower part of the space 80.

[0065] Furthermore, a layer portion 53a is provided on the side surface of the magnetoresistive element 40 (the side surface of the sidewall insulating layer 42), a layer portion 53b is provided on the upper surface of the lower wiring 10, and a layer portion 53c is provided on the upper surface of the insulating portion 60. If the description focuses on the first memory cell 30, then the layer portion 53a is provided on the side surface of the magnetoresistive element 40 included in the first memory cell 30, the layer portion 53b is provided on the upper surface of the first lower wiring 10, and the layer portion 53c is provided on the upper surface of the insulating portion 60 between the first lower wiring 10 and the second lower wiring 10.

[0066] The aforementioned layer portions 53a, 53b, and 53c contain the same material as the selector material layer 53. These layer portions 53a, 53b, and 53c are formed during the formation of the selector material layer 53.

[0067] In this embodiment, layer portion 53a is provided continuously from selector material layer 53, but it can also be provided discontinuously from selector material layer 53. Similarly, layer portion 53b is provided continuously from layer portion 53a, but it can also be provided discontinuously from layer portion 53a. Likewise, layer portion 53c is provided continuously from layer portion 53a, but it can also be provided discontinuously from layer portion 53a.

[0068] In addition, all of the layer portions 53a, 53b and 53c are provided in this embodiment, but at least one of the layer portions 53a, 53b and 53c may also be provided.

[0069] Next, refer to Figure 4A and Figures 4B to 9A and Figure 9B The manufacturing method of the storage device according to this embodiment will be described. Figures 4A to 9A It is a cross-sectional view along the X direction. Figures 4B to 9B It is a cross-sectional view along the Y direction.

[0070] First, such as Figure 4A and Figure 4B As shown, a plurality of lower wirings 10 and a plurality of insulating portions 60 are formed on the insulating layer 100. Specifically, a plurality of lower wirings 10 and a plurality of slots are formed, and the insulating layer is used to fill the plurality of slots to form a plurality of insulating portions 60.

[0071] Next, as Figure 5A and Figure 5B As shown, in Figure 4A and Figure 4B In the process, a main body layer 41L is formed on the structure of the magnetoresistive effect element by film deposition. Next, a columnar pattern 51P is formed on the main body layer 41L using a conductive material for the lower electrode 51 of the selector.

[0072] Next, as Figure 6A and Figure 6B As shown, the columnar pattern 51P is used as a mask, and the main body layer 41L is etched using IBE (Ion Beam Etching) or similar methods, thereby forming the main body 41 of the magnetoresistive effect element. Furthermore, through etching, the thickness of the columnar pattern 51P is reduced, forming the lower electrode 51 of the selector. Next, a sidewall insulating layer 42 is formed on the sidewalls of the thus obtained main body 41 and lower electrode 51. Thus, a magnetoresistive effect element 40 including the main body 41 and the sidewall insulating layer 42 is formed.

[0073] Next, as Figure 7A and Figure 7B As shown, the selector material layer 53 is formed by PVD (Physical Vapor Deposition) such as sputtering. Using PVD, the selector material layer 53 is formed to cover at least the upper portion of the upper surface of the lower electrode 51 and the side surface of the lower electrode 51 (the side surface of the sidewall insulating layer 42). Furthermore, the selector material layer 53 is formed to be separated from adjacent memory cells.

[0074] Furthermore, the selector material layer 53 is formed to be separated from each other between adjacent memory cells. Therefore, when forming the selector material layer 53, a layer portion 53a is formed on the side of the sidewall insulating layer 42 of the magnetoresistive effect element 40, a layer portion 53b is formed on the upper surface of the lower wiring 10, and a layer portion 53c is formed on the upper surface of the insulating portion 60.

[0075] Next, as Figure 8A and Figure 8B As shown, in Figure 7A and Figure 7B In the process of obtaining the structure, the upper electrode layer 52L and the upper wiring layer 20L are formed by PVD such as sputtering.

[0076] Because the selector material layer 53 has the aforementioned shape, the spacing between adjacent selector material layers 53 is relatively narrow. Furthermore, the upper electrode layer 52L and the upper wiring layer 20L are formed using PVD. Therefore, the area between adjacent memory cells is not filled by the upper electrode layer 52L and the upper wiring layer 20L, forming a space 80. Additionally, a protruding portion 52a of the upper electrode layer 52L is formed in the upper part of the space 80, and a material portion 52b on which the material of the upper electrode layer 52L is deposited is formed in the lower part of the space 80.

[0077] Next, as Figure 9A and Figure 9B As shown, a mask pattern 91 is formed on the upper wiring layer 20L. Next, using the mask pattern 91 as a mask, the upper wiring layer 20L and the upper electrode layer 52L are etched using RIE (Reactive Ion Etching). This etching forms the pattern of the upper wiring 20 and the upper electrode 52. Thus, a selector 50 including the lower electrode 51, the upper electrode 52, and the selector material layer 53 is formed, resulting in a memory cell 30 including the magnetoresistive element 40 and the selector 50. Furthermore, in the region between adjacent memory cells 30 in the X direction, the material portion 52b is removed, while in the region between adjacent memory cells 30 in the Y direction, the material portion 52b remains.

[0078] Subsequently, the mask pattern 91 is removed. Then, by filling the areas between adjacent upper wirings 20 in the X direction and the areas between adjacent memory cells 30 in the X direction with an insulating layer to form an insulating portion 70, an insulating portion 70 is obtained. Figure 2A and Figure 2B The structure shown is as shown.

[0079] As described above, in this embodiment, such as Figure 7A and Figure 7B As shown, the selector material layer 53 is formed using PVD, and the selector material layer 53 is formed to cover at least the upper portion of the upper surface of the lower electrode 51 and the side surface of the lower electrode 51 (the side surface of the sidewall insulating layer 42). Furthermore, the selector material layer 53 is formed to be separated from adjacent memory cells 30. Therefore, in this embodiment, the above-described structure can be obtained without patterning the selector material layer 53. Thus, as described below, a memory device with excellent characteristics and reliability, capable of reliably electrically isolating adjacent memory cells 30, can be obtained.

[0080] If memory cells are miniaturized and integration density increases, it becomes difficult to accurately pattern the selector material layer using dry etching methods such as RIE. This is especially true when the selector material layer uses a material containing zirconium oxide (ZrOx) as the main component, making accurate patterning challenging. Furthermore, it becomes even more difficult to form accurate patterns when the selector material layer uses a material containing Zn and Te added to zirconium oxide (ZnTe). This is because compounds containing Zr, Zn, or Te have high boiling points and are difficult to volatilize. Therefore, the following problem exists: dry etching of the materials described above is not easy, and even if etching is possible, the etching products will redeposit on the sidewalls of the selector. Consequently, it is difficult to obtain memory cells with excellent characteristics and reliability.

[0081] A configuration where the selector material layer is not separated between adjacent memory cells is also considered. However, using such a configuration may result in situations where adjacent memory cells cannot be reliably electrically separated. For example, if an alignment misalignment occurs between the upper and lower electrodes of a selector, the distance between the upper electrode of one selector and the lower electrode of another becomes closer between adjacent selectors. As a result, the selector material layer becomes connected between the upper electrode of one selector and the lower electrode of another, which may prevent accurate memory operation.

[0082] In this embodiment, the above-described structure can be obtained without patterning the selector material layer. Therefore, the problems mentioned above can be avoided, and a memory device with excellent characteristics and reliability that can reliably electrically isolate adjacent memory cells can be obtained.

[0083] Furthermore, in this embodiment, layer portions 53a, 53b, and 53c are formed when forming the selector material layer 53. However, these layer portions 53a, 53b, and 53c are not formed between the lower electrode 51 and the upper electrode 52, and therefore will not adversely affect the operation of the selector 50. Rather, since layer portion 53a is formed on the side of the magnetoresistive element 40, the magnetoresistive element 40 can be effectively protected through layer portion 53a during subsequent etching processes, etc.

[0084] Figure 10A and Figure 10B This is a cross-sectional view schematically showing the configuration of a first modified example of the storage device according to this embodiment. Figure 10A It is a cross-sectional view along the X direction. Figure 10B It is a cross-sectional view along the Y direction.

[0085] In this variation, such as Figure 10B As shown, multiple insulating portions 92 are provided in multiple recesses of the upper electrode 52 of the selector 50.

[0086] In the above-described embodiments Figure 8A as well as Figure 8B During the process of forming the upper electrode layer 52L, a space 80 is formed in the region between adjacent memory cells. Therefore, a recess is formed in the upper electrode layer 52L above the space 80. In this modified example, an insulating layer is formed on the upper electrode layer 52L and the recess is filled with the insulating layer, thereby planarizing the insulating layer so that the insulating layer remains only in the recess. After forming the upper wiring layer 20L on the structure obtained in this way, the same process as in the above embodiment is performed, thereby obtaining the structure of this modified example.

[0087] In this modified example, a flat upper wiring 20 can be formed by providing multiple insulating portions 92.

[0088] Figure 11A and Figure 11B This is a cross-sectional view schematically showing the configuration of a second modified example of the storage device of this embodiment. Figure 11A It is a cross-sectional view along the X direction. Figure 11B It is a cross-sectional view along the Y direction.

[0089] In the above embodiments, in Figure 6A and Figure 6B In the process of forming the lower electrode 51, a sidewall insulating layer 42 is also formed on the sidewall of the lower electrode 51. However, in this modified example, the sidewall insulating layer 42 is not formed on the sidewall of the lower electrode 51, but only on the sidewall of the main body portion 41 of the magnetoresistive effect element 40. For example, as Figure 11A and Figure 11B As shown, when the sidewall of the lower electrode 51 extends from the upper side to the lower side, a structure like that in this modified example can be formed. Here, even if the sidewall of the main body 41 is not entirely covered by the sidewall insulating layer 42, the characteristics of the selector 50 will not be significantly impaired. That is, the characteristics of the selector 50 itself will not be greatly affected.

[0090] In this variation, by forming Figure 11A and Figure 11B The construction shown is followed by the same implementation method as described above. Figure 7A and Figures 7B to 9A and Figure 9B The same process can also be used to obtain the sidewall insulating layer 42 and the lower electrode 51 with Figure 11A and Figure 11B The structures shown and other structures have the same characteristics as the embodiments described above. Figure 2A and Figure 2B The storage device shown has the same structure.

[0091] Figure 12A and Figure 12BThis is a cross-sectional view schematically illustrating the configuration of a third modified example of the storage device according to this embodiment. Figure 12A It is a cross-sectional view along the X direction. Figure 12B It is a cross-sectional view along the Y direction.

[0092] In this modified example, a sidewall insulating layer 42 is formed on the sidewall of the main body portion 41 of the magnetoresistive effect element 40 and on the sidewall of the lower portion of the lower electrode 51, but no sidewall insulating layer 42 is formed on the sidewall of the upper portion of the lower electrode 51. For example, as Figure 12A and Figure 12B As shown, when the sidewall of the upper part of the lower electrode 51 extends from the upper side to the lower side, a structure like that in this modified example can be formed.

[0093] In this variation, by forming Figure 12A and Figure 12B The construction shown is followed by the same implementation method as described above. Figure 7A and Figures 7B to 9A and Figure 9B The same process can also be used to obtain the sidewall insulating layer 42 and the lower electrode 51 with Figure 12A and Figure 12B The structures shown and other structures have the same characteristics as the embodiments described above. Figure 2A and Figure 2B The storage device shown has the same structure.

[0094] Furthermore, while the magnetoresistive element is used as a non-volatile variable resistance storage element in the above embodiments, other non-volatile variable resistance storage elements can also be used.

[0095] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage device comprising: The first and second lower wirings extend along the first direction and are adjacent to each other; The first and second upper wirings extend along a second direction that intersects the first direction and are adjacent to each other; The first memory unit is disposed between the first lower wiring and the first upper wiring; The second memory unit is disposed between the first lower wiring and the second upper wiring; A third memory unit is disposed between the second lower wiring and the first upper wiring; and An insulating component is disposed between the first lower wiring and the second lower wiring. Its features are, The first, second, and third memory cells each include a variable resistor storage element and a switching element disposed on the upper side of the variable resistor storage element, stacked along a third direction intersecting the first and second directions. The switching element includes a lower electrode, an upper electrode, and a switching material layer. The switching material layer includes a portion located between the lower electrode and the upper electrode, and is configured to cover at least the upper portion of the upper surface and side surface of the lower electrode. At least one of the following surfaces—the side surface of the variable resistance storage element included in the first memory cell, the upper surface of the first lower wiring, and the upper surface of the insulating portion—is provided with a layer portion containing the same material as the switching material layer.

2. The storage device according to claim 1, characterized in that, The switching material layer included in the first memory cell and the switching material layer included in the second memory cell are separated from each other in at least the upper region of a plane encompassing the lower surface of the lower electrode included in the first memory cell and the lower surface of the lower electrode included in the second memory cell.

3. The storage device according to claim 1, characterized in that, The switching material layer included in the first memory cell and the switching material layer included in the third memory cell are separated from each other in at least the upper region of the plane encompassing the lower surface of the lower electrode included in the first memory cell and the lower surface of the lower electrode included in the third memory cell.

4. The storage device according to claim 1, characterized in that, The layer portion disposed on the side of the variable resistance storage element is continuously disposed from the switching material layer.

5. The storage device according to claim 1, characterized in that, The lower electrode also serves as the upper electrode of the variable resistance storage element.

6. The storage device according to claim 1, characterized in that, The lower electrode includes a portion containing a conductive material selected from carbon, tungsten, and titanium nitrides as its main component.

7. The storage device according to claim 1, characterized in that, The upper electrode included in the first memory unit and the upper electrode included in the third memory unit are continuously disposed thereon.

8. The storage device according to claim 1, characterized in that, The material of the switch material layer is an insulating material.

9. The storage device according to claim 1, characterized in that, The switching material layer contains zirconium oxide, hafnium oxide, or scandium oxide as its main components.

10. The storage device according to claim 9, characterized in that, The material of the switch material layer also contains zinc and tellurium.

11. The storage device according to claim 1, characterized in that, The variable resistance storage element includes a main body portion and a sidewall insulating layer, the sidewall insulating layer including a portion disposed along the sidewall of the main body portion.

12. The storage device according to claim 11, characterized in that, The sidewall insulation layer also includes a portion disposed along the sidewall of the lower electrode.

13. The storage device according to claim 11, characterized in that, The layer portion disposed on the side of the variable resistance storage element is disposed on the side of the sidewall insulating layer.

14. The storage device according to claim 1, characterized in that, The variable resistance storage element is a magnetoresistive element.

15. The storage device according to claim 1, characterized in that, The switching element has the characteristic that it changes from an open state to an on state when the voltage applied between the lower electrode and the upper electrode becomes a threshold voltage or higher.

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