Memory device, manufacturing method thereof, and operating method thereof

Abstract

A memory device includes a first semiconductor chip including a first semiconductor structure and a first interconnect structure, a second semiconductor chip stacked with the first semiconductor chip along a first direction, the second semiconductor chip including a second semiconductor structure and a second interconnect structure, and a first contact structure extending in the first semiconductor chip along the first direction and in contact with the first interconnect structure. The first contact structure includes a first inner conductive layer and a first outer conductive layer surrounding the first inner conductive layer, and the first interconnect structure extends along a second direction perpendicular to the first direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures, manufacturing methods, and operating methods thereof, specifically to memory devices, methods for manufacturing memory, and methods for driving memory. Background Technology

[0002] Planar memory cells have been scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and expensive. As a result, the memory density of planar memory cells is approaching its upper limit.

[0003] High-bandwidth memory (HBM) uses stacked memory devices or memory chips to achieve efficient data movement and access. While using less power with a smaller form factor, HBM devices can achieve high bandwidth. HBM devices have been used in high-performance graphics accelerators, networking devices, high-performance data centers, artificial intelligence (AI) and machine learning (ML) training, and various supercomputers. Summary of the Invention

[0004] According to one aspect of this disclosure, a memory device is disclosed. The memory device includes: a first semiconductor chip, the first semiconductor chip including a first semiconductor structure and a first interconnect structure; a second semiconductor chip stacked with the first semiconductor chip along a first direction, the second semiconductor chip including a second semiconductor structure and a second interconnect structure; and a first contact structure extending in the first semiconductor chip along the first direction and contacting the first interconnect structure. The first contact structure includes a first inner conductive layer and a first outer conductive layer surrounding the first inner conductive layer, and the first interconnect structure extends along a second direction perpendicular to the first direction.

[0005] In some embodiments, the memory device further includes a second contact structure extending along the first direction in both the first semiconductor chip and the second semiconductor chip, and the second contact structure contacts the second interconnect structure. The second contact structure includes a second inner conductive layer and a second outer conductive layer surrounding the second inner conductive layer.

[0006] In some embodiments, the first inner conductive layer and the first outer conductive layer are arranged along the second direction, and the second inner conductive layer and the second outer conductive layer are arranged along the second direction.

[0007] In some embodiments, the second contact structure extends along the first direction and contacts the second interconnect structure without contacting the first interconnect structure.

[0008] In some embodiments, the first contact structure further includes a first dielectric layer disposed between the first inner conductive layer and the first outer conductive layer, and the second contact structure further includes a second dielectric layer disposed between the second inner conductive layer and the second outer conductive layer.

[0009] In some embodiments, the length of the first inner conductive layer along the first direction is greater than the length of the first outer conductive layer along the first direction, and the length of the second inner conductive layer along the first direction is greater than the length of the second outer conductive layer along the first direction.

[0010] In some embodiments, the first interconnect structure includes a first wire extending along the second direction and a second wire extending along the second direction, and the second interconnect structure includes a third wire extending along the second direction and a fourth wire extending along the second direction.

[0011] In some implementations, the first conductor is parallel to the second conductor, and the third conductor is parallel to the fourth conductor.

[0012] In some embodiments, the first outer conductive layer is in contact with the first wire, the first inner conductive layer is in contact with the second wire, the second outer conductive layer is in contact with the third wire, and the second inner conductive layer is in contact with the fourth wire.

[0013] In some embodiments, the width of the first conductor along a third direction perpendicular to the first direction and the second direction is greater than the width of the second conductor along the third direction, and the width of the third conductor along the third direction is greater than the width of the fourth conductor along the third direction.

[0014] In some embodiments, the first semiconductor structure includes a memory array and peripheral circuitry, and the first contact structure is coupled to the peripheral circuitry via the first interconnect structure.

[0015] In some embodiments, the memory array includes memory elements and capacitors, and the memory elements and capacitors are arranged along the first direction.

[0016] In some embodiments, the memory device further includes a substrate die stacked along the first direction with the first semiconductor chip and the second semiconductor chip. The first contact structure contacts the substrate die.

[0017] In some embodiments, the second semiconductor chip is stacked with the first semiconductor chip via a third dielectric layer.

[0018] In some embodiments, the length of the second contact structure along the first direction is greater than the length of the first contact structure along the first direction, and the length of the second interconnect structure along the second direction is greater than the length of the first interconnect structure along the second direction.

[0019] In some embodiments, the diameter of the first inner conductive layer is between 1 micrometer and 10 micrometers, and the diameter of the first outer conductive layer is between 3 micrometers and 20 micrometers.

[0020] In some embodiments, the first inner conductive layer and the first outer conductive layer are formed in a concentric circle pattern in a plan view of the memory device.

[0021] In some embodiments, the first inner conductive layer and the first outer conductive layer form a concentric pillar extending along the first direction.

[0022] According to another aspect of this disclosure, a method for forming a memory device is disclosed. The method includes: forming a first semiconductor chip including a first semiconductor structure and a first interconnect structure; forming a second semiconductor chip including a second semiconductor structure and a second interconnect structure; bonding the first semiconductor chip and the second semiconductor chip along a first direction; and forming a first contact structure including a first inner conductive layer and a first outer conductive layer surrounding the first inner conductive layer. The first contact structure extends in the first semiconductor chip along the first direction and contacts the first interconnect structure, and the first interconnect structure extends along a second direction perpendicular to the first direction.

[0023] In some embodiments, the method further includes forming a second contact structure comprising a second inner conductive layer and a second outer conductive layer surrounding the second inner conductive layer. The second contact structure extends along the first direction in both the first semiconductor chip and the second semiconductor chip, and contacts the second interconnect structure.

[0024] In some embodiments, forming the first semiconductor chip including the first semiconductor structure and the first interconnect structure includes: forming the first semiconductor structure on a substrate; and forming a first wire and a second wire on the first semiconductor structure. The first wire and the second wire extend along a second direction, the second wire is located between the first wire and the first semiconductor structure along the first direction, and the first wire is parallel to the second wire.

[0025] In some embodiments, forming the first contact structure, which includes the first inner conductive layer and the first outer conductive layer surrounding the first inner conductive layer, includes forming a first concentric pillar composed of the first inner conductive layer and the first outer conductive layer surrounding the first inner conductive layer.

[0026] In some embodiments, forming a second contact structure comprising a second inner conductive layer and a second outer conductive layer surrounding the second inner conductive layer includes forming a second concentric pillar composed of the second inner conductive layer and the second outer conductive layer surrounding the second inner conductive layer.

[0027] In some embodiments, forming the first contact structure, which includes the first inner conductive layer and the first outer conductive layer surrounding the first inner conductive layer, includes: forming a first opening in the first semiconductor chip that extends along the first direction and exposes the first interconnect structure; forming the first outer conductive layer in the first opening; forming a first dielectric layer on the first outer conductive layer; and forming the first inner conductive layer on the first dielectric layer.

[0028] In some embodiments, forming the first outer conductive layer in the first opening includes: forming a second dielectric layer in the first opening; removing a bottom portion of the second dielectric layer to expose the first wire; forming the first outer conductive layer in contact with the first wire on the second dielectric layer; and removing a bottom portion of the first outer conductive layer and a third dielectric layer between the first wire and the second wire to expose the second wire.

[0029] In some embodiments, forming the first dielectric layer on the first outer conductive layer includes forming the first dielectric layer in the first opening that contacts the first outer conductive layer and the second wire.

[0030] In some embodiments, forming the first inner conductive layer on the first dielectric layer includes: removing a bottom portion of the first dielectric layer to expose the second wire; and forming the first inner conductive layer in contact with the second wire in the first opening.

[0031] In some embodiments, bonding the first semiconductor chip and the second semiconductor chip along the first direction includes bonding the first semiconductor chip and the second semiconductor chip through a third dielectric layer.

[0032] In some embodiments, the method further includes: bonding the first semiconductor chip and the second semiconductor chip to a substrate die; and bonding the substrate die and the computing die to an interposer. The first inner conductive layer and the first outer conductive layer are coupled to a first differential data driving circuit in the substrate die, and the second inner conductive layer and the second outer conductive layer are coupled to a second differential data driving circuit in the substrate die.

[0033] According to another aspect of this disclosure, a method of operating a memory device is disclosed. The memory device includes: a first semiconductor chip; a first contact structure extending in the first semiconductor chip; the first contact structure including a first inner conductive layer and a first outer conductive layer surrounding the first inner conductive layer. The method of operation includes: transmitting a first data signal from the first semiconductor chip to a data receiver through the first outer conductive layer; and transmitting a second data signal from the first semiconductor chip to the data receiver through the first inner conductive layer. The first data signal and the second data signal are inverted signals.

[0034] In some embodiments, the first semiconductor chip includes a first semiconductor structure and a first interconnect structure, the first interconnect structure including a first wire and a second wire parallel to the first wire. Transmitting the first data signal from the first semiconductor chip to the data receiver through the first external conductive layer includes: transmitting the first data signal from the first wire to the data receiver through the first external conductive layer.

[0035] In some embodiments, transmitting the second data signal from the first semiconductor chip to the data receiver via the first inner conductive layer includes transmitting the second data signal from the second wire to the data receiver via the first inner conductive layer.

[0036] In some embodiments, the operation method further includes: providing a control signal to the drive circuit via a data buffer to trigger a differential signal circuit in the drive circuit; and providing the first data signal and the second data signal via the differential signal circuit.

[0037] In some embodiments, the method further includes: receiving the first data signal and the second data signal through the received data; and performing differential decoding on the first data signal and the second data signal to interpret the voltage difference between the first data signal and the second data signal. Attached Figure Description

[0038] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0039] Figure 1 A schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0040] Figure 2 A schematic diagram of a memory device according to some aspects of this disclosure is shown, the memory device including peripheral circuitry and an array of memory cells, each having a vertical transistor.

[0041] Figure 3 A schematic circuit diagram of a memory device including peripheral circuitry and a dynamic random access memory (DRAM) cell array, according to some aspects of this disclosure, is shown.

[0042] Figure 4 A schematic circuit diagram of a memory device including peripheral circuitry and a phase-change memory (PCM) cell array, according to some aspects of this disclosure, is shown.

[0043] Figure 5 A schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0044] Figures 6A-6C A schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0045] Figure 7 A schematic plan view of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0046] Figure 8 A cross-sectional schematic diagram of a semiconductor structure illustrating a differential transmission path is shown, according to some embodiments of the present disclosure.

[0047] Figure 9 A cross-sectional schematic diagram of a semiconductor structure illustrating a differential operation circuit according to some embodiments of the present disclosure is shown.

[0048] Figures 10A-10B Schematic diagrams of single-ended and differential transmission operations according to some embodiments of this disclosure are shown.

[0049] Figure 11-24 Cross-sectional views of semiconductor structures at various stages of the manufacturing process according to some embodiments of the present disclosure are shown.

[0050] Figure 25A flowchart of a method for forming a semiconductor structure according to some embodiments of the present disclosure is shown.

[0051] Figure 26 A schematic diagram of a differential circuit according to some embodiments of the present disclosure is shown.

[0052] Figure 27 A block diagram of a system having a memory device according to some embodiments of the present disclosure is shown.

[0053] Figure 28A A diagram of a memory card having a memory device according to some embodiments of the present disclosure is shown.

[0054] Figure 28B A diagram of a solid-state drive (SSD) with a memory device according to some embodiments of the present disclosure is shown.

[0055] The contents of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0056] While specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified in ways not specifically described in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0057] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can, at least partly depending on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0058] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” in the case of a layer with an intermediate feature or in between; and “above” or “on top of” means not only “above” or “on top of” but also includes “above” or “on top of” in the case of no intermediate feature or in between (i.e., directly on).

[0059] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0060] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may lie between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a conical surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnects and / or via contacts are formed) and one or more dielectric layers.

[0061] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0062] Embodiments of this disclosure may provide one or more of the following technical advantages and / or benefits. For example, a semiconductor device or semiconductor structure may include multiple memory dies or memory chips stacked in a vertical direction. Multiple memory chips are bonded together using direct bonding technology. In some embodiments, HBM may use through-silicon vias (TSVs) and U-bump technology to achieve die-to-wafer bonding or die-to-die bonding. However, HBM chips have the problem of limited signal transmission frequency. In some embodiments, transmitted signals in the HBM chip are transmitted via TSVs used for single-ended signal transmission, and the signals are susceptible to noise, resulting in limited signal frequency.

[0063] To address one or more of the aforementioned problems, this disclosure introduces a semiconductor structure based on differential transmission. After forming a TSV aperture, a double-layer TSV is formed within the aperture, and differential transmission operation can be performed using the double-layer TSV. Therefore, higher signal transmission frequencies can be achieved without increasing the number of TSVs.

[0064] The technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), etc.). The technology can also be applied to charge-trapping based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating-gate based memory devices. The technology can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (e.g., two-level cell devices), TLC (three-level cell) devices, QLC (four-level cell) devices, or PLC (five-level cell) devices. Alternatively or concurrently, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0065] Figure 1 A schematic cross-sectional view of a semiconductor structure 100 according to some embodiments of the present disclosure is shown. The semiconductor structure 100 includes a plurality of stacked semiconductor chips 102, and the semiconductor chips 102 are bonded to a substrate die 104. Figure 1As shown, the substrate die 104 and the computing die 106 are bonded to the interposer 108. In some embodiments, the substrate die 104 is configured to control a semiconductor chip 102 (e.g., a memory device), and the substrate die 104 and the computing die 106 are integrated on the interposer 108 along the X direction.

[0066] In some embodiments, the semiconductor chip 102 is bonded to the substrate die 104 via a chip-to-chip bonding layer. In some embodiments, the semiconductor chip 102 is bonded to the substrate die 104 via a direct bonding layer comprising at least one dielectric material and not including conductive bonding contacts. In some embodiments, the semiconductor chip 102 is bonded to the substrate die 104 via a hybrid bonding layer comprising at least one dielectric material for bonding contacts and isolating bonding contacts. In some embodiments, the bonding contacts may also connect to an interconnect layer or redistribution layer of the semiconductor chip 102. In some embodiments, the semiconductor chip 102 is bonded to the substrate die 104 via a microbump structure. In some embodiments, tiny copper bumps are formed on the die and then connected and assembled into a package, thereby providing small, fast electrical connections between semiconductor chips 102 or between the semiconductor chip 102 and the substrate die 104.

[0067] In some embodiments, the semiconductor chip 102 may include a memory device 112, a peripheral structure 113, an interconnect layer 114, and a contact structure 116, such as a TSV. Figure 1 As shown, signals in each memory device 112 and peripheral structure 113 can be coupled to the substrate die 104 via an interconnect layer 114 extending in the X direction and a contact structure 116 extending in the Z direction.

[0068] Figure 2 A schematic diagram of a memory device 200, including peripheral circuitry and an array of memory cells, each having vertical transistors, is shown according to some aspects of this disclosure. The memory device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. A semiconductor chip 102 may be an example of the memory device 200, wherein memory device 112 may be the memory cell array 201, and peripheral structure 113 may be the peripheral circuitry 202.

[0069] The memory cell array 201 can be any suitable memory cell array, wherein each memory cell 208 includes a vertical transistor 210 and a storage component 212 coupled to the vertical transistor 210. In some embodiments, the memory cell array 201 is a DRAM cell array, and the storage component 212 is a capacitor for storing charge as binary information stored by the respective DRAM cell. In some embodiments, the memory cell array 201 is a PCM cell array, and the storage component 212 is a PCM element (e.g., including a chalcogenide alloy) for storing the binary information of the respective PCM cell based on the different resistivities of the PCM element in the amorphous and crystalline phases. In some embodiments, the memory cell array 201 is an FRAM cell array, and the storage component 212 is a ferroelectric capacitor for storing the binary information of the respective FRAM cell based on the switching between two polarization states of the ferroelectric material under an external electric field.

[0070] like Figure 2 As shown, memory cells 208 can be arranged as a two-dimensional (2D) array with rows and columns. Memory device 200 may include word lines 204 coupling peripheral circuitry 202 and memory cell array 201 for controlling the switching of vertical transistors 210 in a row of memory cells 208, and bit lines 206 coupling peripheral circuitry 202 and memory cell array 201 for sending data to and / or receiving data from memory cells 208 in a column. That is, each word line 204 is coupled to a corresponding row of memory cells 208, and each bit line is coupled to a corresponding column of memory cells 208.

[0071] Consistent with the scope of this disclosure, vertical transistor 210 (e.g., vertical metal-oxide-semiconductor field-effect transistor (MOSFET)) can replace planar transistors with through transistors in memory cell 208 to reduce the area occupied by through transistors, coupling capacitance, and interconnect wiring complexity, as described in detail below. Figure 2 As shown, in some embodiments, unlike planar transistors where the active region is formed in the substrate, the vertical transistor 210 includes a semiconductor body 214 extending vertically (in the Z direction) above a substrate (not shown). That is, the semiconductor body 214 may extend above the top surface of the substrate to allow channels to be formed not only at the top surface of the semiconductor body 214 but also at one or more of its side surfaces. Figure 2As shown, for example, semiconductor body 214 may have a cuboid shape to expose its four sides. It should be understood that semiconductor body 214 may have any suitable 3D shape, such as a polyhedral or cylindrical shape. That is, the cross-section of semiconductor body 214 in a planar view (e.g., in the XY plane) may have a square, rectangular (or trapezoidal), circular (or elliptical) shape, or any other suitable shape. It should be understood that, consistent with the scope of this disclosure, for semiconductor bodies whose cross-section in a planar view has a circular or elliptical shape, the semiconductor body may still be considered to have multiple sides, such that the gate structure contacts more than one side of the semiconductor body. As described below with respect to the manufacturing process, semiconductor body 214 may be formed from a substrate (e.g., by etching or epitaxy) and therefore have the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate).

[0072] like Figure 2 As shown, the vertical transistor 210 may further include a gate structure 216 that contacts one or more sides of the semiconductor body 214, for example, in one or more planes on the side surface of the active region. In other words, the active region of the vertical transistor 210 (e.g., the semiconductor body 214) may be at least partially surrounded by the gate structure 216. The gate structure 216 may include a gate dielectric 218 over one or more sides of the semiconductor body 214, for example, contacting four side surfaces of the semiconductor body 214, such as... Figure 2 As shown in the diagram. Gate structure 216 may also include a gate electrode 220 located on and in contact with gate dielectric 218. Gate dielectric 218 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, gate dielectric 218 may include silicon oxide, which is in the form of a gate oxide. Gate electrode 220 may include any suitable conductive material, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides. For example, gate electrode 220 may include doped polysilicon, which is in the form of gate polysilicon. In some embodiments, gate electrode 220 includes multiple conductive layers, such as a W layer over a TiN layer. It should be understood that in some examples, gate electrode 220 and word line 204 may be a continuous conductive structure. In other words, the gate electrode 220 can be considered as part of the word line 204 forming the gate structure 216, or the word line 204 can be considered as an extension of the gate electrode 220 to couple to the peripheral circuit 202.

[0073] like Figure 2As shown, the vertical transistor 210 may further include a pair of source and drain electrodes (S / D, doped regions, also referred to as source and drain electrodes) formed at opposite ends of the semiconductor body 214 in the vertical direction (z-direction). The source and drain electrodes may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and drain electrodes may be separated in the vertical direction (z-direction) by a gate structure 216. In other words, the gate structure 216 is formed vertically between the source and drain electrodes. As a result, when the gate voltage applied to the gate electrode 220 of the gate structure 216 is higher than the threshold voltage of the vertical transistor 210, one or more channels (not shown) of the vertical transistor 210 can be formed vertically between the source and drain electrodes in the semiconductor body 214. That is, according to some embodiments, each channel of the vertical transistor 210 is also formed in the semiconductor body 214 along the vertical direction in which it extends.

[0074] In some implementations, such as Figure 2 As shown, the vertical transistor 210 is a multi-gate transistor. That is, the gate structure 216 can be connected to more than one side of the semiconductor body 214 (e.g., Figure 2 The four sides of the semiconductor body 214 are contacted to form more than one gate, allowing more than one channel to be formed between the source and drain during operation. That is, unlike planar transistors that only include a single planar gate (and create a single planar channel), the 3D structure of the semiconductor body 214 and the gate structure 216 surrounding the multiple sides of the semiconductor body 214... Figure 2 The vertical transistor 210 shown may include multiple vertical gates on multiple sides of the semiconductor body 214. As a result, compared to planar transistors, Figure 2 The vertical transistor 210 shown can have a larger gate control region to achieve better channel control with a smaller subthreshold swing. Because the channel is fully depleted, the leakage current of the vertical transistor 210 ( Ioff The size can also be significantly reduced. As described in detail below, multi-gate vertical transistors can include dual-gate vertical transistors (e.g., dual-side-gate vertical transistors), tri-gate vertical transistors (e.g., tri-side-gate vertical transistors), and GAA vertical transistors.

[0075] It should be understood that, although the vertical transistor 210 in Figure 2While shown as a multi-gate transistor, the vertical transistor disclosed herein may also include a single-gate transistor as described in detail below. That is, the gate structure 216 may contact a single side of the semiconductor body 214, for example, for increasing transistor and memory cell density. It should also be understood that although the gate dielectric 218 is shown as separate (a separate structure) from other gate dielectrics of adjacent vertical transistors (not shown), the gate dielectric 218 may be part of a continuous dielectric layer of multiple gate dielectrics having vertical transistors.

[0076] In planar transistors and some lateral multi-gate transistors (e.g., FinFETs), the active region, such as the semiconductor body (e.g., a fin), extends laterally (in the XY plane), and the source and drain are located at different positions in the same lateral plane (XY plane). In contrast, according to some embodiments, in the vertical transistor 210, the semiconductor body 214 extends vertically (in the Z direction), and the source and drain are located in different lateral planes. In some embodiments, the source and drain are formed at opposite ends of the semiconductor body 214 in the vertical direction (Z direction), thus overlapping in a planar view. As a result, the area occupied by the vertical transistor 210 (in the XY plane) can be reduced compared to planar transistors and lateral multi-gate transistors. Furthermore, the metal wiring coupled to the vertical transistor 210 can be simplified because interconnects can be wired in different planes. For example, bit line 206 and memory component 212 can be formed on opposite sides of the vertical transistor 210. In one example, bit line 206 may be coupled to a source or drain at the upper end of semiconductor body 214, while memory component 212 may be coupled to another source or drain at the lower end of semiconductor body 214.

[0077] like Figure 2 As shown, storage component 212 may be coupled to the source or drain of vertical transistor 210. Storage component 212 may include any means capable of storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells. In some embodiments, vertical transistor 210 controls the selection and / or state switching of the corresponding storage component 212 coupled to vertical transistor 210.

[0078] Figure 3 A schematic diagram of a memory device 200, including peripheral circuitry and an array of memory cells, all having vertical transistors, is shown, according to some aspects of this disclosure. Figure 3 In some embodiments shown, each memory cell 208 includes a transistor 304 (e.g., using...). Figure 2 The vertical transistor 210 in the embodiment) and capacitor 306 (e.g., Figure 2 The DRAM cell 302 (example of storage component 212 in the example). The gate of transistor 304 (e.g., corresponding to gate electrode 220) may be coupled to word line 204, one of the source and drain of transistor 304 may be coupled to bit line 206, the other of the source and drain of transistor 304 may be coupled to one electrode of capacitor 306, and the other electrode of capacitor 306 may be coupled to ground.

[0079] Figure 4 A schematic diagram of a memory device 200, including peripheral circuitry and an array of memory cells, all having vertical transistors, is shown, according to some aspects of this disclosure. Figure 4 In some of the embodiments shown, each memory cell 208 includes a transistor 404 (e.g., using...). Figure 2 The vertical transistor 210 is implemented in the middle) and the PCM element 406 (e.g., Figure 2 The PCM cell 402 (example of storage component 212 in the example). The gate of transistor 404 (e.g., corresponding to gate electrode 220) may be coupled to word line 204, one of the source and drain of transistor 404 may be coupled to ground, the other of the source and drain of transistor 404 may be coupled to one electrode of PCM element 406, and the other electrode of PCM element 406 may be coupled to bit line 206.

[0080] Figure 5 A schematic cross-sectional view of a semiconductor structure (e.g., memory device 500) according to some embodiments of the present disclosure is shown. The memory device 500 may include a first semiconductor chip 502 and a second semiconductor chip 503 stacked with the first semiconductor chip 502 along the Z-direction. The memory device 500 also includes a substrate die 554 stacked with the first semiconductor chip 502 and the second semiconductor chip 503 along the Z-direction. Figure 5 As shown, the substrate die 554 and the computing die 556 are bonded to the interposer 558. In some embodiments, the substrate die 554 is configured to control a memory device, and the substrate die 554 and the computing die 556 are integrated on the interposer 558 along the X direction.

[0081] Figure 6AA cross-sectional schematic diagram of a portion of a memory device 500 according to some embodiments of the present disclosure is shown. The memory device 500 includes a first semiconductor chip 502 and a second semiconductor chip 503 along the Z-direction. The first semiconductor chip 502 includes a first semiconductor structure 504 and a first interconnect structure 505, and the second semiconductor chip 503 includes a second semiconductor structure 506 and a second interconnect structure 507. The memory device 500 also includes a first contact structure 510 extending along the Z-direction in the first semiconductor chip 502 and contacting the first interconnect structure 505. The memory device 500 also includes a second contact structure 520 extending along the Z-direction in both the first semiconductor chip 502 and the second semiconductor chip 503, and the second contact structure 520 contacting the second interconnect structure 507. In some embodiments, the second contact structure 520 passes through the first semiconductor chip 502 and extends into the second semiconductor chip 503 to contact the second interconnect structure 507. In some embodiments, the second contact structure 520 passes through the substrate of the first semiconductor chip 502.

[0082] like Figure 6B As shown, the first contact structure 510 includes a first inner conductive layer 516 and a first outer conductive layer 518 surrounding the first inner conductive layer 516, and the first interconnect structure 505 extends along the X direction perpendicular to the Z direction and contacts the first contact structure 510. The second contact structure 520 includes a second inner conductive layer 526 and a second outer conductive layer 528 surrounding the second inner conductive layer 526. The second interconnect structure 507 extends along the X direction perpendicular to the Z direction and contacts the second contact structure 520.

[0083] The first inner conductive layer 516 and the first outer conductive layer 518 are arranged along the X direction, and the second inner conductive layer 526 and the second outer conductive layer 528 are also arranged along the X direction. In some embodiments, the second contact structure 520 extends along the Z direction and contacts the second interconnect structure 507 without contacting the first interconnect structure 505. In other words, the first contact structure 510 only contacts the first interconnect structure 505, and the second contact structure 520 only contacts the second interconnect structure 507 without contacting the first interconnect structure 505.

[0084] In some embodiments, the first contact structure 510 further includes a first dielectric layer 517 disposed between the first inner conductive layer 516 and the first outer conductive layer 518, and the second contact structure 520 further includes a second dielectric layer 527 disposed between the second inner conductive layer 526 and the second outer conductive layer 528. In some embodiments, the length of the first inner conductive layer 516 along the Z direction is greater than the length of the first outer conductive layer 518 along the Z direction. In some embodiments, the length of the second inner conductive layer 526 along the Z direction is greater than the length of the second outer conductive layer 528 along the Z direction.

[0085] like Figure 6A and Figure 6B As shown, the first interconnect structure 505 includes a first conductor 512 extending along the X direction and a second conductor 514 extending along the X direction. In some embodiments, the first conductor 512 is parallel to the second conductor 514. The second interconnect structure 507 includes a third conductor 522 extending along the X direction and a fourth conductor 524 extending along the X direction. In some embodiments, the third conductor 522 is parallel to the fourth conductor 524.

[0086] In some embodiments, the first outer conductive layer 518 contacts the first wire 512, and the first inner conductive layer 516 contacts the second wire 514. In some embodiments, the second outer conductive layer 528 contacts the third wire 522, and the second inner conductive layer 526 contacts the fourth wire 524. Figure 6B As shown, in some embodiments, the length of the second contact structure 520 along the Z direction is greater than the length of the first contact structure 510 along the Z direction. In some embodiments, the length of the second interconnect structure 507 along the X direction is greater than the length of the first interconnect structure 505 along the X direction.

[0087] Figure 6C A cross-sectional schematic diagram of a portion of a memory device 500 according to some embodiments of the present disclosure is shown. For example... Figure 6C As shown, the dimensions of the first conductor 512 and the second conductor 514 may be different. In some embodiments, the width of the first conductor 512 along the Y direction, which is perpendicular to the X and Z directions, is greater than the width of the second conductor 514 along the Y direction. In some embodiments, the width of the third conductor 522 along the Y direction is greater than the width of the fourth conductor 524 along the Y direction.

[0088] Since the second conductor 514 is in contact with the first inner conductive layer 516 and the first conductor 512 is in contact with the first outer conductive layer 518, the width of the first conductor 512 can be greater than the width of the second conductor 514 for TSV attachment when the area of ​​the first outer conductive layer 518 is greater than the area of ​​the first inner conductive layer 516. However, in other embodiments, the width of the first conductor 512 and the width of the second conductor 514 can be designed to be the same.

[0089] Figure 7 A schematic plan view of a semiconductor structure according to some embodiments of the present disclosure is shown. For example... Figure 7 As shown, the first inner conductive layer 516 and the first outer conductive layer 518 form a concentric circle pattern in the plan view of the memory device 500. Furthermore, as... Figures 6A-6CAs shown, the first inner conductive layer 516 and the first outer conductive layer 518 form concentric pillars extending along the Z direction. In some embodiments, the diameter of the first inner conductive layer 516 is between 1 micrometer and 10 micrometers. In some embodiments, the diameter of the first inner conductive layer 516 is between 1 micrometer and 5 micrometers. In some embodiments, the diameter of the first outer conductive layer 518 is between 3 micrometers and 20 micrometers. In some embodiments, the diameter of the first outer conductive layer 518 is between 3 micrometers and 10 micrometers.

[0090] In some embodiments, the first semiconductor structure 504 includes a memory array and peripheral circuitry, and the first contact structure is coupled to the peripheral circuitry via a first interconnect structure 505. In some embodiments, the memory array includes memory elements and capacitors, and the memory elements and capacitors are arranged along the Z-direction. In some embodiments, the memory device 500 may further include a substrate die 554 stacked along the Z-direction with the first semiconductor chip 502 and the second semiconductor chip 503. In some embodiments, the first contact structure 510 and the second contact structure 520 contact the substrate die 554, such as... Figure 5 As shown in the diagram. In some embodiments, the second semiconductor chip 503 is stacked with the first semiconductor chip 502 via a dielectric layer.

[0091] Figure 8 A cross-sectional schematic diagram of a memory device 500 illustrating a differential transmission path is shown, according to some embodiments of the present disclosure. For example... Figure 8 As shown, the differential transmission path includes path P1 and path P2. In some embodiments, path P1 is the path from the differential transmission circuit to the first inner conductive layer 516, and path P2 is the path from the differential transmission circuit to the first outer conductive layer 518. In some embodiments, the first inner conductive layer 516 is connected to metal layer 3 (M3), and the first outer conductive layer 518 is connected to metal layer 4 (M4). In other words, the first inner conductive layer 516 and the first outer conductive layer 518 fall on different metal layers. In some embodiments, the lengths of path P1 and path P2 can be substantially the same by adaptively designing the wiring or layout of the paths through multiple metal layers.

[0092] Figure 9 A cross-sectional schematic diagram of a memory device 500 illustrating a differential operation circuit according to some embodiments of the present disclosure is shown. Figure 9 As shown, the first semiconductor structure 504 may include a differential transmission circuit 902 (e.g., a low-voltage differential signal transmission circuit) and a data buffer circuit 904. In some embodiments, the data buffer circuit 904 transmits control signals to the differential transmission circuit 902 to control the driving of the differential signals.

[0093] Figures 10A-10B Schematic diagrams of single-ended transmission operation and differential transmission operation according to some embodiments of this disclosure are shown. For example... Figure 10A As shown, single-ended transmission receives a signal and compares it to two reference voltage levels (high and low) to determine the signal's value. When noise appears on the transmission path, the determined result will be severely affected. Therefore, there is significant crosstalk between the signals, and the transmission is highly susceptible to interference. Figure 10B As shown, the signal values ​​in differential transmission are determined by the phase difference between two signals, and this phase difference is a relative value. When noise occurs on the transmission path, the two signals will change accordingly, and the correlation values ​​will remain essentially the same. Therefore, differential transmission has strong anti-interference capabilities.

[0094] By using a first contact structure 510 and a second contact structure 520 having an inner conductive layer and an outer conductive layer connected to different metal layers (e.g., wires 512, 514, 522, and 514), differential signal transmission can be achieved to resist external interference to the signal. Furthermore, by using the first contact structure 510 and the second contact structure 520 having an inner conductive layer and an outer conductive layer, a higher signal transmission frequency can be achieved without increasing the number of TSVs.

[0095] Figure 11-24 A cross-sectional view of a memory device 500 at various stages of the manufacturing process according to some embodiments of the present disclosure is shown. Figure 25 A flowchart illustrating a method for forming a memory device 500 according to some embodiments of the present disclosure is shown. To better describe the present disclosure, it will be discussed together. Figure 11-24 The memory device 500 and Figure 25 Method 2500. It should be understood that the operations shown in Method 2500 are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed simultaneously, or in conjunction with... Figure 11-24 and Figure 25 The different sequences shown will be executed.

[0096] like Figure 11 and Figure 25 As shown in operation 2502, a first semiconductor chip 502 is formed. The first semiconductor chip 502 includes a first semiconductor structure 504 and a first interconnect structure 505. In some embodiments, the first semiconductor structure 504 is formed on a substrate 532, and a first wire 512 and a second wire 514 are formed on the first semiconductor structure 504, as shown in the figure. Figure 11 and Figure 12As shown in the diagram. In some embodiments, the first conductor 512 and the second conductor 514 extend along the X direction. The second conductor 514 is located along the Z direction between the first conductor 512 and the first semiconductor structure 504, and the first conductor 512 is parallel to the second conductor 514. In some embodiments, the first conductor 512 and the second conductor 514 may be formed of a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.). In some embodiments, the first conductor 512 and the second conductor 514 are covered by a dielectric layer. In some embodiments, the first semiconductor structure 504 includes a memory array and peripheral circuitry. In some embodiments, the memory array includes memory elements and capacitors, and the memory elements and capacitors are arranged along the Z direction.

[0097] like Figure 25 As shown in operation 2504, a second semiconductor chip 503 is formed. The second semiconductor chip 503 includes a second semiconductor structure 506 and a second interconnect structure 507. In some embodiments, the process for forming the second semiconductor chip 503 can be similar to the process for forming the first semiconductor chip 502. In some embodiments, the first semiconductor chip 502 and the second semiconductor chip 503 can be formed simultaneously on different substrates. In some embodiments, the first semiconductor chip 502 and the second semiconductor chip 503 can be formed simultaneously on the same substrate. In some embodiments, the first semiconductor chip 502 and the second semiconductor chip 503 can be formed sequentially on different substrates. In some embodiments, the first semiconductor chip 502 and the second semiconductor chip 503 can be formed sequentially on the same substrate.

[0098] like Figure 13 and Figure 25 As shown in operation 2506, the first semiconductor chip 502 and the second semiconductor chip 503 are bonded along the Z-direction. In some embodiments, a chip-to-chip bonding layer may be formed on the first semiconductor chip 502 and the second semiconductor chip 503 before bonding. In some embodiments, the chip-to-chip bonding layer may consist only of dielectric material. In other words, there are no metal contacts in the chip-to-chip bonding layer. In some embodiments, the chip-to-chip bonding layer may include a mixture of dielectric-to-dielectric and metal-to-metal bonding layers. In some embodiments, the chip-to-chip bonding layer includes a metal structure and a dielectric bonding material.

[0099] like Figure 14-24 and Figure 25As shown in operation 2508, a first contact structure 510 is formed. The first contact structure 510 includes a first inner conductive layer 516 and a first outer conductive layer 518 surrounding the first inner conductive layer 516. In some embodiments, the first contact structure 510 is a first concentric pillar composed of the first inner conductive layer 516 and the first outer conductive layer 518 surrounding the first inner conductive layer 516. In some embodiments, the first contact structure 510 extends along the Z direction in the first semiconductor chip 502 and contacts a first interconnect structure 505, and the first interconnect structure 505 extends along the X direction perpendicular to the Z direction.

[0100] like Figure 14-24 As shown, a second contact structure 520 is further formed. The second contact structure 520 includes a second inner conductive layer 526 and a second outer conductive layer 528 surrounding the second inner conductive layer 526. In some embodiments, the second contact structure 520 is a second concentric pillar composed of the second inner conductive layer 526 and the second outer conductive layer 528 surrounding the second inner conductive layer 526. The second contact structure 520 extends along the Z direction in the first semiconductor chip 502 and the second semiconductor chip 503, and the second contact structure 520 contacts the second interconnect structure 507.

[0101] like Figure 14 As shown, a first opening 572 is formed in the first semiconductor chip 502, extending along the Z-direction and exposing a first interconnect structure 505. In some embodiments, the first opening 572 extends in the first semiconductor chip 502 along the Z-direction and exposes a first conductive line 512. In some embodiments, the first opening 572 is formed by an etching operation. In some embodiments, the first opening 572 extends only to the first semiconductor chip 502.

[0102] In addition, such as Figure 14 As shown, a second opening 582 is formed in the first semiconductor chip 502 and the second semiconductor chip 503, extending along the Z-direction and exposing the second interconnect structure 507. In some embodiments, the second opening 582 extends along the Z-direction in the first semiconductor chip 502 and the second semiconductor chip 503, exposing the third wire 522. In some embodiments, the second opening 582 is formed by an etching operation. In some embodiments, the second opening 582 passes through the first semiconductor chip 502 and extends into the second semiconductor chip 503.

[0103] like Figure 15As shown, a dielectric layer 574 is formed in a first opening 572, and a dielectric layer 584 is formed in a second opening 582. In some embodiments, dielectric layers 574 and 584 are formed on the sidewalls and bottom of the first and second openings 572 and 582, respectively. In some embodiments, dielectric layers 574 and 584 comprise silicon oxide or silicon nitride.

[0104] Then, as Figure 16 As shown, a first mask layer 590 is formed on the top surface of the memory device 500, and the first mask layer 590 also covers a portion of the dielectric layers 574 and 584. In some embodiments, the first mask layer 590 serves to protect the sidewalls of the dielectric layers 574 and 584 during a subsequent removal operation to remove the bottom of the dielectric layers 574 and 584. Figure 17 As shown, the bottom of dielectric layers 574 and 584 is removed by a removal operation (e.g., an etching process) to expose the first conductor 512 and the third conductor 522.

[0105] like Figure 18 As shown, the first mask layer 590 is removed, and a conductive layer 591 is formed in the first opening 572 and the second opening 582. In some embodiments, the conductive layer 591 is formed of a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.). In some embodiments, the conductive layer 591 is in direct contact with the first conductor 512 and the third conductor 522. In some embodiments, the conductive layer 591 is used as a first outer conductive layer 518 and a second outer conductive layer 528.

[0106] Then, as Figure 19 As shown, a second mask layer 592 is formed on the top surface of the conductive layer 591, and the second mask layer 592 covers a portion of the conductive layer 591 on its sidewalls. In some embodiments, the second mask layer 592 is used to protect the sidewalls of the conductive layer 591 during a subsequent removal operation for removing the bottom of the conductive layer 591 from the first opening 572 and the second opening 582.

[0107] like Figure 20 As shown, a removal operation is performed to remove the bottom of the conductive layer 591 in the first opening 572 and the second opening 582. In some embodiments, the removal operation may remove a portion of the bottom of the conductive layer 591 in the first opening 572 and the second opening 582. Furthermore, the removal operation also removes the dielectric material between the first wire 512 and the second wire 514. In some embodiments, the removal operation also removes the dielectric material between the third wire 522 and the fourth wire 524. In other words, in Figure 20After the removal operation shown, the second wire 514 and the fourth wire 524 are exposed through the first opening 572 and the second opening 582.

[0108] like Figure 21 As shown, the second mask layer 592 is removed, and a dielectric layer 593 is formed on the sidewalls and bottom of the first opening 572 and the second opening 582. Then, a third mask layer 594 is formed on the top surface of the dielectric layer 593, and the third mask layer 594 also covers a portion of the sidewalls of the dielectric layer 593. In some embodiments, the third mask layer 594 serves to protect the sidewalls of the dielectric layer 593 during a subsequent removal operation to remove the bottom of the dielectric layer 593 from the first opening 572 and the second opening 582.

[0109] like Figure 23 As shown, a removal operation is performed to remove the bottom of the dielectric layer 593 in the first opening 572 and the second opening 582 to expose the second conductor 514 and the fourth conductor 524.

[0110] like Figure 24 As shown, the third mask layer 594 is removed, and a first inner conductive layer 516 and a second inner conductive layer 526 are formed in the first opening 572 and the second opening 582. In some embodiments, the first inner conductive layer 516 is in direct contact with the second wire 514. In some embodiments, the second inner conductive layer 526 is in direct contact with the fourth wire 524. In some embodiments, the first inner conductive layer 516 and the second inner conductive layer 526 are formed of a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.).

[0111] In some embodiments, the first semiconductor chip 502 and the second semiconductor chip 503 are bonded to the substrate die 554, and the first inner conductive layer 516 and the first outer conductive layer 518 are coupled to a first differential data driving circuit in the substrate die 554. In some embodiments, the substrate die 554 and the computing die 556 are bonded to an interposer 558.

[0112] In some embodiments, the semiconductor chip and substrate die 554 are stacked (e.g., sequentially) along the Z-direction. The substrate die 554 and computing die 556 are integrated along the X-direction at different locations on the interposer 558. In some embodiments, the memory device 500 can be bonded to the substrate die 554 via a bonding layer. In some embodiments, the bonding layer may be a BGA.

[0113] In some embodiments, the substrate die 554 includes a control circuitry system configured to control the memory device 500. The substrate die 554 is bonded to an interposer 558 via a plurality of bump structures. The substrate die 554 can be coupled to a computing die 556 via the interposer 558. The interposer 558 may have conductive terminals and wiring formed internally within the interposer 558, and the substrate die 554 can be coupled to the computing die 556 via the conductive terminals and internal wiring of the interposer 558. It should be understood that in practice, the substrate die 554, the computing die 556, and the interposer 558 can be integrated together using any suitable packaging technology, including, for example, chip-on-wafer (CoWoS).

[0114] By forming a first contact structure 510 and a second contact structure 520 having an inner conductive layer and an outer conductive layer connected to different metal layers (e.g., wires 512, 514, 522, and 524), differential signal transmission can be achieved to resist external interference to the signal. Furthermore, by using the first contact structure 510 and the second contact structure 520 with inner and outer conductive layers, a higher signal transmission frequency can be achieved without increasing the number of TSVs.

[0115] Figure 26 A schematic diagram of a differential circuit 2600 according to some embodiments of the present disclosure is shown. The differential circuit 2600 is used to control a memory device 500.

[0116] A first data signal is transmitted from the first semiconductor chip 502 to the data receiver through a first outer conductive layer 518, and a second data signal is transmitted from the first semiconductor chip 502 to the data receiver through a first inner conductive layer 516. In some embodiments, the first data signal and the second data signal are inverted signals, for example, Figure 26 The DATA+ and DATA- in the text.

[0117] In some embodiments, a first data signal is transmitted from a first wire 512 to a data receiver via a first outer conductive layer 518. In some embodiments, a second data signal is transmitted from a second wire 514 to a data receiver via a first inner conductive layer 516.

[0118] In some embodiments, the operation method further includes: providing a control signal to the driving circuit via a data buffer to trigger a differential signal circuit in the driving circuit; and providing a first data signal and a second data signal via the differential signal circuit. In some embodiments, the operation method further includes: receiving the first data signal and the second data signal via received data; and performing differential decoding on the first data signal and the second data signal to interpret the voltage difference between the first data signal and the second data signal.

[0119] Figure 27 A block diagram of a system 2700 having a memory device according to some aspects of this disclosure is shown. System 2700 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 27 As shown, system 2700 may include host 2708 and memory system 2702 having one or more memory devices 2704 and memory controller 2706. Host 2708 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host 2708 may be configured to send data to or receive data from memory device 2704.

[0120] According to some embodiments, memory controller 2706 is coupled to memory device 2704 and host 2708 and is configured to control memory device 2704. In some embodiments, memory device 2704 may be the aforementioned memory device 500. Memory controller 2706 may manage data stored in memory device 2704 and communicate with host 2708. In some embodiments, memory controller 2706 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 2706 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), used for data storage in mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 2706 may be configured to control the operation of memory device 2704, such as read, erase, and program operations. In some embodiments, the memory controller 2706 is configured to control the memory cell array via a first peripheral circuit and a second peripheral circuit. The memory controller 2706 may also be configured to manage various functions relating to data stored in or to be stored in the memory device 2704, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 2706 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory device 2704. The memory controller 2706 may also perform any other suitable functions, such as formatting the memory device 2704. The memory controller 2706 may communicate with an external device (e.g., a host 2708) according to a specific communication protocol. For example, the memory controller 2706 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0121] The memory controller 2706 and one or more memory devices 2704 can be integrated into various types of memory devices, for example, included in the same package such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 2702 can be implemented and packaged into different types of end electronic products. Figure 28AIn one example shown, the memory controller 2706 and a single memory device 2704 can be integrated into a memory card 2802. The memory card 2802 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 2802 may also include a connection between the memory card 2802 and a host computer (e.g., Figure 27 The host 2708 in the memory card connector 2804 is coupled to the host 2708. In such a way... Figure 28B In another example shown, the memory controller 2706 and multiple memory devices 2704 can be integrated into the SSD 2806. The SSD 2806 may also include an SSD connector 2808 that connects the SSD 2806 to a host computer (e.g., ...). Figure 27 The host 2708 is coupled to the SSD 2806. In some implementations, the storage capacity and / or operating speed of the SSD 2806 is greater than that of the memory card 2802.

[0122] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance given herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0123] The breadth and scope of this disclosure should not be limited by any of the embodiments described in the foregoing exemplary embodiments, but should be defined solely by the appended claims and their equivalents.

Claims

1. A memory device, comprising: A first semiconductor chip, the first semiconductor chip comprising a first semiconductor structure and a first interconnect structure; The second semiconductor chip is stacked with the first semiconductor chip along a first direction, and the second semiconductor chip includes a second semiconductor structure and a second interconnect structure. as well as A first contact structure extends along the first direction in the first semiconductor chip and contacts the first interconnect structure. The first contact structure includes a first inner conductive layer and a first outer conductive layer surrounding the first inner conductive layer, and the first interconnect structure extends along a second direction perpendicular to the first direction.

2. The memory device according to claim 1, further comprising: A second contact structure extends along the first direction in both the first and second semiconductor chips, and the second contact structure contacts the second interconnect structure. The second contact structure includes a second inner conductive layer and a second outer conductive layer surrounding the second inner conductive layer.

3. The memory device according to claim 2, wherein, The first inner conductive layer and the first outer conductive layer are arranged along the second direction, and the second inner conductive layer and the second outer conductive layer are also arranged along the second direction.

4. The memory device according to claim 2, wherein, The second contact structure extends along the first direction and contacts the second interconnect structure without contacting the first interconnect structure.

5. The memory device according to claim 2, wherein, The first contact structure further includes a first dielectric layer disposed between the first inner conductive layer and the first outer conductive layer, and the second contact structure further includes a second dielectric layer disposed between the second inner conductive layer and the second outer conductive layer.

6. The memory device according to claim 2, wherein, The length of the first inner conductive layer along the first direction is greater than the length of the first outer conductive layer along the first direction, and the length of the second inner conductive layer along the first direction is greater than the length of the second outer conductive layer along the first direction.

7. The memory device according to claim 2, wherein, The first interconnect structure includes a first wire extending along the second direction and a second wire extending along the second direction, and the second interconnect structure includes a third wire extending along the second direction and a fourth wire extending along the second direction.

8. The memory device according to claim 7, wherein, The first conductor is parallel to the second conductor, and the third conductor is parallel to the fourth conductor.

9. The memory device according to claim 7, wherein, The first outer conductive layer is in contact with the first wire, the first inner conductive layer is in contact with the second wire, the second outer conductive layer is in contact with the third wire, and the second inner conductive layer is in contact with the fourth wire.

10. The memory device according to claim 9, wherein, The width of the first conductor along a third direction perpendicular to the first direction and the second direction is greater than the width of the second conductor along the third direction, and the width of the third conductor along the third direction is greater than the width of the fourth conductor along the third direction.

11. The memory device according to claim 1, wherein, The first semiconductor structure includes a memory array and peripheral circuitry, and the first contact structure is coupled to the peripheral circuitry via the first interconnect structure.

12. The memory device according to claim 11, wherein, The memory array includes memory elements and capacitors, and the memory elements and capacitors are arranged along the first direction.

13. The memory device of claim 1, further comprising: A substrate die stacked with the first semiconductor chip and the second semiconductor chip along the first direction. The first contact structure is in contact with the base die.

14. The memory device according to claim 1, wherein, The second semiconductor chip is stacked with the first semiconductor chip through a third dielectric layer.

15. The memory device according to claim 6, wherein, The length of the second contact structure along the first direction is greater than the length of the first contact structure along the first direction, and the length of the second interconnect structure along the second direction is greater than the length of the first interconnect structure along the second direction.

16. The memory device according to claim 1, wherein, The diameter of the first inner conductive layer is between 1 micrometer and 10 micrometers, and the diameter of the first outer conductive layer is between 3 micrometers and 20 micrometers.

17. The memory device according to claim 1, wherein, The first inner conductive layer and the first outer conductive layer form a concentric circle pattern in the plan view of the memory device.

18. The memory device according to claim 1, wherein, The first inner conductive layer and the first outer conductive layer form a concentric pillar extending along the first direction.

19. A method of forming a memory device, comprising: Forming a first semiconductor chip including a first semiconductor structure and a first interconnect structure; Forming a second semiconductor chip including a second semiconductor structure and a second interconnect structure; The first semiconductor chip and the second semiconductor chip are bonded along a first direction; as well as A first contact structure is formed, comprising a first inner conductive layer and a first outer conductive layer surrounding the first inner conductive layer. The first contact structure extends along the first direction in the first semiconductor chip and contacts the first interconnect structure, and the first interconnect structure extends along a second direction perpendicular to the first direction.

20. The method of claim 19, further comprising: A second contact structure is formed, comprising a second inner conductive layer and a second outer conductive layer surrounding the second inner conductive layer, wherein the second contact structure extends along the first direction in the first semiconductor chip and the second semiconductor chip, and the second contact structure contacts the second interconnect structure.

21. The method according to claim 19, wherein, The first semiconductor chip, comprising the first semiconductor structure and the first interconnect structure, includes: The first semiconductor structure is formed on a substrate; and A first conductive line and a second conductive line are formed on the first semiconductor structure. The first wire and the second wire extend along the second direction, the second wire is located between the first wire and the first semiconductor structure along the first direction, and the first wire is parallel to the second wire.

22. The method according to claim 19, wherein, The first contact structure comprising the first inner conductive layer and the first outer conductive layer surrounding the first inner conductive layer includes: A first concentric pillar is formed, consisting of the first inner conductive layer and the first outer conductive layer surrounding the first inner conductive layer.

23. The method of claim 20, wherein, The second contact structure comprising the second inner conductive layer and the second outer conductive layer surrounding the second inner conductive layer includes: A second concentric pillar is formed, consisting of the second inner conductive layer and the second outer conductive layer surrounding the second inner conductive layer.

24. The method according to claim 21, wherein, The first contact structure comprising the first inner conductive layer and the first outer conductive layer surrounding the first inner conductive layer includes: A first opening is formed in the first semiconductor chip, extending along the first direction and exposing the first interconnect structure; The first outer conductive layer is formed in the first opening; A first dielectric layer is formed on the first outer conductive layer; and The first inner conductive layer is formed on the first dielectric layer.

25. The method according to claim 24, wherein, Forming the first outer conductive layer in the first opening includes: A second dielectric layer is formed in the first opening; Remove the bottom portion of the second dielectric layer to expose the first conductor; A first outer conductive layer in contact with the first wire is formed on the second dielectric layer; and Remove the bottom portion of the first outer conductive layer and the third dielectric layer between the first conductor and the second conductor to expose the second conductor.

26. The method of claim 25, wherein, Forming the first dielectric layer on the first outer conductive layer includes: A first dielectric layer is formed in the first opening, which is in contact with the first outer conductive layer and the second wire.

27. The method according to claim 26, wherein, Forming the first inner conductive layer on the first dielectric layer includes: Remove the bottom portion of the first dielectric layer to expose the second conductor; and A first inner conductive layer is formed in the first opening to contact the second wire.

28. The method according to claim 19, wherein, Bonding the first semiconductor chip and the second semiconductor chip along the first direction includes: The first semiconductor chip and the second semiconductor chip are bonded together through a third dielectric layer.

29. The method of claim 20, further comprising: The first semiconductor chip and the second semiconductor chip are bonded to a substrate die, wherein the first inner conductive layer and the first outer conductive layer are coupled to a first differential data driving circuit in the substrate die, and the second inner conductive layer and the second outer conductive layer are coupled to a second differential data driving circuit in the substrate die; and The substrate die and the computing die are bonded to the interposer.

30. A method of operating a memory device, wherein, The memory device includes: a first semiconductor chip, a first contact structure extending in the first semiconductor chip, the first contact structure including a first inner conductive layer and a first outer conductive layer surrounding the first inner conductive layer, and the operation method includes: The first data signal is transmitted from the first semiconductor chip to the data receiver through the first outer conductive layer; and The second data signal is transmitted from the first semiconductor chip to the data receiver through the first inner conductive layer. The first data signal and the second data signal are inverted signals.

31. The operating method according to claim 30, wherein, The first semiconductor chip includes a first semiconductor structure and a first interconnect structure. The first interconnect structure includes a first wire and a second wire parallel to the first wire. Transmitting the first data signal from the first semiconductor chip to the data receiver through the first outer conductive layer includes: The first data signal is transmitted from the first wire to the data receiver through the first outer conductive layer.

32. The method according to claim 31, wherein, Transmitting the second data signal from the first semiconductor chip to the data receiver through the first inner conductive layer includes: The second data signal is transmitted from the second wire to the data receiver through the first inner conductive layer.

33. The method of claim 30, further comprising: A control signal is provided to the drive circuit through a data buffer to trigger the differential signal circuit in the drive circuit. as well as The first data signal and the second data signal are provided by the differential signal circuit.

34. The method of claim 30, further comprising: The first data signal and the second data signal are received by receiving the data. as well as Differential decoding is performed on the first data signal and the second data signal to interpret the voltage difference between the first data signal and the second data signal.

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