Semiconductor dies and semiconductor packages including semiconductor dies

Abstract

The present disclosure relates to semiconductor dies and semiconductor packages including semiconductor dies. A semiconductor package includes a package substrate, a first semiconductor die, and a second semiconductor die. A first data pad of the first semiconductor die and a second data pad of the second semiconductor die are collectively coupled to a substrate data pad of the package substrate. The first semiconductor die electrically couples a data input / output circuit block of the first semiconductor die to the first data pad based on a first enable signal. The second semiconductor die electrically couples a data input / output circuit block of the second semiconductor die to the second data pad based on a second enable signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 63 / 775,153, filed March 20, 2025; U.S. Patent Application No. 19 / 537,713, filed February 12, 2026; and Korean Application No. 10-2025-0120332, filed August 27, 2025 with the Korean Intellectual Property Office, which are incorporated herein by reference in their entirety. Technical Field

[0003] Various embodiments generally relate to a method for designing integrated circuits, and more specifically, to a semiconductor die and a semiconductor package including the semiconductor die. Background Technology

[0004] Recently, with the emergence of big data, artificial intelligence, and high-performance applications, the amount of data processed in computing systems has increased, and computing performance has become more advanced. Typically, a computing system can include host devices and storage devices. Host devices can access storage devices to read data for computation, perform computations on the read data, and write the computed data back to the storage devices. As the computing performance of host devices improves, there is a need to transfer larger amounts of data between host devices and storage devices; therefore, the memory capacity and data bandwidth of storage devices must be expanded to support higher performance requirements.

[0005] To increase memory capacity, stacked semiconductor package structures have been adopted, consisting of multiple memory dies arranged vertically and two or more memory dies commonly connected to a data bus. During a write operation, an external device connected to the data bus must drive the combined load of the two or more memory dies. During a read operation, the memory die performing the read operation must drive the load presented by the remaining memory dies and the external device. Due to these load conditions, achieving data transfer speeds that meet target performance levels becomes difficult. Summary of the Invention

[0006] In one embodiment, a semiconductor die includes a first data pad, a second data pad, a first data input / output circuit, a second data input / output circuit, a first switching circuit, and a second switching circuit. The first data pad can be coupled to a first data transmission line transmitting a first data signal. The second data pad can be coupled to a second data transmission line transmitting a second data signal. The first data input / output circuit can be configured to generate a first data signal based on a first internal data signal, and can also be configured to generate a first internal data signal based on the first data signal. The second data input / output circuit can be configured to generate a second data signal based on a second internal data signal, and can also be configured to generate a second internal data signal based on the second data signal. The first switching circuit can be configured to couple the first data pad to the first data input / output circuit based on an enable signal. The second switching circuit can be configured to couple the second data pad to the second data input / output circuit based on an enable signal.

[0007] In one embodiment, a semiconductor package includes a package substrate, a first semiconductor die, and a second semiconductor die. The package substrate may have substrate data pads coupled to a data bus for transmitting data. The first semiconductor die may be disposed on the package substrate. The second semiconductor die may be disposed on the first semiconductor die. The first semiconductor die may include: a first data pad coupled to the substrate data pad; a first data input / output circuit block configured to generate first internal data based on data and configured to generate data based on the first internal data; and a first switch circuit block configured to selectively couple the first data pad to the first data input / output circuit block based on a first chip select signal. The second semiconductor die may include: a second data pad coupled to the substrate data pad; a second data input / output circuit block configured to generate second internal data based on data and configured to generate data based on the second internal data; and a second switch circuit block configured to selectively couple the second data pad to the second data input / output circuit block based on a second chip select signal.

[0008] In one embodiment, a semiconductor package includes a package substrate, a first semiconductor die, and a second semiconductor die. The package substrate may include substrate data pads coupled to a data bus for transmitting data. The first semiconductor die may be disposed on the package substrate. The second semiconductor die may be disposed on the first semiconductor die. The first data pad of the first semiconductor die and the second data pad of the second semiconductor die may be commonly coupled to the substrate data pads. The first data pad may be selectively coupled to a data input / output circuit block of the first semiconductor die based on a first enable signal, and the second data pad may be selectively coupled to a data input / output circuit block of the second semiconductor die based on a second enable signal.

[0009] In one embodiment, a semiconductor package includes a packaging substrate, a first semiconductor die, a second semiconductor die, a third semiconductor die, and a fourth semiconductor die. The packaging substrate may include a first substrate data pad coupled to a first data bus and a second substrate data pad coupled to a second data bus. The first semiconductor die may be disposed on the packaging substrate. The second semiconductor die may be disposed on the first semiconductor die. The third semiconductor die may be disposed on the second semiconductor die. The fourth semiconductor die may be disposed on the third semiconductor die. The first data pad of the first semiconductor die and the second data pad of the second semiconductor die may be jointly coupled to the first substrate data pad, and the third data pad of the third semiconductor die and the fourth data pad of the fourth semiconductor die may be jointly coupled to the second substrate data pad. When a first chip select signal is enabled, the data input / output circuit block of the first semiconductor die may be coupled to the first data pad, and the data input / output circuit block of the third semiconductor die may be coupled to the third data pad. When the second chip select signal is enabled, the data input / output circuit block of the second semiconductor die can be coupled to the second data pad, and the data input / output circuit block of the fourth semiconductor die can be coupled to the fourth data pad. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating the configuration of a semiconductor package according to an embodiment of the present disclosure.

[0011] Figure 2 This is a diagram illustrating the conceptual connection relationship between the pads of a package substrate and the pads of a plurality of semiconductor dies in a semiconductor package according to an embodiment of the present disclosure.

[0012] Figure 3 This is a diagram illustrating the configuration of a semiconductor die according to an embodiment of the present disclosure.

[0013] Figure 4 This is a diagram illustrating the configuration of a command address control circuit according to an embodiment of the present disclosure.

[0014] Figure 5 This is a timing diagram illustrating the operation of a semiconductor package according to an embodiment of the present disclosure.

[0015] Figure 6 This is a diagram illustrating the configuration of a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0016] Terms such as “first” and “second” are used to distinguish multiple elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, a first element may be named a second element, and in another example, a second element may be named a first element. Terms such as “top,” “above,” “on,” “side,” “upper,” “lower,” “row,” “column,” “inner,” “outer,” and other terms that suggest relative spatial relationships or orientations are used for the convenience of describing or referring to the drawings and are not otherwise restrictive. Section lines running through the drawings show corresponding or similar areas between the drawings, rather than indicating the material associated with these areas. It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, directly connected to, or coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intermediate elements or layers.

[0017] Figure 1 This is a diagram illustrating the configuration of a semiconductor package 100 according to an embodiment of the present disclosure. (See reference...) Figure 1 The semiconductor package 100 may include a package substrate 110 and multiple dies. Figure 1 In this embodiment, semiconductor package 100 is shown to include a first semiconductor die 120, a second semiconductor die 130, a third semiconductor die 140, and a fourth semiconductor die 150, but this is not intended to limit the number of semiconductor dies included in semiconductor package 100. The number of semiconductor dies included in semiconductor package 100 may be less than four or more than four.

[0018] First semiconductor dies 120 to fourth semiconductor dies 150 can be disposed on package substrate 110 and can be packaged into a single package. First semiconductor die 120 can be disposed on package substrate 110. For example, first semiconductor die 120 can be disposed at the center portion of package substrate 110 in the x-axis and z-axis directions. First semiconductor die 120 can be bonded to package substrate 110 using adhesive or die attach film (DAF). Second semiconductor die 130 can be disposed on first semiconductor die 120 in the y-axis direction. Third semiconductor die 140 can be disposed on second semiconductor die 130 in the y-axis direction. Fourth semiconductor die 150 can be disposed on third semiconductor die 140 in the y-axis direction. Second semiconductor dies 130 to fourth semiconductor dies 150 can be bonded to first semiconductor dies 120 to third semiconductor dies 140 respectively using die attach film. First semiconductor dies 120 to fourth semiconductor dies 150 can each include data pads on their first side. The data pads of the first semiconductor die 120 may be referred to as the first data pad 121. The data pads of the second semiconductor die 130 may be referred to as the second data pad 131. The data pads of the third semiconductor die 140 may be referred to as the third data pad 141. The data pads of the fourth semiconductor die 150 may be referred to as the fourth data pad 151. The first semiconductor die 120 to the fourth semiconductor die 150 may be arranged in a stepped shape, such that the first data pads 121 to the fourth data pads 151 are exposed. For example, the second semiconductor die 130 may be disposed on the first semiconductor die 120 and simultaneously in the first direction of the x-axis (in Figure 1 Offset along the x-axis to the left. The third semiconductor die 140 may be disposed on the second semiconductor die 130 and offset from the second semiconductor die 130 in the first direction. The fourth semiconductor die 150 may be disposed on the third semiconductor die 140 and offset from the third semiconductor die 140 in the first direction.

[0019] The package substrate 110 can be coupled to an external device via a data bus 101. The external device can be a host device capable of controlling various operations of the semiconductor package 100, and can include at least one of a central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), multimedia processor (MMP), digital signal processor (DSP), application processor (AP), and memory controller. The package substrate 110 can be coupled to the data bus 101 via package balls 111. The package substrate 110 can include substrate data pads 112. The substrate data pads 112 can be coupled to the data bus 101. The substrate data pads 112 can be located at a position spaced apart from the first semiconductor die 120 in a second direction opposite to the first direction. The number of substrate data pads 112 can be substantially equal to the number of data transmission lines included in the data bus 101. The number of data signals included in the data DQ<1:n> transmitted through the data bus 101 can be n, and the number of substrate data pads 112 can be n. Here, n can be a multiple of 4 or a multiple of 6. The substrate data pad 112 can be coupled to the data bus 101 via signal paths 113 formed in the package substrate 110 and package balls 111. First semiconductor dies 120 to fourth semiconductor dies 150 can share the data bus 101. First data pad 121, second data pad 131, third data pad 141, and fourth data pad 151 can be jointly coupled to the substrate data pad 112. Each of the first data pads 121 to fourth data pads 151 can include n data pads. First data pad 121 can be coupled to the substrate data pad 112 via a first bonding wire W11. Second data pad 131 can be coupled to the first data pad 121 via a second bonding wire W12. Third data pad 141 can be coupled to the second data pad 131 via a third bonding wire W13. Fourth data pad 151 can be coupled to the third data pad 141 via a fourth bonding wire W14. The number of the first to fourth bonding lines W11, W12, W13 and W14 can be n respectively.

[0020] The internal circuitry of the first semiconductor die 120 can be selectively coupled to the first data pad 121 based on the first enable signal EN1. The internal circuitry of the second semiconductor die 130 can be selectively coupled to the second data pad 131 based on the second enable signal EN2. The internal circuitry of the third semiconductor die 140 can be selectively coupled to the third data pad 141 based on the third enable signal EN3. The internal circuitry of the fourth semiconductor die 150 can be selectively coupled to the fourth data pad 151 based on the fourth enable signal EN4. The first semiconductor die 120 to the fourth semiconductor die 150 can be accessed based on different chip select signals. An external device can provide the semiconductor package 100 with the first chip select signal CS1, the second chip select signal CS2, the third chip select signal CS3, and the fourth chip select signal CS4. The package substrate 110 can receive the first chip select signal CS1 to the fourth chip select signal CS4 through the package ball 111, and the first chip select signal CS1 to the fourth chip select signal CS4 can be provided to the first semiconductor die 120 to the fourth semiconductor die 150 respectively. The first semiconductor die 120 can be accessed by the first chip select signal CS1, and the first enable signal EN1 can be generated based on the first chip select signal CS1. The second semiconductor die 130 can be accessed by the second chip select signal CS2, and the second enable signal EN2 can be generated based on the second chip select signal CS2. The third semiconductor die 140 can be accessed by the third chip select signal CS3, and the third enable signal EN3 can be generated based on the third chip select signal CS3. The fourth semiconductor die 150 can be accessed by the fourth chip select signal CS4, and the fourth enable signal EN4 can be generated based on the fourth chip select signal CS4. The internal circuitry of the first semiconductor die 120 to the fourth semiconductor die 150 can be selectively coupled to the first data pad 121 to the fourth data pad 151 based on the first enable signal EN1 to the fourth enable signal EN4 or the first chip select signal CS1 to the fourth chip select signal CS4, respectively. An external device can enable one of the first chip select signals CS1 to the fourth chip select signal CS4 to access one of the first semiconductor die 120 to the fourth semiconductor die 150. For example, when an external device accesses the first semiconductor die 120, the first chip select signal CS1 can be enabled, and the first enable signal EN1 can be enabled based on the first chip select signal CS1, while the second chip select signals CS2 to CS4 and the second enable signals EN2 to EN4 can be disabled. Therefore, the internal circuitry of the first semiconductor die 120 can be coupled to the first data pad 121, while the internal circuitry of the second semiconductor dies 130 to CS4 can be electrically isolated from the second data pads 131 to CS4.Although the data bus 101 is commonly coupled to the first data pads 121 to the fourth data pads 151, it can be coupled to the load of the internal circuitry of the first semiconductor die 120, and may not be coupled to the load of the internal circuitry of the second semiconductor dies 130 to the fourth semiconductor dies 150. Because, in one embodiment, the external device and / or the data bus 101 can handle the load of only one semiconductor die at a time, the data transmission speed of the data bus 101 can be maintained, and the signal integrity (SI) of the data DQ<1:n> transmitted through the data bus 101 can be improved.

[0021] The first semiconductor die 120 may include a first data pad 121, a first data input / output circuit block I / OBLK 122, and a first switch circuit block SW BLK 123. The first data input / output circuit block 122 may be internal circuitry. The first data input / output circuit block 122 can generate first internal data 125 based on data DQ<1:n>, and can also generate data DQ<1:n> based on the first internal data 125. During a write operation of the first semiconductor die 120, the first data input / output circuit block 122 can receive data DQ<1:n> transmitted from an external device via data bus 101 through the first data pad 121, and can generate the first internal data 125 from the data DQ<1:n>. During a read operation of the first semiconductor die 120, the first data input / output circuit block 122 can generate data DQ<1:n> based on the first internal data 125, and can output data DQ<1:n> through the first data pad 121. The first data input / output circuit block 122 may include a data receiving circuit for receiving data DQ<1:n> and a data transmitting circuit for outputting data DQ<1:n>. The first data input / output circuit block 122 may also include a deserializer and a serializer. The deserializer deserializes the data DQ<1:n> to generate first internal data 125, and the serializer serializes the first internal data 125 to generate data DQ<1:n>. The number of data signals included in the data DQ<1:n> may be n, and the number of internal data signals included in the first internal data 125 may be n×m. Here, m may be the burst length. The burst length may be the number of data words transmitted in a write or read operation. For example, when the burst length is 8, each of the n data signals included in the data DQ<1:n> may be an 8-bit serial data signal, and the first internal data 125 may include 8n internal data signals. The first data input / output circuit block 122 may include a number of data input / output circuits corresponding to the number of data transmission lines included in the data bus 101. For example, the first data input / output circuit block 122 may include n data input / output circuits respectively coupled to n data transmission lines.

[0022] The first switching circuit block 123 can couple the first data pad 121 to the first data input / output circuit block 122. The first switching circuit block 123 can receive a first enable signal EN1 and can selectively couple the first data pad 121 to the first data input / output circuit block 122 based on the first enable signal EN1. When the first enable signal EN1 is enabled, the first switching circuit block 123 can couple the first data input / output circuit block 122 to the first data pad 121. When the first enable signal EN1 is disabled, the first switching circuit block 123 can electrically isolate the first data input / output circuit block 122 from the first data pad 121. The first switching circuit block 123 can couple the data input / output circuits included in the first data input / output circuit block 122 to the first data pad 121 in a one-to-one manner. For example, the first switching circuit block 123 can include n switching circuits, which respectively couple n data input / output circuits to n data pads.

[0023] The first semiconductor die 120 may further include a core circuit 124. The core circuit 124 may receive first internal data 125, store the first internal data 125 in the core circuit 124, and output the data stored in the core circuit 124 as the first internal data 125. The core circuit 124 may include a data storage area, a write circuit, and a read circuit. During a write operation, the write circuit may receive the first internal data 125 and store the first internal data 125 in the data storage area. During a read operation, the read circuit may read the data stored in the data storage area and output the read data as the first internal data 125.

[0024] The second semiconductor die 130 to the fourth semiconductor die 150 may include a configuration substantially the same as that of the first semiconductor die 120. The second semiconductor die 130 may include a second data pad 131, a second data input / output circuit block I / OBLK 132, and a second switch circuit block SW BLK 133. The second data input / output circuit block 132 can generate second internal data 135 based on data DQ<1:n>, and can generate data DQ<1:n> based on the second internal data 135. During a write operation of the second semiconductor die 130, the second data input / output circuit block 132 can receive data DQ<1:n> transmitted from an external device via data bus 101 through the second data pad 131, and can generate the second internal data 135 from the data DQ<1:n>. During the read operation of the second semiconductor die 130, the second data input / output circuit block 132 can generate data DQ<1:n> based on the second internal data 135, and can output the data DQ<1:n> through the second data pad 131. The second data input / output circuit block 132 may include a data receiving circuit for receiving the data DQ<1:n> and a data transmitting circuit for outputting the data DQ<1:n>. The second data input / output circuit block 132 may also include a deserializer and a serializer. The deserializer deserializes the data DQ<1:n> to generate the second internal data 135, and the serializer serializes the second internal data 135 to generate the data DQ<1:n>. The number of internal data signals included in the second internal data 135 may be n×m. The second data input / output circuit block 132 may include n data input / output circuits respectively coupled to n data transmission lines.

[0025] The second switching circuit block 133 can couple the second data pad 131 to the second data input / output circuit block 132. The second switching circuit block 133 can receive a second enable signal EN2 and can selectively couple the second data pad 131 to the second data input / output circuit block 132 based on the second enable signal EN2. When the second enable signal EN2 is enabled, the second switching circuit block 133 can couple the second data input / output circuit block 132 to the second data pad 131. When the second enable signal EN2 is disabled, the second switching circuit block 133 can electrically isolate the second data input / output circuit block 132 from the second data pad 131. The second switching circuit block 133 may include n switching circuits that respectively couple n data input / output circuits to n data pads.

[0026] The second semiconductor die 130 may further include a core circuit 134. The core circuit 134 may receive second internal data 135, store the second internal data 135 in the core circuit 134, and output the data stored in the core circuit 134 as the second internal data 135. The core circuit 134 may include a data storage area, a write circuit, and a read circuit. During a write operation, the write circuit may receive the second internal data 135 and store the second internal data 135 in the data storage area. During a read operation, the read circuit may read the data stored in the data storage area and output the read data as the second internal data 135.

[0027] The third semiconductor die 140 may include a third data pad 141, a third data input / output circuit block I / OBLK 142, and a third switch circuit block SW BLK 143. The third data input / output circuit block 142 can generate third internal data 145 based on data DQ<1:n>, and can also generate data DQ<1:n> based on the third internal data 145. During a write operation of the third semiconductor die 140, the third data input / output circuit block 142 can receive data DQ<1:n> transmitted from an external device via the data bus 101 through the third data pad 141, and can generate the third internal data 145 from the data DQ<1:n>. During a read operation of the third semiconductor die 140, the third data input / output circuit block 142 can generate data DQ<1:n> based on the third internal data 145, and can output data DQ<1:n> through the third data pad 141. The third data input / output circuit block 142 may include a data receiving circuit for receiving data DQ<1:n> and a data transmitting circuit for outputting data DQ<1:n>. The third data input / output circuit block 142 may also include a deserializer and a serializer. The deserializer deserializes the data DQ<1:n> to generate third internal data 145, and the serializer serializes the third internal data 145 to generate data DQ<1:n>. The number of internal data signals included in the third internal data 145 may be n×m. The third data input / output circuit block 142 may include n data input / output circuits respectively coupled to n data transmission lines.

[0028] The third switching circuit block 143 can couple the third data pad 141 to the third data input / output circuit block 142. The third switching circuit block 143 can receive a third enable signal EN3 and can selectively couple the third data pad 141 to the third data input / output circuit block 142 based on the third enable signal EN3. When the third enable signal EN3 is enabled, the third switching circuit block 143 can couple the third data input / output circuit block 142 to the third data pad 141. When the third enable signal EN3 is disabled, the third switching circuit block 143 can electrically isolate the third data input / output circuit block 142 from the third data pad 141. The third switching circuit block 143 may include n switching circuits that respectively couple n data input / output circuits to n data pads.

[0029] The third semiconductor die 140 may further include core circuitry 144. Core circuitry 144 may receive third internal data 145, store the third internal data 145 within core circuitry 144, and output the data stored in core circuitry 144 as third internal data 145. Core circuitry 144 may include a data storage area, a write circuit, and a read circuit. During a write operation, the write circuit may receive the third internal data 145 and store the third internal data 145 in the data storage area. During a read operation, the read circuit may read the data stored in the data storage area and output the read data as third internal data 145.

[0030] The fourth semiconductor die 150 may include a fourth data pad 151, a fourth data input / output circuit block I / OBLK 152, and a fourth switch circuit block SW BLK 153. The fourth data input / output circuit block 152 can generate fourth internal data 155 based on data DQ<1:n>, and can also generate data DQ<1:n> based on the fourth internal data 155. During a write operation of the fourth semiconductor die 150, the fourth data input / output circuit block 152 can receive data DQ<1:n> transmitted from an external device via data bus 101 through the fourth data pad 151, and can generate the fourth internal data 155 from the data DQ<1:n>. During a read operation of the fourth semiconductor die 150, the fourth data input / output circuit block 152 can generate data DQ<1:n> based on the fourth internal data 155, and can output data DQ<1:n> through the fourth data pad 151. The fourth data input / output circuit block 152 may include a data receiving circuit for receiving data DQ<1:n> and a data transmitting circuit for outputting data DQ<1:n>. The fourth data input / output circuit block 152 may also include a deserializer and a serializer. The deserializer deserializes the data DQ<1:n> to generate fourth internal data 155, and the serializer serializes the fourth internal data 155 to generate data DQ<1:n>. The number of internal data signals included in the fourth internal data 155 may be n×m. The fourth data input / output circuit block 152 may include n data input / output circuits respectively coupled to n data transmission lines.

[0031] The fourth switching circuit block 153 can couple the fourth data pad 151 to the fourth data input / output circuit block 152. The fourth switching circuit block 153 can receive a fourth enable signal EN4 and can selectively couple the fourth data pad 151 to the fourth data input / output circuit block 152 based on the fourth enable signal EN4. When the fourth enable signal EN4 is enabled, the fourth switching circuit block 153 can couple the fourth data input / output circuit block 152 to the fourth data pad 151. When the fourth enable signal EN4 is disabled, the fourth switching circuit block 153 can electrically isolate the fourth data input / output circuit block 152 from the fourth data pad 151. The fourth switching circuit block 153 may include n switching circuits that respectively couple n data input / output circuits to n data pads.

[0032] The fourth semiconductor die 150 may further include core circuitry 154. Core circuitry 154 may receive fourth internal data 155, store the fourth internal data 155 in core circuitry 154, and output the data stored in core circuitry 154 as fourth internal data 155. Core circuitry 154 may include a data storage area, a write circuit, and a read circuit. During a write operation, the write circuit may receive the fourth internal data 155 and store the fourth internal data 155 in the data storage area. During a read operation, the read circuit may read the data stored in the data storage area and output the read data as fourth internal data 155.

[0033] Figure 2 This is a conceptual diagram illustrating the connection relationship between the pads of the package substrate 110 and the pads of a plurality of semiconductor dies in a semiconductor package 100 according to an embodiment of the present disclosure. Figure 2 The number of pads shown is not limiting but exemplary, and the number of pads included in the package substrate 110 and the first semiconductor dies 120 to the fourth semiconductor dies 150 can vary considerably. (See reference...) Figure 2 The packaging substrate 110 may include first data pads DP11 to eighth data pads DP18, a data clock pad CP11, a read strobe pad CP12, a command address pad CP13, a command clock pad CP14, a first chip select pad CP15, a second chip select pad CP16, a third chip select pad CP17, and a fourth chip select pad CP18. In one embodiment, the first data pads DP11 to fourth data pads DP14 may be disposed on one side of the data clock pad CP11 and the read strobe pad CP12. Figure 2 Above the data clock pad CP11 and read strobe pad CP12), and the fifth data pad DP15 to the eighth data pad DP18 can be located on the other side of the data clock pad CP11 and read strobe pad CP12. Figure 2 Below the data clock pad CP11 and read strobe pad CP12. The first data pads DP11 to the eighth data pads DP18 can correspond to... Figure 1The substrate data pad 112. The first data pad DP11 can be coupled to the first data transmission line 101-1 of the data bus 101, and the first data signal DQ <1> Data can be transmitted via the first data transmission line 101-1. The fourth data pad DP14 can be coupled to the fourth data transmission line 101-4 of the data bus 101, and the fourth data signal DQ... <4> Data can be transmitted via the fourth data transmission line 101-4. The fifth data pad DP15 can be coupled to the fifth data transmission line 101-5 of the data bus 101, and the fifth data signal DQ... <5> Data can be transmitted via the fifth data transmission line 101-5. The eighth data pad DP18 can be coupled to the eighth data transmission line 101-8 of the data bus 101, and the eighth data signal DQ... <8> Data can be transmitted via the eighth data transmission line 101-8. The data clock pad CP11 can be coupled to the data clock bus 102 and can receive the data clock signal WCKT and the complementary data clock signal WCKC via the data clock bus 102. The data clock bus 102 may include two data clock transmission lines that respectively transmit the data clock signal WCKT and the complementary data clock signal WCKC. The data clock pad CP11 may include two pads that are respectively coupled to the two data clock transmission lines and respectively receive the data clock signal WCKT and the complementary data clock signal WCKC. The read strobe pad CP12 can be coupled to the read strobe bus 103, and the read strobe signal RDQST and the complementary read strobe signal RDQSC transmitted from the first semiconductor die 120 to the fourth semiconductor die 150 can be transmitted to an external device via the read strobe pad CP12. The read strobe bus 103 may include two read strobe transmission lines that respectively transmit the read strobe signal RDQST and the complementary read strobe signal RDQSC. The read strobe pad CP12 may include two pads respectively coupled to two read strobe transmission lines and outputting a read strobe signal RDQST and a complementary read strobe signal RDQSC. The command address pad CP13 may be coupled to the command address bus 104 and can receive the command address signal CA<1:k> through the command address bus 104. The command address signal CA<1:k> may include multiple bits, and the command address bus 104 may include multiple signal transmission lines that transmit these multiple bits respectively. The command address pad CP13 may include multiple pads respectively coupled to these multiple signal transmission lines and configured to receive corresponding bits of the command address signal CA<1:k>. The command clock pad CP14 may be coupled to the command clock bus 105, which is coupled to an external device, and can receive the command clock signal CKT and the complementary command clock signal CKC through the command clock bus 105. The command clock bus 105 may include two command clock transmission lines that transmit the command clock signal CKT and the complementary command clock signal CKC respectively.Command clock pad CP14 may include two pads respectively coupled to two command clock transmission lines and configured to receive command clock signal CKT and complementary command clock signal CKC. First chip select pad CP15 may be coupled to first chip select signal transmission line 106 and can receive first chip select signal CS1 through first chip select signal transmission line 106. Second chip select pad CP16 may be coupled to second chip select signal transmission line 107 and can receive second chip select signal CS2 through second chip select signal transmission line 107. Third chip select pad CP17 may be coupled to third chip select signal transmission line 108 and can receive third chip select signal CS3 through third chip select signal transmission line 108. Fourth chip select pad CP18 may be coupled to fourth chip select signal transmission line 109 and can receive fourth chip select signal CS4 through fourth chip select signal transmission line 109.

[0034] The first semiconductor die 120 may include first data pads DP21 to eighth data pads DP28, a data clock pad CP21, a read strobe pad CP22, a command address pad CP23, a command clock pad CP24, and a chip select pad CP25. The first data pads DP21 to fourth data pads DP24 may be located on one side of the data clock pad CP21 and the read strobe pad CP22. Figure 2 Above the data clock pad CP21 and read strobe pad CP22), and the fifth data pad DP25 to the eighth data pad DP28 can be located on the other side of the data clock pad CP21 and read strobe pad CP22. Figure 2 Below the data clock pad CP21 and read strobe pad CP22. The first data pads DP21 to the eighth data pads DP28 can correspond to... Figure 1 The first data pad 121. First data pads DP21 to DP24 can be coupled to the first data pads DP11 to DP14 of the package substrate 110 via bonding wires. Fifth data pads DP25 to DP28 can be coupled to the fifth data pads DP15 to DP18 of the package substrate 110 via bonding wires. Data clock pad CP21 can be coupled to the data clock pad CP11 of the package substrate 110 via bonding wires. Read strobe pad CP22 can be coupled to the read strobe pad CP12 of the package substrate 110 via bonding wires. Command address pad CP23 can be coupled to the command address pad CP13 of the package substrate 110 via bonding wires. Command clock pad CP24 can be coupled to the command clock pad CP14 of the package substrate 110 via bonding wires. Chip select pad CP25 can be coupled to the first chip select pad CP15 of the package substrate 110 via bonding wires.

[0035] The second semiconductor die 130 may include first data pads DP31 to eighth data pads DP38, a data clock pad CP31, a read strobe pad CP32, a command address pad CP33, a command clock pad CP34, and a chip select pad CP35. The first data pads DP31 to fourth data pads DP34 may be located on one side of the data clock pad CP31 and the read strobe pad CP32. Figure 2 Above the data clock pad CP31 and read strobe pad CP32), and the fifth to eighth data pads DP35 and DP38 can be located on the other side of the data clock pad CP31 and read strobe pad CP32. Figure 2 Below the data clock pad CP31 and read strobe pad CP32. The first data pads DP31 to the eighth data pads DP38 can correspond to... Figure 1 The second data pad 131. First data pads DP31 to DP34 can be coupled to first data pads DP21 to DP24 of the first semiconductor die 120 via bonding wires. Fifth data pads DP35 to DP38 can be coupled to fifth data pads DP25 to DP28 of the first semiconductor die 120 via bonding wires. Data clock pad CP31 can be coupled to data clock pad CP21 of the first semiconductor die 120 via bonding wires. Read strobe pad CP32 can be coupled to read strobe pad CP22 of the first semiconductor die 120 via bonding wires. Command address pad CP33 can be coupled to command address pad CP23 of the first semiconductor die 120 via bonding wires. Command clock pad CP34 can be coupled to command clock pad CP24 of the first semiconductor die 120 via bonding wires. Chip select pad CP35 can be coupled to the second chip select pad CP16 of the package substrate 110 via bonding wires.

[0036] The third semiconductor die 140 may include first data pads DP41 to eighth data pads DP48, a data clock pad CP41, a read strobe pad CP42, a command address pad CP43, a command clock pad CP44, and a chip select pad CP45. The first data pads DP41 to fourth data pads DP44 may be located on one side of the data clock pad CP41 and the read strobe pad CP42. Figure 2 Above the data clock pad CP41 and the read strobe pad CP42), and the fifth data pad DP45 to the eighth data pad DP48 can be located on the other side of the data clock pad CP41 and the read strobe pad CP42. Figure 2Below the data clock pad CP41 and read strobe pad CP42. The first data pads DP41 to the eighth data pads DP48 can correspond to... Figure 1 The third data pad 141. First data pads DP41 to fourth data pads DP44 can be coupled to the first data pads DP31 to fourth data pads DP34 of the second semiconductor die 130 via bonding wires. Fifth data pads DP45 to eighth data pads DP48 can be coupled to the fifth data pads DP35 to eighth data pads DP38 of the second semiconductor die 130 via bonding wires. Data clock pad CP41 can be coupled to the data clock pad CP31 of the second semiconductor die 130 via bonding wires. Read strobe pad CP42 can be coupled to the read strobe pad CP32 of the second semiconductor die 130 via bonding wires. Command address pad CP43 can be coupled to the command address pad CP33 of the second semiconductor die 130 via bonding wires. Command clock pad CP44 can be coupled to the command clock pad CP34 of the second semiconductor die 130 via bonding wires. Chip select pad CP45 can be coupled to the third chip select pad CP17 of the package substrate 110 via bonding wire.

[0037] The fourth semiconductor die 150 may include first data pads DP51 to eighth data pads DP58, a data clock pad CP51, a read strobe pad CP52, a command address pad CP53, a command clock pad CP54, and a chip select pad CP55. The first data pads DP51 to fourth data pads DP54 may be located on one side of the data clock pad CP51 and the read strobe pad CP52. Figure 2 Above the data clock pad CP51 and the read strobe pad CP52), and the fifth data pad DP55 to the eighth data pad DP58 can be located on the other side of the data clock pad CP51 and the read strobe pad CP52. Figure 2 Below the data clock pad CP51 and read strobe pad CP52. The first data pads DP51 to the eighth data pads DP58 can correspond to... Figure 1The fourth data pad 151. First data pads DP51 to fourth data pads DP54 can be coupled to the first data pads DP41 to fourth data pads DP44 of the third semiconductor die 140 via bonding wires. Fifth data pads DP55 to eighth data pads DP58 can be coupled to the fifth data pads DP45 to eighth data pads DP48 of the third semiconductor die 140 via bonding wires. Data clock pad CP51 can be coupled to the data clock pad CP41 of the third semiconductor die 140 via bonding wires. Read strobe pad CP52 can be coupled to the read strobe pad CP42 of the third semiconductor die 140 via bonding wires. Command address pad CP53 can be coupled to the command address pad CP43 of the third semiconductor die 140 via bonding wires. Command clock pad CP54 can be coupled to the command clock pad CP44 of the third semiconductor die 140 via bonding wires. Chip select pad CP55 can be coupled to the fourth chip select pad CP18 of the package substrate 110 via bonding wire.

[0038] The first semiconductor die 120 to the fourth semiconductor die 150 may have first data pads DP11 to DP18 commonly coupled to the package substrate 110 and first data pads DP21 to DP28, first data pads DP31 to DP38, first data pads DP41 to DP48, and first data pads DP51 to DP58 commonly coupled to the data bus 101. The data clock pads CP21, CP31, CP41, and CP51 of the first semiconductor die 120 to the fourth semiconductor die 150 may be commonly coupled to the data clock pad CP11 of the package substrate 110 and may jointly receive the data clock signal WCKT and the complementary data clock signal WCKC. The read strobe pads CP22, CP32, CP42, and CP52 of the first to fourth semiconductor dies 120 can be jointly coupled to the read strobe pad CP12 of the package substrate 110, and can jointly output the read strobe signal RDQST and the complementary read strobe signal RDQSC generated from the first to fourth semiconductor dies 120. The command address pads CP23, CP33, CP43, and CP53 of the first to fourth semiconductor dies 120 can be jointly coupled to the command address pad CP13 of the package substrate 110, and can typically jointly receive the command address signal CA<1:k>. The command clock pads CP24, CP34, CP44, and CP54 of the first to fourth semiconductor dies 120 can be jointly coupled to the command clock pad CP14 of the package substrate 110, and can jointly receive the command clock signal CKT and the complementary command clock signal CKC. The chip select pads CP25, CP35, CP45 and CP55 of the first semiconductor die 120 to the fourth semiconductor die 150 can be coupled to the first to fourth chip select pads CP15, CP16, CP17 and CP18 of the packaging substrate 110, respectively, and the first semiconductor die 120 to the fourth semiconductor die 150 can receive different chip select signals.

[0039] Figure 3 This is a diagram illustrating the configuration of a semiconductor die 200 according to an embodiment of the present disclosure. Figure 1 and 2 The first semiconductor die 120 to the fourth semiconductor die 150 shown can all be implemented as semiconductor die 200. (See reference) Figure 3 The semiconductor die 200 may include a first data input / output circuit 211 to an eighth data input / output circuit 218 and a first switching circuit 221 to an eighth switching circuit 228. Figure 1Each of the first to fourth data input / output circuit blocks 122, 132, 142 and 152 shown may include multiple data input / output circuits, such as the first data input / output circuit 211 to the eighth data input / output circuit 218. Figure 1Each of the first to fourth switch circuit blocks 123, 133, 143, and 153 shown may include multiple switch circuits, such as the first switch circuit 221 to the eighth switch circuit 228. The first data input / output circuit 211 may be coupled to the first data pad DPx1 and may be coupled to transmit the first data signal DQ. <1> The first data transmission line 101-1. The first data input / output circuit 211 can be based on the first data signal DQ. <1> Generate a first internal data signal D1<1:m>, and can generate a first data signal DQ based on the first internal data signal D1<1:m>. <1> The first data input / output circuit 211 can receive the first data signal DQ during a write operation on the semiconductor die 200. <1> And it can be obtained from the first data signal DQ <1> A first internal data signal D1<1:m> is generated. The first data input / output circuit 211 can generate a first data signal DQ from the first internal data signal D1<1:m> during a read operation of the semiconductor die 200. <1> And the first data signal DQ can be output through the first data pad DPx1. <1> The fourth data input / output circuit 214 can be coupled to the fourth data pad DPx4, and can also be coupled to transmit the fourth data signal DQ. <4> The fourth data transmission line 101-4. The fourth data input / output circuit 214 can be based on the fourth data signal DQ. <4> The fourth internal data signal D4<1:m> is generated, and the fourth data signal DQ can be generated based on the fourth internal data signal D4<1:m>. <4> The fourth data input / output circuit 214 can receive the fourth data signal DQ during the write operation of the semiconductor die 200. <4> And it can be obtained from the fourth data signal DQ <4> A fourth internal data signal D4<1:m> is generated. The fourth data input / output circuit 214 can generate a fourth data signal DQ from the fourth internal data signal D4<1:m> during a read operation of the semiconductor die 200. <4> Furthermore, the fourth data signal DQ can be output via the fourth data pad DPx4. <4> The fifth data input / output circuit 215 can be coupled to the fifth data pad DPx5, and can also be coupled to transmit the fifth data signal DQ. <5> The fifth data transmission line 101-5. The fifth data input / output circuit 215 can be based on the fifth data signal DQ. <5> The fifth internal data signal D5<1:m> is generated, and the fifth data signal DQ can be generated based on the fifth internal data signal D5<1:m>. <5> The fifth data input / output circuit 215 can receive the fifth data signal DQ during the write operation of the semiconductor die 200. <5> And it can be obtained from the fifth data signal DQ <5> Generate the fifth internal data signal D5<1:m>.The fifth data input / output circuit 215 can generate the fifth data signal DQ from the fifth internal data signal D5<1:m> during the read operation of the semiconductor die 200. <5> Furthermore, the fifth data signal DQ can be output via the fifth data pad DPx5. <5> The eighth data input / output circuit 218 can be coupled to the eighth data pad DPx8, and can also be coupled to transmit the eighth data signal DQ. <8> The eighth data transmission line 101-8. The eighth data input / output circuit 218 can be based on the eighth data signal DQ. <8> The eighth internal data signal D8<1:m> is generated, and the eighth data signal DQ can be generated based on the eighth internal data signal D8<1:m>. <8> The eighth data input / output circuit 218 can receive the eighth data signal DQ during the write operation of the semiconductor die 200. <8> And it can be obtained from the eighth data signal DQ <8> The eighth internal data signal D8<1:m> is generated. The eighth data input / output circuit 218 can generate the eighth data signal DQ from the eighth internal data signal D8<1:m> during the read operation of the semiconductor die 200. <8> Furthermore, the eighth data signal DQ can be output via the eighth data pad DPx8. <8> .

[0040] The first switching circuit 221 can couple the first data input / output circuit 211 to the first data pad DPx1 based on the enable signal ENx. The first switching circuit 221 can selectively couple the first data input / output circuit 211 to the first data pad DPx1 depending on whether the enable signal ENx is enabled. When the enable signal ENx is enabled, the first switching circuit 221 can electrically couple the first data input / output circuit 211 to the first data pad DPx1. When the enable signal ENx is disabled, the first switching circuit 221 can electrically isolate the first data input / output circuit 211 from the first data pad DPx1. The fourth switching circuit 224 can couple the fourth data input / output circuit 214 to the fourth data pad DPx4 based on the enable signal ENx. The fourth switching circuit 224 can selectively couple the fourth data input / output circuit 214 to the fourth data pad DPx4 depending on whether the enable signal ENx is enabled. When the enable signal ENx is enabled, the fourth switch circuit 224 can electrically couple the fourth data input / output circuit 214 to the fourth data pad DPx4. When the enable signal ENx is disabled, the fourth switch circuit 224 can electrically isolate the fourth data input / output circuit 214 from the fourth data pad DPx4. The fifth switch circuit 225 can couple the fifth data input / output circuit 215 to the fifth data pad DPx5 based on the enable signal ENx. The fifth switch circuit 225 can selectively couple the fifth data input / output circuit 215 to the fifth data pad DPx5 depending on whether the enable signal ENx is enabled. When the enable signal ENx is enabled, the fifth switch circuit 225 can electrically couple the fifth data input / output circuit 215 to the fifth data pad DPx5. When the enable signal ENx is disabled, the fifth switch circuit 225 can electrically isolate the fifth data input / output circuit 215 from the fifth data pad DPx5. The eighth switch circuit 228 can couple the eighth data input / output circuit 218 to the eighth data pad DPx8 based on the enable signal ENx. The eighth switch circuit 228 can selectively couple the eighth data input / output circuit 218 to the eighth data pad DPx8 depending on whether the enable signal ENx is enabled. When the enable signal ENx is enabled, the eighth switch circuit 228 can electrically couple the eighth data input / output circuit 218 to the eighth data pad DPx8. When the enable signal ENx is disabled, the eighth switch circuit 228 can electrically isolate the eighth data input / output circuit 218 from the eighth data pad DPx8.

[0041] The semiconductor die 200 may also include a command address control circuit 230. The command address control circuit 230 may be coupled to the command address pad CPx3 and the chip select pad CPx5, and may receive the command address signal CA<1:k> and the chip select signal CSx. The command address control circuit 230 may generate an enable signal ENx based on the command address signal CA<1:k> and the chip select signal CSx. When the chip select signal CSx is enabled, the command address control circuit 230 may decode the command address signal CA<1:k> to generate an internal command signal, and may generate the enable signal ENx from the internal command signal. When the chip select signal CSx is enabled and the command address signal CA<1:k> includes one of a write command and a read command, the command address control circuit 230 may enable the enable signal ENx. The semiconductor die 200 may perform a write operation based on the command address signal CA<1:k> including a write command, and may perform a read operation based on the command address signal CA<1:k> including a read command. During the write operation of the semiconductor die 200, the command address control circuit 230 can receive the first data signal DQ through the first data pads DPx1 to the eighth data pads DPx8. <1> Up to the eighth data signal DQ <8> Previously, the enable signal ENx was enabled, and the first data signal DQ could be received through the first data pad DPx1 to the eighth data pad DPx8. <1> Up to the eighth data signal DQ <8> After completion, the enable signal ENx is disabled. During the read operation of the semiconductor die 200, the command address control circuit 230 can output the first data signal DQ from the first data input / output circuit 211 to the eighth data input / output circuit 218. <1> Up to the eighth data signal DQ <8> Previously, the enable signal ENx was enabled, and the first data signal DQ could be output from the first data input / output circuit 211 to the eighth data input / output circuit 218. <1> Up to the eighth data signal DQ <8> After completion, the enable signal ENx is disabled. The command address control circuit 230 can also be coupled to the command clock pad CPx4, and can also receive the command clock signal CKT and the complementary command clock signal CKC through the command clock pad CPx4. The command address control circuit 230 can receive the command address signal CA<1:k> and the chip select signal CSx synchronously with the command clock signal CKT and the complementary command clock signal CKC. The command address control circuit 230 can use the command clock signal CKT and the complementary command clock signal CKC to generate the enable signal ENx from the internal command signals.

[0042] The semiconductor die 200 may further include a clock receiving circuit 240, a clock control circuit 250, and a gating transmission circuit 260. The clock receiving circuit 240 may be coupled to a data clock pad CPx1 and may receive a data clock signal WCKT and a complementary data clock signal WCKC through the data clock pad CPx1. The clock receiving circuit 240 may differentially amplify the data clock signal WCKT and the complementary data clock signal WCKC. The clock control circuit 250 may receive the data clock signal WCKT and the complementary data clock signal WCKC from the clock receiving circuit 240 and may generate multiple internal clock signals based on the data clock signal WCKT and the complementary data clock signal WCKC. These multiple internal clock signals may include a first internal clock signal ICK, a second internal clock signal QCK, a third internal clock signal IBCK, and a fourth internal clock signal QBCK. The first to fourth internal clock signals ICK, QCK, IBCK, and QBCK may have a 90-degree phase difference and may have a lower frequency than the data clock signal WCKT. For example, clock control circuit 250 can generate first to fourth internal clock signals ICK, QCK, IBCK, and QBCK by dividing the frequencies of data clock signal WCKT and complementary data clock signal WCKC. Gating transmission circuit 260 can receive the first to fourth internal clock signals ICK, QCK, IBCK, and QBCK, and can generate read strobe signal RDQST and complementary read strobe signal RDQSC based on these signals. Gating transmission circuit 260 can be coupled to read strobe pad CPx2, and can output read strobe signal RDQST and complementary read strobe signal RDQSC through read strobe pad CPx2. First data input / output circuits 211 to eighth data input / output circuits 218 can collectively receive the first to fourth internal clock signals ICK, QCK, IBCK, and QBCK. The first data input / output circuits 211 to the eighth data input / output circuits 218 can perform data input / output operations synchronously with the first to fourth internal clock signals ICK, QCK, IBCK, and QBCK. For example, during a write operation, the first data input / output circuits 211 to the eighth data input / output circuits 218 can receive the first data signal DQ synchronously with the first to fourth internal clock signals ICK, QCK, IBCK, and QBCK, respectively. <1> Up to the eighth data signal DQ <8> Furthermore, it can be synchronized with the first to fourth internal clock signals ICK, QCK, IBCK, and QBCK from the first data signal DQ. <1> Up to the eighth data signal DQ <8> The first internal data signal D1<1:m> to the eighth internal data signal D8<1:m> are generated respectively.During the read operation, the first data input / output circuit 211 to the eighth data input / output circuit 218 can synchronously generate the first data signal DQ from the first internal data signal D1<1:m> to the eighth internal data signal D8<1:m> from the first internal data signal D1<1:m> to the eighth internal data signal D8<1:m>, respectively, in accordance with the first to fourth internal clock signals ICK, QCK, IBCK and QBCK. <1> Up to the eighth data signal DQ <8> Furthermore, it can synchronously output the first data signal DQ with the first to fourth internal clock signals ICK, QCK, IBCK, and QBCK, respectively. <1> Up to the eighth data signal DQ <8> .

[0043] Figure 4 This is a diagram illustrating the configuration of a command address control circuit 230 according to an embodiment of the present disclosure. (See reference...) Figure 4 The command address control circuit 230 may include a command decoding circuit 310, a pulse generation circuit 320, and an enable signal generation circuit 330. The command decoding circuit 310 may receive a command address signal CA<1:k>, a chip select signal CSx, a command clock signal CKT, and a complementary command clock signal CKC. When the chip select signal CSx is enabled, the command decoding circuit 310 may generate an internal command signal based on the command address signal CA<1:k>. The internal command signal may include a write signal WT and a read signal RD. When the chip select signal CSx is disabled, the command decoding circuit 310 may not receive the command address signal CA<1:k>. The command decoding circuit 310 may receive the command address signal CA<1:k> by comparing the bits of the command address signal CA<1:k> with a reference voltage. The command decoding circuit 310 may latch the command address signal CA<1:k> synchronously with the command clock signal CKT and the complementary command clock signal CKC. The command decoding circuit 310 may decode the latched command address signal to generate the write signal WT and the read signal RD. When the command address signal CA<1:k> includes a write command, the command decoding circuit 310 can decode the latched command address signal to generate a write signal WT. When the command address signal CA<1:k> includes a read command, the command decoding circuit 310 can decode the latched command address signal to generate a read signal RD.

[0044] The pulse generation circuit 320 can receive the write signal WT, the read signal RD, the command clock signal CKT, and the complementary command clock signal CKC. Furthermore, the pulse generation circuit 320 can receive write delay information WL, read delay information RL, and burst length information BL. The write delay can be from... Figure 3The time delay between the time when the semiconductor die 200 receives the command address signal CA<1:k> including the write command and the time when the semiconductor die 200 receives the data DQ<1:8> through the data bus 101 is represented by the following data delay. The read delay can be the time delay between the time when the semiconductor die 200 receives the command address signal CA<1:k> including the read command and the time when the semiconductor die 200 outputs the data DQ<1:8> through the data bus 101. The pulse generation circuit 320 can generate a write enable signal WTEN from the write signal WT based on the write delay information WL and the burst length information BL, and can generate a read enable signal RDEN from the read signal RD based on the read delay information RL and the burst length information BL. The pulse generation circuit 320 can generate the write enable signal WTEN, the pulse width of which covers the time interval during which the data DQ<1:8> is transmitted through the data bus 101 during the write operation. The pulse generation circuit 320 can generate a write enable signal WTEN. The pulse width of the write enable signal WTEN is enabled before the time corresponding to the write delay information WL elapses from the write signal WT, and remains enabled for a period longer than the time corresponding to the burst length information BL. The pulse generation circuit 320 can generate the write enable signal WTEN synchronously with the command clock signal CKT and the complementary command clock signal CKC by delaying the write signal WT according to the write delay information WL and the burst length information BL. The pulse generation circuit 320 can also generate a read enable signal RDEN. The pulse width of the read enable signal RDEN covers the time interval during which data DQ<1:8> is transmitted through the data bus 101 during a read operation. The pulse generation circuit 320 can also generate a read enable signal RDEN. The pulse width of the read enable signal RDEN is enabled before the time corresponding to the read delay information RL elapses from the read signal RD, and remains enabled for a period longer than the time corresponding to the burst length information BL. The pulse generation circuit 320 can synchronously generate a read enable signal RDEN by delaying the read signal RD according to the read delay information RL and the burst length information BL, in conjunction with the command clock signal CKT and the complementary command clock signal CKC. For example, when the read delay information RL is 10, the burst length information BL is 16, and the frequency ratio of the command clock signal CKT to the data clock signal WCKT is 1:4, the pulse generation circuit 320 can enable the read enable signal RDEN for a period of 10tCK from the read signal RD, and maintain the enabled signal for a period longer than 4tCK. "tCK" can refer to the time corresponding to one period and / or cycle of the command clock signal CKT. In one embodiment, the frequency ratio of the command clock signal CKT to the data clock signal WCKT can be changed to 1:2, 1:8, etc., depending on the application.

[0045] The enable signal generation circuit 330 can receive a write enable signal WTEN and a read enable signal RDEN, and can generate an enable signal ENx based on the write enable signal WTEN and the read enable signal RDEN. When either the write enable signal WTEN or the read enable signal RDEN is enabled, the enable signal generation circuit 330 can enable the enable signal ENx. In one embodiment, the enable signal generation circuit 330 may include an OR gate configured to receive the write enable signal WTEN and the read enable signal RDEN and output the enable signal ENx.

[0046] Figure 5 This is a diagram illustrating the operation of a semiconductor package 100 according to an embodiment of the present disclosure. (See reference...) Figures 1 to 5The operation of a semiconductor package 100 according to an embodiment of the present disclosure will now be described. Before a first time t1, when no command address signal is transmitted from an external device to the semiconductor package 100, the first to fourth enable signals EN1, EN2, EN3, and EN4 can all be kept in an disabled state. The first to fourth switch circuit blocks 123, 133, 143, and 153 can electrically isolate the first to fourth data input / output circuit blocks 122, 132, 142, and 152 from the first to fourth data pads 121, 131, 141, and 151, respectively. At the first time t1, the external device can provide the semiconductor package 100 with a first chip select signal CS1 and a command address signal CA<1:k> including a write command WT CMD, synchronously with the command clock signal CKT. The first chip select signal CS1 can be enabled, and the second to fourth chip select signals CS2, CS3, and CS4 can all be disabled. The first semiconductor die 120 can perform a write operation based on the first chip select signal CS1 and the command address signal CA<1:k>. At a second time t2, an external device can synchronously provide a second chip select signal CS2 and a command address signal CA<1:k> including a read command RD CMD to the semiconductor package 100, in sync with the command clock signal CKT. The second chip select signal CS2 can be enabled, and the first chip select signal CS1, the third chip select signal CS3, and the fourth chip select signal CS4 can all be disabled. The second semiconductor die 130 can perform a read operation based on the second chip select signal CS2 and the command address signal CA<1:k>. t3 can be the time elapsed before the duration corresponding to the write delay information WL from the time the command address signal CA<1:k> including the write command WT CMD is received from the first semiconductor die 120. At a third time t3, the command address control circuit 230 provided in the first semiconductor die 120 can enable a first enable signal EN1. When the first enable signal EN1 is enabled, the first switch circuit block 123 can couple the first data input / output circuit block 122 to the first data pad 121. The second to fourth data input / output circuit blocks 132, 142, and 152 can remain electrically isolated from the second to fourth data pads 131, 141, and 151, allowing external devices and the data bus 101 to only bear the load corresponding to the first data input / output circuit block 122. When the duration corresponding to the write delay information WL has elapsed, the external device can transmit data DQ<1:n> synchronously with the data clock signal WCKT via the data bus 101. Data DQ<1:n> can be transmitted to the semiconductor package 100 within the duration corresponding to the burst length information BL.After semiconductor package 100 completes receiving data DQ<1:n>, at a fourth time t4, the first enable signal EN1 can be disabled, and the first switch circuit block 123 can electrically isolate the first data input / output circuit block 122 from the first data pad 121. t5 can be the time elapsed before the time point from when the command address signal CA<1:k> including the read command RD CMD is received from the second semiconductor die 130, before the duration corresponding to the read delay information RL. At a fifth time t5, the command address control circuit 230 provided in the second semiconductor die 130 enables the second enable signal EN2. When the second enable signal EN2 is enabled, the second switch circuit block 133 can couple the second data input / output circuit block 132 to the second data pad 131. Because the first data input / output circuit block 122, the third data input / output circuit block 142, and the fourth data input / output circuit block 152 are electrically isolated from the first data pad 121, the third data pad 141, and the fourth data pad, respectively, the external device and the data bus 101 can only bear the load corresponding to the second data input / output circuit block 132. When the duration corresponding to the read delay information RL has elapsed, the second semiconductor die 130 can transmit data DQ<1:n> to the external device synchronously with the data clock signal WCKT via the data bus 101. Data DQ<1:n> can be output from the semiconductor package 100 within the duration corresponding to the burst length information BL. After the semiconductor package 100 completes the transmission of data DQ<1:n>, at the sixth time t6, the second enable signal EN2 can be disabled, and the second switch circuit block 133 can electrically isolate the second data input / output circuit block 132 from the second data pad 131. In one embodiment, semiconductor package 100 may include a plurality of semiconductor dies commonly coupled to data bus 101 to increase the capacity of semiconductor package 100, while only one semiconductor die performing a write operation or read operation is coupled to data bus 101, thereby reducing the load on data bus 101 and mitigating and / or preventing a reduction in data transfer speed.

[0047] Figure 6 This is a diagram illustrating the configuration of a semiconductor package 400 according to an embodiment of the present disclosure. (See reference...) Figure 6 Semiconductor package 400 may include package substrate 410 and multiple dies. Figure 6 In the semiconductor package 400, a first semiconductor die 420, a second semiconductor die 430, a third semiconductor die 440, a fourth semiconductor die 450, a fifth semiconductor die 460, a sixth semiconductor die 470, a seventh semiconductor die 480, and an eighth semiconductor die 490 may be included. Although in Figure 6Semiconductor package 400 is shown as including eight semiconductor dies, but this is not intended to limit the number of semiconductor dies included in semiconductor package 400. Semiconductor package 400 may include twelve, sixteen or more semiconductor dies. First semiconductor dies 420 to eighth semiconductor dies 490 may be disposed on package substrate 410 and may be packaged into a single package. First semiconductor die 420 may be disposed on package substrate 410. For example, first semiconductor die 420 may be disposed at the center portion of package substrate 410 in the x-axis and z-axis directions. First semiconductor die 420 may be bonded to package substrate 410 using adhesive or die attach film (DAF). Second semiconductor die 430 may be disposed on first semiconductor die 420 in the y-axis direction. Third semiconductor die 440 may be disposed on second semiconductor die 430 in the y-axis direction. Fourth semiconductor die 450 may be disposed on third semiconductor die 440 in the y-axis direction. Fifth semiconductor die 460 may be disposed on fourth semiconductor die 450 in the y-axis direction. A sixth semiconductor die 470 may be disposed on the fifth semiconductor die 460 in the y-axis direction. A seventh semiconductor die 480 may be disposed on the sixth semiconductor die 470 in the y-axis direction. An eighth semiconductor die 490 may be disposed on the seventh semiconductor die 480 in the y-axis direction. Second semiconductor dies 430 to eighth semiconductor dies 490 may be bonded to first semiconductor dies 420 to seventh semiconductor dies 480 respectively using die attach films. First semiconductor dies 420 to eighth semiconductor dies 490 may each include data pads on their first side. The data pad of the first semiconductor die 420 may be referred to as the first data pad 421. The data pad of the second semiconductor die 430 may be referred to as the second data pad 431. The data pad of the third semiconductor die 440 may be referred to as the third data pad 441. The data pad of the fourth semiconductor die 450 may be referred to as the fourth data pad 451. The data pad of the fifth semiconductor die 460 may be referred to as the fifth data pad 461. The data pad of the sixth semiconductor die 470 may be referred to as the sixth data pad 471. The data pad of the seventh semiconductor die 480 may be referred to as the seventh data pad 481. The data pad of the eighth semiconductor die 490 may be referred to as the eighth data pad 491. The first semiconductor dies 420 to the fourth semiconductor dies 450 may be arranged in a stepped shape, such that the first data pads 421 to the fourth data pads 451 are exposed. Similarly, the fifth semiconductor dies 460 to the eighth semiconductor dies 490 may also be arranged in a stepped shape, such that the fifth data pads 461 to the eighth data pads 491 are exposed. For example, the second semiconductor die 430 may be disposed on the first semiconductor die 420 and simultaneously in the first direction of the x-axis (in Figure 6Offset in the direction to the left along the x-axis. The third semiconductor die 440 may be disposed on the second semiconductor die 430 while being offset from the second semiconductor die 430 in the first direction. The fourth semiconductor die 450 may be disposed on the third semiconductor die 440 while being offset from the third semiconductor die 440 in the first direction. In one embodiment, in order to reduce the size of the semiconductor package 400, the fifth to eighth semiconductor dies 460 may be disposed with a 180-degree rotation relative to the first to fourth semiconductor dies 450, and the fifth to eighth semiconductor dies 460 may be disposed in a second direction opposite to the first direction (in the direction to the left along the x-axis). Figure 6 Offset in the direction to the right along the x-axis. Therefore, the first data pads 421 to the fourth data pads 451 can be exposed in the second direction, while the fifth data pads 461 to the eighth data pads 491 can be exposed in the first direction. The fifth semiconductor die 460 can be disposed on the fourth semiconductor die 450 while being offset from the fourth semiconductor die 450 in the first direction. The sixth semiconductor die 470 can be disposed on the fifth semiconductor die 460 while being offset from the fifth semiconductor die 460 in the second direction. The seventh semiconductor die 480 can be disposed on the sixth semiconductor die 470 while being offset from the sixth semiconductor die 470 in the second direction. The eighth semiconductor die 490 can be disposed on the seventh semiconductor die 480 while being offset from the seventh semiconductor die 480 in the second direction.

[0048] The package substrate 410 can be coupled to an external device via a first data bus 401 and a second data bus 402. The package substrate 410 can also be coupled to the first data bus 401 and the second data bus 402 via package balls 411. First data DQ<1:n> can be transmitted via the first data bus 401. Second data DQ<n+1:2n> Data can be transmitted via the second data bus 402. The package substrate 410 may include a first substrate data pad 412 and a second substrate data pad 413. The first substrate data pad 412 may be coupled to the first data bus 401, and the second substrate data pad 413 may be coupled to the second data bus 402. The first substrate data pad 412 may be disposed at a position spaced apart from the first semiconductor die 420 in a second direction. The second substrate data pad 413 may be disposed at a position spaced apart from the first semiconductor die 420 in a first direction. The number of first substrate data pads 412 may be substantially equal to the number of data transmission lines included in the first data bus 401. The number of second substrate data pads 413 may be substantially equal to the number of data transmission lines included in the second data bus 402. The number of data transmission lines included in the first data bus 401 and the second data bus 402, as well as the number of first substrate data pads 412 and second substrate data pads 413, may be equal to each other. The first data DQ<1:n> and the second data DQ transmitted via the first data bus 401 and the second data bus 402 are...<n+1:2n> The number of data signals included in each of the components can be n, and the number of first substrate data pads 412 and second substrate data pads 413 can both be n. Here, n can be a multiple of 4 or a multiple of 6. The first substrate data pads 412 and second substrate data pads 413 can be coupled to the first data bus 401 and the second data bus 402 respectively through signal paths 414 and 415 formed in the package substrate 410 and package ball 411.

[0049] First semiconductor dies 420 to fourth semiconductor dies 450 can share a first data bus 401. First data pad 421, second data pad 431, third data pad 441, and fourth data pad 451 can be jointly coupled to a first substrate data pad 412. Each of the first to fourth data pads 421, 431, 441, and 451 can include n data pads. First data pad 421 can be coupled to the first substrate data pad 412 via a first bonding wire W21. Second data pad 431 can be coupled to the first data pad 421 via a second bonding wire W22. Third data pad 441 can be coupled to the second data pad 431 via a third bonding wire W23. Fourth data pad 451 can be coupled to the third data pad 441 via a fourth bonding wire W24. The number of first bonding wires W21 to fourth bonding wires W24 can all be n. Fifth semiconductor dies 460 to eighth semiconductor dies 490 can share a second data bus 402. The fifth data pad 461, the sixth data pad 471, the seventh data pad 481, and the eighth data pad 491 can be jointly coupled to the second substrate data pad 413. The fifth to eighth data pads 461, 471, 481, and 491 can each include n data pads. The fifth data pad 461 can be coupled to the second substrate data pad 413 via the fifth bonding wire W25. The sixth data pad 471 can be coupled to the fifth data pad 461 via the sixth bonding wire W26. The seventh data pad 481 can be coupled to the sixth data pad 471 via the seventh bonding wire W27. The eighth data pad 491 can be coupled to the seventh data pad 481 via the eighth bonding wire W28. The number of the fifth to eighth bonding wires W25 can all be n.

[0050] The internal circuitry of the first semiconductor die 420 can be selectively coupled to the first data pad 421 based on the first enable signal EN1. The internal circuitry of the second semiconductor die 430 can be selectively coupled to the second data pad 431 based on the second enable signal EN2. The internal circuitry of the third semiconductor die 440 can be selectively coupled to the third data pad 441 based on the third enable signal EN3. The internal circuitry of the fourth semiconductor die 450 can be selectively coupled to the fourth data pad 451 based on the fourth enable signal EN4. The internal circuitry of the fifth semiconductor die 460 can be selectively coupled to the fifth data pad 461 based on the fifth enable signal EN5. The internal circuitry of the sixth semiconductor die 470 can be selectively coupled to the sixth data pad 471 based on the sixth enable signal EN6. The internal circuitry of the seventh semiconductor die 480 can be selectively coupled to the seventh data pad 481 based on the seventh enable signal EN7. The internal circuitry of the eighth semiconductor die 490 can be selectively coupled to the eighth data pad 491 based on the eighth enable signal EN8. An external device can provide a first chip select signal CS1, a second chip select signal CS2, a third chip select signal CS3, and a fourth chip select signal CS4 to the semiconductor package 400. The first semiconductor die 420 and the fifth semiconductor die 460 can be accessed by the first chip select signal CS1, and the first enable signal EN1 and the fifth enable signal EN5 can be generated based on the first chip select signal CS1. The second semiconductor die 430 and the sixth semiconductor die 470 can be accessed by the second chip select signal CS2, and the second enable signal EN2 and the sixth enable signal EN6 can be generated based on the second chip select signal CS2. The third semiconductor die 440 and the seventh semiconductor die 480 can be accessed by the third chip select signal CS3, and the third enable signal EN3 and the seventh enable signal EN7 can be generated based on the third chip select signal CS3. The fourth semiconductor die 450 and the eighth semiconductor die 490 can be accessed by the fourth chip select signal CS4, and the fourth enable signal EN4 and the eighth enable signal EN8 can be generated based on the fourth chip select signal CS4. The internal circuits of the first semiconductor die 420 to the fourth semiconductor die 450 can be selectively coupled to the first data pad 421 to the fourth data pad 451 based on the first enable signal EN1 to the fourth enable signal EN4 or the first chip select signal CS1 to the fourth chip select signal CS4, respectively. The internal circuits of the fifth semiconductor die 460 to the eighth semiconductor die 490 can be selectively coupled to the fifth data pad 461 to the eighth data pad 491 based on the fifth enable signal EN5 to the eighth enable signal EN8 or the first chip select signal CS1 to the fourth chip select signal CS4, respectively.An external device can enable one of the first chip select signals CS1 to the fourth chip select signal CS4 to access one of the first semiconductor dies 420 to the fourth semiconductor dies 450, along with one of the fifth semiconductor dies 460 to the eighth semiconductor dies 490. For example, when the external device accesses the first semiconductor die 420 and the fifth semiconductor die 460, the first chip select signal CS1 can be enabled, and the first enable signal EN1 and the fifth enable signal EN5 can be enabled based on the first chip select signal CS1, while the second chip select signals CS2 to the fourth chip select signal CS4, the second enable signals EN2 to the fourth enable signals EN4, and the sixth enable signal EN6 to the eighth enable signal EN8 can be disabled. Therefore, the internal circuitry of the first semiconductor die 420 can be coupled to the first data pad 421, while the internal circuitry of the second semiconductor dies 430 to the fourth semiconductor dies 450 can be electrically isolated from the second data pad 431 to the fourth data pad 451. Although the first data bus 401 is commonly coupled to the first data pads 421 through 451, it can be coupled to the load of the internal circuitry of the first semiconductor die 420, but not necessarily to the load of the internal circuitry of the second semiconductor dies 430 through 450. The internal circuitry of the fifth semiconductor die 460 can be coupled to the fifth data pad 461, while the internal circuitry of the sixth semiconductor dies 470 through 490 can be electrically isolated from the sixth data pads 471 through 491. Although the second data bus 402 is commonly coupled to the fifth data pads 461 through 491, it can be coupled to the load of the internal circuitry of the fifth semiconductor die 460, but not necessarily to the load of the internal circuitry of the sixth semiconductor dies 470 through 490. Because, in one embodiment, the external device and / or the first data bus 401 and the second data bus 402 can each bear the load of only one semiconductor die, the data transmission speed of the first data bus 401 and the second data bus 402 can not be reduced, and the signal integrity (SI) of the data transmitted through the first data bus 401 and the second data bus 402 can be improved. Furthermore, in one embodiment, because the semiconductor package 400 can be coupled to more data buses, the data bandwidth between the external device and the semiconductor package 400 can be increased.

[0051] The first semiconductor die 420 to the eighth semiconductor die 490 may have substantially the same structure and may include the same... Figure 1The first semiconductor die 120 to the fourth semiconductor die 150 shown in the figure have substantially the same components. Repeated descriptions of the same components will be omitted. The first semiconductor die 420 may include a first data pad 421, a first data input / output circuit block 422, and a first switch circuit block 423. The first data input / output circuit block 422 may receive first data DQ<1:n> during a write operation and may output first data DQ<1:n> during a read operation. The first switch circuit block 423 may selectively couple the first data pad 421 to the first data input / output circuit block 422 based on a first enable signal EN1. The first semiconductor die 420 may also include command address control circuitry configured to generate the first enable signal EN1 based on a first chip select signal CS1 and a command address signal. The second semiconductor die 430 may include a second data pad 431, a second data input / output circuit block 432, and a second switch circuit block 433. The second data input / output circuit block 432 can receive first data DQ<1:n> during a write operation and can output first data DQ<1:n> during a read operation. The second switch circuit block 433 can selectively couple the second data pad 431 to the second data input / output circuit block 432 based on a second enable signal EN2. The second semiconductor die 430 may also include a command address control circuit configured to generate the second enable signal EN2 based on a second chip select signal CS2 and a command address signal. The third semiconductor die 440 may include a third data pad 441, a third data input / output circuit block 442, and a third switch circuit block 443. The third data input / output circuit block 442 can receive first data DQ<1:n> during a write operation and can output first data DQ<1:n> during a read operation. The third switch circuit block 443 can selectively couple the third data pad 441 to the third data input / output circuit block 442 based on a third enable signal EN3. The third semiconductor die 440 may further include command address control circuitry configured to generate a third enable signal EN3 based on a third chip select signal CS3 and a command address signal. The fourth semiconductor die 450 may include a fourth data pad 451, a fourth data input / output circuit block 452, and a fourth switch circuit block 453. The fourth data input / output circuit block 452 may receive first data DQ<1:n> during a write operation and may output first data DQ<1:n> during a read operation. The fourth switch circuit block 453 may selectively couple the fourth data pad 451 to the fourth data input / output circuit block 452 based on a fourth enable signal EN4. The fourth semiconductor die 450 may further include command address control circuitry configured to generate a fourth enable signal EN4 based on a fourth chip select signal CS4 and a command address signal.

[0052] The fifth semiconductor die 460 may include a fifth data pad 461, a fifth data input / output circuit block 462, and a fifth switch circuit block 463. The fifth data input / output circuit block 462 can receive second data DQ during a write operation.<n+1:2n> Furthermore, it can output a second data DQ during the read operation.<n+1:2n> The fifth switch circuit block 463 can selectively couple the fifth data pad 461 to the fifth data input / output circuit block 462 based on the fifth enable signal EN5. The fifth semiconductor die 460 may also include a command address control circuit configured to generate the fifth enable signal EN5 based on the first chip select signal CS1 and the command address signal. The sixth semiconductor die 470 may include the sixth data pad 471, the sixth data input / output circuit block 472, and the sixth switch circuit block 473. The sixth data input / output circuit block 472 can receive the second data DQ during a write operation.<n+1:2n> Furthermore, it can output a second data DQ during the read operation.<n+1:2n> The sixth switch circuit block 473 can selectively couple the sixth data pad 471 to the sixth data input / output circuit block 472 based on the sixth enable signal EN6. The sixth semiconductor die 470 may also include a command address control circuit configured to generate the sixth enable signal EN6 based on the second chip select signal CS2 and the command address signal. The seventh semiconductor die 480 may include a seventh data pad 481, a seventh data input / output circuit block 482, and a seventh switch circuit block 483. The seventh data input / output circuit block 482 can receive the second data DQ during a write operation.<n+1:2n> Furthermore, it can output a second data DQ during the read operation.<n+1:2n> The seventh switch circuit block 483 can selectively couple the seventh data pad 481 to the seventh data input / output circuit block 482 based on the seventh enable signal EN7. The seventh semiconductor die 480 may also include a command address control circuit configured to generate the seventh enable signal EN7 based on the third chip select signal CS3 and the command address signal. The eighth semiconductor die 490 may include an eighth data pad 491, an eighth data input / output circuit block 492, and an eighth switch circuit block 493. The eighth data input / output circuit block 492 can receive second data DQ during a write operation.<n+1:2n> Furthermore, it can output a second data DQ during the read operation.<n+1:2n> The eighth switch circuit block 493 can selectively couple the eighth data pad 491 to the eighth data input / output circuit block 492 based on the eighth enable signal EN8. The eighth semiconductor die 490 may also include a command address control circuit configured to generate the eighth enable signal EN8 based on the fourth chip select signal CS4 and the command address signal.

[0053] The concept has been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions can be made without departing from the scope and concept of this disclosure. The embodiments disclosed in this specification should be considered illustrative rather than restrictive. Therefore, the scope of this disclosure is not limited to the description provided. All variations within the meaning and equivalent scope of the claims are included within its scope.

Claims

1. A semiconductor die, comprising: A first data pad is coupled to a first data transmission line that transmits a first data signal; The second data pad is coupled to the second data transmission line that transmits the second data signal; A first data input / output circuit, wherein: during a read operation, the first data signal is generated based on a first internal data signal, and during a write operation, the first internal data signal is generated based on the first data signal, wherein input / output represents input and output; A second data input / output circuit, wherein: during the read operation, a second data signal is generated based on a second internal data signal, and during the write operation, a second internal data signal is generated based on the second data signal; A first switching circuit, wherein: based on an enable signal, the first data pad is electrically coupled to the first data input / output circuit; and The second switching circuit electrically couples the second data pad to the second data input / output circuit based on the enable signal.

2. The semiconductor die according to claim 1 further includes a command address control circuit, wherein the command address control circuit generates the enable signal based on the command address signal and the chip selection signal.

3. The semiconductor die according to claim 2, wherein, The command address control circuit includes: The command decoding circuit decodes the command address signal to generate a write signal and a read signal when the chip selection signal is enabled. A pulse generation circuit, comprising: generating a write enable signal from the write signal based on write delay information and burst length information; and generating a read enable signal from the read signal based on read delay information and the burst length information; and An enable signal generating circuit that enables the enable signal when either the write enable signal or the read enable signal is enabled.

4. The semiconductor die according to claim 1 further includes a clock control circuit, wherein the clock control circuit receives a data clock signal and generates a plurality of internal clock signals based on the data clock signal. in, The first data input / output circuit generates the first data signal from the first internal data signal or generates the first internal data signal from the first data signal in sync with the plurality of internal clock signals, and the second data input / output circuit generates the second data signal from the second internal data signal or generates the second internal data signal from the second data signal in sync with the plurality of internal clock signals.

5. The semiconductor die according to claim 4 further includes a gating transmission circuit, wherein the gating transmission circuit generates a read gating signal based on the plurality of internal clock signals.

6. A semiconductor package, comprising: A packaging substrate having substrate data pads coupled to a data bus for transmitting data. A first semiconductor die is disposed on the packaging substrate; as well as A second semiconductor die is disposed on the first semiconductor die. The first semiconductor die includes: A first data pad, which is coupled to the substrate data pad; A first data input / output circuit block, wherein: during a write operation, first internal data is generated based on the data, and during a read operation, the data is generated based on the first internal data, wherein input / output represents input and output; and The first switching circuit block selectively couples the first data pad to the first data input / output circuit block based on a first chip select signal, and The second semiconductor die includes: The second data pad is coupled to the substrate data pad; A second data input / output circuit block, wherein: during a write operation, second internal data is generated based on the data, and during a read operation, the data is generated based on the second internal data; and The second switching circuit block selectively couples the second data pad to the second data input / output circuit block based on the second chip selection signal.

7. The semiconductor package according to claim 6, wherein, The packaging substrate is coupled to an external device via the data bus.

8. The semiconductor package according to claim 6, wherein, The first data pads are respectively coupled to the substrate data pads via first bonding wires, and the second data pads are respectively coupled to the first data pads via second bonding wires.

9. The semiconductor package according to claim 6, wherein, The first semiconductor die further includes a command address control circuit, which generates a first enable signal based on a command address signal and the first chip selection signal, and the first switch circuit block electrically couples the first data pad to the first data input / output circuit block based on the first enable signal.

10. The semiconductor package according to claim 9, wherein, The command address control circuit includes: The command decoding circuit decodes the command address signal to generate a write signal and a read signal when the first chip select signal is enabled. A pulse generation circuit, comprising: generating a write enable signal from the write signal based on write delay information and burst length information, and generating a read enable signal from the read signal based on read delay information and the burst length information; and An enable signal generating circuit that enables the first enable signal when either the write enable signal or the read enable signal is enabled.

11. The semiconductor package according to claim 6, wherein, The second semiconductor die also includes a command address control circuit, which generates a second enable signal based on a command address signal and a second chip selection signal, and the second switch circuit block electrically couples the second data pad to the second data input / output circuit block based on the second enable signal.

12. The semiconductor package of claim 11, wherein, The command address control circuit includes: The command decoding circuit decodes the command address signal to generate a write signal and a read signal when the second chip selection signal is enabled. A pulse generation circuit, comprising: generating a write enable signal from the write signal based on write delay information and burst length information, and generating a read enable signal from the read signal based on read delay information and the burst length information; and An enable signal generating circuit that enables the second enable signal when either the write enable signal or the read enable signal is enabled.

13. A semiconductor package, comprising: A packaging substrate, including substrate data pads coupled to a data bus for transmitting data; A first semiconductor die is disposed on the packaging substrate; as well as A second semiconductor die is disposed on the first semiconductor die. Wherein, the first data pad of the first semiconductor die and the second data pad of the second semiconductor die are jointly coupled to the data pad of the substrate, and Wherein, the first data pad is selectively coupled to the data input / output circuit block of the first semiconductor die based on a first enable signal, and the second data pad is selectively coupled to the data input / output circuit block of the second semiconductor die based on a second enable signal, wherein input / output means input and output.

14. The semiconductor package of claim 13, wherein, During a write operation on the first semiconductor die, the first enable signal is enabled before the data is received through the first data pad and disabled after the data is received through the first data pad. During a read operation on the first semiconductor die, the first enable signal is enabled before the data is output from the data input / output circuit block and disabled after the data is output from the data input / output circuit block.

15. The semiconductor package according to claim 13, wherein, The first semiconductor die further includes a command address control circuit, which generates the first enable signal based on the first chip selection signal and the command address signal.

16. The semiconductor package of claim 15, wherein, The command address control circuit includes: The command decoding circuit decodes the command address signal to generate a write signal and a read signal when the first chip select signal is enabled. A pulse generation circuit, comprising: generating a write enable signal from the write signal based on write delay information and burst length information, and generating a read enable signal from the read signal based on read delay information and the burst length information; and An enable signal generating circuit that enables the first enable signal when either the write enable signal or the read enable signal is enabled.

17. The semiconductor package of claim 13, wherein, During the write operation of the second semiconductor die, the second enable signal is enabled before the data is transmitted through the second data pad and disabled after the data transmission through the second data pad is completed. During the read operation of the second semiconductor die, the second enable signal is enabled before the data is output from the data input / output circuit block and disabled after the data is output from the data input / output circuit block is completed.

18. The semiconductor package of claim 13, wherein, The second semiconductor die also includes a command address control circuit, which generates the second enable signal based on the second chip selection signal and the command address signal.

19. The semiconductor package of claim 18, wherein, The command address control circuit includes: The command decoding circuit decodes the command address signal to generate a write signal and a read signal when the second chip selection signal is enabled. A pulse generation circuit, comprising: generating a write enable signal from the write signal based on write delay information and burst length information, and generating a read enable signal from the read signal based on read delay information and the burst length information; and An enable signal generating circuit that enables the second enable signal when either the write enable signal or the read enable signal is enabled.

20. A semiconductor package, comprising: The packaging substrate includes a first substrate data pad coupled to a first data bus and a second substrate data pad coupled to a second data bus. A first semiconductor die is disposed on the packaging substrate; A second semiconductor die is disposed on the first semiconductor die; A third semiconductor die is disposed on the second semiconductor die; as well as A fourth semiconductor die is disposed on the third semiconductor die. Specifically, the first data pad of the first semiconductor die and the second data pad of the second semiconductor die are jointly coupled to the first substrate data pad, and the third data pad of the third semiconductor die and the fourth data pad of the fourth semiconductor die are jointly coupled to the second substrate data pad. Specifically, when the first chip selection signal is enabled, the data input / output circuit block of the first semiconductor die is electrically coupled to the first data pad, and the data input / output circuit block of the third semiconductor die is electrically coupled to the third data pad, wherein input / output represents input and output, and Specifically, when the second chip selection signal is enabled, the data input / output circuit block of the second semiconductor die is electrically coupled to the second data pad, and the data input / output circuit block of the fourth semiconductor die is electrically coupled to the fourth data pad.

21. The semiconductor package of claim 20, wherein, The first data pad is coupled to the first substrate data pad via a first bonding wire, the second data pad is coupled to the first data pad via a second bonding wire, the third data pad is coupled to the second substrate data pad via a third bonding wire, and the fourth data pad is coupled to the third data pad via a fourth bonding wire.

22. The semiconductor package of claim 20, wherein, The first semiconductor die further includes: A first command address control circuit, wherein: a first enable signal is generated based on the first chip selection signal and the command address signal; and The first switching circuit block electrically couples the data input / output circuit block of the first semiconductor die to the first data pad based on the first enable signal.

23. The semiconductor package of claim 22, wherein, The second semiconductor die also includes: The second command address control circuit, wherein: a second enable signal is generated based on the second chip selection signal and the command address signal; and The second switching circuit block electrically couples the data input / output circuit block of the second semiconductor die to the second data pad based on the second enable signal.

24. The semiconductor package of claim 22, wherein, The third semiconductor die also includes: The third command address control circuit, which: generates a third enable signal based on the first chip selection signal and the command address signal; and The third switching circuit block electrically couples the data input / output circuit block of the third semiconductor die to the third data pad based on the third enable signal.

25. The semiconductor package of claim 22, wherein, The fourth semiconductor die also includes: The fourth command address control circuit generates a fourth enable signal based on the second chip selection signal and the command address signal; and The fourth switching circuit block electrically couples the data input / output circuit block of the fourth semiconductor die to the fourth data pad based on the fourth enable signal.

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