Triode structure and method of manufacturing the same

Abstract

This invention provides a transistor structure and its fabrication method. The transistor structure includes a substrate with a base well region and a collector well region. The base well region contains a heavily doped emitter region and a heavily doped base region, and the collector well region contains a heavily doped collector region. The bottom surface of the base well region is lower than the bottom surface of a first shallow trench isolation structure, and the bottom surface of the collector well region is also lower than the bottom surface of the first shallow trench isolation structure, thus isolating the base well region from the collector well region. A second shallow trench isolation structure is located within the base well region, and the bottom surface of the second shallow trench isolation structure is flush with the bottom surface of the first shallow trench isolation structure. The heavily doped emitter region and the heavily doped base region are located on both sides of the second shallow trench isolation structure. A gradient region includes a plurality of gradient units arranged along a first direction. The gradient region is located on the bottom surface of the second shallow trench isolation structure, and the doping type of the gradient units is opposite to that of the base well region. This reduces the majority carrier doping concentration of the base well region and simplifies the traditional process of gradually changing the base region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, specifically to a transistor structure and its fabrication method. Background Technology

[0002] In modern analog circuit design, high current gain can reduce drive requirements, simplify the front-end circuit, and improve voltage amplification capability. This is usually achieved by creating a gradually varying base region through two or more ion implantations with different energies and doses in the base region to improve current gain. However, this approach often requires multiple ion implantation processes, which can lead to significant lattice damage and may introduce a large number of impurities, negatively impacting the improvement of transistor current gain. Summary of the Invention

[0003] The technical problem solved by this invention is that in order to improve the current gain, existing transistor structures form a gradually changing base region in the substrate through multiple ion implantations. However, this process is prone to introducing a large number of impurities and is complicated to operate, which is not conducive to improving the current gain.

[0004] To solve the above-mentioned technical problems, the present invention provides a transistor structure and its fabrication method. The transistor structure includes: a substrate having adjacent and spaced-apart base well regions and collector well regions within the substrate; the base well regions having independent emitter heavily doped regions and base heavily doped regions; the collector well region having a collector heavily doped region; and the base heavily doped region located between the emitter heavily doped region and the collector heavily doped region. A first shallow trench isolation structure is located within the substrate between the base well regions and the collector well regions. The bottom surface of the base well regions is lower than the bottom surface of the first shallow trench isolation structure, and the bottom surface of the collector well regions is lower than the bottom surface of the first shallow trench isolation structure, thereby separating the base well regions from the collector well regions. The base well region is isolated; the second shallow trench isolation structure is located within the base well region, and the bottom surface of the second shallow trench isolation structure is flush with the bottom surface of the first shallow trench isolation structure. The emitter heavily doped region and the base heavily doped region are located on both sides of the second shallow trench isolation structure, respectively. The gradient region is located within the base well region and on the bottom surface of the second shallow trench isolation structure. The gradient region includes several gradient units arranged along a first direction. Along the first direction, the width of the gradient units gradually increases. The doping type of the gradient units is opposite to that of the base well region, and the doping type of the gradient units is the same as that of the collector well region. The first direction is the direction in which minority carriers in the base well region move from the emitter heavily doped region to the base heavily doped region.

[0005] Optionally, the gradient units are arranged at non-equal intervals, and in the first direction, the spacing width between each gradient unit increases sequentially.

[0006] Optionally, adjacent gradient units have a first width and a second width, respectively, and the spacing between the adjacent gradient units is a third width, wherein the first width is greater than the second width and the third width is equal to the first width.

[0007] Optionally, the emitter heavily doped region is located within the substrate, and along the direction of the substrate surface, the base heavily doped region surrounds the emitter heavily doped region. Adjacent graded units are separated by a portion of the base well region, and the graded region is located between the base heavily doped region and the emitter heavily doped region.

[0008] Optionally, the projection of the gradient unit onto the substrate is a rectangular ring, with the rectangular ring sequentially nested around the heavily doped emitter region, with the same center.

[0009] Optionally, the substrate surface has a rectangular area, and the projection of the gradient unit within the rectangular area is a number of spaced strips. The strips are parallel to the four sides of the rectangular area, and the strips are sequentially nested around the heavily doped emitter region with the same center.

[0010] Optionally, the transistor structure also includes an interlayer dielectric layer located on the surface of the heavily doped emitter region, the heavily doped base region, and the heavily doped collector region. The interlayer dielectric layer has contact holes, and both the surface of the interlayer dielectric layer and the contact holes have metal layers to form the first metal interconnect of the transistor structure.

[0011] This invention also provides a method for fabricating a transistor structure, comprising: providing a substrate; forming a first shallow trench structure and a second shallow trench structure within the substrate, wherein the bottom surface of the second shallow trench isolation structure is flush with the bottom surface of the first shallow trench isolation structure; forming a base well region within the substrate, wherein the bottom surface of the base well region is lower than the bottom surface of the first shallow trench isolation structure, and the second shallow trench isolation structure is located within the base well region; forming a collector well region within the substrate, wherein the first shallow trench isolation structure is formed between the base well region and the collector well region, and the bottom surface of the collector well region is lower than the bottom surface of the first shallow trench isolation structure, thereby isolating the base well region from the collector well region; forming a plurality of gradient units arranged along a first direction within the base well region to form a gradient region, and the gradient unit is further defined by the gradient unit being formed within the base well region. The gradient region is formed on the bottom surface of the second shallow trench isolation structure. The gradient region includes several gradient units arranged along the first direction, and the width of the gradient units gradually increases along the first direction. The doping type of the gradient units is opposite to that of the base well region, and the doping type of the gradient units is the same as that of the collector well region. After the base well region, collector well region, and gradient region are formed, the transistor structure is annealed. After the annealing process, an independent emitter heavily doped region and a base heavily doped region are formed in the base well region. The first direction is the direction in which minority carriers in the base well region move from the emitter heavily doped region to the base heavily doped region. After the annealing process, a collector heavily doped region is formed in the collector well region, and the base heavily doped region is located between the emitter heavily doped region and the collector heavily doped region.

[0012] Optionally, the method for forming a plurality of gradient units arranged along a first direction within the substrate includes: forming a mask layer on the bottom surface of the second shallow trench isolation structure, the mask layer having a plurality of windows spaced at non-equidistant intervals, wherein the spacing width between the windows increases sequentially in the first direction, and adjacent windows have a first predetermined width and a second predetermined width, and adjacent windows have a third predetermined width, wherein the first predetermined width is greater than the second predetermined width, and the third predetermined width is equal to the first predetermined width; after forming the mask layer, gradient units are formed by ion implantation, wherein the spacing width between the gradient units increases sequentially in the first direction, and adjacent gradient units have a first width and a second width, and the spacing between adjacent gradient units is a third width, wherein the first width is greater than the second width, and the third width is equal to the first width; the ion implantation dose of the gradient units is less than the ion implantation dose of the base well region.

[0013] Optionally, the transistor is a PNP type, and the ion implantation process parameters for the graded unit are: implanted ions are boron ions or boron difluoride ions, and the implantation dose is 8 × 10⁻⁶. 12 cm -2 ~1.2×10 13 cm -2 The implantation angle is 0°, and the ion implantation process parameters for the base trap region are: implanted ions are phosphorus ions, and the implantation dose is 1.5 × 10⁻⁶. 13 cm -2 .

[0014] Compared with the prior art, the technical solution of the present invention provides a transistor structure and its fabrication method. The transistor structure includes: a substrate, in which adjacent and spaced-apart base well regions and collector well regions are formed. The base well regions contain independent heavily doped emitter regions and heavily doped base regions, and the collector well region contains a heavily doped collector region. The heavily doped base region is located between the heavily doped emitter region and the heavily doped collector region. A first shallow trench isolation structure is located within the substrate between the base well regions and the collector well regions. The bottom surface of the base well region is lower than the bottom surface of the first shallow trench isolation structure, and the bottom surface of the collector well region is also lower than the bottom surface of the first shallow trench isolation structure, thus isolating the base well region from the collector well region. A second shallow trench isolation structure is located within the base well region. The bottom surface of the second shallow trench isolation structure is flush with the bottom surface of the first shallow trench isolation structure, and the heavily doped emitter region and the heavily doped base region are respectively located within the second shallow trench isolation junction. The gradient region is located on both sides of the structure. Since the gradient region is located in the base well region and on the bottom surface of the second shallow trench isolation structure, the gradient region includes several gradient units arranged along the first direction. Along the first direction, the width of the gradient units gradually increases. The doping type of the gradient units is opposite to that of the base well region, while the doping type of the gradient units is the same as that of the collector well region. The first direction is the direction in which minority carriers in the base well region move from the heavily doped emitter region to the heavily doped base region. Therefore, the width of the gradient units shows a step-increasing width distribution trend from the heavily doped emitter region to the heavily doped collector region. The ion implantation width is narrower closer to the heavily doped emitter region and wider closer to the heavily doped collector region. Combined with the recombination of minority carriers in the gradient units with some majority carriers in the base well region, the majority carrier doping concentration in this region is reduced, the transistor current gain is increased, the number of ion implantation times is reduced, and the process of traditional gradually changing base regions is simplified.

[0015] The method for preparing a transistor structure provided by the technical solution of the present invention has all the above-mentioned technical effects since the transistor structure is formed, and will not be repeated here. Attached Figure Description

[0016] Figures 1 to 5 This is a schematic diagram of each step in the fabrication method of a transistor structure according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of the gradient region according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a gradient unit projected onto a substrate surface according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the gradient unit projected onto the substrate surface according to another embodiment of the present invention.

[0017] Explanation of reference numerals in the attached figures: 100 for the substrate; Base well region 103; Collector well region 102; Launch of the extremely heavy doped region 107; The base-heavy doped region is 106; Collector heavily doped region 105; First shallow trench isolation structure 1041; Second shallow trench isolation structure 1042; Gradient zone 101; Interlayer dielectric layer 110; First direction a; First width d1; Second width d2; The third width is s1. Detailed Implementation

[0018] As in the background art, existing transistor structures form a gradually changing base region in the substrate through multiple ion implantations in order to improve current gain. However, this process is prone to introducing a large number of impurities and is complicated to operate, which is not conducive to improving current gain.

[0019] To solve the above-mentioned technical problems, the present invention provides a transistor structure and its fabrication method. The transistor structure includes: a substrate having adjacent and spaced-apart base well regions and collector well regions within the substrate; the base well regions having independent heavily doped emitter regions and heavily doped base regions; the collector well regions having heavily doped collector regions; and the heavily doped base regions located between the heavily doped emitter regions and the heavily doped collector regions. A first shallow trench isolation structure is located within the substrate between the base well regions and the collector well regions. The bottom surface of the base well regions is lower than the bottom surface of the first shallow trench isolation structure, and the bottom surface of the collector well regions is also lower than the bottom surface of the first shallow trench isolation structure, thus isolating the base well regions from the collector well regions. A second shallow trench isolation structure is located within the base well regions, with its bottom surface flush with the bottom surface of the first shallow trench isolation structure. The heavily doped emitter regions and the heavily doped base regions are respectively located within the second shallow trench isolation structure. The two sides of the structure; since the gradient region is located in the base well region and on the bottom surface of the second shallow trench isolation structure, the gradient region includes several gradient units arranged along the first direction, and the width of the gradient units gradually increases along the first direction. The doping type of the gradient units is opposite to that of the base well region, and the doping type of the gradient units is the same as that of the collector well region. The first direction is the direction in which minority carriers in the base well region move from the heavily doped emitter region to the heavily doped base region. Therefore, the width of the gradient units shows a step-increasing width distribution trend from the heavily doped emitter region to the heavily doped collector region. The ion implantation width is narrower closer to the heavily doped emitter region and wider closer to the heavily doped collector region. Combined with the recombination of minority carriers in the gradient units with some majority carriers in the base well region, the majority carrier doping concentration in this region is reduced, the transistor current gain is increased, the number of ion implantation times is reduced, and the process of traditional slowly changing base regions is simplified.

[0020] To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Additionally, directional terms such as above, below, up, down, upward, downward, left, right, etc., are used relative to exemplary embodiments as they are shown in the figures, with upward or upper directions pointing towards the top of the corresponding figure and downward or lower directions pointing towards the bottom of the corresponding figure.

[0022] Figures 1 to 5 This is a schematic diagram of each step in the fabrication method of a transistor structure according to an embodiment of the present invention.

[0023] Please refer to Figure 1 Provides a base of 100.

[0024] Specifically, a first shallow trench structure 1041 and a second shallow trench structure 1042 are formed in the substrate 100, and the bottom surface of the second shallow trench isolation structure 1042 is flush with the bottom surface of the first shallow trench isolation structure 1041.

[0025] Please refer to Figure 2 A base well region 103 is formed within the substrate 100.

[0026] Furthermore, the bottom surface of the base well region 103 is lower than the first shallow trench isolation structure 1041, and the second shallow trench isolation structure 1042 is located within the base well region 103.

[0027] Please continue to refer to this. Figure 2 A collector well region 102 is formed within the substrate 100.

[0028] Furthermore, a first shallow trench isolation structure 1041 is formed between the base well region 103 and the collector well region 102, and the bottom surface of the collector well region 102 is lower than the bottom surface of the first shallow trench isolation structure 1041, so as to isolate the base well region 103 and the collector well region 102.

[0029] Furthermore, the ion doping type of the base well region 103 is opposite to that of the collector well region 102.

[0030] Please refer to Figure 3 A gradient region 101 is formed within the base trap region 103.

[0031] Furthermore, the gradient region 101 is formed on the bottom surface of the second shallow trench isolation structure 1042. The gradient region 101 may include a plurality of gradient units arranged along the first direction a, and the width of the gradient unit gradually increases along the first direction a. The doping type of the gradient unit is opposite to that of the base well region 103, and the doping type of the gradient unit is the same as that of the collector well region 102.

[0032] Furthermore, after forming the base well region 103, the collector well region 102, and the gradient region 101, the transistor structure is annealed.

[0033] In this embodiment, the annealing process parameters are: rapid thermal annealing (RTA) for 10 seconds in a hydrogen environment at 1000°C.

[0034] In other embodiments, the gradient region 101 can be injected before the formation of the base well region 103 and the collector well region 102.

[0035] In other embodiments, the gradient region 101 can be injected after the formation of the base well region 103 and the collector well region 102.

[0036] Please refer to Figure 5 After annealing, an independent emitter heavy doping region 107 and a base heavy doping region 106 are formed in the base well region 103.

[0037] Furthermore, the first direction a is the direction in which minority carriers in the base well region 103 move from the emitter heavily doped region 107 to the base heavily doped region 106.

[0038] Please continue to refer to this. Figure 5 After annealing, a heavily doped collector region 105 is formed in the collector trap region 102, and a heavily doped base region 106 is located between the heavily doped emitter region 107 and the heavily doped collector region 105.

[0039] In this embodiment, N-type ions are doped into the emitter heavily doped region 107, the base heavily doped region 106, and the collector heavily doped region 105 to form an N-type ohmic contact. The N-type ions can be phosphorus ions or arsenic ions.

[0040] In this embodiment, the arsenic ion implantation energy is 10 keV to 20 keV, and the arsenic ion implantation dose is 3.0 × 10⁻⁶. 15 Up to 5.0×10 15 .

[0041] In other embodiments, P-type ions are doped into the emitter heavily doped region 107, the base heavily doped region 106, and the collector heavily doped region 105 to form a P-type ohmic contact. The P-type ions can be boron ions or boron difluoride ions. The boron ion implantation energy is 10 keV-50 keV, and the boron ion implantation dose is 3.0 × 10⁻⁶. 15 Up to 5.0×10 15 .

[0042] The transistor structure includes a substrate 100, within which there are adjacent and spaced-apart base well regions 103 and collector well regions 102. The base well region 103 contains independent emitter heavily doped regions 107 and base heavily doped regions 106, and the collector well region 102 contains a collector heavily doped region 105. The base heavily doped region 106 is located between the emitter heavily doped region 107 and the collector heavily doped region 105. A first shallow trench isolation structure 1041 is located between the base well region 103 and the collector well region 102 on the substrate 100. Within the base well region 103, the bottom surface of the base well region 103 is lower than the bottom surface of the first shallow trench isolation structure 1041, and the bottom surface of the collector well region 102 is lower than the bottom surface of the first shallow trench isolation structure 1041, so as to isolate the base well region 103 from the collector well region 102; the second shallow trench isolation structure 1042 is located within the base well region 103, and the bottom surface of the second shallow trench isolation structure 1042 is flush with the bottom surface of the first shallow trench isolation structure 1041, and the emitter heavily doped region 107 and the base heavily doped region 106 are respectively located within the second shallow trench isolation structure 1041. The two sides of the trench isolation structure 1042; since the gradient region 101 is located within the base well region 103 and on the bottom surface of the second shallow trench isolation structure 1042, the gradient region 101 includes several gradient units arranged along the first direction a, and the width of the gradient unit gradually increases along the first direction a. The doping type of the gradient unit is opposite to that of the base well region 103, and the doping type of the gradient unit is the same as that of the collector well region 102. The first direction a is the direction in which minority carriers in the base well region 103 move from the emitter heavily doped region 107 to the base heavily doped region. The moving direction of 106 results in a stepped width distribution from the heavily doped emitter region 107 to the heavily doped collector region 105. The ion implantation width is narrower closer to the heavily doped emitter region 107 and wider closer to the heavily doped collector region 105. Combined with the recombination of minority carriers in the gradient unit with some majority carriers in the base well region 103, the majority carrier doping concentration in this region is reduced, the transistor current gain is increased, the number of ion implantation times is reduced, and the process of traditional gradually changing base regions is simplified.

[0043] Please refer to the reference. Figure 3 and Figure 4 A method for forming a plurality of gradient units arranged along a first direction a within a substrate 100 may include: A mask layer (not shown) is formed on the bottom surface of the second shallow trench isolation structure 1042. The mask layer has a plurality of windows (not shown) with non-equidistant spacing between them. In the first direction a, the spacing width between each window increases sequentially, and adjacent windows have a first predetermined width (not shown) and a second predetermined width (not shown). Adjacent windows have a third predetermined width (not shown). The first predetermined width is greater than the second predetermined width, and the third predetermined width is equal to the first predetermined width.

[0044] After the mask layer is formed, gradient units are formed by ion implantation. In the first direction a, the spacing width of each gradient unit increases sequentially, and adjacent gradient units have a first width d1 and a second width d2. The spacing between adjacent gradient units is a third width s1. The first width d1 is greater than the second width d2, and the third width s1 is equal to the first width d1. The ion implantation dose of the gradient unit is less than the ion implantation dose of the base well region 103.

[0045] In this embodiment, the transistor can be PNP type, and the ion implantation process parameters for the graded unit are: the implanted ions are boron ions or boron difluoride ions, and the implantation dose is 8 × 10⁻⁶. 12 cm -2 ~1.2×10 13 cm -2 The implantation angle is 0°, and the ion implantation process parameters for the base trap region 103 are as follows: the implanted ion is phosphorus ion, and the implantation dose is 1.5 × 10⁻⁶. 13 cm -2 .

[0046] For further details, please refer to... Figure 6 An interlayer dielectric layer 110 is deposited on the surfaces of the emitter heavily doped region 107, the base heavily doped region 106, and the collector heavily doped region 105. A contact hole 108 is formed in the interlayer dielectric layer 110. A metal layer 109 is deposited on the surface of the interlayer dielectric layer 110 and in the contact hole 108 to form the first metal interconnect of the transistor.

[0047] In this embodiment, the material of the metal layer 109 is AlCu.

[0048] An embodiment of the present invention also provides a transistor structure formed by the above-described preparation method, please refer to... Figure 5 The transistor structure may include: a substrate 100, a first shallow trench isolation structure 1041, a second shallow trench isolation structure 1042, and a gradient region 101.

[0049] The substrate 100 contains adjacent but spaced-apart base well regions 103 and collector well regions 102. The base well region 103 contains independent emitter heavily doped regions 107 and base heavily doped regions 106. The collector well region 102 contains a collector heavily doped region 105. The base heavily doped region 106 is located between the emitter heavily doped region 107 and the collector heavily doped region 105. A first shallow trench isolation structure 1041 is located within the substrate 100 between the base well regions 103 and the collector well region 102. The bottom surface of the base well region 103 is lower than the bottom surface of the first shallow trench isolation structure 1041, and the bottom surface of the collector well region 102 is lower than the bottom surface of the first shallow trench isolation structure 1041, so as to isolate the base well region 103 from the collector well region 102. The second shallow trench isolation structure 1042 is located within the base well region 103, and its bottom surface is flush with the bottom surface of the first shallow trench isolation structure 1041. The emitter heavily doped region 107 and the base heavily doped region 106 are located on opposite sides of the second shallow trench isolation structure 1042. The gradient region 101 is located within the base well region 103 and on the bottom surface of the second shallow trench isolation structure 1042. The gradient unit has the opposite doping type to the base well region 103 and the same doping type as the collector well region 102. The first direction a is the direction in which minority carriers in the base well region 103 move from the emitter heavily doped region 107 to the base heavily doped region 106.

[0050] In other embodiments, such as the BCD 180 process, the spacing between the emitter heavily doped region 107 and the base heavily doped region 106 can be from 2.0 micrometers to 10.0 micrometers; the value range of the first gradient unit can be from 0.5 micrometers to 2 micrometers.

[0051] Please refer to the reference. Figure 4 and Figure 5 The gradient units are arranged at non-equal intervals, and in the first direction a, the spacing between each gradient unit increases sequentially.

[0052] In other embodiments, the gradient units are arranged at equal intervals.

[0053] Please refer to the reference. Figure 4 and Figure 5 Adjacent gradient units have a first width d1 and a second width d2 respectively, and the spacing between adjacent gradient units is a third width s1. The first width d1 is greater than the second width d2, and the third width s1 is equal to the first width d1.

[0054] Please refer to the reference. Figure 7 and Figure 6The emitter heavy doping region 107 is located within the substrate 100. Along the direction of the surface of the substrate 100, the base heavy doping region 106 surrounds the emitter heavy doping region 107. Adjacent gradient units are separated by a portion of the base well region 103. The gradient region 101 is located between the base heavy doping region 106 and the emitter heavy doping region 107.

[0055] Please continue to refer to this. Figure 7 The projection of the gradient unit onto the surface of the substrate 100 is a rectangular ring. The rectangular ring is sequentially nested around the heavily doped emitter region 107 with the same center. In this way, the majority carriers emitted from the heavily doped emitter region 107, except for those collected by the heavily doped collector region 105 at the bottom of the base well region 103, must pass through the gradient region 101 and be collected by the heavily doped collector region 105. This greatly restricts the flow path of the carriers, thereby achieving the effect of enhancing the current gain of the transistor.

[0056] Please continue to refer to this. Figure 8 The substrate 100 has a rectangular region on its surface. The projection of the gradient unit within the rectangular region is a number of spaced strips. The strips are parallel to the four sides of the rectangular region and are arranged around the emitter heavily doped region 107 with the same center. Thus, the gradient region 101 is not completely closed from the inside out, so that the majority carriers from the emitter heavily doped region 107, except for those collected by the collector heavily doped region 105 from the bottom of the base well region 103 and those collected by the collector heavily doped region 105 through the gradient region 101, still have other current paths. This optimizes the electric field distribution of the gradient region 101, reduces the introduction of excessively strong electric fields at the boundary of the gradient region 101, alleviates the electric field concentration effect, optimizes the current distribution, and improves the stability of the transistor operation.

[0057] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A transistor structure, characterized in that, include: The substrate has adjacent and spaced-apart base well regions and collector well regions. The base well regions have independent emitter heavily doped regions and base heavily doped regions. The collector well regions have collector heavily doped regions. The base heavily doped regions are located between the emitter heavily doped regions and the collector heavily doped regions. A first shallow trench isolation structure is located in the substrate between the base well region and the collector well region. The bottom surface of the base well region is lower than the bottom surface of the first shallow trench isolation structure, and the bottom surface of the collector well region is lower than the bottom surface of the first shallow trench isolation structure, so as to isolate the base well region from the collector well region. The second shallow trench isolation structure is located within the base well region. The bottom surface of the second shallow trench isolation structure is flush with the bottom surface of the first shallow trench isolation structure, and the emitter heavily doped region and the base heavily doped region are located on both sides of the second shallow trench isolation structure. A gradient region is located within the base well region and on the bottom surface of the second shallow trench isolation structure. The gradient region includes a plurality of gradient units arranged along a first direction, and the width of the gradient units gradually increases along the first direction. The doping type of the gradient units is opposite to that of the base well region, and the doping type of the gradient units is the same as that of the collector well region. The first direction is the direction in which minority carriers in the base well region move from the heavily doped emitter region to the heavily doped base region.

2. The transistor structure according to claim 1, characterized in that, The gradient units are arranged at non-equidistant intervals, and in the first direction, the spacing width between each gradient unit increases sequentially.

3. The transistor structure according to claim 2, characterized in that, Adjacent gradient units each have a first width and a second width, and the spacing between adjacent gradient units is a third width, wherein the first width is greater than the second width and the third width is equal to the first width.

4. The transistor structure according to claim 1, characterized in that, The emitter heavily doped region is located within the substrate. Along the direction of the substrate surface, the base heavily doped region surrounds the emitter heavily doped region. Adjacent gradient units are separated by a portion of the base well region. The gradient region is located between the base heavily doped region and the emitter heavily doped region.

5. The transistor structure according to claim 4, characterized in that, The projection of the gradient unit onto the substrate is a rectangular ring, and the rectangular ring is sequentially nested around the heavily doped emitter region with the same center.

6. The transistor structure according to claim 4, characterized in that, The substrate surface has a rectangular area, and the projection of the gradient unit within the rectangular area is a number of spaced stripes. The stripes are parallel to the four sides of the rectangular area, and the stripes are sequentially nested around the heavily doped emitter region with the same center.

7. The transistor structure according to claim 1, characterized in that, Also includes: An interlayer dielectric layer is located on the surface of the heavily doped emitter region, the surface of the heavily doped base region, and the surface of the heavily doped collector region. The interlayer dielectric layer has contact holes, and both the surface of the interlayer dielectric layer and the contact holes have metal layers to form the first metal interconnect of the transistor structure.

8. A method for fabricating a transistor structure, characterized in that, include: Provide a base; A first shallow trench structure and a second shallow trench structure are formed in the substrate, and the bottom surface of the second shallow trench isolation structure is flush with the bottom surface of the first shallow trench isolation structure. A base well region is formed within the substrate, the bottom surface of the base well region being lower than the bottom surface of the first shallow trench isolation structure, and the second shallow trench isolation structure being located within the base well region; A collector well region is formed within the substrate, and a first shallow trench isolation structure is formed between the base well region and the collector well region, with the bottom surface of the collector well region being lower than the bottom surface of the first shallow trench isolation structure to isolate the base well region from the collector well region. A gradient region is formed in the base well region and the gradient region is formed on the bottom surface of the second shallow trench isolation structure. The gradient region includes a plurality of gradient units arranged along a first direction, and the width of the gradient units gradually increases along the first direction. The doping type of the gradient units is opposite to that of the base well region, and the doping type of the gradient units is the same as that of the collector well region. After forming the base well region, the collector well region, and the gradient region, the transistor structure is annealed. After the annealing process, an independent emitter heavy doping region and a base heavy doping region are formed in the base well region. The first direction is the direction in which minority carriers in the base well region move from the emitter heavy doping region to the base heavy doping region. After the annealing process, a heavily doped collector region is formed in the collector well region, and the heavily doped base region is located between the heavily doped emitter region and the heavily doped collector region.

9. The preparation method according to claim 8, characterized in that, A method for forming a plurality of gradient units arranged along a first direction within the substrate includes: A mask layer is formed on the bottom surface of the second shallow trench isolation structure. The mask layer has a plurality of windows, which are not equidistant from each other. In the first direction, the spacing between each window increases sequentially, and adjacent windows have a first predetermined width and a second predetermined width. Adjacent windows have a third predetermined width, the first predetermined width is greater than the second predetermined width, and the third predetermined width is equal to the first predetermined width. After the mask layer is formed, the gradient unit is formed by ion implantation. In the first direction, the spacing width of each gradient unit increases sequentially, and adjacent gradient units have a first width and a second width. The spacing between adjacent gradient units is a third width. The first width is greater than the second width, and the third width is equal to the first width. The ion implantation dose of the gradient unit is less than the ion implantation dose of the base well region.

10. The preparation method according to claim 9, characterized in that, The transistor is a PNP type, and the ion implantation process parameters for the graded unit are as follows: the implanted ions are boron ions or boron difluoride ions, and the implantation dose is 8 × 10⁻⁶. 12 cm -2 ~1.2×10 13 cm -2 The implantation angle is 0°, and the ion implantation process parameters for the base trap region are: implanted ions are phosphorus ions, and the implantation dose is 1.5 × 10⁻⁶. 13 cm -2 .

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