Semiconductor device

Abstract

One embodiment provides a semiconductor device capable of reducing switching loss during diode operation. According to one embodiment, a semiconductor device includes a first electrode and a second electrode and a semiconductor layer therebetween. The semiconductor layer includes a first region to a third region. The semiconductor layer includes first to eighth semiconductor regions. First and second semiconductor regions are provided in the first and second regions, respectively. A third semiconductor region is provided thereon. A plurality of fifth semiconductor regions of a second conductivity type is provided over the third semiconductor region. A plurality of gate electrodes faces the fifth semiconductor regions with a gate insulating layer therebetween, respectively. A plurality of sixth semiconductor regions is provided over the fifth semiconductor regions, respectively. The sixth semiconductor regions are in contact with a plurality of contact portions of the second electrode, respectively. An eighth semiconductor region of the second conductivity type and a ninth semiconductor region of a first conductivity type are provided between another of the fifth semiconductor regions and another of the contact portions, respectively.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2025-044884, filed on March 19, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present invention generally relate to a semiconductor device. Background Technology

[0004] Semiconductor devices (reverse-conducting insulated-gate bipolar transistors: RC-IGBTs) combine the functions of an insulated-gate bipolar transistor with those of a diode. A technique is needed to reduce switching losses during diode operation in such semiconductor devices. Summary of the Invention

[0005] One embodiment provides a semiconductor device capable of reducing switching losses during diode operation.

[0006] According to one embodiment, a semiconductor device includes a first electrode, a second electrode, and a semiconductor layer. The second electrode is separated from the first electrode in a first direction. The semiconductor layer is disposed between the first electrode and the second electrode. The semiconductor layer includes a first region, a second region, and a third region. The third region is located between the first region and the second region in a second direction perpendicular to the first direction. The semiconductor layer includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a fourth semiconductor region of a second conductivity type, a plurality of fifth semiconductor regions of a second conductivity type, a plurality of gate electrodes, a plurality of sixth semiconductor regions of a first conductivity type, a seventh semiconductor region of a second conductivity type, an eighth semiconductor region of a second conductivity type, and a ninth semiconductor region of a first conductivity type. The first semiconductor region is disposed in the first region. The second semiconductor region is disposed in the second region. The third semiconductor region is disposed above the first semiconductor region and the second semiconductor region. The fourth semiconductor region is disposed above the third semiconductor region. The fourth semiconductor region is located in the first region. The plurality of fifth semiconductor regions are disposed above the third semiconductor region. The plurality of fifth semiconductor regions are located in the second region and the third region. The plurality of gate electrodes are respectively opposed to the plurality of fifth semiconductor regions in a second direction through a plurality of gate insulating layers. The plurality of sixth semiconductor regions are respectively disposed above the plurality of fifth semiconductor regions. Multiple sixth semiconductor regions are respectively in contact with multiple contacts of the second electrode in the second direction. A seventh semiconductor region is disposed between one of the multiple fifth semiconductor regions in the second region and one of the multiple contacts. An eighth semiconductor region and a ninth semiconductor region are respectively disposed between another of the multiple fifth semiconductor regions in the third region and another of the multiple contacts. Attached Figure Description

[0007] Figure 1 This is a plan view of the semiconductor device according to the first embodiment;

[0008] Figure 2 yes Figure 1 Enlarged plan view of Part II;

[0009] Figure 3 yes Figure 2 Section III-III view;

[0010] Figure 4 yes Figure 2 Section IV-IV;

[0011] Figure 5 This is an enlarged plan view of a portion of the semiconductor device according to the first embodiment;

[0012] Figure 6This is an enlarged plan view of a portion of the semiconductor device according to the first embodiment;

[0013] Figure 7 This is an enlarged plan view of a portion of the semiconductor device according to the first embodiment;

[0014] Figure 8A and Figure 8B It is shown Figure 1 Enlarged plan view of some examples of VIIIA and VIIIB;

[0015] Figure 9A and Figure 9B It is shown Figure 1 Enlarged plan view of another example of parts VIIIA and VIIIB;

[0016] Figure 10A and Figure 10B It is shown Figure 1 An enlarged plan view of another example of parts VIIIA and VIIIB;

[0017] Figure 11 This is a plan view showing a portion of a semiconductor device according to a modified example of the first embodiment;

[0018] Figure 12 This is a plan view showing a portion of a semiconductor device according to the second embodiment;

[0019] Figure 13 yes Figure 12 XIII-XIII section view;

[0020] Figure 14 yes Figure 12 XIV-XIV section view;

[0021] Figure 15 This is a plan view showing a portion of a semiconductor device according to a third embodiment;

[0022] Figure 16 yes Figure 14 XVI-XVI cross-sectional view;

[0023] Figure 17 yes Figure 15 Cross-sectional view of XVII-XVII. Detailed Implementation

[0024] Embodiments of the present invention will now be described with reference to the accompanying drawings. The drawings are schematic or conceptual; and the relationships between the thickness and width of parts, the dimensional proportions between parts, etc., are not necessarily the same as their actual values. Even when the same parts are shown, dimensions and / or proportions may be shown differently in the drawings. In the drawings and description of this application, parts similar to those described above are referred to by the same reference numerals, and detailed descriptions are appropriately omitted.

[0025] In the following description and figures, the symbol n + n - and p + 'p' represents the relative level of impurity concentration in the conductivity type. That is, a '+' sign indicates a relatively higher impurity concentration than a sign without either '+' or '-'. A '-' sign indicates a relatively lower impurity concentration than a sign without either '+' or '-'.

[0026] N-type is an example of the first conductivity type. P-type is an example of the second conductivity type. The implementation described below can be achieved by inverting the p-type and n-type of the semiconductor region.

[0027] First Implementation Method

[0028] Figure 1 This is a plan view of a semiconductor device according to the first embodiment. Figure 2 yes Figure 1 Enlarged plan view of part II. Figure 3 yes Figure 2 Section III-III view. Figure 4 yes Figure 2 Section IV-IV. Figure 2 Corresponding to Figure 3 and Figure 4 Section II-II view.

[0029] The semiconductor device in this embodiment is an RC-IGBT. For example... Figures 1 to 4 As shown, the semiconductor device 100 according to the embodiment includes a collector 1 (first electrode), an emitter 2 (second electrode), a gate pad 3, and a semiconductor layer S. Note that in Figure 2 Emitter 2 is omitted.

[0030] The XYZ orthogonal coordinate system is used in the description of the implementation. The direction from the collector 1 toward the emitter 2 is considered the Z direction (first direction). Two mutually orthogonal directions perpendicular to the Z direction are considered the X direction (second direction) and the Y direction (third direction). In this specification, the direction from the collector 1 toward the emitter 2 is referred to as "up / above," and the opposite direction is referred to as "down / below." These directions are based on the relative positional relationship between the collector 1 and the emitter 2 and are independent of the direction of gravity.

[0031] like Figure 1 As shown, emitter 2 and gate pad 3 are disposed on the upper surface of semiconductor device 100. Emitter 2 and gate pad 3 are separated from each other. For example, multiple emitters 2 are disposed in the Y direction. Gate wiring 3a is disposed around each emitter 2. A portion of gate wiring 3a extends in the Y direction between emitters 2. Gate wiring 3a is electrically connected to gate pad 3. Semiconductor layer S is disposed below emitter 2, gate pad 3, and gate wiring 3a.

[0032] like Figure 1 and Figure 2 As shown, the semiconductor layer S includes a diode region R1 (first region), an IGBT region R2 (second region), and an IGBT region R3 (third region). In the illustrated example, multiple diode regions R1 and multiple IGBT regions R2 are arranged in both the X and Y directions. In the X direction, diode regions R1 and IGBT regions R2 are arranged alternately. The IGBT region R3 is disposed between the diode regions R1 and the IGBT regions R2.

[0033] like Figure 3 and Figure 4 As shown, collector 1 is disposed on the lower surface of semiconductor device 100. Collector 1 and emitter 2 are separated from each other in the Z direction. Semiconductor layer S is located between collector 1 and emitter 2.

[0034] Semiconductor layer S includes: n + Type cathode region 11 (first semiconductor region), p + Type collector region 12 (second semiconductor region), n - p-type base region 13 (third semiconductor region), p-type anode region 14 (fourth semiconductor region), p + p-type anode region 14a, p-type base region 15 (fifth semiconductor region), n + Type 16 emitter region (sixth semiconductor region), p + Type contact region 17 (seventh semiconductor region), p + Type contact region 18 (eighth semiconductor region), n +Type contact region 19 (ninth semiconductor region), conductive part 20 and gate electrode 21.

[0035] n + The cathode region 11 is disposed within the diode region R1. + The collector region 12 is located in the IGBT region R2. - Type base region 13 is set in n + Type cathode region 11 and p + On type collector region 12. - The concentration of n-type impurities in the base region 13 is lower than that of n-type impurities. + The concentration of n-type impurities in the cathode region 11.

[0036] In IGBT region R3, p + Type collector region 12 can be set at collector 1 and n - Between the base region 13, as shown in the figure. Optionally, in IGBT region R3, n + Type 11 cathode region, or n + Type cathode region 11 and p + Type collector regions 1 and 2 can be set at collectors 1 and n. - Between type base region 13.

[0037] The p-type anode region 14 is located in the diode region R1. - On the base region 13. + Type anode region 14a is disposed on type p anode region 14. + The concentration of p-type impurities in the p-type anode region 14a is higher than that in the p-type anode region 14. The conductive portion 20 is positioned opposite the p-type anode region 14 in the X direction through the insulating layer 20a. The p-type anode region 14 and the conductive portion 20 are alternately arranged in the X direction, and each p-type anode region 14 and each conductive portion 20 extends in the Y direction.

[0038] The p-type base region 15 is set in the n-type region R2 of the IGBT. - On the p-type base region 13. The gate electrode 21 is opposite to the p-type base region 15 in the X direction through the gate insulating layer 21a. The p-type base region 15 and the gate electrode 21 are alternately arranged in the X direction, and each p-type base region 15 and each gate electrode 21 extends in the Y direction.

[0039] Multiple n + Emitter regions 16 are respectively disposed on multiple p-type base regions 15. The emitter 2 includes multiple contacts 2a protruding toward the semiconductor layer S. Multiple n-type base regions 15 +The p-type emitter region 16 is in contact with a plurality of contact portions 2a in the X direction. In other words, at least one n-type base region 15 is provided on a p-type base region 15. + A p-type emitter region 16 and a contact portion 2a are provided. Multiple groups are arranged along the X direction, each group including a p-type base region 15 and at least one n-type base region 16. + The emitter region 16 and a contact portion 2a are included.

[0040] For example, such as Figure 2 As shown, a pair of n-type base regions spaced apart in the X direction are disposed on a p-type base region 15. + Type 16 emitter region. Multiple pairs of n in the Y direction. + The emitter regions 16 are arranged separately from each other. Each pair of n in the X direction... + Between the emitter regions 16, the contact portion 2a extends along the Y direction.

[0041] like Figure 3 and Figure 4 As shown, in IGBT region R2, p + The p-type contact region 17 is disposed between the p-type base region 15 and the contact portion 2a. + The concentration of p-type impurities in the p-type contact region 17 is higher than that in the p-type base region 15. + The contact area 17 extends in the Y direction.

[0042] In IGBT region R3, p + Type contact areas 18 and n + The p-type contact region 19 is disposed between the p-type base region 15 and the contact portion 2a. + The concentration of p-type impurities in the p-type contact region 18 is higher than the concentration of p-type impurities in the p-type base region 15. + The concentration of n-type impurities in contact region 19 is higher than that of n-type impurities. - The concentration of n-type impurities in the base region 13. + The concentration of n-type impurities in contact region 19 can be equal to or lower than n + The concentration of n-type impurities in the n-type emitter region 16. + Type contact areas 18 and n + The contact areas 19 are arranged relative to each other in the Y direction. For example, as shown... Figure 2 As shown, p + Type contact areas 18 and n + The contact areas 19 are alternately arranged in the Y direction.

[0043] like Figure 3 and Figure 4 As shown, the contact portion 2a includes a portion located at p +The first part 2a1 on the contact area 18 and located at n + The second part 2a2 on the contact area 19.

[0044] Emitter 2 is located in p-type anode region 14, p + Type anode region 14a, p-type base region 15, n + Type emitter region 16, p + Type contact area 17, p + Type contact areas 18 and n + The conductive portion 20 is electrically connected to the emitter 2 in a portion not shown. The gate electrode 21 is electrically isolated from the emitter 2 by an insulating layer 22. The gate electrode 21 is electrically connected to the gate wiring 3a in a portion not shown.

[0045] The operation of the semiconductor device 100 will now be described.

[0046] With a positive voltage applied to the collector 1 relative to the emitter 2, a voltage not less than a threshold is applied to the gate electrode 21. As a result, a channel (inversion layer) is formed in the p-type base region 15. Electrons pass through the channel from the n-type base region 15... + Type 16 emitter region injection n - Type base region 13, holes from p + Type collector region 12 injection n - Type base region 13. In n - The carrier density accumulated in the base region 13 increases, and conductivity modulation occurs. As a result, n - The resistance of the p-type base region 13 decreases significantly, and IGBT regions R2 and R3 turn on. Subsequently, when the voltage applied to the gate electrode 21 falls below the threshold, the channel in the p-type base region 15 disappears, and IGBT regions R2 and R3 switch to the off state. After IGBT regions R2 and R3 switch to the off state, the voltage accumulated in the n-type base region 15 decreases significantly. - Electrons in the base region 13 pass through p + The p-type collector region 12 discharges to collector 1. Holes discharge to emitter 2 through p-type base region 15.

[0047] For example, multiple semiconductor devices 100 are used to configure a bridge circuit. When the IGBT regions R2 and R3 of one semiconductor device 100 switch from the on state to the off state, an electromotive force is induced in the emitter 2 of the other semiconductor device 100 due to the inductance of the bridge circuit. As a result, in the other semiconductor device 100, the diode region R1 is activated. Holes are injected from the p-type anode region 14 into the n-type diode region 2. - In the base region 13, electrons emerge from n + Type 11 cathode region injected into n- In base region 13, diode region R1 is used as a freewheeling diode (FWD).

[0048] Examples of the materials used in each component of the semiconductor device 100 will be described below.

[0049] Collector 1, emitter 2, gate pad 3, and gate wiring 3a are made of metallic material, such as aluminum or copper. + Type cathode region 11, p + Type collector region 12, n - p-type base region 13, p-type anode region 14, p + Type anode region 14a, p-type base region 15, n + Type emitter region 16, p + Type contact area 17, p + Type contact areas 18 and n + The contact region 19 comprises a semiconductor material such as silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as a p-type impurity. The conductive portion 20 and the gate electrode 21 comprise conductive materials such as doped conductive polycrystalline silicon. The insulating layer 20a, the gate insulating layer 21a, and the insulating layer 22 comprise insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0050] Semiconductor device 100 has a parasitic thyristor, which includes p + Type collector region 12, n - Type 13 base region, p-type base region 15 and n + The p-type emitter region 16. When IGBT regions R2 and R3 are off, holes flow into the p-type base region 15. If the potential of the p-type base region 15 increases due to the inflow of holes, the parasitic thyristor can operate. The semiconductor device 100 includes p... + Type contact area 17 and p + Type-18 contact area is used to suppress the operation of parasitic thyristors. + Type contact area 17 and p + The p-type impurity concentration in the p-type contact region 18 is higher than that in the p-type base region 15. This is achieved by setting the p... + Type contact area 17 and p + In the p-type contact region 18, holes can more easily discharge to the emitter 2 through these semiconductor regions. As a result, the potential rise of the p-type base region 15 is suppressed, and the operation of the parasitic thyristor is suppressed.

[0051] On the other hand, IGBT regions R2 and R3 have n -Parasitic diodes in IGBT base region 13 and p-type base region 15. When diode region R1 is in the on state, the parasitic diodes in IGBT regions R2 and R3 operate, and holes are injected from emitter 2 into n. - Type base region 13. Specifically, in IGBT region R3 adjacent to diode region R1, more holes pass through p... + Type contact area 18 injection n - Type base region 13. Therefore, during the operation of diode region R1, in n - The number of charge carriers accumulated in the base region 13 increases. When diode region R1 switches to the off state, it takes longer for n to become active. - The carriers accumulated in the base region 13 are discharged. As a result, the switching losses of the semiconductor device 100 increase during the reverse recovery of the diode region R1.

[0052] Regarding this issue, in semiconductor device 100, n + Type contact area 19 is located in IGBT area R3. + The p-type contact region 19 is located between the p-type base region 15 and the contact portion 2a. Unlike IGBT region R2, in IGBT region R3, the p-type base region 15... + A portion of the contact area is n + Type contact area 19 is replaced. When n is set... + When the contact area is 19, p + The contact area between the contact region 18 and the contact portion 2a becomes smaller than p. + Type contact area 18 and p + The contact area 17 similarly extends continuously in the Y direction. Furthermore, due to n + The p-type contact region 19 has the same characteristics as the p-type base region 15 and p-type base region 19. + The conductivity type of contact area 18 is opposite to that of contact area 2, therefore, when setting n... + Hole injection is suppressed in a portion of the contact area 19. This is achieved by setting n... + The type-shaped contact region 19 can reduce the amount of holes injected from the IGBT region R3 during the operation of the diode region R1. Furthermore, during the operation of the diode region R1, in n - A portion of the electrons accumulated in the base region 13 pass through n + Contact region 19 discharges to emitter 2. Therefore, during the operation of diode region R1, the discharge at n can be reduced. - The carrier density accumulated in the base region 13.

[0053] According to the first embodiment, during diode operation, hole injection can be suppressed, and electron discharge can be promoted in IGBT region R3. As a result, the reverse recovery current during reverse recovery of diode region R1 can be reduced, and the switching losses of semiconductor device 100 can be reduced.

[0054] Figures 5 to 7 This is an enlarged plan view of a portion of the semiconductor device according to the first embodiment.

[0055] In the semiconductor device 100, a portion of the p-type base region 15 is disposed in the n direction in the Y direction. + Between type emitter regions 16. For example, such as Figure 5 As shown, n + The distance D1 between the emitter regions 16 in the Y direction is greater than that between an n-type emitter regions. + The length L1 of the emitter region 16 in the Y direction is long. Alternatively, such as... Figure 6 As shown, n + The distance D1 between the emitter regions 16 in the Y direction can be less than one n. + The length L1 of the emitter region 16 in the Y direction.

[0056] p + Type contact areas 18 and n + The p-type contact region 19 is alternately disposed on a p-type base region 15 in the Y direction. For example, as Figure 5 As shown, a p + The length L2 of the contact area 18 in the Y direction is greater than that of an n + The length L3 in the Y direction of the contact area 19 is longer. Alternatively, as... Figure 6 As shown, a p + The length L2 of the contact area 18 in the Y direction can be shorter than one n. + The length L3 of the contact area 19 in the Y direction.

[0057] according to Figure 5 The structure shown has a distance D1 that is longer than its length L1, and n + The area of ​​the emitter region 16 is smaller than that of the previous type. When n + When the area of ​​the emitter region 16 is smaller, the amount of radiation passing through n can be reduced. + The current flowing from the emitter 2 to the collector 1 in the emitter region 16 is reduced. Therefore, the saturation current of the semiconductor device 100 can be reduced. For example, the current flowing through the semiconductor device 100 during a short circuit can be reduced, and damage caused by a short circuit can be suppressed. Additionally, length L2 is longer than length L3, and p + The area of ​​contact region 18 is larger than that of type p. +When the area of ​​contact region 18 is large, holes can more easily pass through p when IGBT regions R2 and R3 are turned off. + The discharge in the p-type contact region 18 is suppressed, and the potential rise in the p-type base region 15 is inhibited. Therefore, the operation of the parasitic thyristor can be suppressed in the IGBT region R3.

[0058] according to Figure 6 The structure shown has a distance D1 shorter than a length L1, and n + The area ratio of the emitter region 16 is larger. When n + When the area ratio of the emitter region 16 is large, more electrons pass through n when IGBT regions R2 and R3 are in the conducting state. + Type 16 emitter region injection n - Type base region 13. Therefore, the switching losses during the turn-on period of IGBT regions R2 and R3, as well as the steady-state losses during the conduction state, can be reduced. Additionally, length L3 is longer than length L2, and n + The area of ​​contact region 19 is larger than that of n. + When the area ratio of the contact region 19 is large, it suppresses the flow of p during the operation of the diode region R1. + Hole injection into the contact region 18. Therefore, the switching losses of the semiconductor device 100 can be reduced.

[0059] like Figure 5 and Figure 6 As shown, preferably, n + The position of at least a portion of the emitter region 16 in the Y direction is related to p + At least a portion of the contact area 18 is positioned identically in the Y direction. For example, in a cross-section perpendicular to the Y direction, there are n + At least a portion of the type emitter region 16 and p + At least a portion of both of the contact areas 18. In this case, in the plan view, p + Type contact area 18 is located in a pair of n arranged in the X direction + At least a portion of the region between the emitter regions 16. Here, the term "plan view" refers to a view of the semiconductor device 100 from the Z direction, in which the emitter 2 and the insulating layer 22 are omitted.

[0060] In other words, preferably, at least a portion of the first part 2a1 of the contact portion 2a is located in a pair of n + Between emitter regions 16. When IGBT regions R2 and R3 are off, holes pass through the p in IGBT region R3. + The discharge from contact region 18 to emitter 2 passes through n. + The amount of holes in contact area 19 is less than that through p+ The amount of holes in contact region 18. Therefore, with p + Compared to the vicinity of contact area 18, in n + Near the contact region 19, the potential of the p-type base region 15 tends to rise more easily. When at least a portion of the first part 2a1 is located in a pair of n + When the emitter region 16 is between the two types, holes can easily pass through the p located directly below the first part 2a1. + Discharge in contact region 18 was suppressed. + The potential rise in the p-type base region 15 near the p-type emitter region 16 is thus suppressed.

[0061] More preferably, in a planar diagram, a pair of n arranged in the X direction + In the region between the emitter regions 16, p is set + The area of ​​contact region 18 is greater than the area of ​​n. + The area of ​​contact region 19. In other words, a pair of n-type contact regions arranged in the X direction. + In the region between the emitter regions 16, the area of ​​the first portion 2a1 in the XY plane is larger than the area of ​​the second portion 2a2 in the XY plane. As a result, in this pair of n + In the region between the emitter regions 16, p can be used + Type-18 contact region releases more holes and can suppress n + The potential rise of the p-type base region 15 near the p-type emitter region 16.

[0062] Most preferably, such as Figure 5 As shown, in the planar diagram, p + Type contact area 18 is set in a pair of n + The entire region between the emitter regions 16. In other words, most preferably, the first portion 2a1 is disposed on the pair of n. + Over the entire region between the 16 type emitter regions. In the planar diagram, n + Type contact area 19 is not located in a pair of n + Between type emitter regions 16. More specifically, n + The emitter region 16 includes a first end E1 and a second end E2 in the Y direction. + The contact area 18 includes a third end E3 and a fourth end E4 in the Y direction. The position P1 of the first end E1 in the Y direction and the position P2 of the second end E2 in the Y direction are located between the position P3 of the third end E3 in the Y direction and the position P4 of the fourth end E4 in the Y direction. Through this pair of n + p is set over the entire region between the emitter regions 16.+ Type-18 contact area further suppresses n + The potential of the p-type base region 15 near the p-type emitter region 16 increases. As a result, the operation of the parasitic thyristor can be suppressed more effectively.

[0063] It should be noted that in a planar diagram, n + Type contact area 19 can be set in a pair of n + Over the entire region between the type emitter regions 16, such as Figure 7 As shown. In this case, when setting n + Hole injection in a portion of the contact region 19 is also suppressed, and the amount of holes injected from the IGBT region R3 during the operation of the diode region R1 can be reduced. Additionally, during the operation of the diode region R1, electrons pass through n... + Contact region 19 is discharged to emitter 2, thereby reducing the discharge in n - The carrier density accumulated in the base region 13 is thus reduced. Therefore, the switching losses of the semiconductor device 100 can be reduced. However, from the perspective of suppressing parasitic thyristor operation, Figure 5 and Figure 6 The structure shown is preferred, as described above.

[0064] Figure 8A and Figure 8B It is shown Figure 1 Enlarged plan view of examples from parts VIIIA and VIIIB. Figure 8A and 8B In the original text, emitter 2 and insulating layer 22 are omitted.

[0065] like Figure 1 As shown, portion VIIIB is located in the Y direction between portion VIIIA and the outer edge of semiconductor device 100. The distance in the Y direction between portion VIIIB and the outer edge of semiconductor device 100 is shorter than the distance in the Y direction between portion VIIIA and the outer edge of semiconductor device 100. An outer peripheral region (termination region) is provided at the outer periphery of semiconductor layer S to improve the breakdown voltage of semiconductor device 100. In the outer peripheral region, diode region R1, IGBT region R2, and IGBT region R3 are not provided. Portion VIIIB is located on the outer peripheral region side of semiconductor device 100 relative to portion VIIIA.

[0066] For example, such as Figure 8A and 8B As shown, p in part VIIIB + The length L2b of the contact area 18 is similar to p in part of VIIIA. + The length L2a of the contact area 18 is the same. n in part VIIIB +The length L3b of the contact area 19 is similar to n in part of VIIIA. + The length L3a of the contact area 19 is the same. Throughout the entire IGBT region R3, p + Type contact areas 18 and n + The contact areas 19 are arranged at equal intervals.

[0067] Figure 9A , Figure 9B , Figure 10A and Figure 10B It is shown Figure 1 An enlarged plan view of another example of sections VIIIA and VIIIB. Figure 8A , 8B In 9A and 9B, the emitter 2 and the insulating layer 22 are omitted.

[0068] like Figure 9A and Figure 9B As shown, p in part VIIIB + The length L2b of the contact area 18 can be greater than that of p in part of VIIIA. + The length L2a of the contact area 18 is long, and n in part of VIIIB is also long. + The length L3b of the contact area 19 can be greater than that of n in part of VIIIA. + The length L3a of the contact area 19 is short. In other words, in Figure 9A and Figure 9B In the example shown, the closer to the outer periphery of the semiconductor device 100, the higher the p + The larger the area ratio of the contact region 18, and n + The smaller the area ratio of the contact region 19.

[0069] In the outer peripheral region of the semiconductor device 100, no emitter 2 is provided. When IGBT regions R2 and R3 are turned off, holes accumulated in the outer peripheral region pass through p located near the outer peripheral region. + Type contact area 17 and p + Discharge occurs in the p-type contact region 18. Therefore, near the outer peripheral region, the potential of the p-type base region 15 tends to rise, and the parasitic thyristor is more likely to operate. (As...) Figure 9A and Figure 9B As shown, through p + The area ratio of the p-type contact region 18 increases as it gets closer to the outer periphery of the semiconductor device 100, which can suppress the potential rise of the p-type base region 15 near the outer periphery. As a result, the operation of parasitic thyristors near the outer periphery can be suppressed.

[0070] Or, such as Figure 10A and 10B As shown, p in part VIIIB+ The length L2b of the contact area 18 can be shorter than p in part of VIIIA. + The length L2a of the contact area 18, and n in part VIIIB + The length L3b of the contact area 19 can be longer than n in part of VIIIA. + The length L3a of the contact area 19. In other words, in Figure 10A and 10B In the example shown, the closer to the outer periphery of the semiconductor device 100, the higher the p + The smaller the area ratio of contact region 18, and n + The larger the area ratio of the contact area 19, the better.

[0071] When diode region R1 switches from the on state to the off state, the accumulated n - Electrons and holes in the base region 13 of type n pass through n + Discharge occurs in the p-type cathode region 11 and the p-type anode region 14. Holes accumulated in the termination region move to the diode region R1 and discharge through the p-type anode region 14. Therefore, holes tend to accumulate in the p-type anode region 14 near the termination region. Figure 10A and 10B The structure shown shows that the closer to the outer periphery of the semiconductor device 100, the higher the p + The smaller the area ratio of contact region 18, and n + The larger the area ratio of the p-type contact region 19, the more carrier injection can be suppressed in the portion near the termination region during the operation of the diode region R1. When the diode region R1 switches to the off state, the amount of holes flowing into the p-type anode region 14 near the termination region can be reduced, and damage to the semiconductor device 100 due to current concentration can be suppressed.

[0072] Emitter 2 (contact 2a) and p in IGBT region R3 + Type 18 ohm contact area. When emitter 2 is connected to p + When the contact area is an 18-ohm contact, it can promote the movement of holes from p + The discharge from contact region 18 to emitter 2 occurs. Because holes can more easily pass through p... + The contact area 18 discharges to the emitter 2, thus suppressing the operation of the parasitic thyristor.

[0073] Emitter 2 (contact 2a) can interact with n in IGBT region R3 + The contact area is a 19-ohm contact or a Schottky contact. Preferably, the emitter 2 (contact 2a) and the n in the IGBT region R3 are... +Type 19 Schottky contact in contact area. When emitter 2 is connected to n + When a 19-ohm contact is used in the contact region, charge carriers can more easily pass between the emitter 2 and n. + The contact areas 19 move between each other. As a result, for example, switching losses during the reverse recovery operation of the diode in the semiconductor device 100 can be reduced.

[0074] When emitter 2 and n + When the contact area is a Schottky contact of type 19, at the emitter 2 and n + A potential barrier is formed between the contact regions 19. When n is set... + When the contact region 19 is formed, the thickness of the p-type base region 15 in the Z direction becomes smaller at the lower part of the contact portion 2a. Additionally, due to the use of n... + The implantation of n-type impurities in the p-type base region 15 may reduce the concentration of p-type impurities. Therefore, the breakdown voltage of the semiconductor device 100 may decrease. To address this issue, a Schottky contact forms a barrier that can suppress the decrease in the breakdown voltage of the semiconductor device 100. For example, when the semiconductor layer S comprises silicon as the semiconductor material, the emitter 2 comprises one or more materials selected from the group consisting of tungsten, platinum, gold, iridium, and aluminum.

[0075] Figure 11 This is a plan view showing a portion of a semiconductor device according to a variation of the first embodiment.

[0076] exist Figure 11 In the semiconductor device 110 shown, compared to the semiconductor device 100, the p-type diode provided in the diode region R1 is omitted. + Anode region 14a and conductive part 20. (Example) Figure 11 As shown, as long as n is set in IGBT region R3 + By using contact area 19, specific configurations in diode region R1 can be modified appropriately.

[0077] Second Implementation Method

[0078] Figure 12 This is a plan view showing a portion of a semiconductor device according to the second embodiment. Figure 13 yes Figure 12 XIII-XIII cross-sectional view. Figure 14 yes Figure 12 XIV-XIV cross-sectional view.

[0079] In the semiconductor device 200 according to the second embodiment, such as Figure 12 As shown, compared to the semiconductor device 100 according to the first embodiment, an insulating portion 25 is provided instead of n. + Type contact area 19.

[0080] Insulating part 25 is in the Y direction with p + The contact areas 18 are arranged side by side. In other words, when viewed from the Y direction, the insulating part 25 and p... + Type 18 contact areas overlap. For example... Figure 14 As shown, the insulating portion 25 is located between the p-type base region 15 and the contact portion 2a in the IGBT region R3. The insulating portion 25 includes an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0081] like Figure 14 As shown, the insulating portion 25 may be disposed only below the contact portion 2a, or it may be disposed both below and beside the contact portion 2a. Preferably, in order to increase the contact area between the contact portion 2a and the p-type base region 15, the insulating portion 25 is disposed only below the contact portion 2a.

[0082] like Figures 12 to 14 As shown, n in semiconductor device 100 + Structures other than the contact area 19 can be applied to structures other than the insulating portion 25 in the semiconductor device 200.

[0083] For example, as in Figure 5 In the example shown, a p + The length of the contact area 18 in the Y direction can be longer than the length of an insulating portion 25 in the Y direction. Alternatively, as in Figure 6 In the example shown, the length of an insulating portion 25 in the Y direction can be greater than that of a p. + The contact area 18 is long in the Y direction. Furthermore, as in... Figure 5 and Figure 6 In the example shown, it is preferred that n + The position of at least a portion of the emitter region 16 in the Y direction is related to p + At least a portion of the contact area 18 is positioned identically in the Y direction. For example, in a plan view, p + Type contact area 18 is located in a pair of n arranged in the X direction + At least a portion of the region between the type emitter regions 16.

[0084] More preferably, in a planar diagram, the pair of n arranged in the X direction + In the region between the emitter regions 16, p is set + The area of ​​the contact region 18 is larger than the area where the insulating part 25 is provided. Most preferably, as in... Figure 5 In the example shown, in the planar diagram, p + Type contact area 18 is set in a pair of n + The entire region between the 16 type emitter regions.

[0085] It should be noted that, in the plan view, the insulating part 25 can be provided in a pair of n + Over the entire region between the type emitter regions 16, such as Figure 7 The example shown. However, from the viewpoint of suppressing the operation of parasitic thyristors, it is preferable to use something similar to... Figure 5 and Figure 6 The structure shown in the example is applied to semiconductor device 200.

[0086] In addition, such as in Figure 9A and Figure 9B In the example shown, p + The area ratio of the contact region 18 can increase as it moves closer to the outer periphery of the semiconductor device 200, and the area ratio of the insulating portion 25 can decrease as it moves closer to the outer periphery of the semiconductor device 200. Alternatively, as in Figure 10A and 10B In the example shown, the area ratio of the insulating portion 25 can increase as it gets closer to the outer periphery of the semiconductor device 200, and p + The area ratio of the contact region 18 can decrease as it moves closer to the outer periphery of the semiconductor device 200. For example, in... Figure 11 As shown in the variant example, p can be omitted in the diode region R1. + Type anode region 14a and conductive part 20.

[0087] Even when insulation part 25 replaces n + When the p-type contact region 19 is used, hole injection from the emitter 2 to the p-type base region 15 is also suppressed during the operation of the diode region R1. As a result, the diode region R1 can operate faster, and the switching losses of the semiconductor device 200 can be reduced.

[0088] Third Implementation Method

[0089] Figure 15 This is a plan view showing a portion of a semiconductor device according to a third embodiment. Figure 16 yes Figure 14 XVI-XVI cross-sectional view. Figure 17 yes Figure 15 Cross-sectional view of XVII-XVII.

[0090] like Figure 16 and 17 As shown, the semiconductor device 300 according to the third embodiment differs from the semiconductor device 100 according to the first embodiment in that the emitter 2 does not include a contact portion 2a. In the semiconductor device 300, since the contact portion 2a is absent, n + Type emitter region 16, p+ Type contact area 17, p + Type contact areas 18 and n + The structure of the contact region 19 is different from that in the semiconductor device 100.

[0091] Specifically, in the IGBT region R2, n + Type 16 emitter region and p + The p-type contact region 17 is alternately disposed along the Y direction on a p-type base region 15. In IGBT region R3, n + Type 16 emitter region and p + The p-type contact region 18 is alternately disposed along the Y direction on a p-type base region 15. + Contact area 19 is p along the XY plane (first plane) + The contact area is surrounded by 18 types.

[0092] For example, p-type base region 15, n + Type emitter region 16, p + Type contact area 17 and p + The contact region 18 is in contact with the gate insulating layer 21a. + The contact region 19 is separated from the gate insulating layer 21a in the X direction. Additionally, n + Type contact area 19 is in the Y direction with n + Type 16 emitter region separation.

[0093] Similarly, in the semiconductor device 300 according to the third embodiment, by setting n + The p-type contact region 19 suppresses hole injection from the emitter 2 to the p-type base region 15 during the operation of the diode region R1. As a result, the operation of the diode region R1 can be further accelerated, and the switching losses of the semiconductor device 300 can be reduced.

[0094] In semiconductor device 300, n + The contact region 19 is separated from the gate insulating layer 21a in the X direction. Therefore, when IGBT regions R2 and R3 are in the on state, n + The contact area 19 is positioned away from the channel. (This is in contrast to n.) + Compared to the case where the contact region 19 and the gate insulating layer 21a are in contact, it is possible to suppress electrons from n + Type contact area 19 to n -The injection of the base region 13 is as follows. As a result, the current flowing from the emitter 2 to the collector 1 can be reduced, and the saturation current of the semiconductor device 300 can be reduced. For example, the current flowing through the semiconductor device 300 during a short circuit can be reduced, and damage caused by a short circuit can be suppressed. Therefore, it is preferable that n + The contact region 19 is separated from the gate insulating layer 21a in the X direction.

[0095] In addition, n + Type contact area 19 is in the Y direction with n + The emitter region 16 is separated. In this case, it is related to n. + Type contact area 19 is in the Y direction with n + Compared to the case of 16-type emitter region contact, p + The contact area 18 can be more widely set in n + The emitter region is near type 16. In n + Near the emitter region 16, the potential rise in the p-type base region 15 is suppressed. Therefore, the operation of the parasitic thyristor can be suppressed. Therefore, it is preferable that the n-type emitter region 16 is located near the base region 15. + Type contact area 19 is in the Y direction with n + Type 16 emitter region separation.

[0096] In this specification, the term "or" means that at least one of the items listed in the sentence may be used.

[0097] The embodiments of the present invention include the following features.

[0098] Feature 1

[0099] A semiconductor device, comprising:

[0100] First electrode;

[0101] The second electrode is separated from the first electrode in a first direction; and

[0102] A semiconductor layer is disposed between the first electrode and the second electrode. The semiconductor layer includes a first region, a second region, and a third region located between the first region and the second region in a second direction perpendicular to the first direction. The semiconductor layer includes:

[0103] A first semiconductor region of a first conductivity type is disposed in the first region;

[0104] A second semiconductor region of a second conductivity type is disposed in the second region;

[0105] A third semiconductor region of the first conductivity type is disposed on the first semiconductor region and the second semiconductor region;

[0106] A fourth semiconductor region of the second conductivity type is disposed above the third semiconductor region, and the fourth semiconductor region is located in the first region;

[0107] A plurality of fifth semiconductor regions of the second conductivity type are disposed on the third semiconductor region, and the plurality of fifth semiconductor regions are located in the second region and the third region;

[0108] Multiple gate electrodes are respectively opposed to the multiple fifth semiconductor regions in the second direction, separated by multiple gate insulating layers;

[0109] A plurality of sixth semiconductor regions of the first conductivity type are respectively disposed on the plurality of fifth semiconductor regions, and the plurality of sixth semiconductor regions are respectively in contact with a plurality of contact portions of the second electrode in the second direction;

[0110] A seventh semiconductor region of the second conductivity type is disposed between one of the plurality of fifth semiconductor regions and one of the plurality of contacts in the second region; and

[0111] The eighth semiconductor region of the second conductivity type and the ninth semiconductor region of the first conductivity type are respectively disposed in the third region between another fifth semiconductor region of the plurality of fifth semiconductor regions and another contact of the plurality of contact portions.

[0112] Feature 2

[0113] The semiconductor device according to feature 1, wherein...

[0114] In the third region, the eighth semiconductor region and the ninth semiconductor region are alternately arranged along a third direction.

[0115] The third direction is perpendicular to the first direction and the second direction.

[0116] Feature 3

[0117] The semiconductor device according to feature 1 or 2, wherein,

[0118] In the third region, at least a portion of one of the plurality of sixth semiconductor regions is located in the same third-direction orientation as at least a portion of the eighth semiconductor region.

[0119] The third direction is perpendicular to the first direction and the second direction.

[0120] Feature 4

[0121] The semiconductor device according to any one of features 1 to 3, wherein...

[0122] In the third region, a pair of sixth semiconductor regions, separated from each other in the second direction, are disposed on one of the plurality of fifth semiconductor regions.

[0123] One of the plurality of contact portions includes:

[0124] The first part is located above the eighth semiconductor region, and

[0125] The second part is located above the ninth semiconductor region.

[0126] At least a portion of the first portion is located between the pair of sixth semiconductor regions in the second direction.

[0127] Feature 5

[0128] The semiconductor device according to any one of features 1 to 3, wherein...

[0129] In the third region, a pair of sixth semiconductor regions, separated from each other in the second direction, are disposed on one of the plurality of fifth semiconductor regions.

[0130] One of the plurality of contact portions includes:

[0131] The first part is located above the eighth semiconductor region, and

[0132] The second part is located above the ninth semiconductor region.

[0133] The first portion is located over the entire region between the pair of sixth semiconductor regions.

[0134] Feature 6

[0135] The semiconductor device according to any one of features 1 to 5, wherein...

[0136] In the third region, two or more sixth semiconductor regions are disposed on one of the plurality of fifth semiconductor regions.

[0137] The two or more sixth semiconductor regions are separated from each other in a third direction perpendicular to the first direction and the second direction.

[0138] Above one of the plurality of fifth semiconductor regions, the distance between adjacent sixth semiconductor regions in the third direction among the two or more sixth semiconductor regions is greater than the length of one of the six semiconductor regions in the third direction.

[0139] Feature 7

[0140] The semiconductor device according to any one of features 1 to 6, wherein,

[0141] The length of the eighth semiconductor region in the third direction is greater than the length of the ninth semiconductor region in the third direction.

[0142] The third direction is perpendicular to the first direction and the second direction.

[0143] Feature 8

[0144] The semiconductor device according to any one of features 1 to 3, wherein...

[0145] In the third region, a pair of sixth semiconductor regions, separated from each other in the second direction, are disposed on one of the plurality of fifth semiconductor regions.

[0146] One of the plurality of contact portions includes:

[0147] The first part is located above the eighth semiconductor region, and

[0148] The second part is located above the ninth semiconductor region.

[0149] In the region between the pair of sixth semiconductor regions, the area of ​​the first portion along the first plane is larger than the area of ​​the second portion along the first plane.

[0150] The first plane is perpendicular to the first direction.

[0151] Feature 9

[0152] The semiconductor device according to any one of features 1 to 8, wherein...

[0153] The plurality of contact portions protrude toward the semiconductor layer.

[0154] The seventh semiconductor region, the eighth semiconductor region, and the ninth semiconductor region are located below the plurality of contacts.

[0155] Feature 10

[0156] A semiconductor device, comprising:

[0157] First electrode;

[0158] The second electrode is separated from the first electrode in a first direction; and

[0159] A semiconductor layer is disposed between the first electrode and the second electrode. The semiconductor layer includes a first region, a second region, and a third region located between the first region and the second region in a second direction perpendicular to the first direction. The semiconductor layer includes:

[0160] A first semiconductor region of a first conductivity type is disposed in the first region;

[0161] A second semiconductor region of a second conductivity type is disposed in the second region;

[0162] A third semiconductor region of the first conductivity type is disposed on the first semiconductor region and the second semiconductor region;

[0163] A fourth semiconductor region of the second conductivity type is disposed above the third semiconductor region, and the fourth semiconductor region is located in the first region;

[0164] A plurality of fifth semiconductor regions of the second conductivity type are disposed on the third semiconductor region, and the plurality of fifth semiconductor regions are located in the second region and the third region;

[0165] Multiple gate electrodes are respectively opposed to the multiple fifth semiconductor regions in the second direction, separated by multiple gate insulating layers;

[0166] A plurality of sixth semiconductor regions of the first conductivity type are respectively disposed on the plurality of fifth semiconductor regions, and the plurality of sixth semiconductor regions are respectively in contact with a plurality of contact portions of the second electrode in the second direction;

[0167] The seventh semiconductor region of the second conductivity type is disposed between the first fifth semiconductor region of the plurality of fifth semiconductor regions and the first contact of the plurality of contacts in the second region;

[0168] An eighth semiconductor region of the second conductivity type is disposed in the third region between a second fifth semiconductor region among the plurality of fifth semiconductor regions and a second contact among the plurality of contacts; and

[0169] An insulating portion is disposed between the second fifth semiconductor region among the plurality of fifth semiconductor regions and the second contact portion among the plurality of contact portions, the insulating portion being parallel to the eighth semiconductor region in a third direction perpendicular to the first direction and the second direction.

[0170] Feature 11

[0171] The semiconductor device according to feature 10, wherein...

[0172] In the third region, the eighth semiconductor region and the insulating portion are alternately arranged along the third direction.

[0173] Feature 12

[0174] The semiconductor device according to feature 10 or 11, wherein,

[0175] In the third region, at least a portion of one of the plurality of sixth semiconductor regions is positioned in the third direction at the same location as at least a portion of the eighth semiconductor region in the third direction.

[0176] Feature 13

[0177] A semiconductor device, comprising:

[0178] First electrode;

[0179] The second electrode is separated from the first electrode in a first direction; and

[0180] A semiconductor layer is disposed between the first electrode and the second electrode. The semiconductor layer includes a first region, a second region, and a third region located between the first region and the second region in a second direction perpendicular to the first direction. The semiconductor layer includes:

[0181] A first semiconductor region of a first conductivity type is disposed in the first region;

[0182] A second semiconductor region of a second conductivity type is disposed in the second region;

[0183] A third semiconductor region of the first conductivity type is disposed on the first semiconductor region and the second semiconductor region;

[0184] A fourth semiconductor region of the second conductivity type is disposed above the third semiconductor region, and the fourth semiconductor region is located in the first region;

[0185] A plurality of fifth semiconductor regions of the second conductivity type are disposed on the third semiconductor region, and the plurality of fifth semiconductor regions are located in the second region and the third region;

[0186] Multiple gate electrodes are respectively opposed to the multiple fifth semiconductor regions in the second direction, separated by multiple gate insulating layers;

[0187] The plurality of sixth semiconductor regions of the first conductivity type are respectively disposed on the plurality of fifth semiconductor regions;

[0188] The seventh semiconductor region of the second conductivity type is disposed above the first fifth semiconductor region of the plurality of fifth semiconductor regions, and the seventh semiconductor region is located in the second region;

[0189] An eighth semiconductor region of the second conductivity type is disposed above a second fifth semiconductor region among the plurality of fifth semiconductor regions, the eighth semiconductor region being located in the third region; and

[0190] A ninth semiconductor region of the first conductivity type is disposed above the second fifth semiconductor region among the plurality of fifth semiconductor regions, the ninth semiconductor region being located in the third region and surrounded by the eighth semiconductor region along a first plane perpendicular to the first direction.

[0191] Feature 14

[0192] The semiconductor device according to feature 13, wherein...

[0193] In the third region, the sixth semiconductor region and the eighth semiconductor region are alternately disposed on the second fifth semiconductor region among the plurality of fifth semiconductor regions along a third direction.

[0194] The third direction is perpendicular to both the first direction and the second direction.

[0195] Each of the plurality of ninth semiconductor regions is surrounded by a plurality of eighth semiconductor regions.

[0196] According to the above embodiments, a semiconductor device is provided that can reduce switching losses when the diode is in operation.

[0197] In the above embodiments, for example, scanning capacitance microscopy (SCM) can be used to confirm the relative levels of impurity concentration between semiconductor regions. The carrier concentration in each semiconductor region can be considered equal to the active impurity concentration in each semiconductor region. Therefore, SCM can also be used to confirm the relative levels of carrier concentration between semiconductor regions. The impurity concentration in each semiconductor region can be measured, for example, using secondary ion mass spectrometry (SIMS).

[0198] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover these forms or modifications that fall within the scope and spirit of the invention. Furthermore, the above embodiments can be combined with each other and can be practiced.

Claims

1. A semiconductor device, comprising: First electrode; The second electrode is separated from the first electrode in a first direction; as well as A semiconductor layer is disposed between the first electrode and the second electrode. The semiconductor layer includes a first region, a second region, and a third region located between the first region and the second region in a second direction perpendicular to the first direction. The semiconductor layer includes: A first semiconductor region of a first conductivity type is disposed in the first region; A second semiconductor region of a second conductivity type is disposed in the second region; A third semiconductor region of the first conductivity type is disposed on the first semiconductor region and the second semiconductor region; A fourth semiconductor region of the second conductivity type is disposed above the third semiconductor region, and the fourth semiconductor region is located in the first region; A plurality of fifth semiconductor regions of the second conductivity type are disposed on the third semiconductor region, and the plurality of fifth semiconductor regions are located in the second region and the third region; Multiple gate electrodes are respectively opposed to the multiple fifth semiconductor regions in the second direction, separated by multiple gate insulating layers; A plurality of sixth semiconductor regions of the first conductivity type are respectively disposed on the plurality of fifth semiconductor regions, and the plurality of sixth semiconductor regions are respectively in contact with a plurality of contact portions of the second electrode in the second direction; A seventh semiconductor region of the second conductivity type is disposed between one of the plurality of fifth semiconductor regions and one of the plurality of contacts in the second region; and The eighth semiconductor region of the second conductivity type and the ninth semiconductor region of the first conductivity type are respectively disposed in the third region between another fifth semiconductor region of the plurality of fifth semiconductor regions and another contact of the plurality of contact portions.

2. The semiconductor device according to claim 1, wherein, In the third region, the eighth semiconductor region and the ninth semiconductor region are alternately arranged along a third direction. The third direction is perpendicular to the first direction and the second direction.

3. The semiconductor device according to claim 1, wherein, In the third region, at least a portion of one of the plurality of sixth semiconductor regions is located in the same third-direction orientation as at least a portion of the eighth semiconductor region. The third direction is perpendicular to the first direction and the second direction.

4. The semiconductor device according to claim 1, wherein, In the third region, a pair of sixth semiconductor regions, separated from each other in the second direction, are disposed on one of the plurality of fifth semiconductor regions. One of the plurality of contact portions includes: The first part is located above the eighth semiconductor region, and The second part is located above the ninth semiconductor region. At least a portion of the first portion is located between the pair of sixth semiconductor regions in the second direction.

5. The semiconductor device according to claim 1, wherein, In the third region, a pair of sixth semiconductor regions, separated from each other in the second direction, are disposed on one of the plurality of fifth semiconductor regions. One of the plurality of contact portions includes: The first part is located above the eighth semiconductor region, and The second part is located above the ninth semiconductor region. The first portion is located over the entire region between the pair of sixth semiconductor regions.

6. The semiconductor device according to claim 1, wherein, In the third region, two or more sixth semiconductor regions are disposed on one of the plurality of fifth semiconductor regions. The two or more sixth semiconductor regions are separated from each other in a third direction perpendicular to the first direction and the second direction. Above one of the plurality of fifth semiconductor regions, the distance between adjacent sixth semiconductor regions in the third direction among the two or more sixth semiconductor regions is greater than the length of one of the six semiconductor regions in the third direction.

7. The semiconductor device according to claim 1, wherein, The length of the eighth semiconductor region in the third direction is greater than the length of the ninth semiconductor region in the third direction. The third direction is perpendicular to the first direction and the second direction.

8. The semiconductor device according to claim 1, wherein, In the third region, a pair of sixth semiconductor regions, separated from each other in the second direction, are disposed on one of the plurality of fifth semiconductor regions. One of the plurality of contact portions includes: The first part is located above the eighth semiconductor region, and The second part is located above the ninth semiconductor region. In the region between the pair of sixth semiconductor regions, the area of ​​the first portion along the first plane is greater than the area of ​​the second portion along the first plane. The first plane is perpendicular to the first direction.

9. The semiconductor device according to claim 1, wherein, The plurality of contact portions protrude toward the semiconductor layer. The seventh semiconductor region, the eighth semiconductor region, and the ninth semiconductor region are located below the plurality of contacts.

10. A semiconductor device, comprising: First electrode; The second electrode is separated from the first electrode in a first direction; as well as A semiconductor layer is disposed between the first electrode and the second electrode. The semiconductor layer includes a first region, a second region, and a third region located between the first region and the second region in a second direction perpendicular to the first direction. The semiconductor layer includes: A first semiconductor region of a first conductivity type is disposed in the first region; A second semiconductor region of a second conductivity type is disposed in the second region; A third semiconductor region of the first conductivity type is disposed on the first semiconductor region and the second semiconductor region; A fourth semiconductor region of the second conductivity type is disposed above the third semiconductor region, and the fourth semiconductor region is located in the first region; A plurality of fifth semiconductor regions of the second conductivity type are disposed on the third semiconductor region, and the plurality of fifth semiconductor regions are located in the second region and the third region; Multiple gate electrodes are respectively opposed to the multiple fifth semiconductor regions in the second direction, separated by multiple gate insulating layers; A plurality of sixth semiconductor regions of the first conductivity type are respectively disposed on the plurality of fifth semiconductor regions, and the plurality of sixth semiconductor regions are respectively in contact with a plurality of contact portions of the second electrode in the second direction; The seventh semiconductor region of the second conductivity type is disposed between the first fifth semiconductor region of the plurality of fifth semiconductor regions and the first contact of the plurality of contacts in the second region; An eighth semiconductor region of the second conductivity type is disposed in the third region between a second fifth semiconductor region among the plurality of fifth semiconductor regions and a second contact among the plurality of contacts; and An insulating portion is disposed between the second fifth semiconductor region among the plurality of fifth semiconductor regions and the second contact portion among the plurality of contact portions, the insulating portion being parallel to the eighth semiconductor region in a third direction perpendicular to the first direction and the second direction.

11. The semiconductor device according to claim 10, wherein, In the third region, the eighth semiconductor region and the insulating portion are alternately arranged along the third direction.

12. The semiconductor device according to claim 10, wherein, In the third region, at least a portion of one of the plurality of sixth semiconductor regions is positioned in the third direction at the same location as at least a portion of the eighth semiconductor region in the third direction.

13. A semiconductor device, comprising: First electrode; The second electrode is separated from the first electrode in a first direction; as well as A semiconductor layer is disposed between the first electrode and the second electrode. The semiconductor layer includes a first region, a second region, and a third region located between the first region and the second region in a second direction perpendicular to the first direction. The semiconductor layer includes: A first semiconductor region of a first conductivity type is disposed in the first region; A second semiconductor region of a second conductivity type is disposed in the second region; A third semiconductor region of the first conductivity type is disposed on the first semiconductor region and the second semiconductor region; A fourth semiconductor region of the second conductivity type is disposed above the third semiconductor region, and the fourth semiconductor region is located in the first region; A plurality of fifth semiconductor regions of the second conductivity type are disposed on the third semiconductor region, and the plurality of fifth semiconductor regions are located in the second region and the third region; Multiple gate electrodes are respectively opposed to the multiple fifth semiconductor regions in the second direction, separated by multiple gate insulating layers; The plurality of sixth semiconductor regions of the first conductivity type are respectively disposed on the plurality of fifth semiconductor regions; The seventh semiconductor region of the second conductivity type is disposed above the first fifth semiconductor region of the plurality of fifth semiconductor regions, and the seventh semiconductor region is located in the second region; An eighth semiconductor region of the second conductivity type is disposed above a second fifth semiconductor region among the plurality of fifth semiconductor regions, the eighth semiconductor region being located in the third region; and A ninth semiconductor region of the first conductivity type is disposed above the second fifth semiconductor region among the plurality of fifth semiconductor regions, the ninth semiconductor region being located in the third region and surrounded by the eighth semiconductor region along a first plane perpendicular to the first direction.

14. The semiconductor device according to claim 13, wherein, In the third region, the sixth semiconductor region and the eighth semiconductor region are alternately disposed above the second fifth semiconductor region among the plurality of fifth semiconductor regions along a third direction. The third direction is perpendicular to both the first direction and the second direction. Each of the plurality of ninth semiconductor regions is surrounded by a plurality of eighth semiconductor regions.

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