High reliability IGBT integrated with depletion mode MOS

Abstract

This invention discloses a high-reliability IGBT with integrated depletion-type MOS, comprising a P-base region (1), a P+ emitter region (2), an N+ emitter region (3), a floating hole collection P+ region (4), a depletion-type MOS P1+ region (5), a depletion-layer MOS oxide gate (6), a depletion-layer MOS channel region (7), a depletion-type MOS P2+ region (8); a depletion-type N-base region (9), a floating P region (10), an N-type carrier storage layer (11), an N-type drift region (12), an N-type electric field buffer layer (13), and a collector P+ region (14). By introducing a depletion-layer MOS, the floating P region can adapt to the device's operating state and change its potential. During conduction, a hole channel is provided through the MOS, preventing excessive hole accumulation at the trench gate during turn-on, thus ensuring the voltage and current change rate during conduction and mitigating EMI. After normal conduction, this depletion-type MOSFET will pinch off, ensuring that holes accumulate in the floating region under normal conduction, thus guaranteeing a low on-state voltage. Under high current, a large number of holes accumulate in the floating P-region, causing its potential to rise. This leads to a decrease in the gate-source voltage of the depletion-type MOSFET, allowing the holes to be extracted from the device, preventing latch-up, and improving the device's short-circuit withstand capability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a high-reliability IGBT with integrated depletion-type MOS. Background Technology

[0002] Insulated Gate Bipolar Transistor (IGBT) combines the advantages of MOSFET and Bipolar Junction Transistor (BJT), offering low drive power, fast switching speed, and strong current capability. It is mainly targeted at the medium-to-high power and medium-to-high frequency market and is widely used in industrial, automotive electronics, and consumer electronics fields.

[0003] One of the most common IGBT failures is short-circuit failure. In this situation, the device is subjected to simultaneous high voltage and high current surges, causing a rapid rise in junction temperature. If not turned off in time or if the device's own withstand capability is insufficient, permanent failure will occur. Especially in IGBTs with a floating P-region structure, a large number of holes are injected into the floating P-region during a short circuit, easily causing the potential in this region to rise and triggering parasitic NPN transistors, leading to latch-up effects and further deteriorating short-circuit withstand capability. In addition, the drastic fluctuations in the floating P-region potential during switching can also generate high electromagnetic interference (EMI) through Miller capacitance coupling, affecting system stability. With the widespread application of IGBTs in important applications such as motor drives and power conversion, the requirements for their short-circuit robustness and EMI characteristics are increasing. Therefore, designing a new IGBT structure that can adaptively adjust the floating P-region potential, suppress latch-up during short circuits, and alleviate EMI during switching has significant engineering value for improving device reliability, reducing system failure rates, and saving costs.

[0004] To address the aforementioned problems, this invention is proposed. Summary of the Invention

[0005] This invention provides a high-reliability IGBT with integrated depletion-mode MOS, which improves the short-circuit withstand capability and mitigates EMI effects during switching while minimizing the impact on forward conduction voltage, thereby enhancing the reliability of the device operation.

[0006] To achieve the above objectives, the present invention proposes the following technical solution:

[0007] A high-reliability IGBT with integrated depletion-type MOS includes: a P-base region 1, a P+ emitter region 2, an N+ emitter region 3, a floating hole collection P+ region 4, a depletion-type MOS P1+ region 5, a depletion-layer MOS oxide gate 6, a depletion-layer MOS channel region 7, a depletion-type MOS P2+ region 8, a depletion-type N-base region 9, a floating P region 10, an N-type carrier storage layer 11, an N-type drift region 12, an N-type electric field buffer layer 13, and a collector P+ region 14.

[0008] A traditional FP-IGBT device consists of a P-base region 1, a P+ emitter region 2, an N+ emitter region 3, a depletion-type N-base region 9, a floating P-region 10, an N-type carrier storage layer 11, an N-type drift region 12, an N-type electric field buffer layer 13, and a collector P+ region 14.

[0009] The depletion layer MOS is located inside the floating P region 10 and is isolated from the conventional IGBT structure by an oxide layer;

[0010] The depletion-type MOS P1+ region 5 and the floating hole collection P+ region 4 of the depletion layer MOS are connected through a floating electrode; the depletion-type MOS oxide gate 6 is connected to the gate of the IGBT; the depletion-type MOS channel region 7 is located below the depletion-type MOS oxide gate 6 and sandwiched between the depletion-type MOS P1+ region 5 and the depletion-type MOS P2+ region 8; the depletion-type MOS P2+ region 8 is connected to the emitter of the IGBT.

[0011] Furthermore, at a relatively low gate voltage (i.e., in the initial stage of the turn-on process), the integrated depletion-type PMOS remains on, connecting the originally floating P-region to the emitter through the PMOS, thus reducing a portion of the Miller capacitance (C). GC ) is transformed into gate-emitter capacitance (C) GE This reduces Miller capacitance, suppresses high dv / dt interference to the gate through Miller capacitance, and mitigates voltage spikes and electromagnetic interference (EMI) effects during switching.

[0012] Furthermore, when the gate voltage is high under normal conduction conditions, the integrated depletion-type PMOS is in the off state, and the floating P region remains floating, causing holes to accumulate in the floating P region and strengthening the carrier aggregation effect, thereby ensuring a low forward conduction voltage drop.

[0013] Furthermore, under high current (such as short circuit) conditions, the floating P region experiences a potential increase due to the accumulation of a large number of holes, causing the gate-source voltage of the depletion-type PMOS to drop below the threshold. The PMOS channel then turns on again, extracting the accumulated holes from the device and preventing the floating P region from triggering parasitic NPN transistors and latch-up effects due to excessively high potential, thereby significantly improving the short-circuit withstand capability of the device.

[0014] The beneficial effects of this invention are as follows: Based on traditional IGBT devices, this invention integrates a depletion-type PMOS within the floating P-region. Through adaptive adjustment of the gate voltage and the floating P-region potential, performance optimization under various operating conditions is achieved. During low gate voltage turn-on, the PMOS conducts to reduce Miller capacitance and suppress EMI; during normal conduction, the PMOS is turned off to maintain a low on-state voltage drop; during high-current short circuits, the PMOS automatically turns on to extract holes and prevent latch-up. This structure significantly improves the short-circuit withstand capability and reliability of the device while minimizing the impact on the forward conduction voltage.

[0015] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0016] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0017] Figure 1 This is a schematic diagram and a cross-sectional view of the novel IGBT device according to Embodiment 1 of the present invention;

[0018] Figure 2 This is the forward conduction voltage curve of the present invention and the FP-IGBT;

[0019] Figure 3 This is a short-circuit curve diagram of the present invention and FP-IGBT;

[0020] Figure 4 This invention relates to the gate voltage-gate charge diagram of FP-IGBT;

[0021] Figure 5 The turn-on curves of the FP-IGBT are shown for different gate resistances.

[0022] Figure 6 The turn-on curves of the device under different gate resistances according to the present invention are shown.

[0023] The attached diagram is labeled as follows: P-base region 1, P+ emitter region 2, N+ emitter region 3, floating hole collection P+ region 4, depletion-type MOS P1+ region 5, depletion-layer MOS oxide gate 6, depletion-layer MOS channel region 7, depletion-type MOS P2+ region 8, depletion-type N-base region 9, floating P region 10, N-type carrier storage layer 11, N-type drift region 12, N-type electric field buffer layer 13, collector P+ region 14. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0026] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0027] Example 1:

[0028] like Figure 1 As shown, this embodiment improves upon the traditional FP (floating P-region)-IGBT device by providing a high-reliability IGBT with integrated depletion-type MOS, including a P-base region 1, a P+ emitter region 2, an N+ emitter region 3, a floating hole collection P+ region 4, a depletion-type MOS P1+ region 5, a depletion-layer MOS oxide gate 6, a depletion-layer MOS channel region 7, a depletion-type MOS P2+ region 8, a depletion-type N-base region 9, a floating P-region 10, an N-type carrier storage layer 11, an N-type drift region 12, an N-type electric field buffer layer 13, and a collector P+ region 14.

[0029] During the forward turn-on process, when the gate voltage is low, the integrated depletion-type PMOS turns on, connecting the floating P-region to the emitter. This transforms part of the Miller capacitance into gate-emitter capacitance, reducing the interference of dv / dt on the gate and thus suppressing voltage spikes and EMI effects during switching. Under normal conduction conditions, when the gate voltage is high, the integrated depletion-type PMOS turns off, and the floating P-region remains floating. Hole accumulation enhances the carrier aggregation effect, thereby ensuring a low forward conduction voltage drop. Under high current (such as short circuit) conditions, the floating P-region experiences a potential rise due to the accumulation of a large number of holes, causing the gate-source voltage of the depletion-type PMOS to drop below the threshold. The PMOS then automatically turns on, extracting holes from the device and preventing the floating P-region from triggering parasitic NPN transistors and latch-up due to excessively high potential, thus significantly improving short-circuit withstand capability.

[0030] Figure 2 The figure shows the forward conduction curves of Example 1 and FP-IGBT. The forward conduction capability of Example 1 is slightly weaker than that of FP-IGBT, but its 100A / cm 2 The forward conduction voltage is 2.289V (the two are very close).

[0031] Figure 3 The figure shows the short-circuit characteristic curves of Example 1 and FP-IGBT. From the figure, it can be seen that the short-circuit withstand capability of the device in Example 1 is significantly stronger than that of FP-IGBT, with an improvement of about 3.3μs.

[0032] Figure 4 The diagram shows the gate voltage-gate charge of Example 1 and the FP-IGBT. It can be seen that Example 1 significantly reduces the Miller plateau compared to the FP-IGBT.

[0033] Figure 5 The voltage and current curves of the FP-IGBT during the forward turn-on process are mainly used as... Figure 6 A comparison chart.

[0034] Figure 6 The voltage and current curves for the forward turn-on process of Example 1 show that, clearly, Example 1 exhibits the best controllability under different gate resistances, with a significant decrease in dv / dt and di / dt.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. This invention discloses a high-reliability IGBT with integrated depletion-mode MOS, comprising: P-base region (1), P+ emitter region (2), N+ emitter region (3), floating hole collection P+ region (4), depletion-type MOS P1+ region (5), depletion-layer MOS oxide gate (6), depletion-layer MOS channel region (7), depletion-type MOS P2+ region (8), depletion-type N-base region (9), floating P region (10), N-type carrier storage layer (11), N-type drift region (12), N-type electric field buffer layer (13), collector P+ region (14); Traditional FP-IGBT devices consist of a P-base region (1), a P+ emitter region (2), an N+ emitter region (3), a depletion-type N-base region (9), a floating P region (10), an N-type carrier storage layer (11), an N-type drift region (12), an N-type electric field buffer layer (13), and a collector P+ region (14). The depletion layer MOS is located inside the floating P region (10) and is isolated from the conventional IGBT structure by an oxide layer; The depletion-type MOS P1+ region (5) of the depletion layer MOS and the floating hole collection P+ region (4) are connected through a floating electrode; the depletion-type MOS oxide gate (6) is connected to the gate of the IGBT; the depletion-type MOS channel region (7) is located below the depletion-type MOS oxide gate (6) and sandwiched between the depletion-type MOS P1+ region (5) and the depletion-type MOS P2+ region (8); the depletion-type MOS P2+ region (8) is connected to the emitter of the IGBT.

2. The high-reliability IGBT with integrated depletion-mode MOS according to claim 1, characterized in that, Including depletion-type MOS: floating hole collection P+ region (4), depletion-type MOS P1+ region (5), depletion layer MOS oxide gate (6), depletion layer MOS channel region (7), depletion-type MOS P2+ region (8), and depletion-type N-base region (9).

3. A high-reliability IGBT with integrated depletion-type MOS according to claim 1, characterized in that, The floating P-region integrates a depletion-type PMOS, which remains on under a relatively small gate voltage. This connects the originally floating P-region to the emitter via the PMOS, thus converting a portion of the C... GC It became C GE This reduces the Miller capacitance, thereby reducing the interference of dv / dt on the gate through the Miller capacitance and suppressing voltage spikes during the switching process.

4. The high-reliability IGBT with integrated depletion-type MOS as described in claim 1, when the gate voltage is large, its integrated depletion-type MOS is turned off, and the floating P region will continue to remain in a floating state, ensuring a low forward conduction voltage.

5. The high-reliability IGBT with integrated depletion-type MOS according to claim 1, under high current, a large number of holes accumulate in the floating P region, causing its potential to rise, which in turn reduces the gate-source voltage of the depletion-type MOS, forms a channel, and the holes are extracted from the device, avoiding latch-up and improving the short-circuit withstand capability of the device.

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