An IGBT device with improved anti-latch-up capability and a method of manufacturing the same

Abstract

The application belongs to the technical field of semiconductor, and particularly relates to an IGBT device with improved anti-latch-up capability and a preparation method thereof. The IGBT device comprises a collector, a buffer layer, a drift region, a carrier storage layer, a P-type base region, an N+ emitter region and a P+ anti-latch-up region alternately arranged on the upper surface of the P-type base region, and an emitter in ohmic contact with the P-type base region, the N+ emitter region and the P+ anti-latch-up region. The path of holes flowing into the emitter through the low-resistivity P+ anti-latch-up region is increased, and the total resistance of the conduction path is reduced. Even if the main discharge path of the hole carriers at the bottom of the N+ emitter region is blocked due to large-size defects in the manufacturing process, the holes can still be discharged efficiently through the P+ anti-latch-up region, thereby effectively inhibiting the increase of local voltage drop caused by current bypassing and avoiding the triggering of the parasitic thyristor. Therefore, the anti-latch-up capability of the IGBT device and the tolerance to process defects generated under non-ideal manufacturing conditions are improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to an IGBT device with improved latch-up resistance and its fabrication method. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs), as important power semiconductor devices, are widely used in power electronics due to their combination of the high input impedance of MOSFETs and the low on-state voltage drop of BJTs. However, the inherent parasitic thyristor (PNPN structure) within IGBTs makes them prone to latch-up under certain operating conditions, leading to device runaway or even permanent damage.

[0003] To suppress latch-up, existing technologies typically reduce the bulk resistance of the P-base region by optimizing the device structure, such as reducing the emitter contact spacing or increasing the P+ doped region, to provide a low-resistance discharge path for hole carriers, thereby avoiding the forward bias of the PN junction formed between the P-base and the N+ emitter region and triggering latch-up.

[0004] However, various process defects are inevitably introduced during actual semiconductor manufacturing. In particular, when the defect size is large (e.g., exceeding the size of a contact hole), it may completely block the shortest, lowest-resistance path for hole carriers from the bottom P-type base region of an N+ emitter region (N+ source) to flow into the emitter metal layer through the nearest contact hole above it. In this case, the hole current is forced to take a longer route, resulting in a significant increase in local voltage drop. Once this voltage drop exceeds the turn-on voltage of the adjacent PN junction, it triggers the parasitic thyristor to conduct, causing latch-up failure. Summary of the Invention

[0005] The technical problem to be solved by this application is to provide an IGBT device with improved anti-latch-up capability and its fabrication method, thereby improving the device's tolerance to manufacturing defects and overall anti-latch-up capability.

[0006] In a first aspect, this application provides an IGBT device with improved latch-up resistance, comprising: The following components are arranged sequentially from bottom to top: collector, buffer layer, drift region, carrier storage layer, P-type base region, N+ emitter region and P+ latch-up region alternately arranged on the upper surface of the P-type base region and on the same horizontal plane, and emitter in ohmic contact with the P-type base region, N+ emitter region and P+ latch-up region. The P+ anti-latch-up region is disposed between two adjacent N+ emission regions; The P+ anti-latch-up region contacts the P-type base region and is configured to provide a parallel, low-resistance auxiliary current path when the main path of hole carriers flowing from the bottom of the N+ emitter region to the emitter metal layer is blocked.

[0007] Optionally, the IGBT device with improved latch-up resistance further includes two trench gates embedded on both sides of the IGBT device, the trench gates passing through the N+ emitter region, the P+ latch-up region, the P-type base region and the carrier storage layer, and extending deep into the drift region, and the inner surface of the trench gates has a gate oxide layer.

[0008] Optionally, the emitter has a central lower protrusion that penetrates the middle portion of the N+ emitter region and the P+ anti-latch-up region and extends deep into the P-type base region. An insulating layer is provided on the bottom surface of the emitter, excluding the central lower protrusion.

[0009] Optionally, the doping concentration of the P+ anti-latch-up region is higher than the doping concentration of the P-type base region.

[0010] Optionally, the doping concentration of the collector is 10. 16 ~10 17 / cm 3 The doping concentration of the buffer layer is 10. 15 ~10 16 / cm 3 The doping concentration of the drift region is 10. 13 ~10 14 / cm 3 The doping concentration of the carrier storage layer is 10. 14 ~10 15 / cm 3 The doping concentration of the P-type base region is 10. 16 ~10 17 / cm 3 The doping concentration of the N+ emitter region is 10. 19 ~10 20 / cm 3 The doping concentration of the P+ anti-latch-up region is 10. 18 ~10 19 / cm 3 .

[0011] Optionally, the doping element of the collector, the P-type base region, and the P+ anti-latch-up region is boron; the doping element of the buffer layer, the drift region, and the carrier storage layer is phosphorus; and the doping element of the N+ emitter region is arsenic.

[0012] Optionally, the width of the N+ emission region ranges from 0.5 μm to 2.0 μm.

[0013] Secondly, this application provides a method for fabricating the IGBT device with improved anti-latch-up capability, comprising the following steps: A collector, a buffer layer, a drift region, and a P-type base region are formed on a semiconductor substrate; Multiple spaced N+ emission regions are formed on the upper surface of the P-type base region by a first ion implantation process; A P+ anti-latch-up region is formed on the upper surface of the P-type base region between adjacent N+ emitter regions by a second ion implantation process. An insulating layer is formed over the N+ emitter region and the P+ anti-latch-up region, and contact holes are etched out. The contact hole is filled with metal, and a metal layer is covered on top of the insulating layer to form an emitter that is in ohmic contact with the N+ emitter region and the P+ latch-up region.

[0014] Optionally, the implantation energy of the first ion implantation process is 20 keV to 80 keV; the implantation energy of the second ion implantation process is 20 keV to 80 keV.

[0015] Optionally, the process also includes steps for fabricating the trench gate and the gate oxide layer: A protective layer is deposited on the surface of the silicon wafer, and windows are etched by photolithography to form trench silicon etching, which etches gate electrode trenches and separation gate electrode trenches. A sacrificial oxide layer is grown on the sidewall of the trench, and then the sacrificial oxide layer is removed. Then a gate oxide layer is grown on the sidewall of the trench, and polysilicon is deposited on the gate oxide layer. Then excess polysilicon on the surface is etched away.

[0016] The beneficial effects of this application are: The IGBT device with improved latch-up resistance provided in the first aspect of this application constructs a parallel low-resistance auxiliary current path by setting a P+ latch-up region between adjacent N+ emitter regions. This increases the pathway for holes to flow into the emitter metal through the low-resistivity P+ latch-up region, reducing the total resistance of the conduction path. Even when large-size defects (such as blocked contact holes) occur during manufacturing, obstructing the main discharge path of hole carriers at the bottom of the N+ emitter region, holes can still be efficiently discharged through the P+ latch-up region. This effectively suppresses the increase in local voltage drop caused by current bypass and avoids the triggering of parasitic thyristors. Therefore, it significantly improves the latch-up resistance and tolerance to process defects of the IGBT device under non-ideal manufacturing conditions.

[0017] The second aspect of this application provides a method for fabricating an IGBT device with improved latch-up resistance. This method involves first forming spaced N+ emitter regions on the upper surface of the P-type base region, and then precisely injecting P+ latch-up-resistant regions at the adjacent gaps. This constructs a critical redundant current path during the device manufacturing stage. This ensures that even if photolithography or etching defects partially block the main discharge channel for hole carriers below the N+ emitter regions, holes can still be effectively discharged through the adjacent low-resistance P+ latch-up-resistant regions. This reduces the risk of local voltage drops exceeding the PN junction turn-on voltage, fundamentally improving the device's tolerance to process defects and overall latch-up reliability in actual production. Attached Figure Description

[0018] Figure 1 A schematic diagram of the structure of the IGBT device provided in the embodiments of this application after completing the N+ emitter region and the P+ anti-lock-in region; Figure 2 This is a schematic diagram of the structure of the IGBT device provided in the embodiments of this application; Figure 3 A hole current flow diagram for an IGBT device provided in an embodiment of this application.

[0019] In the figure: 101, collector; 102, buffer layer; 103, drift region; 104, carrier storage layer; 105, P-type base region; 106, N+ emitter region; 107, P+ latch-up region; 108, gate oxide layer; 109, trench gate; 110, insulating layer; 120, emitter; 121, lower central convex portion. Detailed Implementation

[0020] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0021] like Figures 1-3 As shown, the first aspect of this application provides an IGBT device with improved latch-up resistance, comprising: The following components are arranged sequentially from bottom to top: collector 101, buffer layer 102, drift region 103, carrier storage layer 104, P-type base region 105, N+ emitter region 106 and P+ anti-latch-up region 107 alternately arranged on the upper surface of P-type base region 105 and on the same horizontal plane, and emitter 120 in ohmic contact with P-type base region 105, N+ emitter region 106 and P+ anti-latch-up region 107; The P+ anti-latch-up region 107 is disposed between two adjacent N+ emission regions 106; The P+ anti-latch-up region 107 contacts the P-type base region 105 and is configured to provide a parallel, low-resistance auxiliary current path when the main path of hole carriers flowing from the bottom of the N+ emitter region 106 to the emitter 120 metal layer is blocked.

[0022] The IGBT device with improved latch-up resistance provided in the first aspect of this application constructs a parallel low-resistance auxiliary current path by setting a P+ latch-up resistance region 107 between adjacent N+ emitter regions 106. This increases the pathway for holes to flow into the emitter 120 metal through the low-resistivity P+ latch-up resistance region 107, reducing the total resistance of the conduction path. This ensures that even when large-size defects (such as blocked contact holes) occur during manufacturing, obstructing the main discharge path of hole carriers at the bottom of the N+ emitter region 106, holes can still be efficiently discharged through the P+ latch-up resistance region 107. This effectively suppresses the increase in local voltage drop caused by current bypass and avoids the triggering of parasitic thyristors. Therefore, it significantly improves the latch-up resistance and tolerance to process defects of the IGBT device under non-ideal manufacturing conditions.

[0023] In some possible implementations, the IGBT device with improved latch-up resistance also includes two trench gates 109 embedded on both sides of the IGBT device. The trench gates 109 pass through the N+ emitter region 106, the P+ latch-up region 107, the P-type base region 105 and the carrier storage layer 104, and extend deep into the drift region 103. The inner surface of the trench gates 109 has a gate oxide layer 108.

[0024] Specifically, the trench gate 109 sequentially passes through the N+ source region, the P+ latch-up region 107, the P-type base region 105, and the carrier storage layer 104, extending into the drift region 103. Its inner wall is covered with a gate oxide layer 108 to achieve electrical isolation and gate control functions. This not only helps optimize carrier distribution and reduce on-state voltage drop, but more importantly, by arranging the trench gate 109 in the edge region of the device, it can effectively shield the edge electric field concentration and improve the breakdown voltage stability. At the same time, the trench structure and the internal P+ latch-up region 107 work together to further guide and constrain the hole current to flow along a predetermined low-resistance channel when the main hole discharge path is blocked due to manufacturing defects, reducing the lateral voltage gradient and thus suppressing the triggering conditions of the parasitic thyristor.

[0025] It should be noted that extending into the depth of the drift region 103 refers to key features such as the trench gate 109 or the carrier storage layer 104 extending vertically beyond the metallurgical junction interface between the P-type base region 105 and the N-drift region 103, continuing towards the back side of the silicon wafer to a physical depth sufficient to significantly affect the internal electric field distribution and carrier transport behavior of the device. This "depth" does not refer to reaching the buffer layer 102 or the collector 101 region, but specifically refers to forming a sufficiently long vertical overlap or modulation region within the drift region 103 to enhance the conductivity modulation effect, optimize the electric field tailing characteristics during turn-off, and provide a sufficient lateral resistance discharge path for the anti-latch-up structure. The specific extension depth needs to be designed proportionally according to the device's withstand voltage level and the total thickness of the drift region 103, typically accounting for 1 / 5 to 1 / 3 of the thickness of the drift region 103, to ensure the best trade-off between anti-latch-up capability and conduction loss without sacrificing the breakdown voltage.

[0026] It should also be noted that the gate oxide layer 108 conformally covers the inner wall and bottom surface of the gate electrode trench and the separation gate electrode trench, serving as an insulating medium to physically completely isolate the trench gate 109 subsequently filled inside the trench from the surrounding P-type base region 105, N-type carrier storage layer 104 and N-drift region 103; its outer side is in close contact with the trench silicon interface, its inner side is in direct contact with the polysilicon gate, and its top is covered by the insulating layer 110 and electrically isolated from the emitter 120 metal, thereby forming the gate dielectric core of the trench MOS structure in the vertical direction, ensuring that the gate voltage can be vertically coupled to the channel region to control the device's turn-on and turn-off.

[0027] In some possible implementations, the emitter 120 has a central lower protrusion 121 that penetrates the middle portion of the N+ emitter region 106 and the P+ anti-latch-up region 107 and extends deep into the P-type base region 105. An insulating layer 110 is provided on the bottom surface of the emitter 120 except for the central lower protrusion 121.

[0028] Specifically, the lower protrusion penetrates the middle region between the N+ emitter region 106 and the P+ latch-up region 107, extending deep into the P-type base region 105. This physically establishes a low-resistance, high-reliability ohmic contact channel, ensuring that hole carriers can still be efficiently discharged through this deeply embedded metal protrusion even in cases of incompletely opened contact holes or uneven doping processes. Simultaneously, the remaining bottom surface of the emitter 120 is covered with an insulating layer 110, effectively isolating it from unintended electrical connections with surrounding semiconductor regions and preventing lateral leakage or parasitic conduction. This not only strengthens the synergistic effect of the main current path and the latch-up auxiliary path but also further suppresses the risk of triggering parasitic thyristors due to local voltage increases, improving the IGBT device's latch-up resistance, electrical stability, and overall reliability under complex operating conditions and manufacturing fluctuations.

[0029] It should be noted that "extending deep into the P-type base region 105" refers to the structure such as the lower convex portion 121 in the middle of the emitter 120 extending vertically downward from the surface of the P-type base region 105. Its junction depth significantly exceeds the bottom interface of the N+ emitter region 106 and penetrates into the interior of the P-type base region 105, but has not yet penetrated the metallurgical junction between the P-type base region 105 and the N-drift region 103. This "deep" extension aims to construct a low-resistance vertical hole discharge channel inside the P-type base region 105 through high-concentration P-type doping or metal contact, effectively reducing the parasitic thyristor base region resistance, thereby suppressing the triggering of latch-up effect under transient high current conditions such as device turn-off or short circuit. Its specific extension depth needs to ensure sufficient lateral overlap with the N+ emitter region 106 to ensure the reliability of ohmic contact, while maintaining sufficient thickness of the P-type base region 105 to maintain channel formation capability and threshold voltage stability.

[0030] In some possible implementations, the doping concentration of the P+ latch-up region 107 is higher than that of the P-type base region 105.

[0031] The above implementation reduces the resistivity of the P+ latch-up region 107, thereby providing a low-resistance, high-conductivity auxiliary discharge path for the main hole current during IGBT turn-off. When hole discharge is obstructed due to process defects (such as abnormal doping) at the main emitter 120 contact, the highly doped P+ latch-up region 107 can effectively shunt the holes, suppress the transverse voltage drop caused by hole accumulation between the P-type base region 105 and the N+ emitter region 106, and prevent this voltage from triggering the parasitic thyristor to conduct.

[0032] In some possible implementations, the doping concentration of collector 101 is 10. 16 ~10 17 / cm 3 The doping concentration of the buffer layer 102 is 10. 15 ~10 16 / cm 3 The doping concentration of the drift region 103 is 10. 13 ~10 14 / cm 3 The doping concentration of the carrier storage layer 104 is 10. 14 ~10 15 / cm 3 The doping concentration of the P-type base region 105 is 10. 16 ~10 17 / cm 3 The doping concentration of the N+ emitter region 106 is 10. 19 ~10 20 / cm 3 The doping concentration of the P+ anti-latch-up region 107 is 10. 18 ~10 19 / cm 3 .

[0033] The above implementation ensures, on the one hand, that the drift region 103 has a sufficiently high breakdown voltage and low conduction loss, and on the other hand, that the P+ latch-up region 107 has a resistivity much lower than that of the P-type base region 105, thus providing an efficient and low-resistance auxiliary discharge channel for holes during turn-off transients. Simultaneously, the highly doped N+ emitter region 106 ensures good ohmic contact, while the progressively transitioning buffer layer 102 and carrier storage layer 104 effectively suppress electric field concentration and improve carrier injection efficiency. The synergistic effect of the overall doping structure significantly enhances robustness to process defects while maintaining the device's high voltage and low on-state voltage drop performance, effectively suppressing parasitic thyristor triggering, and greatly improving the IGBT chip's latch-up resistance, operational reliability, and manufacturing yield.

[0034] In some possible implementations, the collector 101, the P-type base region 105, and the P+ latch-up region 107 are doped with boron; the buffer layer 102, the drift region 103, and the carrier storage layer 104 are doped with phosphorus; and the N+ emitter region 106 is doped with arsenic.

[0035] In the above implementation, phosphorus is uniformly used in the low / medium concentration regions of buffer layer 102, drift region 103, and carrier storage layer 104 where a certain junction depth is required. Phosphorus's diffusion behavior at high temperatures is controllable, making it suitable for constructing the wide and gentle doping profile required for the longitudinal electric field distribution of IGBTs. Arsenic is used in the ultra-high concentration region 106 of the N+ emitter region where a shallow junction depth is required. Arsenic has a higher solid solubility in silicon than phosphorus, reaching 10⁻⁶. 20 / cm 3 The above-mentioned slow diffusion allows for the formation of an ideal abrupt junction, which is crucial for emitter metallization contacts. Boron is used in the collector 101, P-type base region 105, and P+ latch-up region 107. In modern silicon-based IGBT processes, aluminum has been largely phased out due to deep-level defects. Although gallium is occasionally used, it is expensive and has a narrow process window. Boron is a P-type doping choice that balances electrical performance, process maturity, and cost. The boron concentration in the P+ latch-up region 107 is significantly higher than that in the P-type base region 105. This concentration gradient design ensures that hole current preferentially flows through the P+ region rather than the base resistance path of the NPN parasitic transistor, thereby improving the dynamic latch-up margin of the device from a physical mechanism.

[0036] In some possible implementations, the width of the N+ emitter region 106 ranges from 0.5 μm to 2.0 μm.

[0037] The above implementation method, while ensuring good electron injection efficiency and low contact resistance, effectively controls its lateral expansion range, avoiding excessive coverage of the P-type base region 105 due to excessive width, which would weaken the hole discharge capability, or poor contact and current congestion due to excessive narrowness. This width range is consistent with high doping concentration (10⁻⁶). 19 ~10 20 / cm 3 The combination of these features not only ensures that the emitter 120 region has excellent ohmic characteristics, but also provides sufficient space for the adjacent P+ latch-up region 107 to form an effective hole bypass channel, thereby synergistically suppressing the conduction conditions of the parasitic thyristor.

[0038] Secondly, this application provides a method for fabricating an IGBT device with improved latch-up resistance, comprising the following steps: A collector 101, a buffer layer 102, a drift region 103, and a P-type base region 105 are formed on a semiconductor substrate; Multiple spaced N+ emission regions 106 are formed on the upper surface of the P-type base region 105 by a first ion implantation process; On the upper surface of the P-type base region 105 between adjacent N+ emitter regions 106, a P+ anti-latch-up region 107 is formed by a second ion implantation process. An insulating layer 110 is formed above the N+ emitter region 106 and the P+ anti-latch-up region 107, and contact holes are etched out. The contact hole is filled with metal and a metal layer is covered over the insulating layer 110 to form an emitter 120 that makes ohmic contact with the N+ emitter region 106 and the P+ latch-up region 107.

[0039] The second aspect of this application provides a method for fabricating an IGBT device with improved latch-up resistance. This method involves first forming spaced N+ emitter regions 106 on the upper surface of the P-type base region 105, and then precisely implanting P+ latch-up resistance regions 107 at the adjacent gaps, thereby constructing a critical redundant current path during the device fabrication stage. Compatible with existing trench IGBT processes, only one additional ion implantation step is required to establish an ohmic contact between the P+ latch-up resistance region 107 and the emitter 120 after metallization. This method ensures that even if the main discharge channel for hole carriers below the N+ emitter region 106 is partially blocked due to photolithography or etching process defects (such as particulate contamination causing incomplete opening of contact holes), holes can still be effectively discharged through the adjacent low-resistance P+ latch-up resistance region 107. This reduces the risk of local voltage drop exceeding the PN junction turn-on voltage, fundamentally improving the device's tolerance to process defects and overall latch-up resistance reliability in actual production.

[0040] In some possible implementations, the implantation energy of the first ion implantation process is 20 keV to 80 keV; the implantation energy of the second ion implantation process is 20 keV to 80 keV.

[0041] The above implementation method, by employing a first ion implantation process and a second ion implantation process with implantation energies of 20keV to 80keV, forms the N+ emitter region 106 and the P+ anti-latch-up region 107, respectively. This method can precisely control the vertical distribution depth of impurities in the silicon substrate while ensuring sufficient doping activation efficiency. This allows the N+ emitter region 106 and the high-concentration P+ anti-latch-up region 107 to achieve a steep and controllable junction depth in the shallow layer, ensuring good ohmic contact and electron injection capability while avoiding excessive penetration into the P-type base region 105 and damage to its electrical integrity. Combined with the structure of the lower protrusion 121 in the middle of the emitter 120 penetrating the N+ emitter region 106 and the P+ anti-latch-up region 107 and extending into the P-type base region 105, this implantation process synergistically achieves efficient lateral and vertical discharge paths for holes during the turn-off transient.

[0042] Some possible implementations also include the fabrication steps of the trench gate 109 and the gate oxide layer 108: A protective layer is deposited on the surface of the silicon wafer, and windows are etched by photolithography to form trench silicon etching, which etches gate electrode trenches and separation gate electrode trenches. A sacrificial oxide layer is grown on the sidewall of the trench, and then the sacrificial oxide layer is removed. Then a gate oxide layer is grown on the sidewall of the trench, and polysilicon is deposited on the gate oxide layer. Then excess polysilicon on the surface is etched away.

[0043] The above implementation first deposits a protective layer on the silicon wafer surface and defines windows using photolithography. Then, anisotropic silicon etching is performed to simultaneously form trenches for the main gate electrode and separate gate electrode trenches for electrical isolation. Next, a sacrificial oxide layer is grown on the trench sidewalls to repair etching damage and improve interface states, and then removed to avoid impurity residue. Based on this, a high-quality, uniformly thick gate oxide layer is thermally grown on the clean trench sidewalls to ensure excellent dielectric properties and interface characteristics. Subsequently, polysilicon is deposited to fill the trenches, and excess polysilicon on the surface is precisely removed using reverse etching, retaining only the gate electrode structure within the trenches. This not only effectively controls the trench morphology and gate dielectric quality but also avoids threshold voltage drift and gate leakage caused by etching defects or interface states. Furthermore, the introduction of separate gate electrode trenches enhances the electrical isolation between adjacent cells.

[0044] Example 1 Step 1: Select a resistivity corresponding to a doping concentration of 5×10⁻⁶. 13 / cm 3 A lightly doped N-type Czochralski single-crystal silicon wafer, 600 μm thick, is used to form the N-drift region 103 of the device; Step 2: A 50nm thick pre-oxidation layer is thermally grown on the front side of the silicon wafer as an implantation barrier layer. Boron (B) ions are implanted using an ion implanter at a dose of 5 × 10⁻⁶. 13 ions / cm 2 The injection energy was 80 keV. Subsequently, high-temperature junction-pushing annealing was performed at 1050℃ in a nitrogen atmosphere for 60 minutes, resulting in a junction depth of approximately 2.5 μm and a surface peak doping concentration of 5 × 10⁻⁶. 16 / cm 3 The P-type base region is 105; Step 3: A 500nm thick silicon dioxide layer is deposited on the silicon wafer surface using LPCVD as a hard mask protective layer. Photoresist is coated and trench windows are photolithographically etched. Anisotropic dry etching (using SF6 / O2 mixed gas) is used to etch silicon to create gate electrode trenches with a depth of 5.0μm and a width of 1.5μm, as well as separation gate electrode trenches. Step 4: In a dry oxygen environment at 950℃, a 50nm thick sacrificial oxide layer is grown on the trench sidewall to repair the etching damage, and then completely removed using hydrofluoric acid solution; In a wet oxygen environment at 900℃, a high-quality gate oxide layer 108 with a thickness of 80nm is regrown on the clean trench sidewall; Phosphorus-doped polysilicon with a thickness of 600nm is deposited using LPCVD to fill the trench, and then excess polysilicon on the surface is etched away by chemical mechanical polishing (CMP) or reactive ion etching (RIE) to make the polysilicon flush with the silicon wafer surface, forming the trench gate 109; Step 5: Inject phosphorus (P) ions, dose 1×10 12 ions / cm 2 Energy 150 keV, after annealing, a doping concentration of 5 × 10⁻⁶ is formed. 14 / cm 3 The N-type carrier storage layer 104 is deposited; a protective layer is deposited and an N+ window is photolithographically patterned, and arsenic (As) ions are implanted at a dose of 5 × 10⁻⁶. 15 ions / cm 2 The injection energy was 50 keV, and the photolithography window size was controlled to achieve a final N+ emitter region width of 1.0 μm and a peak doping concentration of 5 × 10⁶. 19 / cm 3 The P+ window between adjacent N+ emission regions 106 was re-lithographically patterned, and boron (B) ions were implanted at a dose of 2 × 10⁶. 15 ions / cm 2 The injection energy was 40 keV, resulting in a doping concentration of 5 × 10⁻⁶. 18 / cm 3 The P+ anti-latch-up region 107; subjected to rapid thermal annealing (RTA) at 1000°C for 10 seconds to activate all implanted impurities and repair lattice damage, such as Figure 1 As shown; Step 6: Deposit an 800nm ​​thick borosilicate glass as an insulating layer 110 using plasma-enhanced chemical vapor deposition (PECVD), and perform reflow planarization at 850℃; photolithographically print contact hole windows, use dry etching to penetrate the insulating layer, and over-etch into the silicon substrate to a depth of about 1.5μm, so as to reserve a deep trench for the middle lower protrusion 121 of the emitter 120; Step 7: Sputter 50nm Ti as a barrier layer on the front side of the device, followed by magnetron sputtering to deposit a 3μm thick aluminum-silicon-copper alloy metal layer to completely fill the contact holes and deep trenches, forming an emitter 120 with a central lower protrusion 121; perform photolithography and dry etching on excess metal, and finally perform alloying annealing at 450℃ in a nitrogen / hydrogen mixed gas for 30 minutes to form an excellent ohmic contact; Step 8: Flip the silicon wafer and thin the back side to a total thickness of 120 μm using mechanical grinding and chemical mechanical polishing; implant phosphorus ions into the back side (dose 1×10⁻⁶). 13 ions / cm, energy 300keV) and boron ions (dose 1×10 14 ions / cm 2 (Energy 50 keV); using a wavelength of 532 nm and an energy density of 2.5 J / cm³. 2 The pulsed laser is used for localized back-side annealing to activate impurities and form a doping concentration of 5×10⁻⁶. 15 / cm 3 The N-type buffer layer 102 and the doping concentration of 5×10 16 / cm 3 The P+ collector 101 is constructed to avoid damage to the front-side metal and gate oxide layer caused by high temperatures. A 500nm Ni layer is sequentially deposited on the back side to form the metal collector 101, completing the device fabrication. Figure 2 As shown.

[0045] The essence of this invention is to provide an insulated gate bipolar transistor (IGBT) with improved latch-up resistance. Based on the above technical solution, in addition to flowing into the emitter 120 metal through the bottom of the N+ emitter region 106, the hole carriers in the P-type base region 105 also have an additional pathway to flow into the emitter 120 metal through the low resistivity P+ latch-up region, thus reducing the on-resistance. Figure 3As shown. Process defects cause abnormalities in the N+ emitter region 106 contact hole, obstructing the normal bottom pathway of hole carriers in the N+ emitter region 106. However, hole carriers can still flow into the emitter 120 metal through the P+ anti-lock-up region. The PN junction voltage is more difficult to reach the turn-on voltage drop, thus suppressing latch-up and ultimately improving the latch-up resistance of the IGBT device. Compared to conventional IGBTs, the RBSOA (Reverse Bias Safe Operating Area) is increased. When affected by defects in the size of the contact hole, the RBSOA degradation of the IGBT of this invention is reduced compared to conventional IGBTs.

[0046] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of protection of this application is limited to these examples; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0047] One or more embodiments in this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments in this application should be included within the protection scope of this application.

Claims

1. An IGBT device with improved latch-up resistance, characterized in that, include: The following components are arranged sequentially from bottom to top: collector (101), buffer layer (102), drift region (103), carrier storage layer (104), P-type base region (105), N+ emitter region (106) and P+ anti-latch-up region (107) alternately arranged on the upper surface of the P-type base region (105) and on the same horizontal plane, and emitter (120) in ohmic contact with the P-type base region (105), N+ emitter region (106) and P+ anti-latch-up region (107). The P+ anti-latch region (107) is disposed between two adjacent N+ emission regions (106); The P+ anti-latch-up region (107) contacts the P-type base region (105) and is configured to provide a parallel, low-resistance auxiliary current path when the main path of hole carriers flowing from the bottom of the N+ emitter region (106) to the emitter (120) metal layer is blocked. The emitter (120) has a central lower protrusion (121) that penetrates the middle part of the N+ emitter region (106) and the P+ anti-latch-up region (107) and extends to the depth of the P-type base region (105). The bottom surface of the emitter (120) excluding the central lower protrusion (121) is provided with an insulating layer (110).

2. The IGBT device with improved anti-latch-up capability according to claim 1, characterized in that, It also includes two trench gates (109) embedded on both sides of the IGBT device, the trench gates (109) passing through the N+ emitter region (106), the P+ latch-up region (107), the P-type base region (105) and the carrier storage layer (104) and extending deep into the drift region (103), and the inner surface of the trench gates (109) has a gate oxide layer (108).

3. The IGBT device with improved anti-latch-up capability according to claim 2, characterized in that, The doping concentration of the P+ anti-latch-up region (107) is higher than that of the P-type base region (105).

4. The IGBT device with improved anti-latch-up capability according to claim 3, characterized in that, The doping concentration of the collector (101) is 10. 16 ~10 17 / cm 3 The doping concentration of the buffer layer (102) is 10. 15 ~10 16 / cm 3 The doping concentration of the drift region (103) is 10. 13 ~10 14 / cm 3 The doping concentration of the carrier storage layer (104) is 10. 14 ~10 15 / cm 3 The doping concentration of the P-type base region (105) is 10. 16 ~10 17 / cm 3 The doping concentration of the N+ emitter region (106) is 10. 19 ~10 20 / cm 3 The doping concentration of the P+ anti-latch-up region (107) is 10. 18 ~10 19 / cm 3 .

5. The IGBT device with improved latch-up resistance according to claim 4, characterized in that, The collector (101), the P-type base region (105), and the P+ anti-latch-up region (107) are doped with boron; the buffer layer (102), the drift region (103), and the carrier storage layer (104) are doped with phosphorus; and the N+ emitter region (106) is doped with arsenic.

6. The IGBT device with improved anti-latch-up capability according to claim 1, characterized in that, The width of the N+ emission region (106) ranges from 0.5 μm to 2.0 μm.

7. A method for fabricating an IGBT device with improved latch-up resistance as described in any one of claims 3 to 5, characterized in that, Includes the following steps: A collector (101), a buffer layer (102), a drift region (103), and a P-type base region (105) are formed on a semiconductor substrate. Multiple spaced N+ emission regions (106) are formed on the upper surface of the P-type base region (105) by a first ion implantation process. On the upper surface of the P-type base region (105) between adjacent N+ emitter regions (106), a P+ anti-latch-up region (107) is formed by a second ion implantation process. An insulating layer (110) is formed over the N+ emitter region (106) and the P+ anti-latch-up region (107), and contact holes are etched out; The contact hole is filled with metal and covered with a metal layer above the insulating layer (110) to form an emitter (120) that is in ohmic contact with the N+ emitter region (106) and the P+ latch-up region (107).

8. The IGBT device with improved latch-up resistance according to claim 7, characterized in that, The implantation energy of the first ion implantation process is 20 keV to 80 keV; And / or, the implantation energy of the second ion implantation process is 20 keV to 80 keV.

9. The method for fabricating an IGBT device with improved latch-up resistance according to claim 8, characterized in that, It also includes the fabrication steps of the trench gate (109) and the gate oxide layer (108): A protective layer is deposited on the surface of the silicon wafer, and a window is etched to perform trench silicon etching, which etches gate electrode trenches and separation gate electrode trenches. A sacrificial oxide layer is grown on the sidewall of the trench, and then the sacrificial oxide layer is removed. Then a gate oxide layer (108) is grown on the sidewall of the trench, and then polysilicon is deposited on the gate oxide layer (108), and then excess polysilicon on the surface is etched away.

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