A semiconductor structure and its formation method

Abstract

This application provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor substrate in which a first doped region is formed; an epitaxial layer located in the semiconductor substrate and spanning a portion of the first doped region and a portion of the semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, covering the epitaxial layer, a portion of the first doped region, and a portion of the semiconductor substrate; and a second doped region located in the semiconductor substrate on the other side of the gate structure opposite to the first doped region. This application provides a semiconductor structure and a method for forming the same that can improve the subthreshold slope and on / off current ratio of a TFET device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Over the past few decades, integrated circuit technology has been continuously developing in accordance with Moore's Law, with the feature size of semiconductor devices shrinking smaller and smaller. Currently, the miniaturization of MOSFETs is almost at its physical limit, and the main problems it faces include higher leakage current, a subthreshold slope limit of 60mV / dec, and short-channel effects. TFETs (tunneling field-effect transistors) have emerged to address these challenges and are considered a major solution to replace MOSFETs.

[0003] In the development of TFET devices, obtaining a larger current on / off ratio and a steeper subthreshold slope are two major research directions. The on-state current of a TFET device depends on factors such as its tunneling area and tunneling probability. Currently, the conventional way to increase the on-state current is mainly to increase the tunneling area. The subthreshold slope of a TFET device is mainly related to the electric field strength of the tunnel junction and the physical properties of the tunnel junction material itself.

[0004] How to further improve the subthreshold slope and switching current ratio of TFET devices has become a problem that needs to be solved in this field. Summary of the Invention

[0005] This application provides a semiconductor structure and a method for forming the same, which can improve the subthreshold slope and switching current ratio of TFET devices.

[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate in which a first doped region is formed; etching the semiconductor substrate to form an opening spanning a portion of the first doped region and a portion of the semiconductor substrate; forming an epitaxial layer in the opening; forming a gate structure on the surface of the semiconductor substrate covering the epitaxial layer, a portion of the first doped region, and a portion of the semiconductor substrate; and forming a second doped region in the semiconductor substrate on the other side of the gate structure opposite to the first doped region.

[0007] In some embodiments of this application, a method of etching the semiconductor substrate to form an opening spanning a portion of the first doped region and a portion of the semiconductor substrate includes: forming a patterned hard mask layer on the surface of the semiconductor substrate, the patterned hard mask layer defining the location of the opening; etching the semiconductor substrate using the patterned hard mask layer as a mask to form the opening; and removing the patterned hard mask layer.

[0008] In some embodiments of this application, the method of forming an epitaxial layer in the opening includes: forming an epitaxial layer in the opening between a step of etching the semiconductor substrate using the patterned hard mask layer as a mask to form the opening and a step of removing the patterned hard mask layer, wherein the top surface of the epitaxial layer is higher than the top surface of the semiconductor substrate; and after the step of removing the patterned hard mask layer, planarizing the epitaxial layer so that the top surface of the epitaxial layer is flush with the top surface of the semiconductor substrate.

[0009] In some embodiments of this application, the gate structure includes a gate dielectric layer and a gate layer sequentially located on the surface of the semiconductor substrate, and a sidewall located on the sidewalls of the gate dielectric layer and the gate layer.

[0010] In some embodiments of this application, the distance between the epitaxial layer and the first side of the gate dielectric layer and the gate layer is 0 to 5 nanometers; the distance between the epitaxial layer and the second side of the gate dielectric layer and the gate layer is 50% to 70% of the length of the gate dielectric layer and the gate layer.

[0011] In some embodiments of this application, the depth of the epitaxial layer is 20% to 50% of the depth of the first doped region.

[0012] In some embodiments of this application, the epitaxial layer has doped ions, the first doped region has an opposite doping type to the epitaxial layer, and the first doped region has an opposite doping type to the second doped region.

[0013] Another aspect of this application provides a semiconductor structure comprising: a semiconductor substrate having a first doped region formed therein; an epitaxial layer located in the semiconductor substrate and spanning a portion of the first doped region and a portion of the semiconductor substrate; a gate structure located on the surface of the semiconductor substrate covering the epitaxial layer and a portion of the first doped region and a portion of the semiconductor substrate; and a second doped region located in the semiconductor substrate on the other side of the gate structure opposite to the first doped region.

[0014] In some embodiments of this application, the gate structure includes a gate dielectric layer and a gate layer sequentially located on the surface of the semiconductor substrate, and a sidewall located on the sidewalls of the gate dielectric layer and the gate layer.

[0015] In some embodiments of this application, the distance between the epitaxial layer and the first side of the gate dielectric layer and the gate layer is 0 to 5 nanometers; the distance between the epitaxial layer and the second side of the gate dielectric layer and the gate layer is 50% to 70% of the length of the gate dielectric layer and the gate layer.

[0016] In some embodiments of this application, the depth of the epitaxial layer is 20% to 50% of the depth of the first doped region.

[0017] In some embodiments of this application, the epitaxial layer has doped ions, the first doped region has an opposite doping type to the epitaxial layer, and the first doped region has an opposite doping type to the second doped region.

[0018] This application provides a semiconductor structure and a method for forming the same, which can improve the subthreshold slope and switching current ratio of TFET devices. Attached Figure Description

[0019] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0020] in:

[0021] Figures 1 to 8 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation

[0022] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0023] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0024] Figures 1 to 8 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0025] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, wherein a first doped region 101 is formed in the semiconductor substrate 100.

[0026] In some embodiments of this application, the semiconductor structure is, for example, a TFET, and the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above.

[0027] In some embodiments of this application, the first doped region 101 may be formed by ion implantation or epitaxial growth. The doping type of the first doped region 101 may be, for example, p-type.

[0028] refer to Figures 2 to 6 As shown, the semiconductor substrate 100 is etched to form an opening 110 spanning a portion of the first doped region 101 and a portion of the semiconductor substrate 100; an epitaxial layer 120 is formed in the opening 110.

[0029] refer to Figure 2 As shown, a patterned hard mask layer 111 is formed on the surface of the semiconductor substrate 100, and the patterned hard mask layer 111 defines the location of the opening 110. The material of the patterned hard mask layer 111 includes silicon oxide or silicon nitride, etc.

[0030] refer to Figure 3 As shown, the semiconductor substrate 100 is etched using the patterned hard mask layer 111 as a mask to form the opening 110.

[0031] refer to Figure 4 As shown, an epitaxial layer 120 is formed in the opening 110, and the top surface of the epitaxial layer 120 is higher than the top surface of the semiconductor substrate 100. The method for forming the epitaxial layer 120 is, for example, an in-situ doped epitaxial growth process.

[0032] In some embodiments of this application, the epitaxial layer 120 is made of silicon-germanium doped with ions, and the ratio of germanium atoms to silicon atoms in the epitaxial layer 120 is, for example, 2:3. The doping type of the epitaxial layer 120 is opposite to that of the first doped region 101, for example, N-type. To ensure the normal operation of the TFET device, the epitaxial layer 120 should be in a fully depleted state; therefore, the doping concentration of the epitaxial layer 120 can be less than 10% of the doping concentration of the first doped region 101.

[0033] refer to Figure 5 As shown, the patterned hard mask layer 111 is removed. The method for removing the patterned hard mask layer 111 is, for example, a wet etching process.

[0034] refer to Figure 6As shown, the epitaxial layer 120 is planarized using a chemical mechanical polishing (CMP) process so that the top surface of the epitaxial layer 120 is flush with the top surface of the semiconductor substrate 100.

[0035] refer to Figure 7 As shown, a gate structure 130 is formed on the surface of the semiconductor substrate 100, covering the epitaxial layer 120, a portion of the first doped region 101, and a portion of the semiconductor substrate 100.

[0036] In some embodiments of this application, the gate structure 130 includes a gate dielectric layer 131 and a gate layer 132 sequentially located on the surface of the semiconductor substrate 100, and a sidewall 133 located on the sidewalls of the gate dielectric layer 131 and the gate layer 132. The gate structure is a basic structure in semiconductor structures, and its structure and fabrication method are well known to those skilled in the art, and will not be described in detail here.

[0037] refer to Figure 8 As shown, a second doped region 102 is formed in the semiconductor substrate 100 on the other side of the gate structure 130 opposite to the first doped region 101. The boundary of the second doped region 102 is flush with the boundary of the sidewall 133 in the vertical direction.

[0038] In some embodiments of this application, the second doped region 102 can be formed by an ion implantation process. The doping type of the second doped region 102 is opposite to that of the first doped region 101, for example, it is N-type.

[0039] Continue to refer to Figure 8 As shown, in some embodiments of this application, the distance a between the epitaxial layer 120 and the first side of the gate dielectric layer 131 and the gate layer 132 is 0 to 5 nanometers; the distance b between the epitaxial layer 120 and the second side of the gate dielectric layer 131 and the gate layer 132 is 50% to 70% of the length of the gate dielectric layer 131 and the gate layer 132.

[0040] Continue to refer to Figure 8 As shown, in some embodiments of this application, the depth of the epitaxial layer 120 is 20% to 50% of the depth of the first doped region 101.

[0041] Continue to refer to Figure 8 As shown, in some embodiments of this application, the length of a portion of the epitaxial layer 120 located in the first doped region 101 is 50% to 80% of the total length of the epitaxial layer 120.

[0042] In one specific embodiment, the distance 'a' between the epitaxial layer 120 and the first side of the gate dielectric layer 131 and the gate layer 132 is 5 nanometers; the distance 'b' between the epitaxial layer 120 and the second side of the gate dielectric layer 131 and the gate layer 132 is 40 nanometers; the length of the portion of the epitaxial layer 120 located in the first doped region 101 is 15 nanometers; the total length of the epitaxial layer 120 is 20 nanometers; the depth of the epitaxial layer 120 is 10 nanometers; the depth of the first doped region 101 and the second doped region 102 is the same, 50 nanometers; and the doping concentration of the first doped region 101 and the second doped region 102 is the same, 1E20cm⁻¹. -3 The doping concentration of the epitaxial layer 120 is 2E19cm⁻¹. -3 .

[0043] refer to Figure 8 As shown, in the technical solution of this application, due to the presence of the epitaxial layer 120, the TFET device of this application can have tunneling directions in both the lateral and longitudinal directions. Figure 8 (As shown by the middle arrow), a steeper tunneling junction can be obtained, which helps to improve the tunneling efficiency of the belt and reduce the subthreshold slope.

[0044] In the technical solution of this application, due to the presence of the epitaxial layer 120, the TFET device of this application can obtain a steeper tunneling junction compared to conventional TFET devices. This contributes to the improvement of band-to-band tunneling efficiency and the reduction of subthreshold slope. The epitaxial layer 120 uses N-type doped silicon-germanium material to form a Si / SiGe heterojunction. This structure can significantly enhance the tunneling of both the horizontal and vertical junctions, further increasing the on-state current and reducing the subthreshold slope, thus achieving a higher on / off ratio. Furthermore, this novel structure has a two-dimensional tunneling channel, significantly increasing the tunneling area compared to traditional TFETs, resulting in an even higher on / off ratio.

[0045] The technical solution of this application inserts a silicon-germanium epitaxial layer with inverse doping to the source level at the interface between the source and channel of the TFET device to form a three-dimensional heterojunction structure, which can significantly enhance the steepness of the TFET junction, obtain a steeper subthreshold characteristic, and obtain a higher switching current ratio.

[0046] Embodiments of this application also provide a semiconductor structure, referencing Figure 8As shown, it includes: a semiconductor substrate 100 in which a first doped region 101 is formed; an epitaxial layer 120 located in the semiconductor substrate 100 and spanning a portion of the first doped region 101 and a portion of the semiconductor substrate 100; a gate structure 130 located on the surface of the semiconductor substrate 100 covering the epitaxial layer 120 and a portion of the first doped region 101 and a portion of the semiconductor substrate 100; and a second doped region 102 located in the semiconductor substrate 100 on the other side of the gate structure 130 opposite to the first doped region 101.

[0047] In some embodiments of this application, the semiconductor structure is, for example, a TFET, and the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above.

[0048] In some embodiments of this application, the first doped region 101 may be formed by ion implantation or epitaxial growth. The doping type of the first doped region 101 may be, for example, p-type.

[0049] In some embodiments of this application, the epitaxial layer 120 is made of silicon-germanium doped with ions, and the ratio of germanium atoms to silicon atoms in the epitaxial layer 120 is, for example, 2:3. The doping type of the epitaxial layer 120 is opposite to that of the first doped region 101, for example, N-type. To ensure the normal operation of the TFET device, the epitaxial layer 120 should be in a fully depleted state; therefore, the doping concentration of the epitaxial layer 120 can be less than 10% of the doping concentration of the first doped region 101.

[0050] In some embodiments of this application, the gate structure 130 includes a gate dielectric layer 131 and a gate layer 132 sequentially located on the surface of the semiconductor substrate 100, and a sidewall 133 located on the sidewalls of the gate dielectric layer 131 and the gate layer 132. The gate structure is a basic structure in semiconductor structures, and its structure and fabrication method are well known to those skilled in the art, and will not be described in detail here.

[0051] In some embodiments of this application, the second doped region 102 can be formed by an ion implantation process. The doping type of the second doped region 102 is opposite to that of the first doped region 101, for example, it is N-type.

[0052] Continue to refer to Figure 8As shown, in some embodiments of this application, the distance a between the epitaxial layer 120 and the first side of the gate dielectric layer 131 and the gate layer 132 is 0 to 5 nanometers; the distance b between the epitaxial layer 120 and the second side of the gate dielectric layer 131 and the gate layer 132 is 50% to 70% of the length of the gate dielectric layer 131 and the gate layer 132.

[0053] Continue to refer to Figure 8 As shown, in some embodiments of this application, the depth of the epitaxial layer 120 is 20% to 50% of the depth of the first doped region 101.

[0054] Continue to refer to Figure 8 As shown, in some embodiments of this application, the length of a portion of the epitaxial layer 120 located in the first doped region 101 is 50% to 80% of the total length of the epitaxial layer 120.

[0055] In one specific embodiment, the distance 'a' between the epitaxial layer 120 and the first side of the gate dielectric layer 131 and the gate layer 132 is 5 nanometers; the distance 'b' between the epitaxial layer 120 and the second side of the gate dielectric layer 131 and the gate layer 132 is 40 nanometers; the length of the portion of the epitaxial layer 120 located in the first doped region 101 is 15 nanometers; the total length of the epitaxial layer 120 is 20 nanometers; the depth of the epitaxial layer 120 is 10 nanometers; the depth of the first doped region 101 and the second doped region 102 is the same, 50 nanometers; and the doping concentration of the first doped region 101 and the second doped region 102 is the same, 1E20cm⁻¹. -3 The doping concentration of the epitaxial layer 120 is 2E19cm⁻¹. -3 .

[0056] In the technical solution of this application, due to the presence of the epitaxial layer 120, the TFET device of this application can obtain a steeper tunneling junction compared to conventional TFET devices. This contributes to the improvement of band-to-band tunneling efficiency and the reduction of subthreshold slope. The epitaxial layer 120 uses N-type doped silicon-germanium material to form a Si / SiGe heterojunction. This structure can significantly enhance the tunneling of both the horizontal and vertical junctions, further increasing the on-state current and reducing the subthreshold slope, thus achieving a higher on / off ratio. Furthermore, this novel structure has a two-dimensional tunneling channel, significantly increasing the tunneling area compared to traditional TFETs, resulting in an even higher on / off ratio.

[0057] The technical solution of this application inserts a silicon-germanium epitaxial layer with inverse doping to the source level at the interface between the source and channel of the TFET device to form a three-dimensional heterojunction structure, which can significantly enhance the steepness of the TFET junction, obtain a steeper subthreshold characteristic, and obtain a higher switching current ratio.

[0058] In summary, this application provides a semiconductor structure and a method for forming the same, which can improve the subthreshold slope and switching current ratio of TFET devices.

[0059] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0060] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0061] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0062] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0063] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein a first doped region is formed in the semiconductor substrate; The semiconductor substrate is etched to form an opening spanning a portion of the first doped region and a portion of the semiconductor substrate; An epitaxial layer is formed in the opening; A gate structure is formed on the surface of the semiconductor substrate, covering the epitaxial layer, a portion of the first doped region, and a portion of the semiconductor substrate; A second doped region is formed in the semiconductor substrate on the other side of the gate structure relative to the first doped region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method of etching the semiconductor substrate to form an opening spanning a portion of the first doped region and a portion of the semiconductor substrate includes: forming a patterned hard mask layer on the surface of the semiconductor substrate, the patterned hard mask layer defining the location of the opening; etching the semiconductor substrate using the patterned hard mask layer as a mask to form the opening; and removing the patterned hard mask layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The method of forming an epitaxial layer in the opening includes: forming an epitaxial layer in the opening between a step of etching the semiconductor substrate using the patterned hard mask layer as a mask to form the opening and a step of removing the patterned hard mask layer, wherein the top surface of the epitaxial layer is higher than the top surface of the semiconductor substrate; and after the step of removing the patterned hard mask layer, planarizing the epitaxial layer so that the top surface of the epitaxial layer is flush with the top surface of the semiconductor substrate.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The gate structure includes a gate dielectric layer and a gate layer sequentially located on the surface of the semiconductor substrate, and sidewalls located on the sidewalls of the gate dielectric layer and the gate layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The distance between the epitaxial layer and the first side of the gate dielectric layer and the gate layer is 0 to 5 nanometers; the distance between the epitaxial layer and the second side of the gate dielectric layer and the gate layer is 50% to 70% of the length of the gate dielectric layer and the gate layer.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The depth of the epitaxial layer is 20% to 50% of the depth of the first doped region.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The epitaxial layer contains doped ions, and the doping type of the first doped region is opposite to that of the epitaxial layer, and the doping type of the first doped region is opposite to that of the second doped region.

8. A semiconductor structure, characterized in that, include: A semiconductor substrate, wherein a first doped region is formed in the semiconductor substrate; An epitaxial layer is located in the semiconductor substrate and spans a portion of the first doped region and a portion of the semiconductor substrate; A gate structure is located on the surface of the semiconductor substrate, covering the epitaxial layer, a portion of the first doped region, and a portion of the semiconductor substrate; The second doped region is located in the semiconductor substrate on the other side of the gate structure relative to the first doped region.

9. The semiconductor structure as described in claim 8, characterized in that, The gate structure includes a gate dielectric layer and a gate layer sequentially located on the surface of the semiconductor substrate, and sidewalls located on the sidewalls of the gate dielectric layer and the gate layer.

10. The semiconductor structure as described in claim 9, characterized in that, The distance between the epitaxial layer and the first side of the gate dielectric layer and the gate layer is 0 to 5 nanometers; the distance between the epitaxial layer and the second side of the gate dielectric layer and the gate layer is 50% to 70% of the length of the gate dielectric layer and the gate layer.

11. The semiconductor structure as described in claim 8, characterized in that, The depth of the epitaxial layer is 20% to 50% of the depth of the first doped region.

12. The semiconductor structure as described in claim 8, characterized in that, The epitaxial layer contains doped ions, and the doping type of the first doped region is opposite to that of the epitaxial layer, and the doping type of the first doped region is opposite to that of the second doped region.

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