Method for manufacturing semiconductor power device ramp and semiconductor power device ramp

Abstract

The application provides a manufacturing method of a semiconductor power device ramp and the semiconductor power device ramp, and the method comprises the following steps: a growth step, growing a medium layer and a ramp structure on part of the surface of the front surface of a substrate; a deposition step, depositing a film layer by using an isotropic deposition method, and the film layer covers at least the exposed surface of the front surface of the substrate, the exposed surface of the medium layer and the slope surface of the ramp structure; an etching step, etching the film layer, and after etching, the film layer covering the ramp structure is used as a new ramp structure; and a circulation step, circulating the deposition step and the etching step, so that the ramp angle of the new ramp structure is smaller than the ramp angle of the ramp structure obtained in the growth step. By repeatedly performing the isotropic deposition and the anisotropic etching on the medium layer, the application forms a relatively gentle ramp structure, and reduces the difficulty of adjusting the ramp angle.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for fabricating a slope in a semiconductor power device and a slope in a semiconductor power device. Background Technology

[0002] In the field of semiconductor device fabrication, field plates are a commonly used method in junction termination technology. They primarily improve the device's breakdown voltage by altering the surface potential distribution, increasing the radius of curvature of the curved junction, and preventing excessive concentration of the surface electric field. The lateral electric field of the field plate decreases approximately exponentially with distance from the field plate endpoint. To overcome the breakdown defect caused by electric field concentration at the edge of the bias field plate, the concept of a ramp field plate was proposed. As the field plate extends to the left, the oxide layer thickness gradually increases, thus preventing the formation of high electric field peaks at the edge of the ramp field plate and avoiding edge breakdown. Theoretically, the ramp field plate concept can effectively reduce the peak electric field of the PN junction and avoid edge breakdown caused by electric field concentration at the field plate edge, but its implementation in manufacturing is very difficult. Furthermore, for power devices, the design and manufacturing process of the device termination structure are crucial for achieving high blocking voltage efficiency. During the fabrication of the termination structure, the etching angle affects the accumulation effect of the electric field at the device edge. To effectively suppress the field strength accumulation effect at the device edge, the smaller the etching angle of the terminal ramp, the better.

[0003] In the process of fabricating semiconductor power devices, the ramp angle is difficult to adjust due to crystal orientation limitations. Summary of the Invention

[0004] The main objective of this application is to provide a method for fabricating a slope for a semiconductor power device and a slope for a semiconductor power device, so as to at least solve the problem that the slope angle of a slope for a semiconductor power device is difficult to adjust in the prior art.

[0005] To achieve the above objectives, according to one aspect of this application, a method for fabricating a ramp in a semiconductor power device is provided, comprising: a growth step, providing a substrate including a front side and a back side, growing a dielectric layer and a ramp structure on a portion of the front side surface of the substrate, the ramp structure being located on the sidewall of the dielectric layer; a deposition step, depositing a film layer using isotropic deposition, the film layer at least covering the exposed surface of the front side of the substrate, the exposed surface of the dielectric layer, and the ramp surface of the ramp structure; an etching step, etching the film layer using anisotropic etching, such that a portion of the front side of the substrate and the surface of the dielectric layer away from the substrate are exposed, the etched film layer covering the ramp structure and the ramp structure together form a new ramp structure, the longitudinal distance from the ramp surface of the new ramp structure to the front side of the substrate gradually decreasing in the direction away from the dielectric layer; and a cyclic step, cyclically performing the deposition step and the etching step, such that the ramp angle of the new ramp structure is less than the ramp angle of the ramp structure obtained in the growth step, the ramp angle being the angle between the ramp surface and the front side of the substrate.

[0006] Optionally, an isotropic deposition method is used to deposit the film layer, including: depositing the film layer on the exposed surface of the front side of the substrate, the exposed surface of the dielectric layer, and the exposed surface of the slope structure, such that the longitudinal deposition rate and the transverse deposition rate are the same at any location, and the longitudinal deposition rate gradually increases along the direction from the top to the bottom of the slope, and the transverse deposition rate gradually increases, wherein the longitudinal deposition rate is the deposition rate in the direction perpendicular to the front side of the substrate, and the transverse deposition rate is the deposition rate in the direction parallel to the front side of the substrate.

[0007] Optionally, the film layer is etched using an anisotropic etching method, including: etching the film layer using an anisotropic etching method in which the longitudinal etching rate is the same at each location, the lateral etching rate is the same, and the longitudinal etching rate at the same location is greater than the lateral etching rate, wherein the longitudinal etching rate is the etching rate along the direction perpendicular to the front surface of the substrate, and the lateral etching rate is the etching rate along the direction parallel to the front surface of the substrate.

[0008] Optionally, the film layer is etched using an anisotropic etching method where the longitudinal etching rate is the same at each location, the lateral etching rate is the same, and the longitudinal etching rate at the same location is greater than the lateral etching rate. This includes etching the film layer using an anisotropic etching method where the longitudinal etching rate is the same at each location and the lateral etching rate at each location is 0.

[0009] Optionally, a dielectric layer and a ramp structure are grown on a portion of the front surface of the substrate, including: growing the dielectric layer on the front surface of the substrate using a thermal oxidation method, wherein the thickness of the dielectric layer is...

[0010] Optionally, the dielectric layer is grown on the front side of the substrate using a thermal oxidation method, including: thermally oxidizing the substrate at a temperature of 750–1100°C to obtain the dielectric layer.

[0011] Optionally, an isotropic deposition method is used to deposit a film layer, the film layer covering at least the exposed surface of the front side of the substrate, the exposed surface of the dielectric layer, and the slope surface of the slope structure, including: deposition using chemical vapor deposition at a temperature of 700–800°C.

[0012] Optionally, the film layer is etched using anisotropic etching, which includes: performing anisotropic etching on the film layer using a dry etching process, wherein the etching gas used in the dry etching process includes at least one of carbon tetrafluoride, difluoromethane, and nitrogen.

[0013] Optionally, the structure after the film layer is deposited is an intermediate structure, and the film layer is anisotropically etched using a dry etching process, including: introducing the etching gas into a reaction chamber containing the intermediate structure at a rate of 30-50 ml / min to etch the film layer, and controlling the pressure in the reaction chamber to be lower than 6 mTorr.

[0014] Optionally, after performing the deposition step and the etching step at least once in a cycle until the slope angle of the new slope structure is less than or equal to 60°, the method further includes forming a gate structure on the surface of the dielectric layer away from the substrate, the gate structure being adjacent to the etched film layer.

[0015] Optionally, the cyclic step includes: determining whether the slope angle of the new slope structure is greater than 60°; if the slope angle of the new slope structure is greater than 60°, cyclically performing the deposition step and the etching step at least once, until the slope angle of the new slope structure is less than or equal to 60°.

[0016] According to another aspect of this application, a semiconductor power device ramp is provided, which is prepared by any of the methods described above.

[0017] Applying the technical solution of this application, firstly, a substrate is provided through a growth step. The substrate includes a front side and a back side. A dielectric layer and a ramp structure are grown on a portion of the front surface of the substrate, and the ramp structure is located on the sidewall of the dielectric layer. Then, a film layer is deposited using an isotropic deposition method through a deposition step. The film layer at least covers the exposed surface of the front side of the substrate, the exposed surface of the dielectric layer, and the ramp surface of the ramp structure. Next, the film layer is etched using an anisotropic etching method through an etching step, exposing a portion of the front side of the substrate and the surface of the dielectric layer away from the substrate. After etching, the film layer covering the ramp structure and the ramp structure together form a new ramp structure. The longitudinal distance from the ramp surface of the new ramp structure to the front side of the substrate gradually decreases in the direction away from the dielectric layer. Finally, the deposition step and the etching step are cyclically executed through a cyclic step, such that the ramp angle of the new ramp structure is smaller than the ramp angle of the ramp structure obtained in the growth step. The ramp angle is the angle between the ramp surface and the front side of the substrate. This application increases the ratio between the width at the bottom of the slope and the height at the top of the slope structure by performing at least one isotropic deposition and anisotropic etching step on the dielectric layer, thus forming a gentler slope structure that meets the slope angle requirements. The process is simple, and the angle of the slope structure can be controlled by controlling the number of cycle steps, which reduces the difficulty of adjusting the slope structure angle and solves the problem of difficulty in adjusting the slope angle of the gentle slope of semiconductor power devices in the prior art. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 A schematic flowchart of a method for fabricating a semiconductor power device ramp according to an embodiment of this application is shown.

[0020] Figure 2 This illustration shows a schematic diagram of a semiconductor power device prepared by growing a dielectric layer and a ramp structure on the front side of a substrate during the ramp fabrication process according to an embodiment of this application.

[0021] Figure 3 A schematic diagram of a deposited film layer during the preparation of a semiconductor power device according to an embodiment of this application is shown.

[0022] Figure 4 A schematic diagram of a structure forming a ramp structure during the preparation of a semiconductor power device according to an embodiment of this application is shown.

[0023] Figure 5 A schematic diagram of a structure that retains a one-sided ramp structure during the fabrication of an LDMOS device according to an embodiment of this application is shown.

[0024] Figure 6 A schematic diagram of a structure for depositing a gate and a ramp field plate during the fabrication process of an LDMOS device according to an embodiment of this application is shown;

[0025] Figure 7 A schematic diagram of an LDMOS device provided according to an embodiment of this application is shown.

[0026] The above figures include the following reference numerals:

[0027] 10. Substrate; 12. Dielectric layer; 14. Film layer; 16. Ramp structure; 18. Gate; 20. Ramp field plate; 22. Contact hole; 24. Source; 26. Drain. Detailed Implementation

[0028] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0029] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be used interchangeably where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] Currently, the formation of mesa slopes in semiconductors mainly utilizes wet etching, taking advantage of the anisotropy of the material's crystal orientation to create a slope at a certain angle on the side. Although the process is simple, it suffers from poor uniformity, difficulty in controlling the etching endpoint, and the angle is limited by the crystal orientation and cannot be adjusted. Furthermore, this mesa slope formation method is not suitable for amorphous materials.

[0032] This application provides a method for fabricating an angle-controllable gentle slope structure. This method forms the gentle slope through multiple isotropic film depositions followed by anisotropic dry etching after the formation of a normal step. The slope angle can be progressively smaller through multiple processes. This application is simple to implement, overcomes the difficulty in adjusting the slope angle, and improves device performance and yield.

[0033] As described in the background section, the ramp angle of the ramp in the prior art is difficult to adjust. To solve the above technical problem, the embodiments of this application provide a method for manufacturing a ramp in a semiconductor power device and a ramp in a semiconductor power device.

[0034] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0035] Figure 1 This is a flowchart of a method for fabricating a sloped semiconductor power device according to an embodiment of this application. Figure 1 As shown, the method includes the following steps:

[0036] Step S201, growth step, as follows Figure 2 As shown, a substrate 10 is provided, the substrate 10 including a front side and a back side, a dielectric layer 12 and a ramp structure 16 are grown on a portion of the surface of the front side of the substrate 10, the ramp structure 16 being located on the sidewall of the dielectric layer 12.

[0037] Specifically, the substrate 10 material includes any one of silicon, silicon-germanium alloy and gallium arsenide, and the dielectric layer 12 is used as the dielectric layer (or isolation layer) of the field plate structure to prevent current leakage between different areas.

[0038] Step S202, deposition step, as follows Figure 3 As shown, a film layer 14 is formed by isotropic deposition, and the film layer 14 at least covers the exposed surface of the front side of the substrate 10, the exposed surface of the dielectric layer 12, and the slope surface of the slope structure 16.

[0039] Specifically, during the isotropic deposition process, the growth rate of the material on the exposed front surface of the substrate 10 and the exposed surface of the dielectric layer 12 is the same in all directions, ensuring the uniformity of the deposited film layer 14 on the surface of the substrate 10. Isotropic deposition can be achieved by chemical vapor deposition or physical vapor deposition processes.

[0040] Step S203, etching step, as follows Figure 4 As shown, the film layer is etched using anisotropic etching, exposing part of the front side of the substrate 10 and the surface of the dielectric layer 12 away from the substrate 10. After etching, the film layer covering the slope structure and the slope structure together form a new slope structure 16. The longitudinal distance from the slope surface of the new slope structure 16 to the front side of the substrate 10 gradually decreases in the direction away from the dielectric layer 12.

[0041] Step S204, a loop step, repeatedly executing the deposition step and the etching step, such that the slope angle of the new slope structure is smaller than the slope angle of the slope structure obtained in the growth step, the slope angle being the angle between the slope surface and the front surface of the substrate.

[0042] In the above embodiment, firstly, a substrate is provided through a growth step. The substrate includes a front side and a back side. A dielectric layer and a ramp structure are grown on a portion of the front surface of the substrate, and the ramp structure is located on the sidewall of the dielectric layer. Then, a film layer is deposited using an isotropic deposition method through a deposition step. The film layer at least covers the exposed surface of the front side of the substrate, the exposed surface of the dielectric layer, and the ramp surface of the ramp structure. Next, the film layer is etched using an anisotropic etching method through an etching step, exposing a portion of the front side of the substrate and the surface of the dielectric layer away from the substrate. The etched film layer covering the ramp structure and the ramp structure together form a new ramp structure. The longitudinal distance from the ramp surface of the new ramp structure to the front side of the substrate gradually decreases in the direction away from the dielectric layer. Finally, the deposition step and the etching step are cyclically executed through a cyclic step, such that the ramp angle of the new ramp structure is smaller than the ramp angle of the ramp structure obtained in the growth step. The ramp angle is the angle between the ramp surface and the front side of the substrate. This application increases the ratio between the width at the bottom of the slope and the height at the top of the slope structure by performing at least one isotropic deposition and anisotropic etching step on the dielectric layer, thus forming a gentler slope structure that meets the slope angle requirements. The process is simple, and the angle of the slope structure can be controlled by controlling the number of cycle steps, which reduces the difficulty of adjusting the slope structure angle and solves the problem of difficulty in adjusting the slope angle of the gentle slope of semiconductor power devices in the prior art.

[0043] Specifically, growing a dielectric layer and a ramp structure on a portion of the front surface of the substrate includes: first, growing a dielectric layer on a portion of the front surface of the substrate; then, depositing a film layer on the exposed surface of the front surface of the substrate and the exposed surface of the dielectric layer using an isotropic deposition method; next, etching the film layer using an anisotropic etching method, exposing a portion of the front surface of the substrate and the surface of the dielectric layer away from the substrate; and forming a ramp structure on the side of the dielectric layer after etching, wherein the distance from the ramp surface of the ramp structure to the front surface of the substrate gradually decreases in the direction away from the dielectric layer.

[0044] In one optional embodiment, an isotropic deposition method is used to form a film layer, comprising: depositing a film layer on the exposed surface of the front side of the substrate, the exposed surface of the dielectric layer, and the exposed surface of the slope structure, such that the longitudinal deposition rate and the transverse deposition rate are the same at any location, and the longitudinal deposition rate gradually increases along the direction from the top to the bottom of the slope, and the transverse deposition rate gradually increases. The longitudinal deposition rate is the deposition rate in a direction perpendicular to the front side of the substrate, and the transverse deposition rate is the deposition rate in a direction parallel to the front side of the substrate. In this embodiment, during the deposition step, the longitudinal deposition rate of the film layer at any location is the same as the transverse deposition rate of the film layer at that location, so that after the deposition step is completed, the longitudinal growth thickness of the film layer at any location is the same as the transverse growth thickness of the film layer at that location. Based on this, it is also required that the longitudinal deposition rate and the transverse deposition rate of the film layer gradually increase from the top to the bottom of the slope structure. Thus, after the deposition step is completed and before the etching step, the longitudinal growth thickness of the film layer gradually increases from the top to the bottom of the slope structure, and the transverse growth thickness of the film layer also gradually increases. That is, it is possible to increase the ratio between the bottom width and the top height of the slope structure before the etching step, so that the subsequent etching step makes the slope surface flatter and gentler.

[0045] Specifically, the deposition process requires real-time monitoring to ensure that parameters such as the thickness, uniformity, and density of the deposited layer meet the design requirements. After deposition is completed, the resulting structure needs to be cleaned and dried to remove impurities and residues adhering to the surface of the deposited layer.

[0046] In another alternative, an anisotropic etching method is used to etch the film layer, including: etching the film layer using an anisotropic etching method where the longitudinal etching rate is the same at all locations, the lateral etching rate is the same, and the longitudinal etching rate at the same location is greater than the lateral etching rate. The longitudinal etching rate is the etching rate along a direction perpendicular to the front surface of the substrate, and the lateral etching rate is the etching rate along a direction parallel to the front surface of the substrate. In this embodiment, during the etching step, from the top to the bottom of the ramp structure, the longitudinal etching rate is the same at all locations of the film layer, the lateral etching rate is the same at all locations of the film layer, and the longitudinal etching rate at any location is greater than the lateral etching rate at that location. Therefore, after the etching step, the longitudinal etching thickness and lateral etching rate are the same at all locations from the top to the bottom of the ramp structure, and the longitudinal etching thickness at any location is greater than the lateral etching thickness.

[0047] Specifically, after completing one deposition and etching cycle in the embodiment, the bottom of the slope structure extends outward relative to the bottom of the slope structure formed in the previous cycle. That is, the ratio between the width of the slope bottom and the height of the slope top gradually increases, the slope angle of the slope structure decreases, and the slope becomes gentler. As the number of cycles increases, the broken surface of the slope structure gradually becomes gentler and flatter, eventually tending towards a smooth slope.

[0048] In other exemplary embodiments, the film layer is etched using an anisotropic etching method in which the longitudinal etching rate is the same at each location, the lateral etching rate is the same, and the longitudinal etching rate at the same location is greater than the lateral etching rate. This includes etching the film layer using an anisotropic etching method in which the longitudinal etching rate is the same at each location and the lateral etching rate at each location is 0.

[0049] In the embodiment, the transverse etching rate of the film layer at the location is required to be 0. Thus, this etching step does not etch the film layer in the transverse direction, which can increase the ratio between the width of the bottom of the slope structure and the height of the top of the slope, thus making the slope gentler.

[0050] In one alternative embodiment, growing a dielectric layer and a ramp structure on a portion of the front surface of the substrate includes: growing the dielectric layer on the front surface of the substrate using a thermal oxidation method, wherein the thickness of the dielectric layer is... In the aforementioned embodiment, the use of thermal oxidation to grow a dielectric layer on the front side of the substrate ensures the uniformity and stability of the dielectric layer. Furthermore, the dielectric layer has a certain thickness, providing the necessary conditions and foundation for the subsequent formation of the slope structure. Simultaneously, controlling the thickness of the dielectric layer allows for control of the starting position of the slope structure, facilitating precise control over its shape and size.

[0051] In another alternative, the dielectric layer is grown on the front side of the substrate using a thermal oxidation method, comprising: thermally oxidizing the substrate at a temperature of 750–1100°C to obtain the dielectric layer. In this embodiment, growing the dielectric layer using a thermal oxidation method can provide a high-quality dielectric layer with low interface trap density.

[0052] In one alternative embodiment, an isotropic deposition method is used to deposit a film layer, which at least covers the exposed surface of the substrate, the exposed surface of the dielectric layer, and the slope surface of the ramp structure. This includes deposition using chemical vapor deposition (CVD) at a temperature of 700–800°C. In this embodiment, CVD is used to deposit the dielectric layer. CVD can be performed at relatively low temperatures, which helps reduce thermal stress and deformation problems caused by high temperatures.

[0053] Specifically, the thickness of the film can be controlled by adjusting parameters such as the type and flow rate of the reacting gas, reaction time, and temperature.

[0054] In another alternative approach, the film layer is etched using anisotropic etching, comprising: performing anisotropic etching on the film layer using a dry etching process, wherein the etching gas used in the dry etching process includes at least one of carbon tetrafluoride, difluoromethane, and nitrogen. In this embodiment, the dry etching process allows for precise control of the amount of material removed, thereby further ensuring that the film layer can form a preset slope angle.

[0055] In some exemplary embodiments of this application, the structure after depositing the film layer is an intermediate structure. Anisotropic etching of the film layer is performed using a dry etching process, including: introducing the etching gas into a reaction chamber containing the intermediate structure at a rate of 30–50 ml / min to etch the film layer, and controlling the pressure within the reaction chamber to be below 6 mTorr. In these embodiments, controlling the injection rate of the etching gas and the pressure conditions within the reaction chamber helps to further improve the accuracy and efficiency of anisotropic etching.

[0056] Specifically, after each etching step, the thickness of the deposited film and the etching parameters are flexibly adjusted based on the etching results to gradually approach the required slope angle.

[0057] In one alternative embodiment, after cyclically performing the deposition and etching steps at least once until the ramp angle of the new ramp structure is less than or equal to 60°, the method further includes forming a gate structure on the surface of the dielectric layer away from the substrate, the gate structure being adjacent to the etched film layer. In this embodiment, the close proximity between the formed gate structure and the etched film layer helps reduce the resistance and capacitance within the device, further optimizing the internal electric field distribution.

[0058] In another alternative embodiment, the cyclic step includes: determining whether the slope angle of the new slope structure is greater than 60°; if the slope angle of the new slope structure is greater than 60°, cyclically executing the deposition step and the etching step at least once, until the slope angle of the new slope structure is less than or equal to 60°. In this embodiment, by monitoring the slope angle of the new slope structure and cyclically executing the deposition step and the etching step, the slope angle is precisely controlled, so that the slope angle gradually meets the design requirements.

[0059] Embodiments of this application also provide a semiconductor power device ramp, which is fabricated using any of the methods described above.

[0060] In the embodiments described above, the semiconductor power device slope is fabricated using any of the methods described above, forming a relatively gentle slope structure that meets the slope angle requirements, thereby reducing the difficulty of adjusting the slope structure angle.

[0061] Specifically, semiconductor power devices can include MOS devices, LDMOS devices, and power device terminals, etc., with ramp structures serving as transition structures between the source / drain regions and the channel region or as field plates with gradually changing heights.

[0062] The following describes the application of the semiconductor power device fabrication method according to embodiments of this application in LDMOS devices.

[0063] First, proceed to step S201, the growth step, as follows: Figure 2 As shown, a substrate 10 is provided, the substrate 10 including a front side and a back side, a medium layer 12 and a slope structure 16 are grown on a portion of the surface of the front side of the substrate 10, the slope structure 16 is located on the sidewall of the medium layer 12, and the slope surface of the slope structure 16 forms an angle θ with the front side of the substrate 10, that is, the slope angle is θ.

[0064] After step S201, as Figure 3As shown, step S202, the deposition step, is performed, in which a film layer is formed by isotropic deposition. The film layer at least covers the exposed surface of the front side of the substrate 10, the exposed surface of the dielectric layer 12, and the slope surface of the slope structure 16.

[0065] After step S202, as Figure 4 As shown, step S203, the etching step, is performed, in which the film layer is etched using anisotropic etching, so that part of the front side of the substrate 10 and the surface of the dielectric layer 12 away from the substrate 10 are exposed. After etching, the film layer covering the slope structure and the slope structure together form the new slope structure 16. The longitudinal distance from the slope surface of the new slope structure 16 to the front side of the substrate 10 gradually decreases in the direction away from the dielectric layer 12.

[0066] After step S203, step S204 is performed, a loop step, in which the deposition step and the etching step are executed repeatedly, such that the slope angle of the new slope structure is smaller than the slope angle of the slope structure obtained in the growth step, wherein the slope angle is the angle between the slope surface and the front surface of the substrate.

[0067] After step S204, proceed to step S205, as follows: Figure 5 As shown, the medium layer 12 and the new slope structure 16 on one side are removed, while the new slope structure 16 on the other side is retained.

[0068] After step S205, proceed to step S206, as follows: Figure 6 As shown, a gate 18 is deposited on the front side of the substrate 10, the gate 18 is located on one side of the retained new slope structure 16, and the sidewall of the gate 18 contacts the lowest point of the slope of the retained new slope structure 16. A slope field plate 20 is deposited on the slope of the new slope structure 16, the gate 18 is adjacent to the new slope structure 16, and the gate 18 and the slope field plate 20 are patterned.

[0069] After step S206, step S207 is performed, in which a source electrode 24 and a drain electrode 26 are formed in the substrate 10, and contact holes 22 are formed on the exposed surfaces of the source electrode 24 and the drain electrode 26, respectively.

[0070] Subsequent steps follow a standard procedure, ultimately resulting in an LDMOS device structure as follows: Figure 7 As shown.

[0071] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0072] As can be seen from the above description, the embodiments described in this application achieve the following technical effects:

[0073] 1) A method for fabricating a ramp in a semiconductor power device according to this application, firstly, through a growth step, a substrate is provided, the substrate including a front side and a back side, a dielectric layer and a ramp structure are grown on a portion of the front surface of the substrate, the ramp structure being located on the sidewall of the dielectric layer; then, through a deposition step, a film layer is deposited using isotropic deposition, the film layer at least covering the exposed surface of the front side of the substrate, the exposed surface of the dielectric layer, and the ramp surface of the ramp structure; next, through an etching step, the film layer is etched using an anisotropic etching method, so that a portion of the front side of the substrate and the surface of the dielectric layer away from the substrate are exposed, the film layer covering the ramp structure after etching and the ramp structure together form a new ramp structure, the longitudinal distance from the ramp surface of the new ramp structure to the front side of the substrate gradually decreases in the direction away from the dielectric layer; finally, through a cyclic step, the deposition step and the etching step are cyclically executed, so that the ramp angle of the new ramp structure is less than the ramp angle of the ramp structure obtained in the growth step, the ramp angle being the angle between the ramp surface and the front side of the substrate. This application increases the ratio between the width at the bottom of the slope and the height at the top of the slope structure by performing at least one isotropic deposition and anisotropic etching step on the dielectric layer, thus forming a gentler slope structure that meets the slope angle requirements. The process is simple, and the angle of the slope structure can be controlled by controlling the number of cycle steps, which reduces the difficulty of adjusting the slope structure angle and solves the problem of difficulty in adjusting the slope angle of the gentle slope of semiconductor power devices in the prior art.

[0074] 2) The semiconductor power device slope of this application is made by any of the methods described, forming a relatively gentle slope structure that meets the slope angle requirements, thereby reducing the difficulty of adjusting the slope structure angle.

[0075] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a sloped-down semiconductor power device, characterized in that, include: The growth step includes providing a substrate, the substrate having a front side and a back side, and growing a medium layer and a ramp structure on a portion of the surface of the front side of the substrate, the ramp structure being located on the sidewall of the medium layer; In the deposition step, an isotropic deposition method is used to deposit a film layer, which at least covers the exposed surface of the front side of the substrate, the exposed surface of the dielectric layer, and the slope surface of the slope structure; In the etching step, the film layer is etched using anisotropic etching, so that part of the front side of the substrate and the surface of the dielectric layer away from the substrate are exposed. After etching, the film layer covering the slope structure and the slope structure together form the new slope structure. The longitudinal distance from the slope surface of the new slope structure to the front side of the substrate gradually decreases in the direction away from the dielectric layer. The process involves repeatedly performing the deposition and etching steps to achieve a slope angle smaller than that of the slope structure obtained in the growth step, where the slope angle is the angle between the slope surface and the front surface of the substrate.

2. The method according to claim 1, characterized in that, Films are formed by isotropic deposition, including: Films are deposited on the exposed surfaces of the substrate, the dielectric layer, and the ramp structure, such that the longitudinal deposition rate and the transverse deposition rate are the same at any location, and the longitudinal deposition rate gradually increases along the direction from the top to the bottom of the ramp, and the transverse deposition rate gradually increases. The longitudinal deposition rate is the deposition rate in a direction perpendicular to the front surface of the substrate, and the transverse deposition rate is the deposition rate in a direction parallel to the front surface of the substrate.

3. The method according to claim 1, characterized in that, The film layer is etched using anisotropic etching, including: The film layer is etched using an anisotropic etching method, in which the longitudinal etching rate and the lateral etching rate are the same at all locations, and the longitudinal etching rate at the same location is greater than the lateral etching rate. The longitudinal etching rate is the etching rate along the direction perpendicular to the front side of the substrate, and the lateral etching rate is the etching rate along the direction parallel to the front side of the substrate.

4. The method according to claim 3, characterized in that, The film layer is etched using an anisotropic etching method where the longitudinal etching rate is the same at all locations, the lateral etching rate is the same, and the longitudinal etching rate at the same location is greater than the lateral etching rate. This includes etching the film layer using an anisotropic etching method where the longitudinal etching rate is the same at all locations and the lateral etching rate at all locations is 0.

5. The method according to claim 1, characterized in that, A dielectric layer and a ramp structure are grown on a portion of the front surface of the substrate, comprising: growing the dielectric layer on the front surface of the substrate using a thermal oxidation method, wherein the thickness of the dielectric layer is [missing information].

6. The method according to claim 5, characterized in that, The dielectric layer is grown on the front side of the substrate using a thermal oxidation method, which includes: thermally oxidizing the substrate at a temperature of 750–1100°C to obtain the dielectric layer.

7. The method according to claim 1, characterized in that, A film layer is formed by isotropic deposition, wherein the film layer at least covers the exposed surface of the front side of the substrate, the exposed surface of the dielectric layer, and the slope surface of the slope structure, including deposition by chemical vapor deposition at a temperature of 700–800°C.

8. The method according to claim 1, characterized in that, Etching the film layer using anisotropic etching includes: performing anisotropic etching on the film layer using a dry etching process, wherein the etching gas used in the dry etching process includes at least one of carbon tetrafluoride, difluoromethane, and nitrogen.

9. The method according to claim 8, characterized in that, The structure after the film layer is deposited is an intermediate structure. The film layer is anisotropically etched using a dry etching process, including: introducing the etching gas into a reaction chamber containing the intermediate structure at a rate of 30-50 ml / min to etch the film layer, and controlling the pressure in the reaction chamber to be lower than 6 mTorr.

10. The method according to claim 1, characterized in that, After performing the deposition step and the etching step at least once in a cycle until the slope angle of the new slope structure is less than or equal to 60°, the method further includes forming a gate structure on the surface of the dielectric layer away from the substrate, the gate structure being adjacent to the etched film layer.

11. The method according to claim 1, characterized in that, The cyclic steps include: Determine whether the slope angle of the new slope structure is greater than 60°; If the slope angle of the new slope structure is greater than 60°, the deposition step and the etching step are performed at least once in a cycle until the slope angle of the new slope structure is less than or equal to 60°.

12. A slope for a semiconductor power device, characterized in that, The semiconductor power device ramp is fabricated using the method described in any one of claims 1 to 11.

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