Method for manufacturing semiconductor device and semiconductor device

Abstract

Embodiments of the present application relate to a method for manufacturing a semiconductor device and a semiconductor device. In the method for manufacturing a semiconductor device of an embodiment, a structure is prepared. The structure includes a semiconductor layer, a first metal layer provided over a part of the semiconductor layer, and a second metal layer containing aluminum provided over another part of the semiconductor layer, which is provided around the first metal layer along a first surface perpendicular to a first direction from the semiconductor layer toward the first metal layer. In the manufacturing method, a first layer containing substantially no aluminum is formed on a side surface of the second metal layer opposite to the first metal layer. In the manufacturing method, an upper surface of the semiconductor layer is processed by wet etching. In the manufacturing method, a semi-insulating layer which is in contact with the upper surface of the semiconductor layer and is electrically connected to the first metal layer and the second metal layer is formed.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2025-047038 (filed on March 21, 2025). This application incorporates all the contents of the basic application by reference to that basic application. Technical Field

[0003] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Technology

[0004] Semiconductor devices such as diodes, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and Insulated Gate Bipolar Transistors (IGBTs) are used for power conversion and other applications. Semiconductor devices are required to be resistant to short circuits. Summary of the Invention

[0005] In a method for manufacturing a semiconductor device according to an embodiment, a structure is prepared. The structure includes: a semiconductor layer; a first metal layer disposed on a portion of the semiconductor layer; and an aluminum-containing second metal layer disposed on another portion of the semiconductor layer, arranged around the first metal layer along a first surface perpendicular to a first direction from the semiconductor layer toward the first metal layer. In the manufacturing method, a substantially aluminum-free first layer is formed on the side surface of the second metal layer opposite to the first metal layer. In the manufacturing method, the upper surface of the semiconductor layer is processed by wet etching. In the manufacturing method, a semi-insulating layer is formed that is in contact with the upper surface of the semiconductor layer and electrically connected to both the first and second metal layers.

[0006] According to this embodiment, a method for manufacturing a semiconductor device and a semiconductor device capable of suppressing short circuits can be provided. Attached Figure Description

[0007] Figure 1 This is a top view showing the semiconductor device according to the first embodiment.

[0008] Figure 2 yes Figure 1 Sectional view II-II.

[0009] Figure 3 (a) and Figure 3 (b) is a cross-sectional view showing the manufacturing method of the first embodiment.

[0010] Figure 4 (a) and Figure 4(b) is a cross-sectional view showing the manufacturing method of the first embodiment.

[0011] Figure 5 (a) and Figure 5 (b) is a cross-sectional view showing the manufacturing method of the first embodiment.

[0012] Figure 6 (a)~ Figure 6 (c) is a cross-sectional view showing the manufacturing method of the reference example.

[0013] Figure 7 (a) and Figure 7 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first variation of the first embodiment.

[0014] Figure 8 (a) and Figure 8 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first variation of the first embodiment.

[0015] Figure 9 (a) and Figure 9 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second variation of the first embodiment.

[0016] Figure 10 This is a top view showing the semiconductor device according to the second embodiment.

[0017] Figure 11 yes Figure 10 XI-XI sectional view.

[0018] Figure 12 This is a cross-sectional view showing a portion of the semiconductor device according to the third embodiment.

[0019] Explanation of reference numerals in the attached figures

[0020] 1: Lower electrode; 2: Upper electrode; 2a: Side surface; 3: EQPR electrode; 3a: Side surface; 4: Gate pad; 10: Semiconductor layer; 10a: First part; 10b: Second part; 11: n - 12: p-type semiconductor region; 12a: p-type semiconductor region + Type 13: P-type contact area; Type 14: n + Type semiconductor region; 15:p + Type-type collector region; 16:n + Type contact area; 17:n +Type EQPR region; 19: Gate electrode; 19a: Gate insulating layer; 21: First layer; 22: Second layer; 23, 24: Insulating layer; 24: Semi-insulating layer; 100, 200, 300: Semiconductor device; L, L1, L2: Layer; EL: Dissolution layer; M: Mask; ML: Metal layer; ML1: First metal layer; ML2: Second metal layer; ML3: Third metal layer; S1, S2: Sidewalls; ST: Structure Detailed Implementation

[0021] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the proportions between parts, etc., may not be the same as in reality. Furthermore, even when representing the same parts, there may be cases where the dimensions and proportions differ according to the drawings. In this specification and the drawings, elements identical to those already described are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.

[0022] In the following explanation, n + n - and p + The markings "+" and "p" indicate the relative concentration of impurities in each conductivity type. Specifically, a marking with a "+" indicates a relatively higher impurity concentration compared to a marking without any marking. Conversely, a marking with a "-" indicates a relatively lower impurity concentration compared to a marking without any marking.

[0023] The embodiments described below can also be implemented by reversing the p-type and n-type of each semiconductor region.

[0024] (First Implementation)

[0025] Figure 1 This is a top view showing the semiconductor device according to the first embodiment. Figure 2 yes Figure 1 Sectional view II-II.

[0026] like Figure 1 and Figure 2 As shown, the semiconductor device 100 of the first embodiment includes a lower electrode 1 (first electrode), an upper electrode 2 (second electrode), an equivalent-potential ring (EQPR) electrode 3 (third electrode), a semiconductor layer 10, a first layer 21, a second layer 22, an insulating layer 23, an insulating layer 24, and a semi-insulating layer 25. Furthermore, in Figure 1 In this paper, the semi-insulating layer 25 formed on the EQPR electrode 3 is omitted.

[0027] In the description of the implementation, an XYZ orthogonal coordinate system is used. The direction from the lower electrode 1 toward the semiconductor layer 10 is defined as the Z direction (first direction). Two directions perpendicular to and orthogonal to the Z direction are defined as the Y direction and the X direction. For clarity, the direction from the lower electrode 1 toward the semiconductor layer 10 is referred to as "up," and its opposite direction as "down." These directions are based on the relative positional relationship between the lower electrode 1 and the semiconductor layer 10 and are independent of the direction of gravity.

[0028] like Figure 1 As shown, the upper electrode 2 and the EQPR electrode 3 are disposed on the upper surface of the semiconductor device 100 and are separated from each other. The EQPR electrode 3 is located around the upper electrode 2 along the XY plane (first plane). For example, the EQPR electrode 3 is disposed along the outer periphery of the semiconductor device 100.

[0029] like Figure 2 As shown, the lower electrode 1 is disposed on the lower surface of the semiconductor device 100. The semiconductor layer 10 is disposed on the lower electrode 1, located between the lower electrode 1 and the upper electrode 2, and between the lower electrode 1 and the EQPR electrode 3.

[0030] like Figure 1 and Figure 2 As shown, the semiconductor layer 10 includes a first portion 10a and a second portion 10b. The first portion 10a includes a central portion in the XY plane of the semiconductor device 100. The second portion 10b is located around the first portion 10a along the XY plane. The first portion 10a is a cell portion. A cell portion is a region through which current mainly flows when the semiconductor device 100 operates. The second portion 10b is an end portion. An end portion is a region in which the depletion layer extends toward the outer periphery of the semiconductor device 100 when the semiconductor device 100 withstands voltage. An upper electrode 2 is located above the first portion 10a. An EQPR electrode 3 is located above the second portion 10b.

[0031] Semiconductor device 100 is, for example, a diode. Semiconductor layer 10 contains n - p-type semiconductor region 11 (first semiconductor region), p-type semiconductor region 12 (second semiconductor region), p + Type contact region 12a, p-type guard ring region 13 (third semiconductor region), n + Type contact area 16, and n + Type EQPR region 17. n-type is an example of the first conductivity type. p-type is an example of the second conductivity type.

[0032] n + The contact area 16 is disposed above the lower electrode 1 and is electrically connected to the lower electrode 1. - Type semiconductor region 11 is set in n + Above the contact area 16, via n+ The contact area 16 is electrically connected to the lower electrode 1. - The n-type impurity concentration in semiconductor region 11 is higher than that in n + The concentration of n-type impurities in the contact region 16 is low.

[0033] p-type semiconductor region 12 is disposed in the first part 10a in n - Above semiconductor region 11. + The p-type contact region 12a is disposed on a portion of the p-type semiconductor region 12. + The concentration of p-type impurities in the p-type contact region 12a is higher than the concentration of p-type impurities in the p-type semiconductor region 12. The p-type semiconductor region 12 and p... + The contact area 12a is electrically connected to the upper electrode 2.

[0034] p-type guard ring regions 13 are disposed around the p-type semiconductor region 12 along the XY plane. The p-type guard ring regions 13 are located in the second portion 10b. Multiple p-type guard ring regions 13 are disposed in the direction from the first portion 10a toward the second portion 10b. The multiple p-type guard ring regions 13 are separated from each other. The p-type impurity concentration in the p-type guard ring regions 13 can be the same as or higher than the p-type impurity concentration in the p-type semiconductor region 12.

[0035] n + Type EQPR region 17 is arranged along the XY plane around multiple p-type protective ring regions 13. + The EQPR region 17 is separated from the outermost p-type protective ring region 13. For example, n + The EQPR region 17 is disposed along the outer edge of the XY plane on the upper surface of the semiconductor layer 10. + The concentration of n-type impurities in region 17 of type EQPR is higher than that of n-type impurities. - The n-type impurity concentration is high in the semiconductor region 11.

[0036] An insulating layer 23 is disposed between a portion of the semiconductor layer 10 and the inner peripheral portion of the EQPR electrode 3. The outer peripheral portion of the EQPR electrode 3 is disposed between n + Type EQPR region 17 is connected to n + The p-type semiconductor region 17 is electrically connected. An insulating layer 24 is disposed between the outer peripheral portion of the p-type semiconductor region 12 and the outer peripheral portion of the upper electrode 2.

[0037] The EQPR electrode 3 has a side surface 3a opposite to the upper electrode 2. A first layer 21 is disposed on the side surface 3a and is located above the insulating layer 23. The upper electrode 2 has a side surface 2a opposite to the EQPR electrode 3. A second layer 22 is disposed on the side surface 2a and is located above the insulating layer 24.

[0038] A semi-insulating layer 25 covers the outer periphery of the semiconductor device 100. Specifically, the semi-insulating layer 25 is in contact with the outer periphery of the upper surface of the upper electrode 2, the surface of the second layer 22, the surface of the insulating layer 24, the upper surface of the semiconductor layer 10, the surface of the insulating layer 23, the surface of the first layer 21, and the upper surface of the EQPR electrode 3. The semi-insulating layer 25 is electrically connected to the upper electrode 2 and the EQPR electrode 3.

[0039] The semi-insulating layer 25 has a resistivity sufficient to allow a small current to flow. When a potential difference exists between the upper electrode 2 and the EQPR electrode 3, a small current flows through the semi-insulating layer 25 between them. For example, the resistivity of the semi-insulating layer 25 is greater than 1.0 × 10⁻⁶. 8 Ω·cm and less than 1.0×10 13 Ω·cm. The resistivity of the semi-insulating layer 25 can be less than 1.0 × 10⁻⁶ Ω·cm. 12 Ω·cm, or less than 1.0×10 11 Ω·cm.

[0040] The operation of the semiconductor device 100 will be explained. When a positive voltage is applied to the upper electrode 2 relative to the lower electrode 1, the voltage generated by n... - A forward voltage is applied to the diode formed by the p-type semiconductor region 11 and the p-type semiconductor region 12. Current flows from the p-type semiconductor region 12 to the n-type semiconductor region 12. - In semiconductor region 11, semiconductor device 100 is in the on state. Then, when a positive voltage is applied to lower electrode 1 relative to upper electrode 2, current flow stops, and semiconductor device 100 is in the off state. Applying a reverse voltage to the diode depletes the depletion layer from n... - The pn junction extends between the p-type semiconductor region 11 and the p-type semiconductor region 12. In the second part 10b, the depletion layer also extends from the n-type semiconductor region 12. - The pn junction is extended between the p-type semiconductor region 11 and the p-type guard ring region 13.

[0041] Furthermore, near the outer edge of the semiconductor device 100, the extension of the depletion layer is affected by n + Type EQPR region 17 suppression. When the depletion layer reaches the outer edge of the semiconductor device 100, leakage current flows through the side of the semiconductor device 100 between the lower electrode 1 and the upper electrode 2. By utilizing n + The EQPR region 17 suppresses the expansion of the depletion layer and can suppress the generation of leakage current.

[0042] When semiconductor device 100 is in the off state, n +The potential of the EQPR region 17 and the EQPR electrode 3 is substantially the same as that of the lower electrode 1. Due to the potential difference between the upper electrode 2 and the EQPR electrode 3, a small current flows from the EQPR electrode 3 to the upper electrode 2 through the semi-insulating layer 25. This current flow creates a potential gradient in the semi-insulating layer 25. The semi-insulating layer 25 is electrically connected to the p-type guard ring region 13. The potential of each p-type guard ring region 13 is determined according to its position. By providing the semi-insulating layer 25, the potential variation of each p-type guard ring region 13 can be reduced when the semiconductor device 100 is in the off state. As a result, the expansion of the depletion layer in the second part 10b can be stabilized, and the withstand voltage of the semiconductor device 100 can be stabilized.

[0043] An example of the materials used in each component will be described. The lower electrode 1, upper electrode 2, and EQPR electrode 3 contain aluminum. In addition to aluminum, the lower electrode 1, upper electrode 2, and EQPR electrode 3 may also contain copper or silicon. Besides the aluminum-containing layer, the lower electrode 1, upper electrode 2, and EQPR electrode 3 may also contain a barrier layer such as a titanium layer or a titanium nitride layer at the interface with the semiconductor layer 10.

[0044] Semiconductor layer 10 contains silicon, silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity.

[0045] The first layer 21 and the second layer 22 are substantially free of aluminum. "Substantially free" means that aluminum is not intentionally added. For example, if the aluminum content in the first layer 21 and the second layer 22 is less than 0.1% by mass, then the first layer 21 and the second layer 22 can be considered substantially free of aluminum. The content can be analyzed using energy dispersive X-ray spectrophotometry (EDX) on a cross-section.

[0046] For example, the first layer 21 and the second layer 22 contain compounds of metallic materials, semiconductor materials, or compounds of metallic materials. The first layer 21 and the second layer 22 can be conductive or insulating. As an example, the first layer 21 and the second layer 22 contain one or more materials selected from the group consisting of tungsten, molybdenum, titanium nitride, silicon nitride, and tantalum nitride.

[0047] Insulating layers 23 and 24 contain insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Semi-insulating layer 25 contains semi-insulating silicon nitride (SInSiN). Alternatively, semi-insulating layer 25 may also contain semi-insulating polycrystalline silicon (SIPOS).

[0048] Figure 3 of (a), Figure 3 (b) Figure 4 of (a), Figure 4(b) Figure 5 (a) and Figure 5 (b) is a cross-sectional view showing the manufacturing method according to the first embodiment.

[0049] First, prepare using well-known methods. Figure 3 The structure ST is shown in (a). In the structure ST, the semiconductor layer 10 includes n - p-type semiconductor region 11, p-type semiconductor region 12, p + Type 12a contact area, Type 13 p protective ring area, n + Type contact area 16 and n + Type EQPR region 17. In p-type semiconductor region 12 and p + A first metal layer ML1 is disposed above the contact area 12a. An insulating layer IL is disposed above the plurality of p-type protective ring areas 13. A second metal layer ML2 is disposed around the first metal layer ML1 and the insulating layer IL along the XY plane. The second metal layer ML2 is located at n + Above the EQPR region 17. The first metal layer ML1 and the second metal layer ML2 are respectively with Figure 1 as well as Figure 2 The upper electrode 2 and EQPR electrode 3 are shown in the diagram.

[0050] like Figure 3 As shown in (b), layer L is formed along the surface of the first metal layer ML1, the upper surface of the insulating layer IL, and the surface of the second metal layer ML2. Layer L contains one or more materials selected from the group consisting of tungsten, molybdenum, titanium nitride, silicon nitride, and tantalum nitride. When layer L contains tungsten, molybdenum, titanium nitride, or tantalum nitride, layer L can be formed by sputtering. When layer L contains silicon nitride, layer L can be formed by chemical vapor deposition (CVD).

[0051] A portion of layer L is removed using reactive ion etching (RIE). Thus, as... Figure 4 As shown in (a), layer L formed on the upper surface of the first metal layer ML1, the upper surface of the insulating layer IL, and the upper surface of the second metal layer ML2 is removed. RIE is an anisotropic etching process that removes the object using ions incident along the Z-direction. The thickness of layer L in the Z-direction formed on the side surface S1 of the first metal layer ML1 and the side surface S2 of the second metal layer ML2 is greater than the thickness of other portions of layer L in the Z-direction. Therefore, after RIE, layer L remains on the side surfaces S1 and S2. The layer L on side surface S1 and the layer L on side surface S2 are respectively... Figure 2 The second layer 22 and the first layer 21 shown correspond to each other.

[0052] A portion of the insulating layer IL is removed using photolithography and RIE. Thus, as... Figure 4As shown in (b), the insulating layer IL is divided into insulating layer 23 and insulating layer 24. Additionally, each p-type guard ring region 13 is exposed. The exposed upper surface of the semiconductor layer 10 is processed by wet etching. In the wet etching, a fluorine-containing solution is used. Through this wet etching, the thin film of oxide formed on the upper surface of the semiconductor layer 10 is removed. For example, dilute hydrofluoric acid or buffered hydrofluoric acid can be used as the solution.

[0053] like Figure 5 As shown in (a), a semi-insulating layer 25 is formed by CVD on the upper surface of the outer peripheral portion of the first metal layer ML1, the surface of the second layer 22, the surface of the insulating layer 24, the upper surface of the semiconductor layer 10, the surface of the insulating layer 23, the surface of the first layer 21, and the upper surface of the second metal layer ML2. By pre-treating the upper surface of the semiconductor layer 10 using wet etching, a more reliable electrical connection can be made between the p-type guard ring region 13 and the semi-insulating layer 25.

[0054] The lower surface of semiconductor layer 10 is ground until semiconductor layer 10 reaches a specified thickness. For example... Figure 5 As shown in (b), a third metal layer ML3 is formed by sputtering on the ground lower surface. The third metal layer ML3 and Figure 2 Corresponding to the lower electrode 1 shown. Through the above processing, the semiconductor device 100 of the first embodiment is manufactured.

[0055] Figure 6 (a)~ Figure 6 (c) is a cross-sectional view showing the manufacturing method of the reference example.

[0056] In the manufacturing method of the reference example, such as Figure 6 As shown in (a), layer L is not formed on the side surface S1 of the first metal layer ML1 and the side surface S2 of the second metal layer ML2. In this state, the upper surface of the semiconductor layer 10 is processed by wet etching.

[0057] At this point, the hydrofluoric acid-containing solution reacts with the aluminum contained in the first metal layer ML1 and the second metal layer ML2, causing the aluminum to dissolve from the first metal layer ML1 and the second metal layer ML2. A portion of the dissolved aluminum deposits on the upper surface of the semiconductor layer 10, such as... Figure 6 As shown in (b), a dissolution layer EL is formed. Then, as... Figure 6 As shown in (c), a semi-insulating layer 25 is formed.

[0058] The advantages of the manufacturing method of the first embodiment will be explained.

[0059] If it exists Figure 6If a semiconductor device is used in the state of the dissolved layer EL shown in (c), the aluminum contained in the dissolved layer EL will either condense or move along the direction of the electric field. If the aluminum in the dissolved layer EL causes a connection between the upper electrode 2 and the EQPR electrode 3, a short circuit will occur between the lower electrode 1 and the upper electrode 2.

[0060] Regarding this issue, in the manufacturing method of the first embodiment, during wet etching, a first layer 21 is formed at least on the side surface S2 of the second metal layer ML2. The first layer 21 is substantially free of aluminum. Therefore, even if the first layer 21 is exposed to the etching solution used in wet etching, aluminum will not dissolve from the first layer 21. By forming the first layer 21, aluminum dissolution from the side surface S2 can be suppressed. As a result, short circuits between the lower electrode 1 and the upper electrode 2 due to dissolved aluminum can be suppressed.

[0061] The EQPR electrode 3 is disposed around the upper electrode 2, and the surface area of ​​the inner peripheral side of the EQPR electrode 3 is larger than the surface area of ​​the outer peripheral side of the upper electrode 2. Therefore, if the first layer 21 is formed at least on the side S2 of the second metal layer ML2, the amount of aluminum dissolved by wet etching can be effectively reduced.

[0062] According to the first embodiment, a method for manufacturing a semiconductor device capable of suppressing the occurrence of short circuits is provided, as well as a semiconductor device that suppresses the occurrence of short circuits.

[0063] More preferably, such as Figure 4 As shown in (a), a second layer 22 is also formed on the side surface S1 of the first metal layer ML1. By forming the second layer 22 on the side surface S1, it is possible to suppress the dissolution of aluminum from the side surface S1. As a result, it is possible to more reliably suppress the occurrence of short circuits between the lower electrode 1 and the upper electrode 2 caused by the dissolved aluminum.

[0064] The first layer 21 and the second layer 22 are preferably conductive. When the first layer 21 and the second layer 22 are conductive, the side surface S1 of the first metal layer ML1 is electrically connected to the semi-insulating layer 25 via the second layer 22. The side surface S2 of the second metal layer ML2 is electrically connected to the semi-insulating layer 25 via the first layer 21. Thus, the first metal layer ML1 and the second metal layer ML2 are more reliably electrically connected to the semi-insulating layer 25. As a result, the expansion of the depletion layer in the second part 10b can be made more stable.

[0065] Furthermore, in the semiconductor device 100 according to the embodiment, a first layer 21 is provided on the side of the EQPR electrode 3. The first layer 21 is preferably conductive. The conductive first layer 21, provided on the side of the EQPR electrode 3, functions substantially as part of the EQPR electrode 3. By providing the conductive first layer 21, the resistance of the EQPR electrode 3 can be reduced compared to the case where the first layer 21 is not provided. Therefore, the EQPR electrode 3 is more reliably electrically connected to the semi-insulating layer 25.

[0066] Furthermore, it is preferable that a conductive second layer 22 is provided on the side of the upper electrode 2 in the semiconductor device 100. The conductive second layer 22 functions essentially as part of the upper electrode 2. By providing the conductive second layer 22, the resistance of the upper electrode 2 can be reduced compared to the case where the second layer 22 is not provided. As a result, the upper electrode 2 is more reliably electrically connected to the semi-insulating layer 25.

[0067] (First variation)

[0068] Figure 7 of (a), Figure 7 (b) Figure 8 (a) and Figure 8 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first variation of the first embodiment.

[0069] First, such as Figure 7 As shown in (a), a structure is prepared to form an insulating layer IL and a metal layer ML on a semiconductor layer 10. The metal layer ML covers the upper surface of the semiconductor layer 10 and the surface of the insulating layer IL.

[0070] A layer L1 is formed on top of the metal layer ML. Layer L1 contains one or more materials selected from the group consisting of tungsten, molybdenum, titanium nitride, silicon nitride, and tantalum nitride. Through photolithography and RIE, such as... Figure 7 As shown in (b), a portion of layer L1 is removed. Layer L1 remains above the portion of the metal layer ML where the upper electrode 2 and the EQPR electrode 3 are formed.

[0071] A portion of the metal layer ML is removed using photolithography and RIE. This results in the metal layer ML being divided into a first metal layer ML1 and a second metal layer ML2. (Example:) Figure 8 As shown in (a), layer L2 is formed on the surface of layer L1, the side surface S1 of the first metal layer ML1, the surface of the insulating layer IL, and the side surface S2 of the second metal layer ML2. Layer L2 contains one or more materials selected from the group consisting of tungsten, molybdenum, titanium nitride, silicon nitride, and tantalum nitride. The material of layer L2 may be the same as or different from the material of layer L1.

[0072] A portion of layer L2 is removed via RIE. The Z-direction thickness of layer L2 formed on sides S1 and S2 is greater than the Z-direction thickness of other portions of layer L2. Therefore, as... Figure 8 As shown in (b), layer L2 remains on sides S1 and S2. In addition, layer L1, which is covered by layer L2, also remains.

[0073] Afterwards, execution and Figure 4 The process is the same as the process shown in (b) thereafter. That is, a portion of the insulating layer IL is removed to form a semi-insulating layer 25, and a third metal layer ML3 is formed. Through the above processes, the semiconductor device 100 is manufactured.

[0074] According to the first variation, similar to the first embodiment described above, the leaching of aluminum from the first metal layer ML1 and the second metal layer ML2 is suppressed.

[0075] Furthermore, in the manufacturing method of the first modified example, the upper surface of the first metal layer ML1 and the upper surface of the second metal layer ML2 are covered by layer L1, and the side surface S1 of the first metal layer ML1 and the side surface S2 of the second metal layer ML2 are covered by layer L2. Layers L1 and L2 formed on the surface of the EQPR electrode 3 are equivalent to... Figure 2 The first layer 21 is shown. Layers L1 and L2 formed on the surface of the upper electrode 2 correspond to the second layer 22. That is, according to the manufacturing method of the first modified example, and... Figure 2 Compared to the configuration shown, the first layer 21 is further formed on the upper surface of the EQPR electrode 3, and the second layer 22 is further formed on the upper surface of the upper electrode 2. In this case, in order to electrically connect the first metal layer ML1 and the second metal layer ML2 to the semi-insulating layer 25, at least one of layer L1 and layer L2 is conductive. Preferably, both layer L1 and layer L2 are conductive.

[0076] (Second variation)

[0077] Figure 9 (a) and Figure 9 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second variation of the first embodiment.

[0078] In the manufacturing method of the second variation, the following steps are first performed: Figure 3 As shown in (b), layer L is formed. Then, through photolithography and RIE, as... Figure 9 As shown in (a), a mask M is formed on the first metal layer ML1 and the second metal layer ML2. The mask M may be a photoresist.

[0079] like Figure 9 As shown in (b), layer L formed on top of insulating layer IL is removed using a RIE with mask M. Mask M is then removed. Afterwards, a process is performed with… Figure 4 The process is the same as the process shown in (b) thereafter. That is, a portion of the insulating layer IL is removed, wet etching is performed to form a semi-insulating layer 25, and a third metal layer ML3 is formed.

[0080] According to the second variation, similar to the first embodiment and its first variation, the leaching of aluminum from the first metal layer ML1 and the second metal layer ML2 is suppressed.

[0081] Furthermore, in the manufacturing method of the second modification, similarly to the first modification, the surfaces of the first metal layer ML1 and the second metal layer ML2 are covered by layer L. Therefore, in order to electrically connect the first metal layer ML1 and the second metal layer ML2 to the semi-insulating layer 25, layer L is conductive.

[0082] (Second Implementation)

[0083] Figure 10 This is a top view showing the semiconductor device according to the second embodiment. Figure 11 yes Figure 10 The XI-XI sectional view. Additionally, in Figure 10 In this paper, the semi-insulating layer 25 formed on the EQPR electrode 3 is omitted.

[0084] The semiconductor device 200 in the second embodiment is a MOSFET. For example... Figure 10 As shown, the semiconductor device 200, compared to the semiconductor device 100 of the first embodiment, further includes a gate pad 4. Additionally, as... Figure 11 As shown, semiconductor layer 10 also includes n + Type semiconductor region 14 (fourth semiconductor region) and gate electrode 19.

[0085] like Figure 10 As shown, on the upper surface of the semiconductor device 200, the upper electrode 2 and the gate pad 4 are separated from each other and electrically isolated. The gate pad 4 is located on the first portion 10a. The EQPR electrode 3 and the semi-insulating layer 25 are disposed around the upper electrode 2 and the gate pad 4 along the XY plane.

[0086] like Figure 11 As shown, n + A p-type semiconductor region 14 is disposed on top of the p-type semiconductor region 12. A gate electrode 19 is opposite to the p-type semiconductor region 12 through a gate insulating layer 19a.

[0087] exist Figure 11 In the example shown, the p-type semiconductor region 12 and the gate electrode 19 are alternately arranged in the X direction. A pair of n-type semiconductor regions 12, separated from each other in the X direction, are disposed above one p-type semiconductor region 12. + Type semiconductor region 14. In a pair of n +p is disposed between the semiconductor regions 14 + Type contact region 12a. Each p-type semiconductor region 12, each p... + Type contact area 12a, each n + The semiconductor region 14 and each gate electrode 19 extend along the Y direction.

[0088] The gate electrode 19 contains semiconductor materials such as polycrystalline silicon. To reduce the resistivity of the gate electrode 19, p-type or n-type impurities can be added to the gate electrode 19. The gate insulating layer 19a contains insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0089] Other structures in semiconductor device 200 may be the same as those in semiconductor device 100. For example, a plurality of p-type guard ring regions 13 are provided in the second portion 10b. A first layer 21, a second layer 22, an insulating layer 23, an insulating layer 24, and a semi-insulating layer 25 are provided on the second portion 10b.

[0090] In the semiconductor device 200, the lower electrode 1 functions as the drain electrode, and the upper electrode 2 functions as the source electrode. When a positive voltage is applied to the lower electrode 1 relative to the upper electrode 2, a voltage exceeding a threshold value is applied to the gate electrode 19. This forms a channel in the p-type semiconductor region 12. Electrons pass through this channel from the n-type semiconductor region 12... + Type semiconductor region 14 flows to n - In the p-type semiconductor region 11, the semiconductor device 200 is in the on state. Subsequently, when the voltage applied to the gate electrode 19 becomes lower than the threshold, the channel in the p-type semiconductor region 12 disappears, and the semiconductor device 200 switches to the off state. When the semiconductor device 200 switches to the off state, the depletion layer from the n-type semiconductor region 12... - The pn junction and n between p-type semiconductor region 11 and p-type semiconductor region 12 - The pn junction is extended between the p-type semiconductor region 11 and the p-type guard ring region 13.

[0091] In the manufacturing method of semiconductor device 200, it is possible to apply Figure 3 (a)~ Figure 5 The process shown in (b). For example, firstly, with Figure 3 The example shown in (a) similarly prepares the structure ST. In the structure ST, the semiconductor layer 10 contains n - p-type semiconductor region 11, p-type semiconductor region 12, p + Type 12a contact area, Type 13 p protective ring area, n + Type semiconductor region 14, n + Type contact area 16, n +The EQPR region 17 and gate electrode 19 are then formed. Subsequently, layer L is formed, a portion of layer L is removed, a portion of insulating layer IL is removed, wet etching is performed, semi-insulating layer 25 is formed, and third metal layer ML3 is formed.

[0092] In the manufacturing method of the semiconductor device 200 according to the second embodiment, similarly to the first embodiment, a first layer 21 is formed on the side surface S2 of the second metal layer ML2 during wet etching. This suppresses the leaching of aluminum from the side surface S2. Consequently, in the semiconductor device 200, the occurrence of a short circuit between the lower electrode 1 and the upper electrode 2 caused by the leached aluminum can be suppressed.

[0093] (Third Implementation)

[0094] Figure 12 This is a cross-sectional view showing a portion of the semiconductor device according to the third embodiment.

[0095] The semiconductor device 300 in the third embodiment is an IGBT. For example... Figure 12 As shown, in semiconductor device 300, compared to semiconductor device 200, semiconductor layer 10 includes p + Type collector region 15 is used to replace n + Type contact area 16. p + Type collector region 15 is disposed between lower electrode 1 and n - Between the semiconductor regions 11. Other structures in semiconductor device 300 may be the same as those in semiconductor device 200.

[0096] In the semiconductor device 300, the lower electrode 1 functions as the collector electrode, and the upper electrode 2 functions as the emitter electrode. When a positive voltage is applied to the lower electrode 1 relative to the upper electrode 2, a voltage exceeding a threshold value is applied to the gate electrode 19. This forms a channel (inversion layer) in the p-type semiconductor region 12. Electrons pass through the channel from the n-type semiconductor region 12... + Type semiconductor region 14 flows to n - Type semiconductor region 11, holes from p + Type collector region 15 flows to n - Type semiconductor region 11. Accumulated in n - The carrier density in semiconductor region 11 increases, resulting in conductivity modulation. Therefore, n - When the resistance of the p-type semiconductor region 11 decreases significantly, the semiconductor device 300 becomes conductive. Subsequently, when the voltage applied to the gate electrode 19 becomes lower than the threshold, the channel of the p-type semiconductor region 12 disappears, and the semiconductor device 300 switches to the off state.

[0097] In the manufacturing method of semiconductor device 300, it is possible to apply Figure 3 (a)~ Figure 5 The process shown in (b). For example, firstly, with Figure 3 The example shown in (a) similarly prepares the structure ST. In the structure ST, the semiconductor layer 10 contains n - p-type semiconductor region 11, p-type semiconductor region 12, p + Type 12a contact area, Type 13 p protective ring area, n + Type semiconductor region 14, n + Type contact area 16, n + The EQPR region 17 and gate electrode 19 are then formed. Subsequently, layer L is formed, a portion of layer L is removed, a portion of insulating layer IL is removed, wet etching is performed, semi-insulating layer 25 is formed, and third metal layer ML3 is formed.

[0098] In the manufacturing method of the semiconductor device 300 according to the third embodiment, similarly to the first embodiment, a first layer 21 is formed on the side surface S2 of the second metal layer ML2 during wet etching. This suppresses the leaching of aluminum from the side surface S2. Consequently, in the semiconductor device 300, the occurrence of a short circuit between the lower electrode 1 and the upper electrode 2 caused by the leached aluminum can be suppressed.

[0099] The embodiments of the present invention include the following features.

[0100] (Feature 1)

[0101] A method for manufacturing a semiconductor device, wherein,

[0102] A structure comprising a semiconductor layer, a first metal layer, and an aluminum-containing second metal layer is prepared. The first metal layer is disposed on a portion of the semiconductor layer, and the second metal layer is disposed on another portion of the semiconductor layer, and is disposed around the first metal layer along a first surface perpendicular to a first direction from the semiconductor layer toward the first metal layer.

[0103] On the side of the second metal layer opposite to the first metal layer, a first layer that is substantially free of aluminum is formed.

[0104] The upper surface of the semiconductor layer is treated by wet etching.

[0105] A semi-insulating layer is formed that is in contact with the upper surface of the semiconductor layer and electrically connected to the first metal layer and the second metal layer.

[0106] (Feature 2)

[0107] The method for manufacturing a semiconductor device according to feature 1, wherein,

[0108] The first layer is conductive and is electrically connected to the semi-insulating layer.

[0109] (Feature 3)

[0110] The method for manufacturing a semiconductor device according to feature 2, wherein,

[0111] The first layer is also formed on the upper surface of the second metal layer.

[0112] (Feature 4)

[0113] The method for manufacturing a semiconductor device according to any one of features 1 to 3, wherein,

[0114] On the side of the first metal layer opposite to the second metal layer, a second layer that is substantially free of aluminum is also formed.

[0115] After the first layer and the second layer are formed, the upper surface of the semiconductor layer is treated by wet etching.

[0116] (Feature 5)

[0117] The method for manufacturing a semiconductor device according to any one of features 1 to 4, wherein,

[0118] In the wet etching process, a fluorine-containing solution is used.

[0119] (Feature 6)

[0120] The method for manufacturing a semiconductor device according to any one of features 1 to 5, wherein,

[0121] After the semi-insulating layer is formed, a third metal layer is formed on the lower surface of the semiconductor layer.

[0122] (Feature 7)

[0123] The method for manufacturing a semiconductor device according to any one of features 1 to 6, wherein,

[0124] The semiconductor layer comprises:

[0125] First semiconductor region of first conductivity type;

[0126] A second semiconductor region of a second conductivity type is disposed between the first semiconductor region and the first metal layer; and

[0127] A third semiconductor region of the second conductivity type is disposed around the second semiconductor region along the first surface.

[0128] The third semiconductor region is electrically connected to the semi-insulating layer.

[0129] (Feature 8)

[0130] The method for manufacturing a semiconductor device according to feature 7, wherein...

[0131] The semiconductor layer further comprises:

[0132] A fourth semiconductor region of a first conductivity type is disposed on top of the second semiconductor region; and

[0133] The gate electrode is opposite to the second semiconductor region through the gate insulating layer.

[0134] (Feature 9)

[0135] A method for manufacturing a semiconductor device according to any one of features 1 to 8, wherein,

[0136] The resistivity of the semi-insulating layer is greater than 1.0 × 10⁻⁶. 8 Ω·cm and less than 1.0×10 13 Ω·cm.

[0137] (Feature 10)

[0138] A method for manufacturing a semiconductor device according to any one of features 1 to 9, wherein,

[0139] The first layer contains one or more materials selected from the group consisting of tungsten, molybdenum, titanium nitride, silicon nitride and tantalum nitride.

[0140] (Feature 11)

[0141] A semiconductor device comprising:

[0142] First electrode;

[0143] A semiconductor layer is disposed on the first electrode;

[0144] The second electrode is disposed on a portion of the semiconductor layer;

[0145] An aluminum-containing third electrode is disposed on another portion of the semiconductor layer, and is disposed around the second electrode along a first surface perpendicular to a first direction from the first electrode toward the semiconductor layer;

[0146] A semi-insulating layer, in contact with the upper surface of the semiconductor layer, and electrically connected to the second electrode and the third electrode; and

[0147] The first conductive layer, disposed between the side of the third electrode and the semi-insulating layer, is substantially aluminum-free.

[0148] Based on the embodiments described above, a method for manufacturing a semiconductor device and a semiconductor device capable of suppressing the occurrence of short circuits are provided.

[0149] The relative levels of impurity concentrations among the semiconductor regions in the embodiments described above can be confirmed, for example, using scanning electrostatic capacitance microscopy (SCM). Furthermore, the carrier concentration in each semiconductor region can be considered equal to the concentration of impurities activated in that semiconductor region. Therefore, the relative levels of carrier concentrations among the semiconductor regions can also be confirmed using SCM. Additionally, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).

[0150] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and also within the scope of the invention as described in the claims and its equivalents. Furthermore, the above-described embodiments can be combined with each other for implementation.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Prepare a structure comprising a semiconductor layer, a first metal layer, and an aluminum-containing second metal layer. The first metal layer is disposed on a portion of the semiconductor layer, and the second metal layer is disposed on another portion of the semiconductor layer, and is disposed around the first metal layer along a first surface perpendicular to a first direction from the semiconductor layer toward the first metal layer. On the side of the second metal layer opposite to the first metal layer, a first layer that is substantially free of aluminum is formed. The upper surface of the semiconductor layer is treated by wet etching. A semi-insulating layer is formed that is in contact with the upper surface of the semiconductor layer and electrically connected to the first metal layer and the second metal layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The first layer is conductive and is electrically connected to the semi-insulating layer.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The first layer is also formed on the upper surface of the second metal layer.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, On the side of the first metal layer opposite to the second metal layer, a second layer that is substantially free of aluminum is also formed. After the first layer and the second layer are formed, the upper surface of the semiconductor layer is treated by wet etching.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, In the wet etching process, a fluorine-containing solution is used.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After the semi-insulating layer is formed, a third metal layer is formed on the lower surface of the semiconductor layer.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The semiconductor layer comprises: First semiconductor region of first conductivity type; A second semiconductor region of a second conductivity type is disposed between the first semiconductor region and the first metal layer; as well as A third semiconductor region of the second conductivity type is disposed around the second semiconductor region along the first surface. The third semiconductor region is electrically connected to the semi-insulating layer.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The semiconductor layer further comprises: A fourth semiconductor region of a first conductivity type is disposed on top of the second semiconductor region; and The gate electrode is opposite to the second semiconductor region through the gate insulating layer.

9. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The resistivity of the semi-insulating layer is greater than 1.0 × 10⁻⁶. 8 Ω·cm and less than 1.0×10 13 Ω·cm.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 9, characterized in that, The first layer contains one or more materials selected from the group consisting of tungsten, molybdenum, titanium nitride, silicon nitride and tantalum nitride.

11. A semiconductor device, characterized in that, have: First electrode; A semiconductor layer is disposed on the first electrode; The second electrode is disposed on a portion of the semiconductor layer; An aluminum-containing third electrode is disposed on another portion of the semiconductor layer, and is disposed around the second electrode along a first surface perpendicular to a first direction from the first electrode toward the semiconductor layer; A semi-insulating layer, in contact with the upper surface of the semiconductor layer, and electrically connected to the second electrode and the third electrode; and The first conductive layer, disposed between the side of the third electrode and the semi-insulating layer, is substantially aluminum-free.

Images