Transistor structure and method of forming the same

Abstract

A transistor structure and a method of forming the same, the method comprising forming a channel region in a fin structure; forming a source / drain region adjacent to the channel region; forming a thermal oxide layer on the channel region; depositing a rare earth oxide layer on the thermal oxide layer; annealing the rare earth oxide layer and the thermal oxide layer; removing the rare earth oxide layer; depositing a high-k dielectric layer on the thermal oxide layer; and depositing a gate electrode on the high-k dielectric layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to transistor structures and methods for forming transistor structures. Background Technology

[0002] With the advancement of semiconductor technology, the demand for higher storage capacity, faster processing systems, higher efficiency, and lower cost is increasing. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin field-effect transistors (finFETs), and gate-all-around field-effect transistors (GAAFETs). This shrinking has increased the complexity of semiconductor manufacturing processes. Maintaining or improving the quality of shrunk transistors is particularly challenging when reducing the size of critical components that directly affect transistor performance, such as the interface layer above the transistor's transmission channel. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method is provided. The method includes: forming a channel region in a fin structure; forming a source / drain (S / D) region adjacent to the channel region; forming a thermal oxide layer on the channel region; depositing a rare earth oxide layer on the thermal oxide layer; annealing the rare earth oxide layer and the thermal oxide layer; removing the rare earth oxide layer; depositing a high-k dielectric layer on the thermal oxide layer; and depositing a gate electrode on the high-k dielectric layer.

[0004] According to some embodiments of this disclosure, a method is provided. The method includes: forming a nanostructure in a fin structure; forming a source / drain (S / D) region adjacent to the nanostructure; and forming a gate structure surrounding the nanostructure, wherein forming the gate structure includes: forming a thermal oxide layer on the nanostructure; depositing a rare earth oxide layer on the thermal oxide layer; forming a rare earth silicate layer between the thermal oxide layer and the rare earth oxide layer; removing the rare earth oxide layer; depositing a high-k dielectric layer on the thermal oxide layer; and depositing a gate electrode on the high-k dielectric layer.

[0005] According to some embodiments of this disclosure, a structure is provided. The structure includes: a substrate; a fin structure on the substrate, wherein the fin structure includes a channel region; a source / drain (S / D) region on the fin structure and adjacent to the channel region; and a gate structure surrounding the channel region, wherein the gate structure includes: a thermal oxide layer on the channel region; a high-k dielectric layer on the thermal oxide layer, wherein the interface between the high-k dielectric layer and the thermal oxide layer contains rare-earth elements; and a gate electrode on the high-k dielectric layer. Attached Figure Description

[0006] The nature of this disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with general industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of illustration and discussion.

[0007] Figure 1 This is an isometric view of a semiconductor device including a semiconductor transistor according to some embodiments.

[0008] Figure 2 This is a cross-sectional view of a semiconductor device including a semiconductor transistor according to some embodiments.

[0009] Figure 3 According to some embodiments Figure 2 An enlarged cross-sectional view of a portion of a semiconductor device.

[0010] Figure 4A and Figure 4B This is a flowchart of a method for forming a semiconductor transistor according to some embodiments.

[0011] Figure 5 and Figure 6 An isometric view of an intermediate structure during the manufacture of a semiconductor transistor according to some embodiments.

[0012] Figure 7-19 This is a cross-sectional view of an intermediate structure during the manufacture of a semiconductor transistor according to some embodiments.

[0013] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally indicate the same, functionally similar, and / or structurally similar elements. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, in the following description, forming a first feature over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. As used herein, a first feature formed over a second feature means that the first feature is formed in direct contact with the second feature. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. This repetition itself does not prescribe a relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of explanation, this document may use spatial relative terms such as “under,” “below,” “below,” “above,” “on,” and similar terms to describe the relationship of one element or feature relative to another element(s) as illustrated in the accompanying drawings. Besides the orientations shown in the drawings, these spatial relative terms are intended to cover different orientations of the device during use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative terms used herein may be interpreted accordingly.

[0016] In some embodiments, the terms “about” and “substantially” may indicate a value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and are not intended to be limiting. It should be understood that the terms “about” and “substantially” may refer to a percentage of a value as interpreted by those skilled in the art based on the teachings herein.

[0017] It should be noted that references to "an embodiment," "an exemplary embodiment," "exemplary," etc., in this specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether explicitly stated or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0018] It should be understood that the wording or terminology used herein is for illustrative and not restrictive purposes, and that the wording or terminology used herein should be interpreted by a person skilled in the art in light of the teachings herein.

[0019] As an example, and not a limitation, a nanostructured transistor with nanosheet (NS) or nanowire (NW) channel regions, such as a GAA nanosheet (NS) or nanowire (NW) FET (collectively referred to as "GAAFET"), can be formed as follows: A fin structure having alternating silicon-germanium (SiGe) and silicon (Si) NS or NW layers is formed on a substrate (e.g., on a semiconductor substrate). A sacrificial gate structure is then formed on a middle portion of the fin structure to cover the top and sidewall surfaces of the fin structure, such that the edge portions of the fin structure are not covered by the sacrificial gate structure. The edge portions of the fin structure not covered by the sacrificial gate structure are removed. Subsequently, the edge portions of the SiGe NS or NW layers are recessed relative to the edge portions of the SiGe NS or NW layers, and an inner spacer structure is formed by depositing a dielectric material to fill the space formed by the etched portions of the SiGe NS or NW layers. Next, a source / drain (S / D) epitaxial structure is formed to abut (or contact) the edge portion of the fin-like structure, such that the S / D epitaxial structure contacts the Si NS or NW layer and is isolated (or separated) from the SiGe NS or NW layer by an inner spacer structure. The source / drain may refer individually or collectively to a source or a drain depending on the context. In a subsequent operation, a sacrificial gate structure is removed to expose the top and sidewall surfaces of the fin-like structure. The SiGe NS or NW layer is selectively removed from the fin-like structure. During the selective removal process, the Si NS or NW layer and the inner spacer structure are not removed. Subsequently, a gate structure is formed to surround the Si NS or NW layer. Similar to the SiGe NS or NW layer, the gate structure is isolated (or separated) from the S / D epitaxial structure by an inner spacer structure before their selective removal. The gate structure includes an interface layer (IL) above a Si NS or NW layer, a gate dielectric layer on the IL, and a gate electrode including a suitable work function metal on the gate dielectric layer.

[0020] The structure of a GAAFET can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual or multiple patterning procedures. Dual or multiple patterning procedures combine photolithography and self-alignment processes, allowing patterns with, for example, smaller pitches to be built compared to those achievable using a single direct photolithography process in other ways. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0021] As semiconductor devices continue to shrink, in exemplary GAAFETs formed via the processes described above, critical dimensions of the GAAFET (such as the length / width of the Si NS or NW layer serving as the channel and the metal gate structure) are reduced. Highly sensitive to the shrinkage process, the quality of the interphase (IL) becomes increasingly critical to the electrical performance and reliability of the GAAFET. The IL can be formed by exposing the Si NS or NW layer to a chemical solution to oxidize the surface of the Si NS or NW layer. The IL may include silicon oxide (e.g., SiO₂). x ), of which SiO x The ratio of oxygen (O) atoms to Si atoms in the IL is less than 2. The IL formed in this way may include oxygen vacancies as defects, which can act as tunneling aid traps for leakage current between the channel and gate structure, thus affecting electrical performance and causing GAAFET degradation. As an alternative to shrinking, increasing the thickness of the IL can suppress leakage current, but still impairs the gate structure's ability to regulate channel conductivity. Furthermore, it is difficult to control the growth rate of the IL during the process of increasing its thickness, thus affecting the uniformity and quality of the IL.

[0022] The embodiments described herein relate to overcoming the challenges mentioned above. In some embodiments, a structure of a semiconductor device may include a gate structure and a channel layer. The gate structure may include an IL on the channel layer. The IL may include silicon dioxide (SiO2) having a stoichiometric ratio of O atoms to Si atoms of about 2. SiO2 is used in the IL instead of SiO. xIn this case, the integrity of the IL can be improved due to the absence of oxygen vacancies, and leakage current between the channel layer and the gate structure can be effectively suppressed. In some embodiments, a method of forming the structure may include forming a channel layer and forming a gate structure. Forming the gate structure may include forming an IL on the channel layer, and forming a high-k dielectric layer and a gate electrode on the IL. Forming the IL may include forming a thermal oxide layer on the channel layer, depositing a rare earth oxide layer (e.g., yttrium oxide (Y₂O₃)) on the thermal oxide layer, annealing the rare earth oxide layer and the thermal oxide layer to reduce the density of oxygen vacancies in the thermal oxide layer, and removing the rare earth oxide layer. Specifically, during the annealing of the rare earth oxide layer and the thermal oxide layer, O atoms in the rare earth oxide layer may diffuse into the thermal oxide layer to replace oxygen vacancies in the thermal oxide layer, thereby increasing the O atom to Si atom ratio to about 2 and improving the quality of the IL. Furthermore, due to the reaction between the rare-earth metal atoms in the rare-earth oxide layer and the Si atoms in the thermal oxide layer, the annealing process can also promote the formation of a silicate layer (e.g., rare-earth silicate) between the rare-earth oxide layer and the thermal oxide layer. After removing the rare-earth oxide layer, the silicate layer can then be removed, thereby reducing the thickness of the leakage current (IL). This is consistent with the shrinkage process and contrasts with the aforementioned approach of increasing the IL thickness to suppress leakage current. This method of forming the IL can also be applied to the fabrication processes of other semiconductor transistors, such as planar MOSFETs and FinFETs.

[0023] According to some embodiments, a semiconductor device 100 having a plurality of transistors 105 formed above a substrate 102 is referenced. Figure 1 and Figure 2 To illustrate. The semiconductor device 100 may be included in a microprocessor, memory cell or other integrated circuit (IC). Figure 1 An isometric view of a semiconductor device 100 is shown. Figure 2 Examples along Figure 1 A cross-sectional view (e.g., along the xz plane) of the semiconductor device 100 captured by line AB.

[0024] See Figure 1The substrate 102 may be a semiconductor material, such as silicon. In some embodiments, the substrate 102 may include a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 102 may include: (i) an elemental semiconductor, such as silicon (Si) or germanium (Ge); (ii) a compound semiconductor, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium aluminum arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) a combination thereof. Furthermore, the substrate 102 may be doped depending on design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 102 may be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, a crystal orientation of the substrate 102 may be (100), (110), or (111).

[0025] Although Figure 1 and Figure 2 The diagram shows a fin structure 110 housing two transistors 105, but any number of transistors 105 may be arranged along the fin structure 110. In some embodiments, the transistors 105 may include a plurality of fin structures 110 extending along a first horizontal direction (e.g., in the x-direction) and a gate structure 115 traversing the plurality of fin structures 110 along a second horizontal direction (e.g., in the y-direction). In some embodiments, a crystal orientation of the fin structure 110 may be the same as the crystal orientation of the substrate 102.

[0026] See Figure 1 and Figure 2One or more nanosheet (NS) layers 120 may be disposed above the fin structure 110. Each NS layer 120 may be covered by a gate structure 115 to serve as a channel for a transistor 105. For example, a top surface, a side surface, and a bottom surface of each NS layer 120 may be surrounded by and in contact with the gate structure 115. The fin structure 110 and the NS layer 120 may be made of a material similar to (e.g., within about 5% lattice mismatch) the substrate 102. In some embodiments, a crystal orientation of the NS layer 120 may be the same as the crystal orientation of the fin structure 110. In some embodiments, each of the fin structure 110 and the NS layer 120 may be made of Si or SiGe. Each of the fin structure 110 and the NS layer 120 may be undoped, doped with a p-type dopant, doped with an n-type dopant, or doped with an intrinsic dopant. In some embodiments, the fin structure 110 and the NS layer 120 may be doped together with a p-type dopant or with an n-type dopant. In some embodiments, the thickness of each of the NS layers 120 may be between about 5 nm and about 10 nm. Although Figure 1 Each transistor 105 is shown to include four NS layers 120, and Figure 2 Each transistor 105 is shown to include three NS layers 120, but any number of NS layers 120 may be included in each transistor 105. For example, each transistor 105 may include one, two, five, or six NS layers 120.

[0027] See Figure 1 and Figure 2 The gate structure 115 may be a multilayer structure that surrounds each NS layer 120 to regulate the transistor 105. The gate structure 115 may have a length Lc, which represents the channel length of the transistor 105. The length Lc may have any suitable horizontal (e.g., in the x-direction) dimension, such as about 3 nm to about 200 nm. In some embodiments, the height of the gate structure 115 on the fin structure 110 along a vertical direction (e.g., in the z-direction) may be between about 10 nm and about 20 nm. In some embodiments, the height of the gate structure 115 on the fin structure 110 may be greater than about 20 nm. In some embodiments, the thickness of the gate structure 115 between adjacent NS layers 120 may be between about 5 nm and about 15 nm, corresponding to the spacing between adjacent NS layers 120. By way of example and not limitation, each gate structure 115 may include a dielectric stack formed of an IL 115a and a gate dielectric layer 115b. Furthermore, for simplicity, each gate structure 115 may include a gate electrode 115c with a capping layer, one or more work function metal layers, and not individually shown in Figure 1The gate dielectric layer 115b may comprise any suitable dielectric material having any suitable thickness that provides channel modulation for the transistor 105. In some embodiments, the gate dielectric layer 115b may be made of a high-k dielectric material. For example, high-k dielectric materials may include hafnium oxide (HfO2), aluminum oxide (Al2O3), scandium oxide (ScO2), zirconium oxide (ZrO2), calcium oxide (CaO), magnesium oxide (MgO), zirconium silicate (ZrSiO4), or a combination thereof. In some embodiments, the gate dielectric layer 115b may comprise lanthanum oxide (La2O3) on a high-k dielectric to form an N-dipole in the gate dielectric layer 115b for tuning the threshold voltage of the transistor 105. In some embodiments, the concentration of carbon atoms in the gate dielectric layer 115b may be less than about 0.2%. In some embodiments, the gate dielectric layer 115b may have a thickness ranging from about 1 nm to about 5 nm. Based on the disclosure herein, other materials and thicknesses of the gate dielectric layer 115b are within the scope and spirit of this disclosure. The gate electrode 115c may serve as a gate terminal of the transistor 105. The gate electrode 115c may include any suitable conductive material that provides a suitable work function to regulate the transistor 105. In some embodiments, the gate electrode 115c may be made of titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, copper, or nickel. Based on the disclosure herein, other materials of the gate electrode 115c are within the scope and spirit of this disclosure.

[0028] In some embodiments, IL 115a may be formed as a thermal oxide layer in a thermal process. Therefore, IL 115a may be referred to as thermal oxide layer 115a. Figure 3 for Figure 2 A magnified cross-sectional view of region 300. Unless otherwise noted, those with the same annotations... Figure 1 and Figure 2 The discussion of the components in the text is applicable to Figure 3 .like Figure 3 As shown, the thickness d of IL 115a can be between about 0.2 nm and about 2 nm. For example, the thickness of IL 115a can be about 1 nm. In some embodiments, IL 115a may include a SiO2 layer having an O atom to Si atom ratio of about 2. As explained below, the SiO2 layer can be formed by forming a thermal oxide layer on NS layer 120 and then removing and / or reducing oxygen vacancies in the thermal oxide layer to transform it into a SiO2 layer. In some embodiments, IL 115a may not contain oxygen vacancies. In some embodiments, IL 115a may not contain Si dangling bonds, such that Si atoms in IL 115a are in Si 4+Valence state. As described below, removing and / or reducing oxygen vacancies in the thermal oxide layer 115a may include forming a rare earth oxide layer on the thermal oxide layer 115a followed by an annealing process, such that O atoms in the rare earth oxide layer can diffuse into the thermal oxide layer 115a and replace the oxygen vacancies therein. The rare earth oxide layer may subsequently be removed before forming the gate dielectric layer 115b. However, residues of rare earth elements may remain on the top surface of the thermal oxide layer 115a. After the gate dielectric layer 115b is formed on the thermal oxide layer 115a, these rare earth elements may remain at the interface between the gate dielectric layer 115b and the thermal oxide layer 115a. In some embodiments, the annealing process may cause the rare earth elements to react with Si atoms in the thermal oxide layer 115a to form rare earth silicates. Subsequently, residues of these rare earth silicates may be present at the interface between the gate dielectric layer 115b and the thermal oxide layer 115a. In some embodiments, rare earth elements and / or rare earth silicates can be detected by microscopic methods, such as scanning electron microscopy (SEM) and energy-dispersive X-ray spectroscopy (EDS).

[0029] In some embodiments, rare earth elements may include yttrium, scandium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, or diurethane. In some embodiments, rare earth elements may include yttrium silicate, scandium silicate, lanthanum silicate, cerium silicate, praseodymium silicate, neodymium silicate, promethium silicate, samarium silicate, europium silicate, gadolinium silicate, terbium silicate, dysprosium silicate, holmium silicate, erbium silicate, thulium silicate, ytterbium silicate, or diurethane silicate.

[0030] See Figure 1 and Figure 2 The S / D epitaxial structure 125 may be disposed above each opposite side (e.g., along the x-direction) of the NS layer 120 to serve as the source and drain terminals of the transistor 105. The S / D epitaxial structure 125 may be disposed on the fin structure 110. The S / D epitaxial structure 125 may be made of an epitaxially grown semiconductor material similar to (e.g., with a lattice mismatch within about 5%) the NS layer 120. In some embodiments, the S / D epitaxial structure 125 may be made of Si, Ge, SiGe, InGaAs, or GaAs. The S / D epitaxial structure 125 may be doped with p-type dopant, n-type dopant, or intrinsic dopant. In some embodiments, the S / D epitaxial structure 125 may have a different doping type than the NS layer 120. In some embodiments, the n-type dopant in the S / D epitaxial structure 125 may include P, As, Sb, or a combination thereof. In some embodiments, a crystal orientation of the S / D epitaxial structure 125 may be the same as the crystal orientation of the NS layer 120.

[0031] See Figure 1 and Figure 2The semiconductor device 100 may include an inner spacer structure 130 that abuts (or contacts) a side surface of the gate structure 115. The inner spacer structure 130 may separate the gate structure 115 from the S / D epitaxial structure 125. For example, the inner spacer structure 130 may be formed on opposite sides of the gate structure 115 along the channel direction of the transistor 105 (e.g., along the x-direction) to separate the gate structure 115 from the S / D epitaxial structure 125. In some embodiments, the inner spacer structure 130 may be formed between two vertically (e.g., in the z-direction) adjacent NS layers 120. In some embodiments, the inner spacer structure 130 may be formed between the fin structure 110 and the NS layer 120. In some embodiments, the inner spacer structure 130 may include a silicon-based dielectric, such as silicon nitride (SiN), silicon oxy-carbon-nitride (SiOCN), silicon carbon-nitride (SiCN), or silicon oxy-nitride (SiON). In some embodiments, the inner spacer structure 130 may include a low-k material, such as a porous material, and a carbon-rich silicon oxide-based dielectric.

[0032] See Figure 1 and Figure 2 The semiconductor device 100 may further include a gate spacer 135 formed between the gate structure 115 and the S / D epitaxial structure 125, which may provide structural support during the formation of the gate structure 115. Additionally, the gate spacer 135 may provide electrical isolation and protection for the gate structure 115 during the formation of the S / D junction. The gate spacer 135 may be made of any suitable dielectric material. In some embodiments, the gate spacer 135 may be made of silicon oxide, silicon nitride, or a low-k material having a dielectric constant of less than about 3.9. In some embodiments, the gate spacer 135 may have any suitable thickness, such as between about 5 nm and about 15 nm. Other materials and thicknesses of the gate spacer 135 are within the scope and spirit of this disclosure based on the present disclosure.

[0033] In some embodiments, as described below, IL 115a can be formed simultaneously with the exposure of the side surface of the gate spacer 135. Therefore, when the rare earth oxide layer is formed on IL 115a, the side surface of the gate spacer 135 can also be covered by the rare earth oxide layer deposited during the ALD process. After subsequent annealing and removal of the rare earth oxide layer, residues of rare earth elements may remain on the side surface of the gate spacer 135. Subsequently, once the gate structure 115 is formed to contact the gate spacer 135, the rare earth elements may remain at the interface between the gate dielectric layer 115b and the gate spacer 135. For example, as... Figure 3 As shown, the gate dielectric layer 115b is in contact with one side surface 135s of the gate spacer 135. In some embodiments, rare earth elements may be present at the side surface 135s. In some embodiments, the rare earth elements at the side surface 135s can be detected by microscopic methods, such as scanning electron microscopy (SEM) and energy-dispersive X-ray spectroscopy (EDS).

[0034] See Figure 1 The semiconductor device 100 may further include shallow trench isolation (STI) regions 138, which are configured to provide electrical isolation between fin structures 110. STI regions 138 may also provide electrical isolation between transistor 105 and adjacent active and passive components integrated with or disposed on substrate 102. STI regions 138 may include one or more dielectric material layers, such as a nitride layer, an oxide layer disposed on the nitride layer, and an insulating layer disposed on the nitride layer. In some embodiments, the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. Other dielectric materials for STI regions 138 are within the scope and spirit of this disclosure.

[0035] See Figure 1 and Figure 2 The semiconductor device 100 may further include an interlayer dielectric (ILD) layer 165 to provide electrical isolation for structural elements it surrounds or covers, such as the gate structure 115 and the S / D epitaxial structure 125. In some embodiments, a gate spacer 135 may be disposed between the gate structure 115 and the ILD layer 165. In some embodiments, the ILD layer 165 may be disposed on the S / D epitaxial structure 125. The ILD layer 165 may include any suitable dielectric material to provide electrical insulation, such as silicon oxide, silicon dioxide, silicon oxycarbonate, silicon oxynitride, silicon oxycarbonitride, and silicon carbonitride. The ILD layer 165 may have any suitable thickness, such as from about 50 nm to about 200 nm, to provide electrical insulation. Other insulating materials and thicknesses of the ILD layer 165 are within the scope and spirit of this disclosure.

[0036] See Figure 1 and Figure 2The semiconductor device 100 may further include dielectric layers 152, 154, and 156 on the transistor 105. In some embodiments, dielectric layers 152, 154, and 156 may include silicon oxide and / or silicon nitride. For example, dielectric layers 152 and 156 may be silicon oxide layers, and dielectric layer 154 may be a silicon nitride layer. In some embodiments, dielectric layers 152, 154, and 156 may be etch stop layers.

[0037] See Figure 1 and Figure 2 The semiconductor device 100 may further include an S / D contact 163 that contacts the S / D epitaxial structure 125. The S / D contact 163 may be disposed on the S / D epitaxial structure 125 and surrounded by an ILD layer 165. In some embodiments, the S / D contact 163 may be disposed through one or more of dielectric layers 152, 154, and 156. In some embodiments, a silicide layer 164 may be disposed between the S / D contact 163 and the S / D epitaxial structure 125. In some embodiments, a height of the S / D contact 163 may be between about 10 nm and about 50 nm. The S / D contact 163 may include any suitable conductive material that provides low contact resistance to the S / D epitaxial structure 125. In some embodiments, the S / D contact 163 may be made of polysilicon, titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, nickel, or a combination thereof. Based on the disclosure herein, other materials concerning S / D contact 163 are within the scope and spirit of this disclosure.

[0038] See Figure 1 and Figure 2The semiconductor device 100 may further include one or more gate contact vias 167 that contact the gate electrode 115c. The gate contact vias 167 may be disposed on the gate structure 115 and pass through one or more of the dielectric layers 152, 154, and 156. In some embodiments, an interface between the gate contact via 167 and the gate electrode 115c may be substantially flat. In some embodiments, the interface between the gate contact via 167 and the gate electrode 115c may be curved. In some embodiments, a horizontal cross-section of the gate contact via 167 may have a rectangular shape or a cylindrical shape. In some embodiments, the gate contact via 167 may have a push-out shape, wherein the width of a top surface is greater than the width of a bottom surface. In some embodiments, the gate contact via 167 may have a uniform width from its top surface to its bottom surface. In some embodiments, the width of the top surface of the gate contact via 167 may be between about 2 nm and about 40 nm. In some embodiments, the width of the bottom surface of the gate contact via 167 may be between about 1 nm and about 40 nm. In some embodiments, the ratio of the width of the top surface of the gate contact via 167 to the width of the bottom surface of the gate contact via 167 may be between about 1 and about 3. In some embodiments, the height of the gate contact via 167 may be between about 10 nm and about 50 nm. In some embodiments, the aspect ratio of the gate contact via 167 may be between about 5:1 and about 20:1.

[0039] Although Figure 1 and Figure 2 The transistor 105 is illustrated as an embodiment of a GAAFET, but it should be understood that, Figure 1 and Figure 2 The IL 115a described can be applied to other types of transistors, such as MOSFETs, FinFETs, complementary fin field-effect transistors (CFETs), or vertical fin field-effect transistors (VFETs).

[0040] According to some embodiments, Figure 4A Examples used to form Figure 1 and Figure 2 A flowchart of a method 400 for transistor 105 is shown. Figure 4B A flowchart detailing an operation 440 of manufacturing method 400, and particularly relating to the formation of IL 115a of transistor 105, is provided. This disclosure is not limited to this operational description, and additional operations may be performed. Other manufacturing operations may be performed among the various operations of method 400, and are omitted only for clarity. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously, or in different ways. Figure 4A and Figure 4BThe operations are performed in a specific order as shown. In some embodiments, one or more other operations may be performed in addition to or in lieu of the operations currently described. For illustrative purposes, method 400 is referred to... Figures 5-19 The structure shown is used for illustration. Unless otherwise stated, those with the same annotations... Figure 1 and Figure 2 The discussion of the components in the text is applicable to Figures 5-19 .

[0041] See Figure 4A Method 400 begins with operations 410 and procedures for forming a fin structure having channel regions on a substrate (e.g., substrate 102). In some embodiments, forming the fin structure may include forming a stack of alternating first and second NS layers on the substrate. Figure 5 An isometric view of a substrate 102 and a stack 520 forming alternating first and second NS layers 520a and 520b. In some embodiments, the first and second NS layers 520a and 520b are formed on an exposed top surface of the substrate 102. In some embodiments, the first NS layer 520a is a sacrificial NS layer that undergoes subsequent removal, and the second NS layer 520b corresponds to... Figure 1 The NS layer 120 is shown. In some embodiments, the material of the first NS layer 520a in the stack 520 is selected such that the first NS layer 520a can be selectively removed from the stack 520 by etching, without removing the second NS layer 520b. For example, the first NS layer 520a may be a SiGe NS layer and the second NS layer 520b may be a Si NS layer.

[0042] The first and second NS layers 520a and 520b can be grown using any suitable method. For example, the first and second NS layers 520a and 520b can be grown using a chemical vapor deposition (CVD) process with a precursor gas such as silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), germanane (GeH4), digermanane (Ge2H6), other suitable gases, or combinations thereof. In some embodiments, the first NS layer 520a may include Ge at a concentration between about 20% and about 30%, while the second NS layer 520b is substantially free of germanium—for example, having a Ge concentration of less than about 1%. In some embodiments, the second NS layer 520b, which corresponds to... Figure 1 The NS layer 120 forms the channel region of transistor 105 and can be lightly doped or inherently (e.g., undoped). If lightly doped, the doping level of the second NS layer 520b is less than about 10. 13 atoms / cm 3The first and second NS layers 520a and 520b can be deposited sequentially without vacuum interruption (e.g., in situ) to avoid the formation of any interposer layer. In some embodiments, in a subsequent etch operation, the first NS layer 520a may be doped to increase its etch selectivity compared to the second NS layer 520b.

[0043] In some embodiments, the thickness of the first NS layer 520a is controlled by the spacing between each interval of the second NS layers 520b in the stack 520. The thicknesses of the first and second NS layers 520a and 520b can range, for example, from about 3 nm to about 15 nm. Since the first and second NS layers 520a and 520b are grown separately, the thickness of each NS layer can be adjusted independently, for example, based on the deposition time. In some embodiments, additional or fewer numbers of the first and second NS layers 520a and 520b can be formed in the stack 520. In some embodiments, the total number of NS layers can be 2n, where n is the number of first NS layers 520a or the number of second NS layers 520b in the stack 520. In some embodiments, n can be 1, 2, 3, 4, 5, 6, or any integer greater than 6.

[0044] See Figure 4A Operation 410 may further include a process of patterning the stack 520 to form a fin structure. In some embodiments, the stack 520 is patterned to form a fin structure having a width along the y-direction and a length along the x-direction. The fin structure can be formed by patterning using any suitable method. For example, the fin structure can be patterned using one or more photolithography processes including dual patterning or multiple patterning processes. Dual patterning or multiple patterning processes can combine photolithography and self-alignment processes, allowing patterns with, for example, smaller pitches to be constructed compared to those achievable using a single direct photolithography process in other ways. In some embodiments, a sacrificial layer is formed on the stack 520 and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask structure to pattern the fin structure.

[0045] As an example, not a limitation. Figure 6This is an isometric view of the fin structure 620 formed from the stack 520 using the aforementioned patterning process. In some embodiments, the fin structure 620 may be formed by etching the first and second NS layers 520a and 520b into the first and second NS layers 620a and 620b. In some embodiments, the aforementioned patterning process does not terminate on the top surface of the substrate 102, but continues to etch a top portion of the substrate 102 to form the fin structure 110 from the substrate 102 beneath the fin structure 620. Since the fin structure 620 and the fin structure 110 are formed using the same patterning process, the fin structure 620 and the fin structure 110 are substantially aligned with each other. For example, the sidewall surfaces of the fin structure 620 in the xz plane and the yz plane are substantially aligned with the corresponding sidewall surfaces of the fin structure 110, such as... Figure 6 As shown.

[0046] Additional fin structures, such as fin structure 620, may be formed on the substrate 102 in the same or different regions of the substrate 102. For simplicity, these additional fin structures are not shown on the substrate 102. Figure 6 As shown in the figure. As an example and not a limitation, each fin structure 620 has a width along the y-direction between approximately 15 nm and approximately 150 nm.

[0047] In some embodiments, the first and second NS layers 620a and 620b are referred to as “nanosheets” when their width along the y-direction is substantially different from their height along the z-direction—for example, when their width is greater than / narrower than their height. In some embodiments, the first and second NS layers 620a and 620b may also be referred to as “nanowires” when their width along the y-direction is substantially equal to their height along the z-direction. In some embodiments, the first and second NS layers 620a and 620b are deposited as nanosheets and subsequently patterned to form nanowires with substantially equal height and width. By way of example and not limitation, the first and second NS layers 620a and 620b will be illustrated in the context of nanosheet (NS) layers. For the purposes of this disclosure, nanowires (NW) are within the spirit and scope of this disclosure. Furthermore, for illustrative purposes and without limiting the scope of this disclosure, the first and second NS layers 620a and 620b in method 400 will be illustrated in the context of SiGe and Si NS layers, respectively.

[0048] In some embodiments, after the fin structure 620 is formed, an STI region 138 may be formed on an etched or recessed portion of the substrate 102 to cover the sidewall surface of the fin structure 110. In some embodiments, the STI region 138 may electrically isolate the fin structure 110 and include one or more silicon oxide-based dielectrics. By way of example and not limitation, the STI region 138 may be formed as follows: An isolation structure material (e.g., a silicon oxide-based dielectric) is blanket-deposited over the fin structure 620 and the substrate 102. The initially deposited isolation structure material is planarized (e.g., using a chemical mechanical polishing (CMP) process) such that the top surface of the isolation structure material is substantially coplanar with the top surface of the fin structure 620. The planarized isolation structure material is then etched back such that the resulting STI region 138 has a height substantially similar to that of the fin structure 110, such as Figure 6 As shown. In some embodiments, the fin structure 620 protrudes from the STI region 138, such that the STI region 138 does not cover the sidewall portion of the fin structure 620, as... Figure 6 As shown.

[0049] See Figure 4A Operation 410 may further include a process of forming a sacrificial gate structure on the fin structure. For example, the sacrificial gate structure 700 may be formed on the fin structure 620, as shown in reference... Figure 7 As illustrated. In some embodiments, the sacrificial gate structures 700 are formed such that their lengths are along the y-direction—for example, perpendicular to the y-axis. Figure 6 The isometric view shows the fin structure 620—and their width along the x-direction. This is an example, not a limitation. Figure 7 For the sample taken along the cutting line AB Figure 6 A cross-sectional view. Figure 7 The sacrificial gate structure 700 is shown formed on a portion of the fin structure 620. Because Figure 7 This is a cross-sectional view, not an isometric view, therefore the portion of the sacrificial gate structure 700 covering the sidewall portion of the fin structure 620 is not shown. Additionally, in Figure 7 In the cross-sectional view, only Figure 6 One of the fin structures 620. In some embodiments, portions of the sacrificial gate structure 700 are formed between and within the fin structures 620. Figure 6 The STI region 138 is shown.

[0050] In some embodiments, the sacrificial gate structure 700 may cover the top and sidewall portions of the fin structure 620. During a subsequent gate replacement procedure, the sacrificial gate structure 700 is then replaced with... Figure 1The gate structure 115 is shown. The sacrificial gate structure 700 may include a sacrificial gate electrode 700a formed in a sacrificial gate dielectric (not shown for simplicity). Figure 7 (Middle) Above. The sacrificial gate structure 700 may also include a capping layer 705 formed on the top surface of the sacrificial gate structure 700. In some embodiments, the capping layer 705 may protect the sacrificial gate electrode 700a from subsequent etching operations. During this fabrication stage, gate spacers 135 may be formed on the side surfaces of the sacrificial gate structure 700. As discussed above, the gate spacers 135 are not removed during the gate replacement procedure; rather, the gate spacers 135 facilitate the following: Figure 1 The formation of the gate structure 115 shown.

[0051] By way of example and not limitation, the sacrificial gate structure 700 may be formed by depositing and patterning a sacrificial gate electrode 700a over the fin structure 620. In some embodiments, the sacrificial gate structure 700 is formed over a plurality of fin structures 620. Figure 7 As shown, a portion of the fin structure 620 is not covered by the sacrificial gate structure 700. This is because the width of the sacrificial gate structure 700 is narrower than the length of the fin structure 620 along the x-direction. In some embodiments, the sacrificial gate structure 700 serves as a mask structure in subsequent etching operations to define... Figure 1 The channel region of transistor 105 is shown. For this reason, the lateral dimensions (e.g., width and length) of the sacrificial gate structure 700 and the gate structure 115 are substantially similar.

[0052] See Figure 4A Operation 410 may further include a procedure of removing a portion of the fin structure exposed by the sacrificial gate structure, as described in reference to Figure 8 As explained. See also Figure 8The removal process can remove portions of the fin structure 620 not covered by the sacrificial gate structure 700. In some embodiments, the removal process involves a dry etching process, a wet etching process, or a combination thereof. The removal process is selective for the first NS layer 620a and the second NS layer 620b, shaping them into a first NS layer 820a and an NS layer 120, respectively. The removal process can further remove portions of the fin structure 110. In some embodiments, the dry etching process includes: an etchant having an oxygen-containing gas, a fluorine-containing gas (e.g., carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3), and / or hexafluoroethane (C2F6)); a chlorine-containing gas (e.g., chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4), and / or boron trichloride (BCl3)); a bromine-containing gas (e.g., hydrogen bromide (HBr) and / or bromoform (CHBr3)); an iodine-containing gas; other suitable etching gases and / or plasma; or combinations thereof. Wet etching chemistry may include diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH); or combinations thereof.

[0053] In some embodiments, the etchant used in the aforementioned etching process does not substantially etch the sacrificial gate structure 700—which is protected by the capping layer 705 and the gate spacer 135—and Figure 6 The STI region 138 is shown. This is because the capping layer 705, the gate spacer 135, and the STI region 138 comprise a material with low etch selectivity, such as a silicon nitride-based material (e.g., silicon nitride, silicon carbon nitride, and silicon carbon oxy-nitride), or a silicon oxide-based material. In some embodiments, Figure 6 The STI region 138 shown is used as an etch stop layer in the above etch process.

[0054] After removing the portion of the fin structure 620 not covered by the sacrificial gate structure 700, an opening 840 is formed in each fin structure 620, such as Figure 8 As shown, opening 840 divides each fin structure 620 into separate portions, each portion being covered by a sacrificial gate structure 700. Each portion may include a stack of a first NS layer 820a as a sacrificial layer and NS layers 120 as channel regions.

[0055] See Figure 4A Method 400 can then proceed to operation 420, wherein the inner spacer structure is formed between the channel areas. For example, as shown in reference... Figure 9 and Figure 10As explained, the inner spacer structure 130 can be formed in the opening 840. The process of forming the inner spacer may include (i) selectively etching the edge portion of the first NS layer 820a to form the recess structure 945, as shown in the reference. Figure 9 As explained, and (ii) the formation of an inner spacer structure 130 in the recessed structure 945, as shown in reference Figure 10 As described. According to some embodiments, Figure 9 The exposed edge of the first NS layer 820a is shown after being laterally etched (e.g., recessed) along the x-direction and becoming the first NS layer 920a. Figure 8 The structure. According to some embodiments, the exposed edge of the first NS layer 820a is along such a structure. Figure 9 The amount of recessed (e.g., partially etched) in the x-direction is approximately 3 nm to approximately 10 nm to form the recessed structure 945.

[0056] In some embodiments, selective etching of the first NS layer 820a can be achieved using a dry etching process selective for SiGe. For example, halogen-based chemicals exhibit high etch selectivity for Ge and low etch selectivity for Si. Therefore, halogen gases etch Ge-containing layers, such as the first NS layer 820a, at a higher etch rate than substantially Ge-free layers (such as NS layer 120). In some embodiments, halogen-based chemicals include fluorine-based and / or chlorine-based gases. Alternatively, a wet etching chemical with high selectivity for SiGe can be used. By way of example and not limitation, a wet etching chemical may include a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), or a mixture of ammonium hydroxide and H2O2 and water (APM). The aforementioned etching process is timed to remove the desired amount of SiGe.

[0057] In some embodiments, the first NS layer 820a with a higher Ge atom concentration has a higher etch rate than the NS layer 120 with a lower or zero Ge atom concentration. Therefore, the etch rate of the aforementioned etching process can be adjusted by regulating the Ge atom concentration (e.g., Ge content) in the first NS layer 820a. As discussed above, the Ge content in the first NS layer 820a can be in the range of about 20% to about 30%. A SiGe nanosheet layer with about 20% Ge can be etched more slowly than a SiGe nanosheet layer with about 30% Ge. Therefore, the Ge concentration can be adjusted accordingly to achieve the desired etch rate and selectivity between the first NS layer 820a and the NS layer 120.

[0058] See Figure 9 and Figure 10 Once the concave structure 945 is formed, a dielectric layer can be deposited in a blanket-like manner. Figure 9The portion of the dielectric layer above the entire structure, and outside the recessed structure 945, can be removed, leaving the inner spacer structure 130 filling the recessed structure 945, as shown in the reference. Figure 10 As explained.

[0059] See Figure 4A Method 400 can then proceed to operation 430, wherein a source / drain (S / D) region is formed adjacent to the channel region. For example, as shown in reference... Figure 11 As explained, the S / D epitaxial structure 125 can be formed by epitaxially growing a semiconductor material in the opening 840 and is adjacent to the NS layer 120.

[0060] In some embodiments, such as reference Figure 11 As explained, the S / D epitaxial structure 125 can be epitaxially grown using a CVD process, which is similar to the process used in operation 405 to form the first and second N / S layers 520a and 520b, as shown in reference. Figure 5 As described above. In some embodiments, the S / D epitaxial structure 125 may be epitaxially grown on the side surface of the NS layer 120 in a horizontal direction (e.g., along the x-axis). In some embodiments, the S / D epitaxial structure 125 may be epitaxially grown on the top surface of the fin structure 110 in a vertical direction (e.g., along the z-axis). In some embodiments, the S / D epitaxial structure 125 may be grown using a plasma-enhanced CVD (PECVD) process. In some embodiments, a precursor gas (e.g., SiH4, SiH2Cl2, SiHCl3, or a combination thereof) may be used to grow a semiconductor material (e.g., Si) having the same or similar crystalline structure as the NS layer 120. In some embodiments, an etching gas (e.g., hydrogen chloride (HCl)) may be used to selectively remove semiconductor material having an amorphous structure formed on the dielectric surface (e.g., the side surfaces of the inner spacer structure 130 and the gate spacer 135). Removing the semiconductor material with an amorphous structure ensures that the crystalline structure of the S / D epitaxial structure 125 is crystalline. In some embodiments, a dopant precursor gas, such as phosphine (PH3), arsine (AsH3), antimonyane (SbH3), or a combination thereof, can be used in a CVD or PECVD process to dope the S / D epitaxial structure 125. In some embodiments, after the S / D epitaxial structure 125 is formed, an ILD layer 165 can be formed by depositing a dielectric material layer to fill the space in the opening 840 and on top of the S / D epitaxial structure 125.

[0061] See Figure 4A Method 400 can proceed to operation 440, wherein an IL is formed on the channel region. Prior to the formation of the IL, the surface of the channel region can be exposed by removing the sacrificial gate structure 700 and the first NS layer 920a, as shown in the reference. Figure 12As described above. In some embodiments, removing the sacrificial gate structure 700 may include removing the capping layer 705 to expose the sacrificial gate electrode 700a, and subsequently removing the sacrificial gate electrode 700a to expose the fin structure 620 between the S / D epitaxial structures 125. In some embodiments, removing the first NS layer 920a may include selectively etching the first NS layer 920a without removing the NS layer 120, as described above. Figure 12 As explained.

[0062] After the surface of the channel region is exposed, IL can form on the channel region. For example, see reference... Figure 13 As explained, IL115a can be formed on the exposed surface of NS layer 120. Operation 440 further refers to... Figure 13 The displayed magnified area is 1300. Figures 14-17 Detailed in Figure 4B middle.

[0063] See Figure 4B Operation 440 begins with operation 442, which involves forming a thermal oxide layer on the channel region. For example, see reference... Figure 14 As described, a thermal oxide layer 1415 may be formed on the NS layer 120. In some embodiments, the thermal oxide layer 1415 may be formed by exposing the surface of the NS layer 120 to a gas mixture, such as a gas mixture of nitrogen (N2), oxygen (O2), and hydrogen (H2), a gas mixture of nitrogen dioxide (N2O), H2, and N2, a gas mixture of nitrous oxide (NO2), H2, and N2, and a gas mixture of water vapor (H2O), N2, O2, and H2. In some embodiments, the pressure of the gas mixture may be controlled between about 0.1 Torr and about 2.3 × 10⁻⁶. 4 Between Torr. In some embodiments, the temperature of the NS layer 120 may be raised above room temperature while the NS layer 120 is exposed to a gas mixture. For example, the temperature of the NS layer 120 may be between about 400 °C and about 1000 °C. In some embodiments, the duration of the NS layer 120's exposure to the gas mixture may be controlled between about 100 ns and about 1 hour. In some embodiments, Si atoms at the surface of the NS layer 120 may be oxidized by a chemical solution to form a thermal oxide layer 1415. The oxidation of Si atoms at the surface of the NS layer 120 by exposing the surface of the NS layer 120 to a chemical solution is incomplete, such that the thermal oxide layer 1415 includes Si atoms at the surface of the NS layer 120. 3+ Si 2+ or Si 1+The Si atoms in the state have dangling bonds corresponding to oxygen vacancies 1470. In some embodiments, oxidation of the Si atoms at the surface of the NS layer 120 can form a thermal oxide layer 1415 with a thickness d1 between about 0.2 nm and about 2 nm. The presence of the thermal oxide layer 1415 above the surface of the NS layer 120 prevents further oxidation into the NS layer 120.

[0064] See Figure 4B Operation 440 continues with operation 444, which involves depositing a rare earth oxide layer on the thermal oxide layer. For example, see reference... Figure 15 As described, the rare earth oxide layer 1515 may be deposited on the thermal oxide layer 1415. In some embodiments, depositing the rare earth oxide layer 1515 may include depositing rare earth oxide materials such as yttrium oxide, scandium oxide, lanthanum oxide, cerium oxide, praseodymium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide, ytterbium oxide, diurethane oxide, and / or a combination thereof. For example, depositing the rare earth oxide layer 1515 may include depositing yttrium oxide (Y₂O₃). In some embodiments, the rare earth oxide layer 1515 may be deposited by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process to conformally cover the exposed surface of the thermal oxide layer 1415. In some embodiments, the rare earth oxide layer 1515 may also be deposited on the exposed side surface 135s of the gate spacer 135. In some embodiments, the thickness of the rare earth oxide layer 1515 can be controlled to be between about 5 nm and about 20 nm during the deposition process.

[0065] See Figure 4B Operation 440 continues with operation 446 and a procedure for annealing the rare earth oxide layer and the thermal oxide layer. This annealing procedure can remove SiO from the thermal oxide layer. x It transforms into SiO2. The annealing process can also form a rare-earth silicate layer between the thermal oxide layer and the rare-earth oxide layer. For example, see reference... Figure 16 As explained, an annealing process 1650 can promote the diffusion of oxygen atoms from the rare earth oxide layer 1515 to the thermal oxide layer 1415, and through interaction with Si 3+ Si 2+ or Si 1+ The Si atoms in the state replace the oxygen vacancies 1470. By controlling the parameters of the annealing process 1650, such as temperature and duration, the oxygen vacancies 1470 in the thermal oxide layer 1415 can be sufficiently reduced or removed to allow the SiO in the thermal oxide layer 1415 to be replaced. xThe annealing process transforms into SiO2 to form IL 115a. In some embodiments, the temperature of the annealing process 1650 may be between about 400 °C and about 1000 °C. In some embodiments, the duration of the annealing process 1650 may be between about 100 ns and about 1 hour. In some embodiments, the annealing process 1650 may be performed in a gaseous environment having N2, O2, H2, argon (Ar), or a combination thereof.

[0066] In some embodiments, during the annealing process 1650, the rare earth oxide layer 1515 may react with Si atoms 1675 near the surface of the thermally heated oxide layer 1415 to form a silicate layer 1615. For example, the Y₂O₃ of the rare earth oxide layer 1515 can react with the Si atoms 1675 on the surface of the rare earth oxide layer 1415 in the reaction Y₂O₃ + SiO₂ x → Y2(SiO x ) + 3O to SiO x The reaction releases approximately 53 ± 5 kJ / mol of energy. This energy release can further promote the diffusion of additional oxygen atoms generated in the reaction into the thermal oxide layer 1415 and reduce the total number of oxygen vacancies 1470. The SiO₂ consumed in the reaction... x The thickness of the thermal oxide layer 1415 can be reduced from, for example... Figure 15 The d1 shown is reduced to the following: Figure 16 As shown in the figure. In some embodiments, the thickness reduction Δd (a difference between thickness d1 and d) may be about 0.1 nm. In some embodiments, the ratio between the thickness reduction Δd and thickness d1 may be between about 5% and about 20%. In some embodiments, if the ratio between the thickness reduction Δd and thickness d1 is less than about 5%, the oxygen vacancies in the thermal oxide layer 1415 are not completely removed during the annealing process, and the quality of the thermal oxide layer 1415 is not sufficiently improved. In some embodiments, if the ratio between the thickness reduction Δd and thickness d1 is greater than about 20%, the thickness d of the thermal oxide layer 1415 may be excessively reduced, which may affect the uniformity of the thermal oxide layer 1415. In some embodiments, the annealing process 1650 may also form a rare earth silicate layer 1635 between the gate spacer 135 and the rare earth oxide layer 1515.

[0067] See Figure 4B Operation 440 continues with operation 448 and a procedure to remove the rare earth oxide layer and rare earth silicate layer. For example, it can remove, for instance, the rare earth oxide layer and rare earth silicate layer. Figure 16 The rare earth oxide layer 1515, silicate layer 1615, and rare earth silicate layer 1635 shown are left as referenced. Figure 17The IL 115a described herein. In some embodiments, removal of the rare earth oxide layer and the rare earth silicate layer may include performing a wet etching process in a chemical solution. In some embodiments, the chemical solution may include DI water, H2O2, HCl, DiCO2, or a combination thereof. For example, the chemical solution may include a mixture of H2O2, HCl, and DI water. In some embodiments, the temperature of the chemical solution may be at or above room temperature. For example, the temperature of the chemical solution may be about 50 °C. In some embodiments, after the silicate layer is removed, a small amount of rare earth elements (e.g., Y) may remain on a surface 115s of the IL 115a and / or the side surface 135s of the gate spacer 135. In some embodiments, the rare earth elements may be completely removed without leaving any residue on surfaces 115s and 135s. After operations 442-448, the IL 115a formed on the NS layer 120 may have: (i) its Si atoms are in Si 4+ (ii) Its thickness is reduced.

[0068] See Figure 4A Method 400 can continue with operations 450 and procedures including depositing a gate dielectric layer on the IL and depositing a gate electrode on the gate dielectric layer to form a metal gate structure. For example, see reference... Figure 18 As described above, the gate dielectric layer 115b may be deposited on the IL 115a, and the gate electrode 115c may be deposited on the gate dielectric layer 115b to form a metal gate structure 115. The metal gate structure 115 is electrically isolated from the S / D epitaxial structure 125 by an inner spacer structure 130 and a gate spacer 135. In some embodiments, depositing the gate dielectric layer 115b may include depositing a high-k dielectric material (e.g., HfO2, Al2O3, ScO2, ZrO2, CaO, MgO, and / or ZrSiO4) in a CVD or ALD process. In some embodiments, depositing the gate dielectric layer 115b may further include depositing a lanthanum oxide (La2O3) layer to form an N-dipole in the gate dielectric layer 115b for tuning the threshold voltage of the transistor 105. In some embodiments, depositing the gate electrode 115c may include depositing one or more work function metal layers and an electrode contact layer (e.g., titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, copper, or nickel) in a CVD or ALD process. In some embodiments, one or more of dielectric layers 152, 154, and 156 may be formed over the metal gate structure 115 and the ILD layer 165 by sequentially depositing dielectric layers such as silicon oxide and silicon nitride, as shown in the figure. Figure 19 As explained.

[0069] See Figure 4AMethod 400 can then proceed to operation 460 and procedure for forming contact structures on the gate electrode and the S / D region. For example, a gate contact via 167 can be formed on the gate electrode 115c, and an S / D contact 163 can be formed on the S / D epitaxial structure 125, as shown in reference. Figure 2 As explained.

[0070] In some embodiments, forming the gate contact via 167 may include: (i) forming an opening through one or more of the dielectric layers 152, 154 and 156 to expose the gate electrode 115c; and (ii) depositing a metal material (e.g., W, Cu and / or Mo) in the opening.

[0071] In some embodiments, forming the S / D contact 163 may include: (i) forming an opening through one or more of the dielectric layers 152, 154 and 156 and through the ILD layer 165 to expose the S / D epitaxial structure 125; (ii) forming a silicide layer 164 on the S / D epitaxial structure 125; and (iii) depositing a metallic material (e.g., W, Cu and / or Mo) in the opening.

[0072] The embodiments described herein relate to a structure of a semiconductor device and a method for forming the structure. The structure may include a transistor on a substrate. The transistor may include a channel region, a source / drain region adjacent to the channel region, and a gate structure on the channel region. The gate structure may include an IL on a surface of the channel region, a gate dielectric layer on the IL, and a gate electrode on the gate dielectric layer. The IL may be a thermal oxide layer comprising SiO2 having an O-to-Si ratio of about 2, and may be free of dangling bonds and oxygen vacancies. The method for forming the structure may include: forming a thermal oxide layer on the channel region; depositing a rare earth oxide layer on the thermal oxide layer; and performing an annealing process to promote the diffusion of oxygen atoms from the rare earth oxide layer into the thermal oxide layer, thereby reducing and removing oxygen vacancies in the thermal oxide layer. The annealing process may be achieved by removing SiO2 atoms from the thermal oxide layer. x The process involves converting the rare earth oxide layer to SiO2 to improve the quality of the interphase (IL). The method may further include removing the rare earth oxide layer and depositing the gate dielectric layer and the gate electrode on the IL to form the gate structure in the channel region.

[0073] In some embodiments, a method includes: forming a channel region in a fin structure on a substrate; forming a source / drain (S / D) region adjacent to the channel region; forming a thermal oxide layer on the channel region; depositing a rare earth oxide layer on the thermal oxide layer; annealing the rare earth oxide layer and the thermal oxide layer to reduce a density of oxygen vacancies in the thermal oxide layer; removing the rare earth oxide layer; depositing a high-k dielectric layer on the thermal oxide layer; and depositing a gate electrode on the high-k dielectric layer.

[0074] In some embodiments, a method includes: forming a channel region in a fin structure; forming a source / drain (S / D) region adjacent to the channel region; forming a thermal oxide layer on the channel region; depositing a rare earth oxide layer on the thermal oxide layer; annealing the rare earth oxide layer and the thermal oxide layer; removing the rare earth oxide layer; depositing a high-k dielectric layer on the thermal oxide layer; and depositing a gate electrode on the high-k dielectric layer.

[0075] In some embodiments, annealing the rare earth oxide layer and the thermal oxide layer includes forming a rare earth silicate layer between the rare earth oxide layer and the thermal oxide layer.

[0076] In some embodiments, the method further includes removing the rare earth silicate layer after removing the rare earth oxide layer.

[0077] In some embodiments, annealing the rare earth oxide layer and the thermal oxide layer includes causing oxygen atoms to diffuse from the rare earth oxide layer to the thermal oxide layer.

[0078] In some embodiments, annealing the rare earth oxide layer and the thermal oxide layer involves increasing the oxygen-to-silicon ratio in the thermal oxide layer.

[0079] In some embodiments, depositing the rare earth oxide layer includes depositing the rare earth oxide layer by means of an atomic layer deposition process.

[0080] In some embodiments, forming the thermal oxide layer involves exposing the channel region to a gas mixture containing oxygen, nitrogen dioxide, or nitrogen oxides.

[0081] In some embodiments, a method includes forming a nanostructure in a fin structure, forming a source / drain (S / D) region adjacent to the nanostructure, and forming a gate structure surrounding the nanostructure. In some embodiments, forming the gate structure includes: forming a thermal oxide layer on the nanostructure; depositing a rare earth oxide layer on the thermal oxide layer; forming a rare earth silicate layer between the thermal oxide layer and the rare earth oxide layer; removing the rare earth oxide layer; depositing a high-k dielectric layer on the thermal oxide layer; and depositing a gate electrode on the high-k dielectric layer.

[0082] In some embodiments, depositing the rare earth oxide layer includes depositing yttrium oxide, scandium oxide, lanthanum oxide, cerium oxide, praseodymium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide, ytterbium oxide, or ruthenium oxide.

[0083] In some embodiments, forming the rare earth silicate layer includes annealing the rare earth oxide layer and the thermal oxide layer.

[0084] In some embodiments, forming the rare earth silicate layer involves increasing the oxygen-to-silicon ratio in the thermal oxide layer.

[0085] In some embodiments, forming the rare earth silicate layer involves reducing the thickness of the thermal oxide layer by about 5% to about 20%.

[0086] In some embodiments, forming the rare earth silicate layer involves removing oxygen vacancies in the thermal oxide layer.

[0087] In some embodiments, forming the rare earth silicate layer involves increasing the oxygen-to-silicon ratio in the thermal oxide to about 2:1.

[0088] In some embodiments, a structure includes a substrate and a fin structure on the substrate, wherein the fin structure includes a channel region. The structure further includes: a source / drain (S / D) region on the fin structure and adjacent to the channel region; and a gate structure surrounding the channel region. The gate structure includes a thermal oxide layer on the channel region, a high-k dielectric layer on the thermal oxide layer, and a gate electrode on the high-k dielectric layer. An interface between the high-k dielectric layer and the thermal oxide layer includes rare-earth elements.

[0089] In some embodiments, the oxygen-to-silicon ratio in the thermal oxide layer is approximately 2:1.

[0090] In some embodiments, the thickness of the thermal oxide layer is about 1 nm.

[0091] In some embodiments, the rare earth elements include yttrium, scandium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, or ruthenium.

[0092] In some embodiments, the structure further includes a gate spacer between the S / D region and the gate structure, wherein an interface between the gate spacer and the high-k dielectric layer contains the rare earth element.

[0093] In some embodiments, the interface comprises rare earth silicates.

[0094] In some embodiments, a structure includes a substrate and a fin structure on the substrate, wherein the fin structure includes a channel region. The structure further includes: a source / drain (S / D) region on the fin structure and adjacent to the channel region; and a gate structure surrounding the channel region. The gate structure includes a thermal oxide layer on the channel region, a high-k dielectric layer on the interphase layer (IL), and a gate electrode on the work function layer. An interface between the high-k dielectric layer and the thermal oxide layer includes rare-earth elements.

[0095] It will be understood that the implementation section, rather than the summary section of the disclosure, is intended to interpret the claims in terms of language. The summary section of this disclosure may set forth one or more, but not all, possible embodiments of this disclosure as conceived by the inventors, and is therefore not intended to limit the appended claims in any way.

[0096] The foregoing disclosure outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other programs and structures to perform the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a transistor structure, characterized in that: Include: Channel areas are formed in the fin structure; This forms a source / drain region adjacent to the channel region; A thermal oxide layer is formed in this channel region; A rare earth oxide layer is deposited on the thermal oxide layer; Anneal the rare earth oxide layer and the thermal oxide layer; Remove the rare earth oxide layer; A high-k dielectric layer is deposited on the thermal oxide layer; as well as A gate electrode is deposited on this high-k dielectric layer.

2. The method for forming a transistor structure as described in claim 1, characterized in that: Annealing the rare earth oxide layer and the thermal oxide layer together forms a rare earth silicate layer between the rare earth oxide layer and the thermal oxide layer.

3. The method for forming a transistor structure as described in claim 1, characterized in that: Annealing the rare earth oxide layer and the thermal oxide layer involves allowing oxygen atoms to diffuse from the rare earth oxide layer to the thermal oxide layer.

4. A method for forming a transistor structure, characterized in that: Include: Nanostructures are formed within the fin structure; Forming source / drain regions adjacent to the nanostructure; and Forming a gate structure surrounding the nanostructure, wherein forming the gate structure comprises: A thermal oxide layer is formed on this nanostructure; A rare earth oxide layer is deposited on the thermal oxide layer; A rare earth silicate layer is formed between the thermal oxide layer and the rare earth oxide layer; Remove the rare earth oxide layer; A high-k dielectric layer is deposited on the thermal oxide layer; as well as A gate electrode is deposited on this high-k dielectric layer.

5. The method for forming a transistor structure as described in claim 4, characterized in that: Forming this rare earth silicate layer involves increasing the oxygen-to-silicon ratio in the thermal oxide layer.

6. The method for forming a transistor structure as described in claim 4, characterized in that: Forming the rare earth silicate layer involves reducing the thickness of the thermal oxide layer by about 5% to about 20%.

7. A transistor structure, characterized in that: Include: Matrix; A fin structure on the substrate, wherein the fin structure includes a channel region; Source / drain region, which is located on the fin structure and adjacent to the channel region; as well as A gate structure surrounding the channel region, wherein the gate structure comprises: A thermal oxide layer on the channel region; A high-k dielectric layer is provided on the thermal oxide layer, wherein the interface between the high-k dielectric layer and the thermal oxide layer contains rare earth elements. as well as The gate electrode is located on the high-k dielectric layer.

8. The transistor structure as described in claim 7, characterized in that: The oxygen-to-silicon ratio in this thermal oxide layer is approximately 2:

1.

9. The transistor structure as described in claim 7, characterized in that: The thickness of the thermal oxide layer is approximately 1 nm.

10. The transistor structure as described in claim 7, characterized in that: The gate spacer is further included between the source / drain region and the gate structure, wherein the rare earth element is contained at the interface between the gate spacer and the high-k dielectric layer.

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